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* RISC-V: Provide a cleaner raw_smp_processor_id()Palmer Dabbelt2018-10-221-10/+4
| | | | | | | | | | | I'm not sure how I managed to miss this the first time, but this is much better. Signed-off-by: Palmer Dabbelt <palmer@sifive.com> [Atish: code comment formatting and other fixes] Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* clocksource: new RISC-V SBI timer driverPalmer Dabbelt2018-08-131-3/+0
| | | | | | | | | | | | | | | | | | | The RISC-V ISA defines a per-hart real-time clock and timer, which is present on all systems. The clock is accessed via the 'rdtime' pseudo-instruction (which reads a CSR), and the timer is set via an SBI call. Contains various improvements from Atish Patra <atish.patra@wdc.com>. Signed-off-by: Dmitriy Cherkasov <dmitriy@oss-tech.org> Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com> [hch: remove dead code, add SPDX tags, used riscv_of_processor_hart(), minor cleanups, merged hotplug cpu support and other improvements from Atish] Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* RISC-V: simplify software interrupt / IPI codeChristoph Hellwig2018-08-131-3/+0
| | | | | | | | | Rename handle_ipi to riscv_software_interrupt, drop the unused return value and move the prototype to irq.h together with riscv_timer_interupt. This allows simplifying the upcoming interrupt handling support. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* RISC-V: Init and Halt CodePalmer Dabbelt2017-09-261-0/+52
This contains the various __init C functions, the initial assembly kernel entry point, and the code to reset the system. When a file was init-related this patch contains the entire file. Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
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