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* powerpc/booke: Merge the 32 bit e5500/e500mc cpu setup code.Varun Sethi2012-09-121-0/+4
| | | | | | | | | | Merge the 32 bit cpu setup code for e500mc/e5500 and define the "cpu_restore" routine (for e5500/e6500) only for the 64 bit case. The cpu_restore routine is used in the 64 bit case for setting up the secondary cores. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Disintegrate asm/system.h for PowerPCDavid Howells2012-03-281-0/+1
| | | | | | | | Disintegrate asm/system.h for PowerPC. Signed-off-by: David Howells <dhowells@redhat.com> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> cc: linuxppc-dev@lists.ozlabs.org
* Merge remote-tracking branch 'kumar/next' into nextBenjamin Herrenschmidt2012-03-211-0/+18
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| * powerpc: Add initial e6500 cpu supportKumar Gala2012-03-151-0/+18
| | | | | | | | | | | | Add basic support for e6500 core in its single threaded mode. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/44x: The bug fixed support for APM821xx SoC and Bluestone boardVinh Nguyen Huu Tuong2012-03-171-1/+1
|/ | | | | | | | | This patch consists of: - Fix the pvr mask for checking pvr in cputable.c - Fix the cpu name as consistent with cpu name is describled in dts file Signed-off-by: Vinh Nguyen Huu Tuong <vhtnguyen@apm.com> Signed-off-by: Josh Boyer <jwboyer@gmail.com>
* powerpc/476fpe: Add 476fpe SoC codeTony Breeds2011-12-091-0/+14
| | | | | | | Based on original work by David 'Shaggy' Kleikamp. Signed-off-by: Tony Breeds <tony@bakeyournoodle.com> Signed-off-by: Josh Boyer <jwboyer@gmail.com>
* powerpc/40x: Add APM8018X SOC supportTanmay Inamdar2011-11-301-0/+13
| | | | | | | | | | | The AppliedMicro APM8018X embedded processor targets embedded applications that require low power and a small footprint. It features a PowerPC 405 processor core built in a 65nm low-power CMOS process with a five-stage pipeline executing up to one instruction per cycle. The family has 128-kbytes of on-chip memory, a 128-bit local bus and on-chip DDR2 SDRAM controller with 16-bit interface. Signed-off-by: Tanmay Inamdar <tinamdar@apm.com> Signed-off-by: Josh Boyer <jwboyer@gmail.com>
* powerpc: various straight conversions from module.h --> export.hPaul Gortmaker2011-10-311-1/+1
| | | | | | | | | All these files were including module.h just for the basic EXPORT_SYMBOL infrastructure. We can shift them off to the export.h header which is a way smaller footprint and thus realize some compile time gains. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
* powerpc: Return the_cpu_ spec from identify_cpuScott Wood2011-08-051-5/+6
| | | | | | | | | | | Commit af9eef3c7b1ed004c378c89b87642f4937337d50 caused cpu_setup to see the_cpu_spec, rather than the source struct. However, on 32-bit, the return value of identify_cpu was being used for feature fixups, and identify_cpu was returning the source struct. So if cpu_setup patches the feature bits, the update won't affect the fixups. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc/book3e: Fix CPU feature handling on e5500 in 32-bit modeKumar Gala2011-06-021-1/+1
| | | | | | | | We are missing FPU feature bit that user space may require. In the 64-bit mode this gets set since we pull it in via COMMON_USER_PPC64. We just explicitly set it so user space will be happy again. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc: Free up some CPU feature bits by moving out MMU-related featuresMatt Evans2011-04-271-26/+19
| | | | | | | | | Some of the 64bit PPC CPU features are MMU-related, so this patch moves them to MMU_FTR_ bits. All cpu_has_feature()-style tests are moved to mmu_has_feature(), and seven feature bits are freed as a result. Signed-off-by: Matt Evans <matt@ozlabs.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: Add A2 cpu supportBenjamin Herrenschmidt2011-04-271-2/+23
| | | | | | | | | Add the cputable entry, regs and setup & restore entries for the PowerPC A2 core. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: Define CPU feature for Architected 2.06 HV modeBenjamin Herrenschmidt2011-04-201-0/+6
| | | | | | | | | | This bit indicates that we are operating in hypervisor mode on a CPU compliant to architecture 2.06 or later (currently server only). We set it on POWER7 and have a boot-time CPU setup function that clears it if MSR:HV isn't set (booting under a hypervisor). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc/book3e: Fix CPU feature handling on 64-bit e5500Kumar Gala2011-04-121-1/+1
| | | | | | | | | | | | | The CPU_FTRS_POSSIBLE and CPU_FTRS_ALWAYS defines did not encompass e5500 CPU features when built for 64-bit. This causes issues with cpu_has_feature() as it utilizes the POSSIBLE & ALWAYS defines as part of its check. Create a unique CPU_FTRS_E5500 (as its different from CPU_FTRS_E500MC), created a new group for 64-bit Book3e based CPUs and add CPU_FTRS_E5500 to that group. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Merge remote branch 'jwb/next' into nextBenjamin Herrenschmidt2011-03-171-4/+18
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| * powerpc/476: define specific cpu table entry DD2 coreDave Kleikamp2011-02-021-4/+18
| | | | | | | | | | | | | | | | | | | | The DD2 core still has some unstability. Define CPU_FTR_476_DD2 to enable workarounds in later patches. This is based on an earlier, unreleased patch for DD1 by Ben Herrenschmidt. Signed-off-by: Dave Kleikamp <shaggy@linux.vnet.ibm.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* | powerpc: Pass the right cpu_spec to ->setup_cpu() on 64-bitBenjamin Herrenschmidt2011-02-071-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | When calling setup_cpu() on 64-bit, we pass a pointer to the cputable entry we have found. This used to be fine when cur_cpu_spec was a pointer to that entry, but nowadays, we copy the entry into a separate variable, and we do so before we call the setup_cpu() callback. That means that any attempt by that callback at patching the CPU table entry (to adjust CPU features for example) will patch the wrong table. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc: machine_check_generic is wrong on 64bitAnton Blanchard2011-01-211-23/+0
|/ | | | | | | | | | | | Decoding machine checks is CPU specific and so machine_check_generic doesn't do the right thing on 64bit chips. Luckily we never call into this code because we call ppc_md.machine_check_exception instead if available. Since we check cur_cpu_spec->machine_check before calling it, we may as well remove machine_check_generic from 64bit archs. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: Add POWER7+ cputable entryMichael Neuling2010-11-291-0/+16
| | | | | | | | This adds the POWER7+ cputable entry for the PVR 0x004a0000. Rest is the same as vanilla POWER7. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: Remove POWER6 oprofile workarounds for POWER7Michael Neuling2010-11-291-4/+0
| | | | | | | These are not needed on POWER7 so remove them. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: Remove unneeded cpu_setup/restore from POWER7 cputable entryMichael Neuling2010-11-291-2/+0
| | | | | | | These are not needed so just remove them Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* Merge remote branch 'jwb/next' into nextBenjamin Herrenschmidt2010-10-151-0/+15
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| * powerpc/44x: Add support for the AMCC APM821xx SoCTirumala Marri2010-10-131-0/+15
| | | | | | | | | | | | | | | | This patch adds CPU, device tree, defconfig and bluestone board support for APM821xx SoC. Signed-off-by: Tirumala R Marri <tmarri@apm.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* | powerpc/fsl-booke: Add support for FSL 64-bit e5500 coreKumar Gala2010-10-141-1/+27
|/ | | | | | | | The new e5500 core is similar to the e500mc core but adds 64-bit support. We support running it in 32-bit mode as it is identical to the e500mc. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/47x: Remove redundant line from cputable.cDave Kleikamp2010-08-231-1/+0
| | | | | | | | There are two entries for .cpu_user_features in arch/powerpc/kernel/cputable.c. Remove the one that doesn't belong Signed-off-by: Dave Kleikamp <shaggy@linux.vnet.ibm.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* powerpc/40x: Distinguish AMCC PowerPC 405EX and 405EXr correctlyLee Nipper2010-07-261-7/+111
| | | | | | | | | | | | | | | | | | The recent AMCC 405EX Rev D without Security uses a PVR value that matches the old 405EXr Rev A/B with Security. The 405EX Rev D without Security would be shown incorrectly as an 405EXr. The pvr_mask of 0xffff0004 is no longer sufficient to distinguish the 405EX from 405EXr. This patch replaces 2 entries in the cpu_specs table and adds 8 more, each using pvr_mask of 0xffff000f and appropriate pvr_value to distinguish the AMCC PowerPC 405EX and 405EXr instances. The cpu_name for these entries now includes the Rev, in similar fashion to the 440GX. Signed-off-by: Lee Nipper <lee.nipper@gmail.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* powerpc/e500mc: Implement machine check handler.Scott Wood2010-05-211-1/+1
| | | | | | | | | | | Most of the MSCR bit assigments are different in e500mc versus e500, and they are now write-one-to-clear. Some e500mc machine check conditions are made recoverable (as long as they aren't stuck on), most notably L1 instruction cache parity errors. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/4xx: Simple platform for the ISS 4xx simulatorTorez Smith2010-05-051-0/+15
| | | | | | | | | | | This is a trivial 4xx plaform that uses the new simple bsp from Josh and is handy to use in simulators such as ISS or even Mambo who don't properly implement most of the actual devices in the SoC but really only the core. Signed-off-by: Torez Smith <lnxtorez@linux.vnet.ibm.com> Signed-off-by: Dave Kleikamp <shaggy@linux.vnet.ibm.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* powerpc/476: add machine check handler for 47x coreDave Kleikamp2010-05-051-0/+1
| | | | | | | | The 47x core's MCSR varies from 44x, so it needs it's own machine check handler. Signed-off-by: Dave Kleikamp <shaggy@linux.vnet.ibm.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* powerpc/47x: Base ppc476 supportDave Kleikamp2010-05-051-0/+13
| | | | | | | | | | | | | | | | This patch adds the base support for the 476 processor. The code was primarily written by Ben Herrenschmidt and Torez Smith, but I've been maintaining it for a while. The goal is to have a single binary that will run on 44x and 47x, but we still have some details to work out. The biggest is that the L1 cache line size differs on the two platforms, but it's currently a compile-time option. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Torez Smith <lnxtorez@linux.vnet.ibm.com> Signed-off-by: Dave Kleikamp <shaggy@linux.vnet.ibm.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* powerpc/perf: e500 supportScott Wood2010-03-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | This implements perf_event support for the Freescale embedded performance monitor, based on the existing perf_event.c that supports server/classic chips. Some limitations: - Performance monitor interrupts are regular EE interrupts, and thus you can't profile places with interrupts disabled. We may want to implement soft IRQ-disabling, with perfmon interrupts exempted and treated as NMIs. - When trying to schedule multiple event groups at once, and using restricted events, situations could arise where scheduling fails even though it would be possible. Consider three groups, each with two events. One group has restricted events, the others don't. The two non-restricted groups are scheduled, then one is removed, which happens to occupy the two counters that can't do restricted events. The remaining non-restricted group will not be moved to the non-restricted-capable counters to make room if the restricted group tries to be scheduled. Signed-off-by: Scott Wood <scottwood@freescale.com> Acked-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc: broadway processor supportAlbert Herranz2009-12-121-3/+3
| | | | | | | | | | | | | | This patch extends the cputable entry of the 750CL to also match the 750CL-based "Broadway" cpu found on the Nintendo Wii. As of this patch, the following "Broadway" design revision levels have been seen in the wild: - DD1.2 (87102) - DD2.0 (87200) Signed-off-by: Albert Herranz <albert_herranz@yahoo.es> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
* powerpc/oprofile: Add ppc750 CL as supported by oprofileDragos Tatulea2009-10-141-0/+2
| | | | | | | Here's a patch that adds the ppc750 CL cpu as supported by oprofile. Signed-off-by: Dragos Tatulea <dtatulea@ixiacom.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc/book3e-64: Move the default cpu table entryKumar Gala2009-08-281-22/+27
| | | | | | | | | Move the default cpu entry table for CONFIG_PPC_BOOK3E_64 to the very end since we will probably want to support both 32-bit and 64-bit kernels for some processors that are higher up in the list. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: Add AMCC 460EX/460GT Rev. B support to cputable.cStefan Roese2009-08-201-2/+28
| | | | | | Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: Remaining 64-bit Book3E supportBenjamin Herrenschmidt2009-08-201-2/+25
| | | | | | | | This contains all the bits that didn't fit in previous patches :-) This includes the actual exception handlers assembly, the changes to the kernel entry, other misc bits and wiring it all up in Kconfig. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: Add 2.06 tlbie mnemonicsMilton Miller2009-05-211-2/+4
| | | | | | | | | | | This adds the PowerPC 2.06 tlbie mnemonics and keeps backwards compatibilty for CPUs before 2.06. Only useful for bare metal systems. Signed-off-by: Milton Miller <miltonm@bga.com> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc/pseries: Really fix the oprofile CPU type on pseriesBenjamin Herrenschmidt2009-05-151-1/+1
| | | | | | | | | | | My previous pach for fixing the oprofile CPU type got somewhat mismerged (by my fault) when it collided with another related patch. This should finally (fingers crossed) fix the whole thing. We make sure we keep the -old- oprofile type and CPU type whenever one of them was specified in the first pass through the function. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: Fix setting of oprofile cpu typeBenjamin Herrenschmidt2009-05-011-2/+2
| | | | | | | | | | | | commit 2657dd4e301d4841ed67a4fac7d145ad8f3e1b28 introduced a bug where we would now always override the "real" oprofile CPU type with the "compatible" one provided by a pseudo-PVR in the device-tree which is incorrect and breaks oprofile on all current configs since the "compatible" ones aren't yet recognized. This fixes it. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc adjust oprofile_cpu_type version 3Michael Wolf2009-05-011-4/+9
| | | | | | | | | | | | | Oprofile is changing the naming it is using for the compatibility modes. Instead of having compat-power<x>, oprofile will go to family naming convention and use ibm-compat-v<x>. Currently only ibm-compat-v1 will be defined. The notion of compatibility events just started with POWER6. So there is no way that any other tool could exist that is using these oprofile_cpu_type strings we want to change. Signed-off-by: Mike Wolf <mjw@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* Revert "powerpc: Add support for early tlbilx opcode"Kumar Gala2009-04-231-1/+1
| | | | | | | This reverts commit e9965577406a2148ade97b5e0ce7c448b4ba4ef6. Our HW guys were able to fix this so it never sees the light of day. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc: Add support for early tlbilx opcodeKumar Gala2009-04-071-1/+1
| | | | | | | | During the ISA 2.06 development the opcode for tlbilx changed and some early implementations used to old opcode. Add support for a MMU_FTR fixup to deal with this. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mm: e300c2/c3/c4 TLB errata workaroundKumar Gala2009-03-241-3/+6
| | | | | | | | | | | | | Complete workaround for DTLB errata in e300c2/c3/c4 processors. Due to the bug, the hardware-implemented LRU algorythm always goes to way 1 of the TLB. This fix implements the proposed software workaround in form of a LRW table for chosing the TLB-way. Based on patch from David Jander <david@protonic.nl> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc/oprofile: Enable support for ppc750 processorsOctavian Purdila2009-03-111-0/+8
| | | | | | | | This patch enables oprofile for all 3 FX variants and GX variant of the 750 processor. Signed-off-by: Octavian Purdila <opurdila@ixiacom.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: Make sure we copy all cpu_spec features except PMC related onesMichael Ellerman2009-03-111-12/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | When identify_cpu() is called a second time with a logical PVR, it only copies a subset of the cpu_spec fields so as to avoid overwriting the performance monitor fields that were initialized based on the real PVR. However some of the other, non performance monitor related fields are also not copied: * pvr_mask * pvr_value * mmu_features * machine_check The fact that pvr_mask is not copied can result in show_cpuinfo() showing the cpu as "unknown", if we override an unknown PVR with a logical one - as reported by Shaggy. So change the logic to copy all fields, and then put back the PMC related ones in the case that we're overwriting a real PVR with a logical one. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Dave Kleikamp <shaggy@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: Deindentify identify_cpu()Michael Ellerman2009-03-111-58/+64
| | | | | | | | | The for-loop body of identify_cpu() has gotten a little big, so move the loop body logic into a separate function. No other changes. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Dave Kleikamp <shaggy@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc/fsl-booke: Add support for tlbilx instructionsKumar Gala2009-03-091-1/+2
| | | | | | | | The e500mc core supports the new tlbilx instructions that do core local invalidates and also provide us the ability to take down all TLB entries matching a given PID. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* AMCC PPC 460SX redwood SoC platform initial frameworkMadhulika Madishetty2009-02-141-0/+14
| | | | | | | | | | | | | This patch contains initial framework for the AMCC Redwood board. Signed-off-by: Madhulika Madishetty <mmadishetty@amcc.com> Signed-off-by: Tirumala Marri <tmarri@amcc.com> Signed-off-by: Feng Kan <fkan@amcc.com> Signed-off-by: Vidhyananth Venkatasamy <vvenkatasamy@amcc.com> Signed-off-by: Preetesh Parekh <pparekh@amcc.com> Acked-by: Loc Ho <lho@amcc.com> Acked-by: Feng Kan <fkan@amcc.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* powerpc/fsl-booke: Cleanup init/exception setup to be runtimeKumar Gala2009-01-281-0/+8
| | | | | | | | | | | | | | | | | | We currently have a few variants of fsl-booke processors (e500v1, e500v2, e500mc, and e200). They all have minor differences that we had previously been handling via ifdefs. To move towards having this support the following changes have been made: * PID1, PID2 only exist on e500v1 & e500v2 and should not be accessed on e500mc or e200. We use MMUCFG[NPIDS] to determine which case we are since we only touch PID1/2 in extremely early init code. * Not all IVORs exist on all the processors so introduce cpu_setup functions for each variant to setup the proper IVORs that are either unique or exist but have some variations between the processors Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mm: Introduce MMU featuresBenjamin Herrenschmidt2008-12-211-0/+113
| | | | | | | | | | | | We're soon running out of CPU features and I need to add some new ones for various MMU related bits, so this patch separates the MMU features from the CPU features. I moved over the 32-bit MMU related ones, added base features for MMU type families, but didn't move over any 64-bit only feature yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
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