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* [MIPS] Replace 40c7869b693b18412491fdcff64682215b739f9e kludgeAtsushi Nemoto2008-01-111-2/+0
| | | | | Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Malta: Fix software reset on big endianDmitri Vorobiev2008-01-111-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I noticed that the commit f197465384bf7ef1af184c2ed1a4e268911a91e3 (MIPS Tech: Get rid of volatile in core code) broke the software reset functionality for MIPS Malta boards in big-endian mode. According to the MIPS Malta board user's manual, writing the magic 32-bit GORESET value into the SOFTRES register initiates board soft reset. My experimentation has shown that the endianness of the GORESET integer should thereby be the same as the endianness, which has been set for the CPU itself. The writew() function used to write the magic value in the code introduced by the commit mentioned above, however, swaps bytes for big-endian kernels and transfers 16 bits instead of 32. The patch below replaces the writew() function by the __raw_writel() routine, which leaves the byte order intact and transfers the whole MIPS machine word. Trivial code cleanup (replacing spaces by a tab and cutting oversized lines to make checkpatch.pl happy) is also included. The patch was tested using a Malta evaluation board running in both BE and LE modes. For both modes, software reset was fully functional after the change. P.S. I suspect that the same commit broke the "standby" functionality for MIPS Atlas boards. However, I did not touch the Atlas code as I don't have such board at my disposal and also because the linux-mips.org Web site claims that Atlas support is scheduled for removal. Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Atlas, Malta: Don't free firmware memory on free_initmem.Ralf Baechle2007-12-141-0/+2
| | | | | | | A proper fix for this needs to turn a few MIPS-generic bits which I don't want at this stage. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Don't byteswap writes to display when running bigendianChris Dearman2007-12-091-2/+2
| | | | | Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] time: Replace plat_timer_setup with modern APIs.Ralf Baechle2007-10-291-30/+22
| | | | | | plat_timer_setup is no longer getting called. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Malta: Delete dead code.Ralf Baechle2007-10-221-13/+0
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix "no space between function name and open parenthesis" warnings.Ralf Baechle2007-10-114-12/+12
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] i8253 PIT clocksource and clockevent driversRalf Baechle2007-10-111-0/+4
| | | | | | Derived from the i386 variant with a few x86 complexities chopped off. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Dyntick support for SMTC:Ralf Baechle2007-10-111-1/+0
| | | | | | | | | The kernel currently only supports broadcasting of the timer interrupt from a single timer, not multicasting into two multicast groups of processors. So the implemented mechanism for SMTC works by broadcasting the cp0 compare interrupt on VPE 0 and ignoring it on any additional VPEs. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Implement clockevents for R4000-style cp0 count/compare interruptRalf Baechle2007-10-111-16/+10
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Consolidate all variants of MIPS cp0 timer interrupt handlers.Ralf Baechle2007-10-111-107/+5
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Deforest the function pointer jungle in the time code.Ralf Baechle2007-10-111-2/+2
| | | | | | | Hard to follow who is pointing what to where and why so it's simply getting in the way of the time code renovation. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Use -Werror on subdirectories which build cleanly.Ralf Baechle2007-07-311-0/+2
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] MTI: Add CoreFPGA4 ID.Chris Dearman2007-07-311-0/+1
| | | | | Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SMTC: smtc_timer_broadcast ignores its arguments, make it void.Ralf Baechle2007-07-311-2/+2
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Don't drag a platform specific header into generic arch code.Ralf Baechle2007-06-201-34/+16
| | | | | | | | For some platforms it's definitions may conflict. So that's the one-liner. The rest is 10 square kilometers of collateral damage fixup this include used to paper over. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix builds where MSC01E_xxx is undefined.Chris Dearman2007-06-141-1/+4
| | | | | Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Separate performance counter interruptsChris Dearman2007-06-141-25/+93
| | | | | | | | Support for performance counter overflow interrupt that is on a separate interrupt from the timer. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Malta: Fix for SOCitSC based MaltasChris Dearman2007-06-142-31/+51
| | | | | | | And an attempt to tidy up the core/controller differences. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SMTC: Fix build error caused by nonsense code.Chris Dearman2007-06-111-14/+2
| | | | | Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Atlas, Malta, SEAD: Remove scroll from interrupt handler.Ralf Baechle2007-06-062-29/+26
| | | | | | | | Aside of being handy for debugging this has never been a particularly good idea but is now getting in the way of dyntick / tickless kernels and general cleanups. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] MIPS Tech: Get rid of volatile in core code.Ralf Baechle2007-04-272-10/+10
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] merge GT64111 PCI routines and GT64120 PCI_0 routinesYoichi Yuasa2007-04-271-2/+2
| | | | | | | | | This patch has merged GT64111 PCI routines and GT64120 PCI_0 routines. GT64111 PCI is almost the same as GT64120's PCI_0. This patch don't change GT64120 PCI routines. Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] mips-boards: More liberal check for mips-board consoleThiemo Seufer2007-03-191-1/+1
| | | | | | | | Allows overriding the MALTA/ATLAS/etc. default console setting with non-serial console devices. Signed-Off-By: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Atlas, Malta: Fix build warning.Ralf Baechle2007-03-071-2/+2
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix and cleanup the mess that a dozen prom_printf variants are.Ralf Baechle2007-03-044-21/+15
| | | | | | early_printk is a so much saner thing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] No need to write c0_compare in plat_timer_setupAtsushi Nemoto2007-03-041-3/+0
| | | | | | | | If R4k counter was used for hpt_timer and interrupt source, c0_hpt_timer_init() initializes the c0_compare register. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Kill redundant EXTRA_AFLAGSAtsushi Nemoto2007-02-261-2/+0
| | | | | | | | | | Many Makefiles in arch/mips have EXTRA_AFLAGS := $(CFLAGS) line. This is redundant while AFLAGS contains $(cflags-y) and any options only listed in CFLAGS (not in cflags-y) should be unnecessary for asm sources. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] prom_free_prom_memory cleanupAtsushi Nemoto2007-02-061-14/+4
| | | | | | | | | Current prom_free_prom_memory() implementations are almost same as free_init_pages(), or no-op. Make free_init_pages() extern (again) and make prom_free_prom_memory() use it. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix build errors on SEADAtsushi Nemoto2007-01-081-2/+7
| | | | | | | Quick and dirty fix for build errors on SEAD. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] use generic_handle_irq, handle_level_irq, handle_percpu_irqAtsushi Nemoto2006-11-301-0/+1
| | | | | | | | | | | | | | Further incorporation of generic irq framework. Replacing __do_IRQ() by proper flow handler would make the irq handling path a bit simpler and faster. * use generic_handle_irq() instead of __do_IRQ(). * use handle_level_irq for obvious level-type irq chips. * use handle_percpu_irq for irqs marked as IRQ_PER_CPU. * setup .eoi routine for irq chips possibly used with handle_percpu_irq. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix warning in mips-boards generic PCIYoichi Yuasa2006-11-011-1/+1
| | | | | | | | | arch/mips/mips-boards/generic/pci.c: In function `mips_pcibios_init': arch/mips/mips-boards/generic/pci.c:227: warning: comparison of distinct pointer types lacks a cast arch/mips/mips-boards/generic/pci.c:228: warning: comparison of distinct pointer types lacks a cast Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] 16K & 64K page size fixesRalf Baechle2006-11-011-1/+1
| | | | | | Derived from Peter Watkins <treestem@gmail.com>'s work. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] VSMP: Synchronize cp0 counters on bootup.Ralf Baechle2006-10-311-2/+3
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Flags must be unsigned long.Ralf Baechle2006-10-311-1/+1
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Cleanup remaining references to mips_counter_frequency.Ralf Baechle2006-10-211-1/+1
| | | | | | Noticed by Samium Gromoff but his patch got stale in flight ... Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Cleanup unnecessary <asm/ptrace.h> inclusions.Ralf Baechle2006-10-091-1/+0
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Complete fixes after removal of pt_regs argument to int handlers.Ralf Baechle2006-10-081-11/+11
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Atlas: update interrupt handlingMaciej W. Rozycki2006-09-271-1/+6
| | | | | | | | The following change updates the Atlas interrupt handling to match that of Malta. Tested with a 5Kc and a 34Kf successfully. Signed-off-by: Maciej W. Rozycki <macro@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Patch to arch/mips/mips-boards/generic/time.cKevin D. Kissell2006-09-271-21/+36
| | | | | | | | | | | | | | | | | | | | | | | | | In hooking up the perf counter overflow interrupt to the experimental deprecated-real-soon-now /proc/perf interface last night, I had to revisit arch/mips/mips-boards/generic/time.c, and discovered that when the 2.6.9-based SMTC prototype was merged with the more recent tree, it was missed that arch/mips/kernel/time.c had changed so that even in SMP kernels, timer_interrupt() calls local_timer_interrupt(), so there is no longer a need to invoke it directly from mips_timer_interrupt() in those cases where timer_interrupt() has been called. So I got rid of that, and added the invocation of perf_irq() if Cause.PCI is set, more-or-less following the same logic as in the non-SMTC case, with the modifications that (a) a runtime check for Release 2 isn't done, because it's redundant in SMTC), and (b) we check for a clock interrupt regardless of the value returned by the perf counter service - I don't understand why we'd want to control that with perf_irq(), but maybe one of you knows the story. I also got rid of the stupid warning about the unused variable when compiled for SMTC (another artifact of the merge). The result hasn't been beaten to death, but boots, seems stable, and supports extended precision event counting. Signed-off-by: Kevin D. Kissell <kevink@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Atlas, Malta, SEAD: Don't disable interrupts in mips_time_init().Ralf Baechle2006-07-131-5/+1
| | | | | | By the time it's called from time_init interrupts are still disabled. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Replace board_timer_setup function pointer by plat_timer_setup.Ralf Baechle2006-07-131-1/+1
| | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
* [MIPS] Malta: Fix build of certain configs.Ralf Baechle2006-07-131-24/+26
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* Remove obsolete #include <linux/config.h>Jörn Engel2006-06-305-5/+0
| | | | | Signed-off-by: Jörn Engel <joern@wohnheim.fh-wedel.de> Signed-off-by: Adrian Bunk <bunk@stusta.de>
* [MIPS] Malta: Handle byteswapping hardare bug in big endian mode.Elizabeth Oldham2006-06-191-0/+9
| | | | | | | | The SOC-it system controller running in big endian mode might forget byteswapping when DMAing to the last word of physical memory. Fixed by ignoring the last page of memory. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] 24K LV: Add core card id.Chris Dearman2006-04-272-0/+2
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] kgdb: Let gcc compute the array size itself.Ralf Baechle2006-04-191-1/+1
| | | | | | This is the same method as used in the serial driver. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] MT: Improved multithreading support.Ralf Baechle2006-04-192-8/+61
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix the crime against humanity that mipsIRQ.S is.Ralf Baechle2006-04-192-159/+2
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fixup damage done by 22a9835c350782a5c3257343713932af3ac92ee0.Ralf Baechle2006-04-191-2/+3
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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