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* MIPS: Discard .eh_frame sections in linker script.David Daney2013-08-261-0/+1
| | | | | | | | | | Some toolchains (including Cavium OCTEON SDK) are emitting .eh_frame sections by default. Discard them as they are useless in the kernel. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5684/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Use r4k_wait for OCTEON3 CPUs.David Daney2013-08-261-0/+1
| | | | | | | Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5636/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Probe for new OCTEON CPU/SoC types.David Daney2013-08-261-0/+7
| | | | | | | | | Add probing for CNF71XX, CN78XX and CN70XX. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5635/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BMIPS: fix hardware interrupt routing for boot CPU != 0Florian Fainelli2013-08-051-2/+8
| | | | | | | | | | | | | | | | The hardware interrupt routing for boot CPU != 0 is wrong because it will route all the hardware interrupts to TP0 which is not the one we booted from. Fix this by properly checking which boot CPU we are booting from and updating the right interrupt mask for the boot CPU. This fixes booting on BCM3368 with bmips_smp_emabled = 0. Signed-off-by: Florian Fainelli <florian@openwrt.org> Cc: linux-mips@linux-mips.org Cc: blogic@openwrt.org Cc: jogo@openwrt.org Cc: cernekee@gmail.com Patchwork: https://patchwork.linux-mips.org/patch/5650/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BMIPS: fix slave CPU booting when physical CPU is not 0Florian Fainelli2013-07-302-3/+13
| | | | | | | | | | | | | | | | The current BMIPS SMP code assumes that the slave CPU is physical and logical CPU 1, but on some systems such as BCM3368, the slave CPU is physical CPU0. Fix the code to read the physical CPU (thread ID) we are running this code on, and adjust the relocation vector address based on it. This allows bringing up the second CPU on BCM3368 for instance. Signed-off-by: Florian Fainelli <florian@openwrt.org> Cc: linux-mips@linux-mips.org Cc: cernekee@gmail.com Cc: jogo@openwrt.org Cc: blogic@openwrt.org Patchwork: https://patchwork.linux-mips.org/patch/5621/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BMIPS: do not change interrupt routing depending on boot CPUFlorian Fainelli2013-07-301-7/+1
| | | | | | | | | | | | | | | Commit 4df715aa ("MIPS: BMIPS: support booting from physical CPU other than 0") changed the interupt routing when we are booting from physical CPU 0, but the settings are actually correct if we are booting from physical CPU 0 or CPU 1. Revert that specific change. Signed-off-by: Florian Fainelli <florian@openwrt.org> Cc: linux-mips@linux-mips.org Cc: cernekee@gmail.com Cc: jogo@openwrt.org Cc: blogic@openwrt.org Patchwork: https://patchwork.linux-mips.org/patch/5622/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2013-07-192-2/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MIPS fixes from Ralf Baechle: "MIPS fixes for 3.11. Half of then is for Netlogic the remainder touches things across arch/mips. Nothing really dramatic and by rc1 standards MIPS will be in fairly good shape with this applied. Tested by building all MIPS defconfigs of which with this pull request four platforms won't build. And yes, it boots also on my favorite test systems" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: MIPS: kvm: Kconfig: Drop HAVE_KVM dependency from VIRTUALIZATION MIPS: Octeon: Fix DT pruning bug with pip ports MIPS: KVM: Mark KVM_GUEST (T&E KVM) as BROKEN_ON_SMP MIPS: tlbex: fix broken build in v3.11-rc1 MIPS: Netlogic: Add XLP PIC irqdomain MIPS: Netlogic: Fix USB block's coherent DMA mask MIPS: tlbex: Fix typo in r3000 tlb store handler MIPS: BMIPS: Fix thinko to release slave TP from reset MIPS: Delete dead invocation of exception_exit().
| * MIPS: BMIPS: Fix thinko to release slave TP from resetFlorian Fainelli2013-07-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 4df715aa ["MIPS: BMIPS: support booting from physical CPU other than 0"] introduced a thinko which will prevents slave CPUs from being released from reset on systems where we boot from TP0. The problem is that we are checking whether the slave CPU logical CPU map is 0, which is never true for systems booting from TP0, so we do not release the slave TP from reset and we are just stuck. Fix this by properly checking that the CPU we intend to boot really is the physical slave CPU (logical and physical value being 1). Signed-off-by: Florian Fainelli <florian@openwrt.org> Cc: linux-mips@linux-mips.org Cc: blogic@openwrt.org Cc: jogo@openwrt.org Cc: cernekee@gmail.com Cc: Florian Fainelli <florian@openwrt.org> Patchwork: https://patchwork.linux-mips.org/patch/5598/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Delete dead invocation of exception_exit().Ralf Baechle2013-07-171-1/+0
| | | | | | | | | | | | | | panic() doesn't return so this call was useless. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Reported-by: Alexander Sverdlin <alexander.sverdlin@nsn.com>
* | MIPS: Delete __cpuinit/__CPUINIT usage from MIPS codePaul Gortmaker2013-07-1418-54/+46
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 3747069b25e419f6b51395f48127e9812abc3596 upstream. The __cpuinit type of throwaway sections might have made sense some time ago when RAM was more constrained, but now the savings do not offset the cost and complications. For example, the fix in commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time") is a good example of the nasty type of bugs that can be created with improper use of the various __init prefixes. After a discussion on LKML[1] it was decided that cpuinit should go the way of devinit and be phased out. Once all the users are gone, we can then finally remove the macros themselves from linux/init.h. Note that some harmless section mismatch warnings may result, since notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c) and are flagged as __cpuinit -- so if we remove the __cpuinit from the arch specific callers, we will also get section mismatch warnings. As an intermediate step, we intend to turn the linux/init.h cpuinit related content into no-ops as early as possible, since that will get rid of these warnings. In any case, they are temporary and harmless. Here, we remove all the MIPS __cpuinit from C code and __CPUINIT from asm files. MIPS is interesting in this respect, because there are also uasm users hiding behind their own renamed versions of the __cpuinit macros. [1] https://lkml.org/lkml/2013/5/20/589 [ralf@linux-mips.org: Folded in Paul's followup fix.] Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5494/ Patchwork: https://patchwork.linux-mips.org/patch/5495/ Patchwork: https://patchwork.linux-mips.org/patch/5509/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2013-07-1324-136/+180
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MIPS updates from Ralf Baechle: "MIPS updates: - All the things that didn't make 3.10. - Removes the Windriver PPMC platform. Nobody will miss it. - Remove a workaround from kernel/irq/irqdomain.c which was there exclusivly for MIPS. Patch by Grant Likely. - More small improvments for the SEAD 3 platform - Improvments on the BMIPS / SMP support for the BCM63xx series. - Various cleanups of dead leftovers. - Platform support for the Cavium Octeon-based EdgeRouter Lite. Two large KVM patchsets didn't make it for this pull request because their respective authors are vacationing" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (124 commits) MIPS: Kconfig: Add missing MODULES dependency to VPE_LOADER MIPS: BCM63xx: CLK: Add dummy clk_{set,round}_rate() functions MIPS: SEAD3: Disable L2 cache on SEAD-3. MIPS: BCM63xx: Enable second core SMP on BCM6328 if available MIPS: BCM63xx: Add SMP support to prom.c MIPS: define write{b,w,l,q}_relaxed MIPS: Expose missing pci_io{map,unmap} declarations MIPS: Malta: Update GCMP detection. Revert "MIPS: make CAC_ADDR and UNCAC_ADDR account for PHYS_OFFSET" MIPS: APSP: Remove <asm/kspd.h> SSB: Kconfig: Amend SSB_EMBEDDED dependencies MIPS: microMIPS: Fix improper definition of ISA exception bit. MIPS: Don't try to decode microMIPS branch instructions where they cannot exist. MIPS: Declare emulate_load_store_microMIPS as a static function. MIPS: Fix typos and cleanup comment MIPS: Cleanup indentation and whitespace MIPS: BMIPS: support booting from physical CPU other than 0 MIPS: Only set cpu_has_mmips if SYS_SUPPORTS_MICROMIPS MIPS: GIC: Fix gic_set_affinity infinite loop MIPS: Don't save/restore OCTEON wide multiplier state on syscalls. ...
| * Merge branch '3.10-fixes' into mips-for-linux-nextRalf Baechle2013-07-126-48/+19
| |\ | | | | | | | | | | | | This that should have been fixed but weren't, way to much, intrusive and late.
| | * MIPS: Flush TLB handlers directly after writing themJonas Gorski2013-06-251-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When having enabled MIPS_PGD_C0_CONTEXT, trap_init() might call the generated tlbmiss_handler_setup_pgd before it was committed to memory, causing boot failures: trap_init() |- per_cpu_trap_init() | |- TLBMISS_HANDLER_SETUP() | |- tlbmiss_handler_setup_pgd() |- flush_tlb_handlers() To avoid this, move flush_tlb_handlers() into build_tlb_refill_handler() right after they were generated. We can do this as the cache handling is initialized just before creating the tlb handlers. This issue was introduced in 3d8bfdd0307223de678962f1c1907a7cec549136 ("MIPS: Use C0_KScratch (if present) to hold PGD pointer."). Signed-off-by: Jonas Gorski <jogo@openwrt.org> Cc: linux-mips@linux-mips.org Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Jayachandran C <jchandra@broadcom.com> Cc: David Daney <david.daney@cavium.com> Patchwork: https://patchwork.linux-mips.org/patch/5539/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * MIPS: Fix rtlx build error.Ralf Baechle2013-06-211-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CC arch/mips/kernel/rtlx.o /home/ralf/src/linux/upstream-sfr/arch/mips/kernel/rtlx.c: In function ‘file_write’: /home/ralf/src/linux/upstream-sfr/arch/mips/kernel/rtlx.c:439:23: error: unused variable ‘rt’ [-Werror=unused-variable] /home/ralf/src/linux/upstream-sfr/arch/mips/kernel/rtlx.c: In function ‘rtlx_module_init’: /home/ralf/src/linux/upstream-sfr/arch/mips/kernel/rtlx.c:523:3: error: implicit declaration of function ‘set_vi_handler’ [-Werror=implicit-function-declaration] cc1: all warnings being treated as errors Caused by 496ad9aa8ef448058e36ca7a787c61f2e63f0f54 [new helper: file_inode(file)]. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * MIPS: Fix execution hazard during watchpoint register probePaul Burton2013-06-211-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Writing a value to a WatchLo* register creates an execution hazard, so if its value is then read before that hazard is cleared then said value may be invalid. The mips_probe_watch_registers function must therefore clear the execution hazard between setting the match bits in a WatchLo* register & reading the register back in order to check which are set. This fixes intermittent incorrect watchpoint register probing on some MIPS cores such as interAptiv & proAptiv. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Acked-by: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/5474/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * MIPS: Move gas macro MAPPED_KERNEL_SETUP_TLB to IP27-specific code.Ralf Baechle2013-06-211-39/+0
| | | | | | | | | | | | | | | | | | It's IP27-specific and can only cause trouble in head.S. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: microMIPS: Fix improper definition of ISA exception bit.Steven J. Hill2013-07-012-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ISA exception bit selects whether exceptions are taken in classic or microMIPS mode. This bit is Config3.ISAOnExc and was improperly defined as bits 16 and 17 instead of just bit 16. A new function was added so that platforms could set this bit when running a kernel compiled with only microMIPS instructions. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5377/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Declare emulate_load_store_microMIPS as a static function.David Daney2013-07-011-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is only used from within a single file, it should not be globally visible. Signed-off-by: David Daney <david.daney@cavium.com> Acked-by: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5325/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Fix typos and cleanup commentTony Wu2013-07-011-3/+0
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Tony Wu <tung7970@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5535/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Cleanup indentation and whitespaceTony Wu2013-07-012-1/+1
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Tony Wu <tung7970@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5536/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: BMIPS: support booting from physical CPU other than 0Florian Fainelli2013-07-011-6/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BMIPS43xx CPUs have two hardware threads, and on some SoCs such as 3368, the bootloader has configured the system to boot from TP1 instead of the more usual TP0. Create the physical to logical CPU mapping to cope with that, do not remap the software interrupts to be cross CPUs such that we do not have to do use the logical CPU mapping further down the code, and finally, reset the slave TP1 only if booted from TP0. Signed-off-by: Jonas Gorski <jogo@openwrt.org> Signed-off-by: Florian Fainelli <florian@openwrt.org> Cc: linux-mips@linux-mips.org Cc: blogic@openwrt.org Cc: cernekee@gmail.com Patchwork: https://patchwork.linux-mips.org/patch/5553/ Patchwork: https://patchwork.linux-mips.org/patch/5556/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: GIC: Fix gic_set_affinity infinite loopTony Wu2013-07-011-8/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is an infinite loop in gic_set_affinity. When irq_set_affinity gets called on gic controller, it blocks forever. Signed-off-by: Tony Wu <tung7970@gmail.com> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5537/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Get rid of MIPS I flag and test macros.Ralf Baechle2013-07-013-12/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MIPS I is the ancestor of all MIPS ISA and architecture variants. Anything ever build in the MIPS empire is either MIPS I or at least contains MIPS I. If it's running Linux, that is. So there is little point in having cpu_has_mips_1 because it will always evaluate as true - though usually only at runtime. Thus there is no point in having the MIPS_CPU_ISA_I ISA flag, so get rid of it. Little complication: traps.c was using a test for a pure MIPS I ISA as a test for an R3000-style cp0. To deal with that, use a check for cpu_has_3kex or cpu_has_4kex instead. cpu_has_3kex is a new macro. At the moment its default implementation is !cpu_has_4kex but this may eventually change if Linux is ever going to support the oddball MIPS processors R6000 and R8000 so users of either of these macros should not make any assumptions. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/5551/
| * | MIPS: r4k,octeon,r2300: stack protector: change canary per taskGregory Fong2013-07-014-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For non-SMP, uses the new random canary value that is stored in the task struct whenever a new task is forked. Based on ARM version in df0698be14c6683606d5df2d83e3ae40f85ed0d9 and subject to the same limitations: the variable GCC expects, __stack_chk_guard, is global, so this will not work on SMP. Quoting Nicolas Pitre <nico@fluxnic.net>: "One way to overcome this GCC limitation would be to locate the __stack_chk_guard variable into a memory page of its own for each CPU, and then use TLB locking to have each CPU see its own page at the same virtual address for each of them." Signed-off-by: Gregory Fong <gregory.0xf0@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5488/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: initial stack protector supportGregory Fong2013-07-011-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implements basic stack protector support based on ARM version in c743f38013aeff58ef6252601e397b5ba281c633 , with Kconfig option, constant canary value set at boot time, and script to check if compiler actually supports stack protector. Tested by creating a kernel module that writes past end of char[]. Signed-off-by: Gregory Fong <gregory.0xf0@gmail.com> Cc: linux-mips@linux-mips.org Cc: Filippo Arcidiacono <filippo.arcidiacono@st.com> Cc: Carmelo Amoroso <carmelo.amoroso@st.com> Patchwork: https://patchwork.linux-mips.org/patch/5448/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Allow platform specific scratch registersJayachandran C2013-06-131-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | XLR/XLP COP0 scratch is register 22, sel 0-7. Add a function c0_kscratch() which returns the scratch register for the platform, and use the return value while generating TLB handlers. Setup kscratch_mask to 0xf for XLR/XLP since the config4 register does not exist. This allows the kernel to allocate scratch registers 0-3 if needed. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5445/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Allow kernel to use coprocessor 2Jayachandran C2013-06-131-10/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Kernel threads should be able to use COP2 if the platform needs it. Do not call die_if_kernel() for a coprocessor unusable exception if the exception due to COP2 usage. Instead, the default notifier for COP2 exceptions is updated to call die_if_kernel. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Cc: ddaney.cavm@gmail.com Patchwork: https://patchwork.linux-mips.org/patch/5415/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Move cop2 save/restore to switch_to()Jayachandran C2013-06-131-27/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the common code for saving and restoring platform specific COP2 registers to switch_to(). This will make supporting new platforms (like Netlogic XLP) easier. The platform specific COP2 definitions are to be specified in asm/processor.h and in asm/cop2.h. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Cc: ddaney.cavm@gmail.com Patchwork: https://patchwork.linux-mips.org/patch/5411/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: kernel: mcount.S: Drop FRAME_POINTER codepathMarkos Chandras2013-06-111-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_FRAME_POINTER is not selectable for MIPS so this codepath was never executed. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Acked-by: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5440/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Implement HAVE_CONTEXT_TRACKING.Ralf Baechle2013-06-105-14/+86
| | | | | | | | | | | | | | | | | | This enables support for CONFIG_NO_HZ_FULL. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Cleanup flags in syscall flags handlers.Ralf Baechle2013-06-104-4/+4
| | | | | | | | | | | | | | | | | | This will simplify further modifications. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: using strlcpy() instead of strncpy()Chen Gang2013-06-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Ensure strings are always '\0' terminated. Or in the next pr_info() shit may hit the fan. Signed-off-by: Chen Gang <gang.chen@asianux.com> Acked-by: John Crispin <blogic@openwrt.org> Cc: david.daney@cavium.com Cc: linux-mips@linux-mips.org Cc: Linux-Arch <linux-arch@vger.kernel.org> Cc: linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org> Patchwork: https://patchwork.linux-mips.org/patch/5331/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | mips: remove savemaxmem parameter setupZhang Yanfei2013-07-031-10/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | saved_max_pfn is used to know the amount of memory that the previous kernel used. And for powerpc, we set saved_max_pfn by passing the kernel commandline parameter "savemaxmem=". The only user of saved_max_pfn in mips is read_oldmem interface. Since we have removed read_oldmem, so we don't need this parameter anymore. Signed-off-by: Zhang Yanfei <zhangyanfei@cn.fujitsu.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: "Eric W. Biederman" <ebiederm@xmission.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Dave Hansen <dave@sr71.net> Cc: Fenghua Yu <fenghua.yu@intel.com> Cc: Heiko Carstens <heiko.carstens@de.ibm.com> Cc: Martin Schwidefsky <schwidefsky@de.ibm.com> Cc: Matt Fleming <matt.fleming@intel.com> Cc: Michael Holzheu <holzheu@linux.vnet.ibm.com> Cc: Paul Mackerras <paulus@samba.org> Cc: Tony Luck <tony.luck@intel.com> Cc: Vivek Goyal <vgoyal@redhat.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | | Merge tag 'v3.10' into sched/coreIngo Molnar2013-07-016-19/+49
|\ \ \ | | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge in a recent upstream commit: c2853c8df57f include/linux/math64.h: add div64_ul() because: 72a4cf20cb71 sched: Change cfs_rq load avg to unsigned long relies on it. [ We don't rebase sched/core for this, because the handful of followup commits after the broken commit are not behavioral changes so are unlikely to be needed during bisection. ] Signed-off-by: Ingo Molnar <mingo@kernel.org>
| * | MIPS: ftrace: Add missing CONFIG_DYNAMIC_FTRACEMarkos Chandras2013-06-101-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | arch_ftrace_update_code and ftrace_modify_all_code are only available if CONFIG_DYNAMIC_FTRACE is selected. Fixes the following build problem on MIPS randconfig: arch/mips/kernel/ftrace.c: In function 'arch_ftrace_update_code': arch/mips/kernel/ftrace.c:31:2: error: implicit declaration of function 'ftrace_modify_all_code' [-Werror=implicit-function-declaration] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Acked-by: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5435/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Alchemy: fix wait functionManuel Lauss2013-06-101-6/+7
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Only an interrupt can wake the core from 'wait', enable interrupts locally before executing 'wait'. [ralf@linux-mips.org: This leave the race between an interrupt that's setting TIF_NEED_RESCHEd and entering the WAIT status. but at least it's going to bring Alchemy back from the dead, so I'm going to apply this patch.] Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Cc: Maciej W. Rozycki <macro@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/5408/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Compat: Fix cputime_to_timeval() arguments in compat binfmt_elf.Ralf Baechle2013-06-062-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | cputime_to_timeval() takes a struct timeval *as its second argument but a struct compat_timeval * will be passed resulting in: CC arch/mips/kernel/binfmt_elfn32.o In file included from arch/mips/kernel/binfmt_elfn32.c:122:0: arch/mips/kernel/../../../fs/binfmt_elf.c: In function ‘fill_prstatus’: arch/mips/kernel/../../../fs/binfmt_elf.c:1330:3: warning: passing argument 2 of ‘cputime_to_timeval’ from incompatible pointer type [enabled by default] In file included from include/asm-generic/cputime.h:12:0, from /home/ralf/src/linux/linux-mips/arch/mips/include/asm/cputime.h:4, from include/linux/sched.h:28, from include/linux/ptrace.h:5, from include/uapi/linux/elfcore.h:7, from include/linux/elfcore.h:7, from arch/mips/kernel/binfmt_elfn32.c:55: include/asm-generic/cputime_nsecs.h:92:91: note: expected ‘struct timeval *’ but argument is of type ‘struct compat_timeval *’ In file included from arch/mips/kernel/binfmt_elfn32.c:122:0: arch/mips/kernel/../../../fs/binfmt_elf.c:1331:3: warning: passing argument 2 of ‘cputime_to_timeval’ from incompatible pointer type [enabled by default] In file included from include/asm-generic/cputime.h:12:0, from /home/ralf/src/linux/linux-mips/arch/mips/include/asm/cputime.h:4, from include/linux/sched.h:28, from include/linux/ptrace.h:5, from include/uapi/linux/elfcore.h:7, from include/linux/elfcore.h:7, from arch/mips/kernel/binfmt_elfn32.c:55: include/asm-generic/cputime_nsecs.h:92:91: note: expected ‘struct timeval *’ but argument is of type ‘struct compat_timeval *’ In file included from arch/mips/kernel/binfmt_elfn32.c:122:0: arch/mips/kernel/../../../fs/binfmt_elf.c:1336:3: warning: passing argument 2 of ‘cputime_to_timeval’ from incompatible pointer type [enabled by default] In file included from include/asm-generic/cputime.h:12:0, from /home/ralf/src/linux/linux-mips/arch/mips/include/asm/cputime.h:4, from include/linux/sched.h:28, from include/linux/ptrace.h:5, from include/uapi/linux/elfcore.h:7, from include/linux/elfcore.h:7, from arch/mips/kernel/binfmt_elfn32.c:55: include/asm-generic/cputime_nsecs.h:92:91: note: expected ‘struct timeval *’ but argument is of type ‘struct compat_timeval *’ In file included from arch/mips/kernel/binfmt_elfn32.c:122:0: arch/mips/kernel/../../../fs/binfmt_elf.c:1337:3: warning: passing argument 2 of ‘cputime_to_timeval’ from incompatible pointer type [enabled by default] In file included from include/asm-generic/cputime.h:12:0, from /home/ralf/src/linux/linux-mips/arch/mips/include/asm/cputime.h:4, from include/linux/sched.h:28, from include/linux/ptrace.h:5, from include/uapi/linux/elfcore.h:7, from include/linux/elfcore.h:7, from arch/mips/kernel/binfmt_elfn32.c:55: include/asm-generic/cputime_nsecs.h:92:91: note: expected ‘struct timeval *’ but argument is of type ‘struct compat_timeval *’ In file included from arch/mips/kernel/binfmt_elfn32.c:122:0: arch/mips/kernel/../../../fs/binfmt_elf.c:1339:2: warning: passing argument 2 of ‘cputime_to_timeval’ from incompatible pointer type [enabled by default] In file included from include/asm-generic/cputime.h:12:0, from /home/ralf/src/linux/linux-mips/arch/mips/include/asm/cputime.h:4, from include/linux/sched.h:28, from include/linux/ptrace.h:5, from include/uapi/linux/elfcore.h:7, from include/linux/elfcore.h:7, from arch/mips/kernel/binfmt_elfn32.c:55: include/asm-generic/cputime_nsecs.h:92:91: note: expected ‘struct timeval *’ but argument is of type ‘struct compat_timeval *’ In file included from arch/mips/kernel/binfmt_elfn32.c:122:0: arch/mips/kernel/../../../fs/binfmt_elf.c:1340:2: warning: passing argument 2 of ‘cputime_to_timeval’ from incompatible pointer type [enabled by default] In file included from include/asm-generic/cputime.h:12:0, from /home/ralf/src/linux/linux-mips/arch/mips/include/asm/cputime.h:4, from include/linux/sched.h:28, from include/linux/ptrace.h:5, from include/uapi/linux/elfcore.h:7, from include/linux/elfcore.h:7, from arch/mips/kernel/binfmt_elfn32.c:55: include/asm-generic/cputime_nsecs.h:92:91: note: expected ‘struct timeval *’ but argument is of type ‘struct compat_timeval *’ AS arch/mips/kernel/scall64-n32.o CC arch/mips/kernel/signal_n32.o CC arch/mips/kernel/binfmt_elfo32.o In file included from arch/mips/kernel/binfmt_elfo32.c:165:0: arch/mips/kernel/../../../fs/binfmt_elf.c: In function ‘fill_prstatus’: arch/mips/kernel/../../../fs/binfmt_elf.c:1330:3: warning: passing argument 2 of ‘cputime_to_timeval’ from incompatible pointer type [enabled by default] In file included from include/asm-generic/cputime.h:12:0, from /home/ralf/src/linux/linux-mips/arch/mips/include/asm/cputime.h:4, from include/linux/sched.h:28, from include/linux/ptrace.h:5, from include/uapi/linux/elfcore.h:7, from include/linux/elfcore.h:7, from arch/mips/kernel/binfmt_elfo32.c:78: include/asm-generic/cputime_nsecs.h:92:91: note: expected ‘struct timeval *’ but argument is of type ‘struct compat_timeval *’ In file included from arch/mips/kernel/binfmt_elfo32.c:165:0: arch/mips/kernel/../../../fs/binfmt_elf.c:1331:3: warning: passing argument 2 of ‘cputime_to_timeval’ from incompatible pointer type [enabled by default] In file included from include/asm-generic/cputime.h:12:0, from /home/ralf/src/linux/linux-mips/arch/mips/include/asm/cputime.h:4, from include/linux/sched.h:28, from include/linux/ptrace.h:5, from include/uapi/linux/elfcore.h:7, from include/linux/elfcore.h:7, from arch/mips/kernel/binfmt_elfo32.c:78: include/asm-generic/cputime_nsecs.h:92:91: note: expected ‘struct timeval *’ but argument is of type ‘struct compat_timeval *’ In file included from arch/mips/kernel/binfmt_elfo32.c:165:0: arch/mips/kernel/../../../fs/binfmt_elf.c:1336:3: warning: passing argument 2 of ‘cputime_to_timeval’ from incompatible pointer type [enabled by default] In file included from include/asm-generic/cputime.h:12:0, from /home/ralf/src/linux/linux-mips/arch/mips/include/asm/cputime.h:4, from include/linux/sched.h:28, from include/linux/ptrace.h:5, from include/uapi/linux/elfcore.h:7, from include/linux/elfcore.h:7, from arch/mips/kernel/binfmt_elfo32.c:78: include/asm-generic/cputime_nsecs.h:92:91: note: expected ‘struct timeval *’ but argument is of type ‘struct compat_timeval *’ In file included from arch/mips/kernel/binfmt_elfo32.c:165:0: arch/mips/kernel/../../../fs/binfmt_elf.c:1337:3: warning: passing argument 2 of ‘cputime_to_timeval’ from incompatible pointer type [enabled by default] In file included from include/asm-generic/cputime.h:12:0, from /home/ralf/src/linux/linux-mips/arch/mips/include/asm/cputime.h:4, from include/linux/sched.h:28, from include/linux/ptrace.h:5, from include/uapi/linux/elfcore.h:7, from include/linux/elfcore.h:7, from arch/mips/kernel/binfmt_elfo32.c:78: include/asm-generic/cputime_nsecs.h:92:91: note: expected ‘struct timeval *’ but argument is of type ‘struct compat_timeval *’ In file included from arch/mips/kernel/binfmt_elfo32.c:165:0: arch/mips/kernel/../../../fs/binfmt_elf.c:1339:2: warning: passing argument 2 of ‘cputime_to_timeval’ from incompatible pointer type [enabled by default] In file included from include/asm-generic/cputime.h:12:0, from /home/ralf/src/linux/linux-mips/arch/mips/include/asm/cputime.h:4, from include/linux/sched.h:28, from include/linux/ptrace.h:5, from include/uapi/linux/elfcore.h:7, from include/linux/elfcore.h:7, from arch/mips/kernel/binfmt_elfo32.c:78: include/asm-generic/cputime_nsecs.h:92:91: note: expected ‘struct timeval *’ but argument is of type ‘struct compat_timeval *’ In file included from arch/mips/kernel/binfmt_elfo32.c:165:0: arch/mips/kernel/../../../fs/binfmt_elf.c:1340:2: warning: passing argument 2 of ‘cputime_to_timeval’ from incompatible pointer type [enabled by default] In file included from include/asm-generic/cputime.h:12:0, from /home/ralf/src/linux/linux-mips/arch/mips/include/asm/cputime.h:4, from include/linux/sched.h:28, from include/linux/ptrace.h:5, from include/uapi/linux/elfcore.h:7, from include/linux/elfcore.h:7, from arch/mips/kernel/binfmt_elfo32.c:78: include/asm-generic/cputime_nsecs.h:92:91: note: expected ‘struct timeval *’ but argument is of type ‘struct compat_timeval *’ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: rtlx: Fix implicit declaration of function set_vi_handler()Yoichi Yuasa2013-06-061-0/+1
| | | | | | | | | | | | | | | | | | | | arch/mips/kernel/rtlx.c: In function 'rtlx_module_init': arch/mips/kernel/rtlx.c:523:3: error: implicit declaration of function 'set_vi_handler' [-Werror=implicit-function-declaration] Signed-off-by: Yoichi Yuasa <yuasa@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5340/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Trap exception handling fixesMaciej W. Rozycki2013-05-231-13/+15
| | | | | | | | | | | | | | | | | | | | | | 2a0b24f56c2492b932f1aed617ae80fb23500d21 broke Trap exception handling in the standard MIPS mode. Additionally the microMIPS-mode trap code mask is wrong, as it's a 4-bit field. Here's a fix. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5309/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | sched: Rename sched.c as sched/core.c in comments and DocumentationViresh Kumar2013-06-192-4/+5
|/ | | | | | | | | | | | | | | | | Most of the stuff from kernel/sched.c was moved to kernel/sched/core.c long time back and the comments/Documentation never got updated. I figured it out when I was going through sched-domains.txt and so thought of fixing it globally. I haven't crossed check if the stuff that is referenced in sched/core.c by all these files is still present and hasn't changed as that wasn't the motive behind this patch. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Peter Zijlstra <peterz@infradead.org> Link: http://lkml.kernel.org/r/cdff76a265326ab8d71922a1db5be599f20aad45.1370329560.git.viresh.kumar@linaro.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
* MIPS: N64: Wire getdents64(2)Aron Xu2013-05-221-0/+1
| | | | | | | | | | | | | | | | | | | As a relatively new ABI, N64 only had getdents syscall while other modern architectures have getdents64. This was noticed when Python 3.3 shifted to the latter one for aarch64. [ralf@linux-mips.org: The history of getdents64 is a little complicated. Commit 1a1d77dd589de5a567fa95e36aa6999c704ceca4 [Merge with 2.4.0-test7.] added N64 getdents(2) to arch/mips64/kernel/scall_64.S as syscall 5213, then dropped again in 578720675c44e54e8aa7c68f6dce59ed37ce3d3b [Overhaul of the 64-bit syscall interface. Now heritage free.] for 2.5.18 in 2002.] Signed-off-by: Aron Xu <aron@debian.org> Acked-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5285/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* kprobes/mips: Fix to check double free of insn slotMasami Hiramatsu2013-05-221-1/+4
| | | | | | | | | | | | | | | | | | Fix to check double free of insn_slot at arch_remove_kprobe as other arches do. Signed-off-by: Masami Hiramatsu <masami.hiramatsu.pt@hitachi.com> Cc: David Daney <ddaney@caviumnetworks.com> Cc: Maneesh Soni <manesoni@cisco.com> Cc: Victor Kamensky <kamensky@cisco.com> Cc: linux-mips@linux-mips.org Cc: Ingo Molnar <mingo@redhat.com> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: yrl.pp-manager.tt@hitachi.com Cc: systemtap@sourceware.org Patchwork: https://patchwork.linux-mips.org/patch/5293/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Idle: Break r4k_wait into two functions and fix it.Ralf Baechle2013-05-222-3/+9
| | | | | | | | | | | | local_irq_enable() may expand into very different code, so it rather should stay in C. Also this keeps the assembler code size constant which keeps the rollback code simple. So it's best to split r4k_wait into two parts, one C and one assembler. Finally add the local_irq_enable() to r4k_wait to ensure the WAIT instruction in __r4k_wait() will work properly. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Idle: Do address fiddlery in helper functions.Ralf Baechle2013-05-222-6/+4
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Idle: Consolidate all declarations in <asm/idle.h>.Ralf Baechle2013-05-225-4/+5
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Idle: Don't call local_irq_disable() in cpu_wait() implementations.Ralf Baechle2013-05-221-3/+0
| | | | | | The generic idle loop has already disabled interrupts so this is redundant. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Idle: Re-enable irqs at the end of r3081, au1k and loongson2 cpu_wait.Ralf Baechle2013-05-221-0/+2
| | | | | | | | | | Without this, the WARN_ON_ONCE(irqs_disabled()); in the idle loop will be triggered. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Idle: Make call of function pointer readable.Ralf Baechle2013-05-221-1/+1
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Idle: Consistently reformat inline assembler.Ralf Baechle2013-05-221-18/+21
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Idle: cleaup SMTC idle hook as per Linux coding style.Ralf Baechle2013-05-221-2/+7
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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