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* [MIPS] Fix shadow register support.Ralf Baechle2007-11-151-0/+5
| | | | | | | | | | | | | Shadow register support would not possibly have worked on multicore systems. The support code for it was also depending not on MIPS R2 but VSMP or SMTC kernels even though it makes perfect sense with UP kernels. SR sets are a scarce resource and the expected usage pattern is that users actually hardcode the register set numbers in their code. So fix the allocator by ditching it. Move the remaining CPU probe bits into the generic CPU probe. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Add BUG_ON assertion for attempt to run kernel on the wrong CPU type.Franck Bui-Huu2007-10-111-0/+8
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Make facility to convert CPU types to strings generally available.Ralf Baechle2007-10-111-2/+91
| | | | | | | So far /proc/cpuinfo has been the only user but human readable processor name are more useful than that for proc. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.Ralf Baechle2007-10-111-8/+0
| | | | | | | | | | | It may not be perfect yet but the SB1 code is badly borken and has horrible performance issues. Downside: This seriously breaks support for pass 1 parts of the BCM1250 where indexed cacheops don't work quite reliable but I seem to be the last one on the planet with a pass 1 part anyway. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Add support for BCM47XX CPUs.Aurelien Jarno2007-10-111-0/+20
| | | | | | | | | | | | | | Note that the BCM4710 does not support the wait instruction, this is not a mistake in the code. It originally comes from the OpenWrt patches. Cc: Michael Buesch <mb@bu3sch.de> Cc: Felix Fietkau <nbd@openwrt.org> Cc: Florian Schirmer <jolt@tuxbox.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] 20Kc: Disable use of WAIT instruction.Ralf Baechle2007-09-141-1/+8
| | | | | | | | Another issue with 20Kc's WAIT, waiting for more details. With the 2.6.23 release immindent simply disable the use of WAIT instead of a more fancy workaround. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Workaround for RM7000 WAIT instruction aka erratum 38Ralf Baechle2007-07-201-1/+25
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] PMC MSP71xx mips commonMarc St-Jean2007-07-101-0/+20
| | | | | | | Patch to add mips common support for the PMC-Sierra MSP71xx devices. Signed-off-by: Marc St-Jean <Marc_St-Jean@pmc-sierra.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] define Hit_Invalidate_I to Index_Invalidate_I for loongson2Fuxin Zhang2007-07-101-0/+8
| | | | | Signed-off-by: Fuxin Zhang <zhangfx@lemote.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Enable support for the userlocal hardware registerRalf Baechle2007-07-101-0/+2
| | | | | | | | Which will cut down the cost of RDHWR $29 which is used to obtain the TLS pointer and so far being emulated in software down to a single cycle operation. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix scheduling latency issue on 24K, 34K and 74K coresRalf Baechle2007-07-061-2/+13
| | | | | | | | | | | | | | | | | | | | | | | The idle loop goes to sleep using the WAIT instruction if !need_resched(). This has is suffering from from a race condition that if if just after need_resched has returned 0 an interrupt might set TIF_NEED_RESCHED but we've just completed the test so go to sleep anyway. This would be trivial to fix by just disabling interrupts during that sequence as in: local_irq_disable(); if (!need_resched()) __asm__("wait"); local_irq_enable(); but the processor architecture leaves it undefined if a processor calling WAIT with interrupts disabled will ever restart its pipeline and indeed some processors have made use of the freedom provided by the architecture definition. This has been resolved and the Config7.WII bit indicates that the use of WAIT is safe on 24K, 24KE and 34K cores. It also is safe on 74K starting revision 2.1.0 so enable the use of WAIT with interrupts disabled for 74K based on a c0_prid of at least that. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] 20K: Handle WAIT related bugs according to errata informationRalf Baechle2007-06-261-1/+11
| | | | | | | | We used to avoid the WAIT entirely on the 20K but really only need to do this on early revs of the 20K. Without this a 20K was a bit of a power hog. Well, in the lower power power hog category ;-) Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Make some __setup functions staticAtsushi Nemoto2007-02-201-1/+1
| | | | | | | | This fixes some sparse warnings. ("warning: symbol 'foo' was not declared. Should it be static?") Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Include <asm/bugs> to for declaration of check_bugs32.Ralf Baechle2007-02-181-0/+1
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Whitespace cleanups.Ralf Baechle2007-02-061-1/+1
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Don't print presence of WAIT instruction on bootup.Ralf Baechle2006-11-301-16/+3
| | | | | | Not useful and quite a big of noise on bootup of large systems. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix RM9000 wait instruction detection.Ralf Baechle2006-10-091-1/+8
| | | | | | | | Only revisions < 4.0 don't have a functional wait instruction. From Thomas Koeller (Thomas.Koeller@baslerweb.com). Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Reduce race between cpu_wait() and need_resched() checkingAtsushi Nemoto2006-09-271-17/+45
| | | | | | | | | | | | | If a thread became runnable between need_resched() and the WAIT instruction, switching to the thread will delay until a next interrupt. Some CPUs can execute the WAIT instruction with interrupt disabled, so we can get rid of this race on them (at least UP case). Original Patch by Atsushi with fixing up for MIPS Technology's cores by Ralf based on feedback from the RTL designers. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Save 2k text size in cpu-probeThiemo Seufer2006-07-131-1/+1
| | | | | | | | The appended patch drops the inline for decode_configs, this saves about 2k of text size. Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Uses MIPS_CONF_AR instead of magic constants.Thiemo Seufer2006-07-131-2/+2
| | | | | Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Remove obsolete #include <linux/config.h>Jörn Engel2006-06-301-1/+0
| | | | | Signed-off-by: Jörn Engel <joern@wohnheim.fh-wedel.de> Signed-off-by: Adrian Bunk <bunk@stusta.de>
* [MIPS] MIPS32/MIPS64 secondary cache managementChris Dearman2006-06-291-2/+0
| | | | | Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SB1: Only pass1 FPUs are broken beyond recovery.Ralf Baechle2006-06-061-1/+1
| | | | | | | The wrong revision number in the check was forcing a fallback to FPU emulation for all SB1 cores in 2.6. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Treat R14000 like R10000.Kumba2006-06-011-0/+9
| | | | | Signed-off-by: Joshua Kinard <kumba@gentoo.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix detection and handling of the 74K processor.Chris Dearman2006-06-011-0/+4
| | | | | | | | Nothing exciting; Linux just didn't know it yet so this is most adding a value to a case statement. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] War on whitespace: cleanup initial spaces followed by tabs.Ralf Baechle2006-03-211-3/+3
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Get rid of CONFIG_SB1_PASS_1_WORKAROUNDS #ifdef crapola.Ralf Baechle2006-02-071-4/+3
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Introduce machinery for testing for MIPSxxR1/2.Ralf Baechle2006-01-101-5/+30
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Rename MIPS_CPU_ISA_M{32,64} -> MIPS_CPU_ISA_M{32,64}R1.Ralf Baechle2006-01-101-6/+6
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] R10000 and R12000 need to set MIPS_CPU_4K_CACHE ...Ralf Baechle2005-12-011-2/+2
| | | | | | ... because they have R4000-style caches. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Add support for SB1A CPU.Andrew Isaacson2005-10-291-0/+3
| | | | | Signed-Off-By: Andy Isaacson <adi@broadcom.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Sibyte fixesAndrew Isaacson2005-10-291-1/+1
| | | | | | | Fix typo in cpu_probe_sibyte. Signed-Off-By: Andy Isaacson <adi@broadcom.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Detect 4KSD and treat it like 4KSc.Ralf Baechle2005-10-291-0/+1
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Cleanup the mess in cpu_cache_init.Ralf Baechle2005-10-291-7/+18
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* R4600 has 32 FPRs.Thiemo Seufer2005-10-291-1/+2
| | | | | Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Philips PNX8550 support: MIPS32-like core with 2 Trimedias on it.Pete Popov2005-10-291-0/+19
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Detect the MIPS R2 vectored interrupt, external interrupt controllerRalf Baechle2005-10-291-0/+6
| | | | | | options and the precense of the MT ASE. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* New kernel option nowait allows disabling the use of the wait instruction.Ralf Baechle2005-10-291-0/+16
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Detect the 34K.Ralf Baechle2005-10-291-0/+5
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* For MIPS32/MIPS64 cp0.config.mt == 1 implies a standard (R4k-style)Maciej W. Rozycki2005-10-291-5/+1
| | | | | | TLB, so no need to set it separately for each implementation. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Support the MIPS32 / MIPS64 DSP ASE.Ralf Baechle2005-10-291-0/+3
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* 64-bit fixes for Alchemy code ;)Ralf Baechle2005-10-291-6/+5
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* No point in checking cpu_has_tlb before we've computed the CPU options.Ralf Baechle2005-10-291-4/+4
| | | | | | | | | | So for now we just unconditionally set the option - Linux wouldn't work without a TLB anyway. Setting MIPS_CPU_4KTLB was missing for Alchemy and Sandcraft, add that back. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Cleanup decoding of MIPSxx config registers.Ralf Baechle2005-10-291-43/+98
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Fix BogoMIPS display on UP and some minor cosmetical things.Ralf Baechle2005-10-291-1/+0
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Detect the 4KEcR2 and for now detect handle it like the 4KEc.Ralf Baechle2005-10-291-0/+4
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Fixed buglet with previous patch that broke non au1x builds.Pete Popov2005-10-291-9/+7
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Remove CONFIG_PM dependency from au1x wait in cpu_probe.Pete Popov2005-10-291-24/+19
| | | | | | Additional work necessary to completely remove that config option. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Base Au1200 2.6 support.Pete Popov2005-10-291-0/+5
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [PATCH] more vr4181 removalAdrian Bunk2005-09-051-6/+0
| | | | | | | Signed-off-by: Adrian Bunk <bunk@stusta.de> Cc: Yoichi Yuasa <yuasa@hh.iij4u.or.jp> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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