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* MIPS: ath79: Switch to the clkdev frameworkGabor Juhos2013-09-031-71/+52
| | | | | | | | | | | | | | | | | | | | | | | | | The ath79 code uses static clock devices and provides its own clk_{get,put} implementations. Change the code to use dynamically allocated clock devices and register the clocks within the clkdev framework. Additionally, remove the local clk_{get,put} implementation. The clkdev framework has a common implementation of those. Also move the call of ath79_clock_init() from plat_mem_init() to plat_time_init(). Otherwise it would not be possible to use memory allocation functions from ath79clock_init() becasuse the memory subsystem is not yet initialized when plat_mem_init() runs. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5780/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ath79: Use local variables for clock ratesGabor Juhos2013-09-031-52/+106
| | | | | | | | | | | | | | Use local variables for ref, cpu, ddr and ahb rates in SoC specific clock init functions. The patch has no functional changes, it is an interim change in preparation of the next patch. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5781/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ath79: Use ath79_get_sys_clk_rate to get basic clock ratesGabor Juhos2013-09-031-11/+0
| | | | | | | | | | | | | | | | | | | | Instead of accessing the rate field of the static clock devices directly, use the recently introduced helper function to get the rate of the basic clocks. The static ath79_{ahb,cpu,ddr,ref}_clk variables will be removed by a subsequent patch. The actual change is in preparation of that. Also move the clock frequency printing code into the plat_time_init function. We are getting the cpu clock rate there already so we can save an extra call of the helper. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5782/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ath79: Use a helper function to get system clock ratesGabor Juhos2013-09-031-0/+16
| | | | | | | | | | | | The ath79 platform uses similar code to get the rate of various clocks during init. Separate the similar code into a new helper function and use that to avoid code duplication. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5778/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ath79: Use local ref clock rate in ar934x_get_pll_freqGabor Juhos2013-09-031-2/+2
| | | | | | | | | | | The reference clock rate is passed in the first argument of the function. Use that instead of the rate of the global ath79_ref_clk variable. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5779/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ath79: Fix ar933x watchdog clockFelix Fietkau2013-09-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The watchdog device on the AR933x is connected to the AHB clock, however the current code uses the reference clock. Due to the wrong rate, the watchdog driver can't calculate correct register values for a given timeout value and the watchdog unexpectedly restarts the system. The code uses the wrong value since the initial commit 04225e1d227c8e68d685936ecf42ac175fec0e54 (MIPS: ath79: add AR933X specific clock init) The patch fixes the code to use the correct clock rate to avoid the problem. Cc: stable@vger.kernel.org Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/5777/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge branch 'mips-next-3.9' of ↵Ralf Baechle2013-02-211-0/+78
|\ | | | | | | git://git.linux-mips.org/pub/scm/john/linux-john into mips-for-linux-next
| * MIPS: ath79: add clock setup code for the QCA955X SoCsGabor Juhos2013-02-191-0/+78
| | | | | | | | | | | | | | | | | | | | | | | | The patch adds code to get various clock frequencies from the PLLs used in the QCA955x SoCs. Cc: Rodriguez, Luis <rodrigue@qca.qualcomm.com> Cc: Giori, Kathy <kgiori@qca.qualcomm.com> Cc: QCA Linux Team <qca-linux-team@qca.qualcomm.com> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4945/ Signed-off-by: John Crispin <blogic@openwrt.org>
* | MIPS: Whitespace cleanup.Ralf Baechle2013-02-011-1/+1
|/ | | | | | | | Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ath79: Fix CPU/DDR frequency calculation for SRIF PLLsGabor Juhos2012-10-011-28/+81
| | | | | | | | | | | | | | | | | Besides the CPU and DDR PLLs, the CPU and DDR frequencies can be derived from other PLLs in the SRIF block on the AR934x SoCs. The current code does not checks if the SRIF PLLs are used and this can lead to incorrectly calculated CPU/DDR frequencies. Fix it by calculating the frequencies from SRIF PLLs if those are used on a given board. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: <stable@vger.kernel.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/4324/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ath79: use correct fractional dividers for {CPU,DDR}_PLL on AR934xGabor Juhos2012-10-011-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | The current dividers in the code are wrong and this leads to broken CPU frequency calculation on boards where the fractional part is used. For example, if the SoC is running from a 40MHz reference clock, refdiv=1, nint=14, outdiv=0 and nfrac=31 the real frequency is 579.375MHz but the current code calculates 569.687MHz instead. Because the system time is indirectly related to the CPU frequency the broken computation causes drift in the system time. The correct divider is 2^6 for the CPU PLL and 2^10 for the DDR PLL. Use the correct values to fix the issue. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: stable@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/4305/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ath79: add clock initialization code for AR934XGabor Juhos2012-05-151-0/+81
| | | | | | | | | Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com> Cc: linux-mips@linux-mips.org Cc: mcgrof@infradead.org Patchwork: https://patchwork.linux-mips.org/patch/3507/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ath79: add AR933X specific clock initGabor Juhos2011-12-071-0/+55
| | | | | | | | | Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Cc: Kathy Giori <kgiori@qca.qualcomm.com> Cc: "Luis R. Rodriguez" <rodrigue@qca.qualcomm.com> Patchwork: https://patchwork.linux-mips.org/patch/2522/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add initial support for the Atheros AR71XX/AR724X/AR931X SoCsGabor Juhos2011-01-181-0/+183
This patch adds initial support for various Atheros SoCs based on the MIPS 24Kc core. The following models are supported at the moment: - AR7130 - AR7141 - AR7161 - AR9130 - AR9132 - AR7240 - AR7241 - AR7242 The current patch contains minimal support only, but the resulting kernel can boot into user-space with using of an initramfs image on various boards which are using these SoCs. Support for more built-in devices and individual boards will be implemented in further patches. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: Imre Kaloz <kaloz@openwrt.org> Cc: linux-mips@linux-mips.org Cc: Luis R. Rodriguez <lrodriguez@atheros.com> Cc: Cliff Holden <Cliff.Holden@Atheros.com> Cc: Kathy Giori <Kathy.Giori@Atheros.com> Patchwork: https://patchwork.linux-mips.org/patch/1947/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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