| Commit message (Collapse) | Author | Age | Files | Lines |
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The value stored into the SDRAMC LPR register should be the current
value of the register with the Self-refresh value set in the lower bit
field.
The bug involved only the Self-refresh value being written to the
register, thus over writing any low-power ram settings.
Signed-off-by: Humphrey Bucknell <hbucknell@saitek.com>
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
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Update all avr32-specific files to use the new platform-specific header
locations. Drivers shared with ARM are left alone for now.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
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Implement Standby support. In this mode, we'll suspend all drivers,
put the SDRAM in self-refresh mode and switch off the HSB bus
("frozen" mode.)
Implement Suspend-to-mem support. In this mode, we suspend all
drivers, put the SDRAM into self-refresh mode and switch off all
internal clocks except the 32 kHz oscillator ("stop" mode.)
The lowest-level suspend code runs from a small portion of SRAM
allocated at startup time. This gets rid of a small potential race
with the SDRAM where we might try to enter self-refresh mode in the
middle of an icache burst. We also relocate all interrupt and
exception handlers to SRAM during the small window when we enter and
exit the low-power modes.
We don't need to do any special tricks to start and stop the PLL. The
main clock is automatically gated by hardware until the PLL is stable.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
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Create a new file, pm-at32ap700x.S, in mach-at32ap and move the CPU
idle sleep code there. Make it possible to disable the sleep code.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
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