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* ARM: 5686/1: at91: Correct AC97 reset line in at91sam9263ek boardNicolas Ferre2009-09-061-1/+1
| | | | | | | | Board code was wrongly setting up the reset pin for AC97 on at91sam9263ek. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Andrew Victor <linux@maxim.org.za> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 5640/1: This patch modifies the support of AC97 on the at91sam9263 ek boardsedji gaouaou2009-09-063-12/+10
| | | | | | | | | This patch modifies the support of AC97 on the at91sam9263 ek board, so it would share the code with AVR32. Plus it removes a typo in at91sam9263_devices.c. Signed-off-by: Sedji Gaouaou <sedji.gaouaou@atmel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 5632/1: Board-specific data for IDE support on afeb9260Sergey Matyukevich2009-08-011-0/+12
| | | | | | | | | | | | This patch adds board-specific data for IDE support on afeb9260. Depends on #5631/1 Tested-by: Sergey Matyukevich <geomatsi@gmail.com> Signed-off-by: Sergey Matyukevich <geomatsi@gmail.com> Acked-by: Andrew Victor <linux@maxim.org.za> Acked-by: Sergey Lapin <slapin@ossfans.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 5631/1: Platform data for CF/IDE support in AT91SAM9260Sergey Matyukevich2009-08-011-0/+116
| | | | | | | | | | This patch adds platform data for CF/IDE support and SMC init code for AT91SAM9260 SoC. Tested-by: Sergey Matyukevich <geomatsi@gmail.com> Signed-off-by: Sergey Matyukevich <geomatsi@gmail.com> Acked-by: Andrew Victor <linux@maxim.org.za> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 5630/1: Add support for Eukrea's CPUAT91Eric Bénard2009-07-304-0/+1509
| | | | | | | | | CPUAT91 is based on Atmel's AT91RM9200 with up to 16MB Strataflash, up to 128MB SDRAM and an ethernet PHY in RMII mode. Signed-off-by: Eric Benard <ebenard@eukrea.com> Acked-by: Andrew Victor <linux@maxim.org.za> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 5629/1: Add support for Eukrea's CPU9260 & CPU9G20Eric Bénard2009-07-305-0/+3067
| | | | | | | | | | CPU9260 and CPU9G20 share the same PCB populated with either Atmel's AT91SAM9260B or AT91SAM9G20B with up to 64MB Strataflash, up to 128MB SDRAM, up to 2GB NAND and an ethernet PHY in RMII mode. Signed-off-by: Eric Benard <eric@eukrea.com> Acked-by: Andrew Victor <linux@maxim.org.za> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 5622/1: at91: at91sam9g45 headers: DMA peripheral identifiersNicolas Ferre2009-07-251-0/+17
| | | | | | | | | It adds DMA peripheral identifiers for hardware handshaking interface. It will be used in platform code. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Andrew Victor <linux@maxim.org.za> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 5596/1: at91sam9g20-ek: Register WM8731 in board fileMark Brown2009-07-091-0/+1
| | | | | | | | | | The WM8731 driver has been updated to allow registration via normal device model methods rather than from within the ASoC driver probe so update the AT91SAM9G20-EK to make use of this. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: Andrew Victor <linux@maxim.org.za> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 5570/1: at91: Support for at91sam9g10: core chip & board supportNicolas Ferre2009-07-025-4/+62
| | | | | | | | | | | | | | | From: Hong Xu <hong.xu@atmel.com> Here are the modification to at91sam9261 files dedicated to the support of at91sam9g10. This direction has been adopted to minimize code duplication. All at91sam9261 drivers are enabled in _devices and board- files. Modificaton to peripherals that support at91sam9g10 will be added in future patches. Signed-off-by: Hong Xu <hong.xu@atmel.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Andrew Victor <linux@maxim.org.za> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 5568/1: at91: Basic support for at91sam9g10: header filesNicolas Ferre2009-07-024-1/+16
| | | | | | | | | | | | | | From: Hong Xu <hong.xu@atmel.com> AT91sam9g10 is an ARM 926ej-s SOC. It is an evolution of the at91sam9261 with a faster clock speed: 266/133MHz. Here is the basic header file support for this product. Signed-off-by: Hong Xu <hong.xu@atmel.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Andrew Victor <linux@maxim.org.za> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 5567/1: at91: Support for at91sam9g10: clocks managementNicolas Ferre2009-07-021-2/+4
| | | | | | | | | | | | From: Hong Xu <hong.xu@atmel.com> Add the at91sam9g10 support to the AT91 generic clock file. It takes advantage of the management by functionalities of those PLLs and clocks. Signed-off-by: Hong Xu <hong.xu@atmel.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Andrew Victor <linux@maxim.org.za> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 5572/1: at91: Support for at91sam9g45 series: core chip & board supportNicolas Ferre2009-06-278-3/+2020
| | | | | | | | | | | | | | | | | | | | | | | | | Here are the at91 specific files dedicated to the at91sam9g45 series. They mimic the traditional at91 way of managing chips & boards. The first board that embeds at91sam9g45 chip is the AT91SAM9G45-EKES. In the future, the main board for this 9g45 series will be the AT91SAM9M10G45-EK (I choose this last name for the board file). Simple drivers are enabled in _devices and board- files. Newer peripheral support will be added in future patches. Incuded peripherals support (for now): - USART - SPI - Ethernet - NAND flash - LCD - gpio/joystick/buttons - leds and pwm Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Andrew Victor <linux@maxim.org.za> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 5571/1: at91: Basic support for at91sam9g45 series: header files.Nicolas Ferre2009-06-275-0/+314
| | | | | | | | | | | | AT91sam9g45 series is an ARM 926ej-s SOC family clocked at 400/133MHz. It embedds USB high speed host and device, LCD, DDR2 RAM, and a full set of peripherals. Here is the basic header file support for this product series. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Andrew Victor <linux@maxim.org.za> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 5569/1: at91: Support for at91sam9g45: clocks managementNicolas Ferre2009-06-271-10/+52
| | | | | | | | | | | Add the at91sam9g45 series support to the AT91 generic clock file. This takes care of the particularities of the PMC for this series. It also takes advantage of the management by functionalities of those PLLs and clocks. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Andrew Victor <linux@maxim.org.za> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 5566/1: Remove at91_gpiolib_requestRyan Mallon2009-06-271-15/+0
| | | | | | | | | | | Remove at91_gpiolib_request. It returns -EPERM if a request pin is not in GPIO mode, however we want to be able to gpio_request alternative function pins to reserve them, and in some cases we need to be able to use the gpiolib functions on alternative function pins. Signed-off-by: Ryan Mallon <ryan@bluewatersys.com> Acked-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 5564/1: at91: add gpio button and leds support for at91sam9rlekNicolas Ferre2009-06-271-0/+79
| | | | | | | | | | This adds input keyboard gpio support on at91sam9rlek board. It adds button 1 and 2 (left and right click). It also adds gpio leds ds1, ds2 and ds3. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Andrew Victor <linux@maxim.org.za> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge git://git.infradead.org/mtd-2.6Linus Torvalds2009-06-222-14/+25
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * git://git.infradead.org/mtd-2.6: (63 commits) mtd: OneNAND: Allow setting of boundary information when built as module jffs2: leaking jffs2_summary in function jffs2_scan_medium mtd: nand: Fix memory leak on txx9ndfmc probe failure. mtd: orion_nand: use burst reads with double word accesses mtd/nand: s3c6400 support for s3c2410 driver [MTD] [NAND] S3C2410: Use DIV_ROUND_UP [MTD] [NAND] S3C2410: Deal with unaligned lengths in S3C2440 buffer read/write [MTD] [NAND] S3C2410: Allow the machine code to get the BBT table from NAND [MTD] [NAND] S3C2410: Added a kerneldoc for s3c2410_nand_set mtd: physmap_of: Add multiple regions and concatenation support mtd: nand: max_retries off by one in mxc_nand mtd: nand: s3c2410_nand_setrate(): use correct macros for 2412/2440 mtd: onenand: add bbt_wait & unlock_all as replaceable for some platform mtd: Flex-OneNAND support mtd: nand: add OMAP2/OMAP3 NAND driver mtd: maps: Blackfin async: fix memory leaks in probe/remove funcs mtd: uclinux: mark local stuff static mtd: uclinux: do not allow to be built as a module mtd: uclinux: allow systems to override map addr/size mtd: blackfin NFC: fix hang when using NAND on BF527-EZKITs ...
| * Merge branch 'next-mtd' of git://aeryn.fluff.org.uk/bjdooks/linuxDavid Woodhouse2009-06-0835-147/+195
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| | * [MTD] [NAND] S3C2410: Allow the machine code to get the BBT table from NANDMichel Pollet2009-06-081-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Added a flag to allow the machine code to tell the NAND subsystem that it should try to pickup a BBT from the flash, and also skip the NAND full scan at startup. Signed-off-by: Michel Pollet <buserror@gmail.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
| | * [MTD] [NAND] S3C2410: Added a kerneldoc for s3c2410_nand_setMichel Pollet2009-06-081-10/+12
| | | | | | | | | | | | | | | | | | | | | | | | Converted the old comnent to kerneldoc. Signed-off-by: Michel Pollet <buserror@gmail.com> [ben-linux@fluff.org: updated subject, spello fix] Signed-off-by: Ben Dooks <ben-linux@fluff.org>
| | * [MTD] [NAND] S3C2410: Small colon cleanupNelson Castillo2009-05-301-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | checkpatch would complain with "disable_ecc : 1". Signed-off-by: Nelson Castillo <arhuaco@freaks-unidos.net> [ben-linux@fluff.org: subject cleanup] Signed-off-by: Ben Dooks <ben-linux@fluff.org>
| * | mtd: nand: davinci_nand, 4-bit ECC for smallpageDavid Brownell2009-06-051-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Minimal support for the 4-bit ECC engine found on DM355, DM365, DA830/OMAP-L137, and similar recent DaVinci-family chips. This is limited to small-page flash for now; there are some page layout issues for large page chips. Note that most boards using this engine (like the DM355 EVM) include 2GiB large page chips. Sanity tested on DM355 EVM after swapping the socketed NAND for a small-page one. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* | | Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2009-06-2253-150/+5226
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (49 commits) [ARM] idle: clean up pm_idle calling, obey hlt_counter [ARM] S3C: Fix gpio-config off-by-one bug [ARM] S3C64XX: add to_irq() support for EINT() GPIO [ARM] S3C64XX: clock.c: fix typo in usb-host clock ctrlbit [ARM] S3C64XX: fix HCLK gate defines [ARM] Update mach-types [ARM] wire up rt_tgsigqueueinfo and perf_counter_open OMAP2 clock/powerdomain: off by 1 error in loop timeout comparisons OMAP3 SDRC: set FIXEDDELAY when disabling SDRC DLL OMAP3: Add support for DPLL3 divisor values higher than 2 OMAP3 SRAM: convert SRAM code to use macros rather than magic numbers OMAP3 SRAM: add more comments on the SRAM code OMAP3 clock/SDRC: program SDRC_MR register during SDRC clock change OMAP3 clock: add a short delay when lowering CORE clk rate OMAP3 clock: initialize SDRC timings at kernel start OMAP3 clock: remove wait for DPLL3 M2 clock to stabilize [ARM] Add old Feroceon support to compressed/head.S [ARM] 5559/1: Limit the stack unwinding caused by a kthread exit [ARM] 5558/1: Add extra checks to ARM unwinder to avoid tracing corrupt stacks [ARM] 5557/1: Discard some ARM.ex*.*exit.text sections when !HOTPLUG or !HOTPLUG_CPU ...
| * | | [ARM] idle: clean up pm_idle calling, obey hlt_counterRussell King2009-06-221-26/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pm_idle is used by infrastructure (eg, cpuidle) which expects architectures to call it in a certain way. Arrange for ARM to follow x86's lead on this and call pm_idle() with interrupts already disabled. However, we expect pm_idle() to enable interrupts before it returns. Also, OMAP wants to be able to disable hlt-ing, so allow hlt_counter to prevent all calls to pm_idle. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | Merge branch 'next-s3c' of git://aeryn.fluff.org.uk/bjdooks/linux into develRussell King2009-06-224-7/+13
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| | * | | [ARM] S3C: Fix gpio-config off-by-one bugMarek Szyprowski2009-06-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix gpio-config off-by-one bug. Without this patch, touching GPA0 pin on S3C64XX platform causes kernel oops. Reviewed-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
| | * | | [ARM] S3C64XX: add to_irq() support for EINT() GPIOMarek Szyprowski2009-06-221-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | N group Add to_irq() function to onvert gpio to irq for external interrupt group (GPN). Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
| | * | | [ARM] S3C64XX: clock.c: fix typo in usb-host clock ctrlbitPeter Korsgaard2009-06-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The usb-host clock was using the wrong define (the SCLK enable for the usb-host-bus) to change the HCLK register instead of the HCLK_UHOST bit. Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
| | * | | [ARM] S3C64XX: fix HCLK gate definesPeter Korsgaard2009-06-221-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A few typos seems to have sneaked into the HCLK gate defines, causing the usb host clock to not get enabled. Fix them according to the reference manual and throw in the 3d accel bit for good measure. Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
| * | | | [ARM] Update mach-typesRussell King2009-06-201-2/+37
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | [ARM] wire up rt_tgsigqueueinfo and perf_counter_openRussell King2009-06-202-0/+4
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | Merge branch 'omap-clock-for-next' of git://git.pwsan.com/linux-2.6 into develRussell King2009-06-207-62/+163
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| | * | | | OMAP2 clock/powerdomain: off by 1 error in loop timeout comparisonsRoel Kluin2009-06-192-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | with while (i++ < MAX_CLOCK_ENABLE_WAIT); i can reach MAX_CLOCK_ENABLE_WAIT + 1 after the loop, so if (i == MAX_CLOCK_ENABLE_WAIT) that's still success. Signed-off-by: Roel Kluin <roel.kluin@gmail.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | * | | | OMAP3 SDRC: set FIXEDDELAY when disabling SDRC DLLPaul Walmsley2009-06-191-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Correspondence with the TI OMAP hardware team indicates that SDRC_DLLA_CTRL.FIXEDDELAY should be initialized to 0x0f. This number was apparently derived from process validation. This is only used when the SDRC DLL is unlocked (e.g., SDRC clock frequency less than 83MHz). Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | * | | | OMAP3: Add support for DPLL3 divisor values higher than 2Tero Kristo2009-06-194-14/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously only 1 and 2 was supported. This is needed for DVFS VDD2 control. Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
| | * | | | OMAP3 SRAM: convert SRAM code to use macros rather than magic numbersPaul Walmsley2009-06-191-15/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert omap3_sram_configure_core_dpll() to use macros rather than magic numbers. Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | * | | | OMAP3 SRAM: add more comments on the SRAM codePaul Walmsley2009-06-191-21/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clean up comments and copyrights on the CORE DPLL3 M2 divider change code. Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | * | | | OMAP3 clock/SDRC: program SDRC_MR register during SDRC clock changePaul Walmsley2009-06-194-8/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Program the SDRC_MR_0 register as well during SDRC clock changes. This register allows selection of the memory CAS latency. Some SDRAM chips, such as the Qimonda HYB18M512160AF6, have a lower CAS latency at lower clock rates. Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | * | | | OMAP3 clock: add a short delay when lowering CORE clk ratePaul Walmsley2009-06-194-18/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When changing the SDRAM clock from 166MHz to 83MHz via the CORE DPLL M2 divider, add a short delay before returning to SDRAM to allow the SDRC time to stabilize. Without this delay, the system is prone to random panics upon re-entering SDRAM. This time delay varies based on MPU frequency. At 500MHz MPU frequency at room temperature, 64 loops seems to work okay; so add another 32 loops for environmental and process variation. Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | * | | | OMAP3 clock: initialize SDRC timings at kernel startPaul Walmsley2009-06-192-3/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On the OMAP3, initialize SDRC timings when the kernel boots. This ensures that the kernel is running with known, optimized SDRC timings, rather than whatever was configured by the bootloader. Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | * | | | OMAP3 clock: remove wait for DPLL3 M2 clock to stabilizePaul Walmsley2009-06-191-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The original CDP kernel that this code comes from waited for 0x800 loops after switching the CORE DPLL M2 divider. This does not appear to be necessary. Signed-off-by: Paul Walmsley <paul@pwsan.com>
| * | | | | Merge branch 'for-rmk' of git://git.marvell.com/orion into develRussell King2009-06-194-3/+19
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| | * | | | | [ARM] Add old Feroceon support to compressed/head.SJoonyoung Shim2009-06-191-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch supports the cache handling for some old Feroceon cores for which the CPU ID is like 0x41159260. This is a complement to commit ab6d15d50637fc25ee941710b23fed09ceb28db3. Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
| | * | | | | [ARM] orion5x: register the crypto device on SOCs that support itNicolas Pitre2009-06-152-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Not all Orion variants do implement the crypto unit. Signed-off-by: Nicolas Pitre <nico@marvell.com>
| | * | | | | [ARM] orion5x: increment window counter after adding sram mappingSebastian Andrzej Siewior2009-06-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Without incrementing the counter the next window setup will overwrite the SRAM mapping. Signed-off-by: Sebastian Andrzej Siewior <sebastian@breakpoint.cc> Signed-off-by: Nicolas Pitre <nico@marvell.com>
| * | | | | | [ARM] 5559/1: Limit the stack unwinding caused by a kthread exitCatalin Marinas2009-06-191-1/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When a kthread function returns, it branches to do_exit(). However, the unwinding information isn't valid anymore and any stack trace caused by do_exit() may be incorrect. This patch adds a kernel_thread_exit() function and annotated with '.cantunwind' so that the unwinder stops when reaching it. Tested-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | | | [ARM] 5558/1: Add extra checks to ARM unwinder to avoid tracing corrupt stacksCatalin Marinas2009-06-191-10/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are situations where the unwinder goes beyond stack boundaries and unwinds random data. This patch moves the stack boundaries check after the unwind_exec_insn() call and adds an extra check for possible infinite loops (like "mov pc, lr" with pc == lr). The patch also fixes a bug in the unwind instructions interpreter. The 0xb0 instruction can only set PC to LR if this wasn't already set by a previous instruction (this is used on exceptions taken while in kernel mode where svc_entry is annotated with ".save {r0 - pc}"). Tested-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | | | [ARM] 5557/1: Discard some ARM.ex*.*exit.text sections when !HOTPLUG or ↵Catalin Marinas2009-06-191-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | !HOTPLUG_CPU Not discarding these sections when hotplug isn't available prevents the kernel from building. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | | | [ARM] 5540/1: 32-bit Thumb-2 {ld,st}{m,rd} alignment fault fixup supportGeorge G. Davis2009-06-191-20/+119
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From: Min Zhang <mzhang@mvista.com> Add alignment fault fixup support for 32-bit Thumb-2 LDM, LDRD, POP, PUSH, STM and STRD instructions. Alignment fault fixup support for the remaining 32-bit Thumb-2 load/store instruction cases is not included since ARMv6 and later processors include hardware support for loads and stores of unaligned words and halfwords. Signed-off-by: Min Zhang <mzhang@mvista.com> Signed-off-by: George G. Davis <gdavis@mvista.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | | | [ARM] 5556/1: Fix the irq_desc.cpu referencesCatalin Marinas2009-06-192-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The cpu member of struct irq_desc was recently renamed to node. The patch renames the ARM references to the old member. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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