summaryrefslogtreecommitdiffstats
path: root/arch/arm
Commit message (Collapse)AuthorAgeFilesLines
* Merge tag 'fixes-nc-for-linus' of ↵Linus Torvalds2014-10-0840-169/+293
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC non-critical bug fixes from Arnd Bergmann: "These are bug fixes for harmless problems that were not important enough to get fixed in 3.17. The majority of these are OMAP specific, but there are also a couple for Marvell mvebu, cns3xxx, and others, as well as some updates for the MAINTAINERS file. In particular, Robert Jarzmik and Daniel Mack now volunteered to help out maintaining the PXA platform, Krzysztof Halasa took over the cns3xxx platform, Carlo Caione is the maintainer for the new Amlogic meson platform, and Matthias Brugger is now listed for the mediatek platform he recently contributed" * tag 'fixes-nc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (42 commits) MAINTAINERS: update Shawn's email address MAINTAINERS: condense some Tegra related entries MAINTAINERS: add Alexandre Courbot for Tegra MAINTAINERS: CNS3xxx and IXP4xx update. MAINTAINERS: Add maintainers entry for Mediatek SoCs arm, vt8500, LLVMLlinux: Use mcr instead of mcr% for mach-vt8500 MAINTAINERS: add a third maintainer to mach-bcm CNS3xxx: Fix PCIe read size limit. CNS3xxx: Fix logical PCIe topology. CNS3xxx: Fix debug UART. MAINTAINERS: Add entry for the Amlogic MesonX SoCs MAINTAINERS: update ARM pxa maintainers ARM: at91/PMC: don't forget to write PMC_PCDR register to disable clocks ARM: at91: fix at91sam9263ek DT mmc pinmuxing settings ARM: mvebu: Netgear RN102: Use Hardware BCH ECC ARM: Kirkwood: Fix DT based DSA. ARM: OMAP2+: make of_device_ids const ARM: omap2: make arrays containing machine compatible strings const ARM: LPC32xx: Fix reset function ARM: mvebu: Netgear RN2120: Use Hardware BCH ECC ...
| * Merge tag 'at91-fixes-non-critical' of git://github.com/at91linux/linux-at91 ↵Arnd Bergmann2014-09-262-0/+3
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into next/fixes-non-critical Pull "Fixes non critical for AT91" from Nicolas Ferre: - mmc pinmux for at91sam9263 was missing - little fix of the old clock implementation Signed-off-by: Arnd Bergmann <arnd@arndb.de> * tag 'at91-fixes-non-critical' of git://github.com/at91linux/linux-at91: ARM: at91/PMC: don't forget to write PMC_PCDR register to disable clocks ARM: at91: fix at91sam9263ek DT mmc pinmuxing settings
| | * ARM: at91/PMC: don't forget to write PMC_PCDR register to disable clocksLudovic Desroches2014-09-241-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When introducing support for sama5d3, the write to PMC_PCDR register has been accidentally removed. Reported-by: Nathalie Cyrille <nathalie.cyrille@atmel.com> Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: <stable@vger.kernel.org> # 3.10.x and later
| | * ARM: at91: fix at91sam9263ek DT mmc pinmuxing settingsAndreas Henriksson2014-09-241-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As discovered on a custom board similar to at91sam9263ek and basing its devicetree on that one apparently the pin muxing doesn't get set up properly. This was discovered since the custom boards u-boot does funky stuff with the pin muxing and leaved it set to SPI which made the MMC driver not work under Linux. The fix is simply to define the given configuration as the default. This probably worked by pure luck before, but it's better to make the muxing explicitly set. Signed-off-by: Andreas Henriksson <andreas.henriksson@endian.se> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: <stable@vger.kernel.org> # 3.11+
| * | arm, vt8500, LLVMLlinux: Use mcr instead of mcr% for mach-vt8500Behan Webster2014-09-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ASM below does not compile with clang and is not the way that the mcr command is used in other parts of the kernel. arch/arm/mach-vt8500/vt8500.c:72:11: error: invalid % escape in inline assembly string asm("mcr%? p15, 0, %0, c7, c0, 4" : : "r" (0)); ~~~~~^~~~~~~~~~~~~~~~~~~~~~~~ 1 error generated. There are other forms that are supported on different ARM instruction sets but generally the kernel just uses mcr as it is supported in all ARM instruction sets. Signed-off-by: Behan Webster <behanw@converseincode.com> Reviewed-by: Mark Charlebois <charlebm@gmail.com> Acked-by: Will Deacon <will.deacon@arm.com> Acked-by: Tony Prisk <linux@prisktech.co.nz> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | CNS3xxx: Fix PCIe read size limit.Krzysztof Hałasa2014-09-251-6/+9
| | | | | | | | | | | | | | | | | | | | | | | | Max_Read_Request_Size is 3 bits wide, not 2 bits. Also fix the message. Signed-off-by: Krzysztof Hałasa <khalasa@piap.pl> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | CNS3xxx: Fix logical PCIe topology.Krzysztof Hałasa2014-09-251-15/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Without this patch, each root port and the device connected directly to it seem to be located on a shared (virtual) bus #0. It creates problems with enabling devices (the PCI code doesn't know that the root bridge must be enabled in order to access other devices). The PCIe topology shown by lspci doesn't reflect reality, e.g.: 0000:00:00.0 PCI bridge: Cavium Networks Device 3400 0000:00:01.0 PCI bridge: Texas Instruments XIO2001 PCI Express-to-PCI Bridge 0000:02:... 0001:00:00.0 PCI bridge: Cavium Networks Device 3400 (for the second lane/bus) -+-[0001:00]---00.0-[01]-- \-[0000:00]-+-00.0-[01]-- | ^^^^ root bridge \-01.0-[02]----... ^^^^ first external device With this patch, the first external PCIe device is connected to bus #1 (behind the root bridge). -+-[0001:00]---00.0-[01]-- \-[0000:00]---00.0-[01-02]----------00.0-[02]----... ^^^^ root bridge ^^^^ first external device Signed-off-by: Krzysztof Hałasa <khalasa@piap.pl> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | CNS3xxx: Fix debug UART.Krzysztof Hałasa2014-09-251-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | UARTs on CNS3xxx are 8250-compatible, not AMBA. The base address for UART0 is 0x78000000 (physical) and 0xfb002000 (virtual). Signed-off-by: Krzysztof Hałasa <khalasa@piap.pl> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | Merge tag 'mvebu-fixes-3.17' of git://git.infradead.org/linux-mvebu into ↵Olof Johansson2014-09-2310-69/+81
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | next/fixes-non-critical Merge "mvebu fixes for v3.17" from Jason Cooper: - kirkwood - final driver cleanup of ARCH_KIRKWOOD removal - fix DT based DSA - mvebu - use BCH ECC for the RN2120 and RN104/2 nand chips * tag 'mvebu-fixes-3.17' of git://git.infradead.org/linux-mvebu: ARM: mvebu: Netgear RN102: Use Hardware BCH ECC ARM: Kirkwood: Fix DT based DSA. ARM: mvebu: Netgear RN2120: Use Hardware BCH ECC ARM: mvebu: Netgear RN104: Use Hardware BCH ECC cpufreq: Remove ARCH_KIRKWOOD dependency watchdog: Remove ARCH_KIRKWOOD dependency rtc: Remove ARCH_KIRKWOOD dependency leds: Remove ARCH_KIRKWOOD dependency thermal: Remove ARCH_KIRKWOOD dependency ata: Remove ARCH_KIRKWOOD dependency cpuidle: kirkwood: Remove ARCH_KIRKWOOD dependency
| | * | ARM: mvebu: Netgear RN102: Use Hardware BCH ECCklightspeed@killerwolves.net2014-09-141-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The bootloader on the Netgear ReadyNAS RN102 uses Hardware BCH ECC (strength = 4), while the pxa3xx NAND driver by default uses Hamming ECC (strength = 1). This patch changes the ECC mode on these machines to match that of the bootloader and of the stock firmware. That way, it is now possible to update the kernel from userland (e.g. using standard tools from mtd-utils package); u-boot will happily load and boot it. Fixes: 92beaccd8b49 ("ARM: mvebu: Enable NAND controller in ReadyNAS 102 .dts file") Cc: <stable@vger.kernel.org> #v3.14+ Signed-off-by: Ben Peddell <klightspeed@killerwolves.net> Acked-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: Arnaud Ebalard <arno@natisbad.org> Link: https://lkml.kernel.org/r/1410339341-3372-1-git-send-email-klightspeed@killerwolves.net Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| | * | ARM: Kirkwood: Fix DT based DSA.Andrew Lunn2014-09-137-69/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During the conversion of boards to use DT to instantiate Distributed Switch Architecture, nobody volunteered to test. As to be expected, the conversion was flawed. Testers and access to hardware has now become available, and this patch hopefully fixes the problems. dsa,mii-bus must be a phandle to the top level mdio node, not the port specific subnode of the mdio device. dsa,ethernet must be a phandle to the port subnode within the ethernet DT node, not the ethernet node. Don't pinctrl hog the card detect gpio for mvsdio. Rename the .dts files to make it clearer which file is for the Z0 stepping and which for the A0 or later stepping. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Cc: seugene@marvell.com Tested-by: Eugene Sanivsky <seugene@marvell.com> Fixes: e2eaa339af44: ("ARM: Kirkwood: convert rd88f6281-setup.c to DT.") Fixes: e7c8f3808be8: ("ARM: kirkwood: Convert mv88f6281gtw_ge switch setup to DT") Cc: <stable@vger.kernel.org> #v3.15+ Link: https://lkml.kernel.org/r/1409592941-22244-1-git-send-email-andrew@lunn.ch Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| | * | ARM: mvebu: Netgear RN2120: Use Hardware BCH ECCArnaud Ebalard2014-09-091-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The bootloader on the Netgear ReadyNAS RN2120 uses Hardware BCH ECC (strength = 4), while the pxa3xx NAND driver by default uses Hamming ECC (strength = 1). This patch changes the ECC mode on these machines to match that of the bootloader and of the stock firmware. That way, it is now possible to update the kernel from userland (e.g. using standard tools from mtd-utils package); u-boot will happily load and boot it. The issue was initially reported and fixed by Ben Pedell for RN102. The RN2120 shares the same Hynix H27U1G8F2BTR NAND flash and setup. This patch is based on Ben's fix for RN102. Fixes: ad51eddd95ad ("ARM: mvebu: Enable NAND controller in ReadyNAS 2120 .dts file") Cc: <stable@vger.kernel.org> # v3.14+ Signed-off-by: Arnaud Ebalard <arno@natisbad.org> Link: https://lkml.kernel.org/r/61f6a1b7ad0adc57a0e201b9680bc2e5f214a317.1410035142.git.arno@natisbad.org Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| | * | ARM: mvebu: Netgear RN104: Use Hardware BCH ECCArnaud Ebalard2014-09-091-0/+4
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The bootloader on the Netgear ReadyNAS RN104 uses Hardware BCH ECC (strength = 4), while the pxa3xx NAND driver by default uses Hamming ECC (strength = 1). This patch changes the ECC mode on these machines to match that of the bootloader and of the stock firmware. That way, it is now possible to update the kernel from userland (e.g. using standard tools from mtd-utils package); u-boot will happily load and boot it. The issue was initially reported and fixed by Ben Pedell for RN102. The RN104 shares the same Hynix H27U1G8F2BTR NAND flash and setup. This patch is based on Ben's fix for RN102. Fixes: 0373a558bd79 ("ARM: mvebu: Enable NAND controller in ReadyNAS 104 .dts file") Cc: <stable@vger.kernel.org> # v3.14+ Signed-off-by: Arnaud Ebalard <arno@natisbad.org> Link: https://lkml.kernel.org/r/920c7e7169dc6aaaa3eb4bced2336d38e77b8864.1410035142.git.arno@natisbad.org Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * | Merge tag 'fixes-v3.18-not-urgent' of ↵Olof Johansson2014-09-2370-561/+362
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/fixes-non-critical Merge "non-urgent omap fixes for v3.18 merge window" from Tony Lindgren: Fixes for omaps that were not considered urgent enough for the -rc cycle: - Fixes for .dts files to differentiate panda and beaglebone versions - Powerdomain fixes from Nishant Menon mostly for newer omaps - Fixes for __initconst and of_device_ids const usage * tag 'fixes-v3.18-not-urgent' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: OMAP2+: make of_device_ids const ARM: omap2: make arrays containing machine compatible strings const ARM: OMAP4+: PM: Use only valid low power state for CPU hotplug ARM: OMAP4+: PM: use only valid low power state for suspend ARM: OMAP4+: PM: Make logic state programmable ARM: OMAP2+: powerdomain: introduce logic for finding valid power domain ARM: OMAP2+: powerdomain: pwrdm_for_each_clkdm iterate only valid clkdms ARM: OMAP5: powerdomain data: fix powerdomain powerstate ARM: OMAP: DRA7: powerdomain data: fix powerdomain powerstate ARM: dts: am335x-bone*: Fix model name and update compatibility information ARM: dts: omap4-panda: Fix model and SoC family details + Linux 3.17-rc3 Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | ARM: OMAP2+: make of_device_ids constUwe Kleine-König2014-09-117-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | of_device_ids (i.e. compatible strings and the respective data) are not supposed to change at runtime. All functions working with of_device_ids provided by <linux/of.h> work with const of_device_ids. So mark the non-const function parameters and structs for OMAP2+ as const, too. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * | ARM: omap2: make arrays containing machine compatible strings constUwe Kleine-König2014-09-111-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The definition static const char *omap3_boards_compat[] __initconst = { defines a changable array of constant strings. That is you must not do: *omap3_boards_compat[0] = 'f'; but omap3_boards_compat[0] = "another string"; is fine. So the annotation __initconst is wrong and yields a compiler error when other really const variables are added with __initconst. As the struct machine_desc member dt_compat is declared as const char *const *dt_compat; making the arrays const is the better alternative over changing all annotations to __initdata. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * | Merge branch 'pull/v3.18/powerdomain-fixes' of ↵Tony Lindgren2014-09-086-16/+106
| | |\ \ | | | | | | | | | | | | | | | https://github.com/nmenon/linux-2.6-playground into omap-for-v3.18/fixes-not-urgent
| | | * | ARM: OMAP4+: PM: Use only valid low power state for CPU hotplugNishanth Menon2014-09-081-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Not all SoCs support OFF mode - for example DRA74/72. So, use valid power state during CPU hotplug. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
| | | * | ARM: OMAP4+: PM: use only valid low power state for suspendNishanth Menon2014-09-081-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We are using power domain state as RET and logic state as OFF. This state is OSWR. This may not always be supported on ALL power domains. In fact, on certain power domains, this might result in a hang on certain platforms. Instead, depend on powerdomain data to provide accurate information about the supported powerdomain states and use the appropriate function to query and use it as part of suspend path. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
| | | * | ARM: OMAP4+: PM: Make logic state programmableNishanth Menon2014-09-081-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the logic state as different for each power domain. This allows us to customize the deepest power state we should target over all for each powerdomain in the follow on patches. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
| | | * | ARM: OMAP2+: powerdomain: introduce logic for finding valid power domainNishanth Menon2014-09-082-0/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | powerdomain configuration in OMAP is done using PWRSTCTRL register for each power domain. However, PRCM lets us write any value we'd like to the logic and power domain target states, however the SoC integration tends to actually function only at a few discrete states. These valid states are already in our powerdomains_xxx_data.c file. So, provide a function to easily query valid low power state that the power domain is allowed to go to. Based on work originally done by Jean Pihet <j-pihet@ti.com> https://patchwork.kernel.org/patch/1325091/ . There is no attempt to create a new powerdomain solution here, except fixing issues seen attempting invalid programming attempts. Future consolidation to the generic powerdomain framework should consider this requirement as well. Similar solutions have been done in product kernels in the past such as: https://android.googlesource.com/kernel/omap.git/+blame/android-omap-panda-3.0/arch/arm/mach-omap2/pm44xx.c Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
| | | * | ARM: OMAP2+: powerdomain: pwrdm_for_each_clkdm iterate only valid clkdmsNishanth Menon2014-09-081-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | No need to invoke callback when the clkdm pointer is NULL. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
| | | * | ARM: OMAP5: powerdomain data: fix powerdomain powerstateNishanth Menon2014-09-081-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the power domain power states for final production chip capability. OFF mode, OSWR etc have been descoped for various domains. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
| | | * | ARM: OMAP: DRA7: powerdomain data: fix powerdomain powerstateNishanth Menon2014-09-082-7/+8
| | | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DRA7 supports only CSWR for CPU, MPU power domains. Core power domain supports upto INA. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
| | * | ARM: dts: am335x-bone*: Fix model name and update compatibility informationNishanth Menon2014-09-033-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Beaglebone white and beaglebone black differ in tiny little aspects. This is the reason why we maintain seperate dts for these platforms. However, there is no real way to decode from dtb which platform it is since compatible and model name are the same for both platforms. Fix this so that beaglebone black and beaglebone are identifiable, while maintaining compatibility for older zImages which might use old beaglebone compatible flag for black as well. Reported-by: Tom Rini <trini@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * | ARM: dts: omap4-panda: Fix model and SoC family detailsNishanth Menon2014-09-033-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently we claim that omap4-panda and omap4-panda-es are essentially the same, but they are not since PandaBoard-ES uses OMAP4460 and PandaBoard uses OMAP4430. So, split the common definition and make the model name available. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | | ARM: LPC32xx: Fix reset functionRoland Stigge2014-09-101-23/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the recent change to the reset function API (commit 7b6d864b48d95e6ea1df7df64475b9cb9616dcf9), the mode argument changed from a char to an enum. lpc23xx_restart() only handles REBOOT_SOFT and REBOOT_HARD, but the new kernel code emits REBOOT_COLD (0) on reboots now which leads to lpc32xx simply not rebooting (but halting). This patch fixes this by just resetting unconditionally as on other platforms (e.g. mach-bcm2835). Pulling lpc32xx_watchdog_reset() into lpc23xx_restart() since the while() in lpc23xx_restart() is part of the procedure anyway and lpc32xx_watchdog_reset() isn't used anywhere else anymore. Signed-off-by: Roland Stigge <stigge@antcom.de>
| * | | ARM: spear: Remove references to PLAT_SPEAR_SINGLEPaul Bolle2014-09-051-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Kconfig symbol PLAT_SPEAR_SINGLE briefly appeared during the v3.10 development cycle. It was removed in a merge commit before v3.10. A few references to it were left in the tree, probably because they didn't generate merge conflicts. Whatever it was, they're useless now and can safely be removed. Reported-by: Martin Walch <walch.martin@web.de> Signed-off-by: Paul Bolle <pebolle@tiscali.nl> Reviewed-by: Rajeev Kumar <rajeev-dlh.kumar@st.com> Cc: Rajeev Kumar <rajeev_kumar@mentor.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | | ARM: cns3xxx: fix allmodconfig panic in pci driverXia Kaixu2014-09-044-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The kernel panic occurs when running an allmodconfig kernel on OMAP4460. The inicall "cns3xxx_pcie_init" does not check which hardware it's running on and just tries to access to its specific registers. Now call it from .init_late callback from the two machine descriptors. Signed-off-by: Xia Kaixu <kaixu.xia@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Anton Vorontsov <anton@enomsg.org> Cc: Felix Fietkau <nbd@openwrt.org> Cc: Imre Kaloz <kaloz@openwrt.org> Cc: linaro-kernel@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org
| * | | ARM: davinci: board-da850-evm: Add needed regulators for tlv320aic3106 codecPeter Ujfalusi2014-08-261-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IOVDD: tps65070's dcdc2 AVDD and DRVDD: fixed regulator derived from 5V via TPS73701DCQ DVDD: fixed regulator derived from 5V via TPS73701DCQ This patch needed to be able to probe the audio codec. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
| * | | ARM: davinci: board-da850-evm: Mark dcdc2 of TPS65070 as always_onPeter Ujfalusi2014-08-261-0/+1
| | |/ | |/| | | | | | | | | | | | | | | | | | | DCDC2 should not be turned off since it is powering the CPU among other things. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
* | | Merge branch 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-armLinus Torvalds2014-10-0831-115/+462
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull ARM updates from Russell King: "Included in these updates are: - Performance optimisation to avoid writing the control register at every exception. - Use static inline instead of extern inline in ftrace code. - Crypto ARM assembly updates for big endian - Alignment of initrd/.init memory to page sizes when freeing to ensure that we fully free the regions - Add gcov support - A couple of preparatory patches for VDSO support: use _install_special_mapping, and randomize the sigpage placement above stack. - Add L2 ePAPR DT cache properties so that DT can specify the cache geometry. - Preparatory patch for FIQ (NMI) kernel C code for things like spinlock lockup debug. Following on from this are a couple of my patches cleaning up show_regs() and removing an unused (probably since 1.x days) do_unexp_fiq() function. - Use pr_warn() rather than pr_warning(). - A number of cleanups (smp, footbridge, return_address)" * 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm: (21 commits) ARM: 8167/1: extend the reserved memory for initrd to be page aligned ARM: 8168/1: extend __init_end to a page align address ARM: 8169/1: l2c: parse cache properties from ePAPR definitions ARM: 8160/1: drop warning about return_address not using unwind tables ARM: 8161/1: footbridge: select machine dir based on ARCH_FOOTBRIDGE ARM: 8158/1: LLVMLinux: use static inline in ARM ftrace.h ARM: 8155/1: place sigpage at a random offset above stack ARM: 8154/1: use _install_special_mapping for sigpage ARM: 8153/1: Enable gcov support on the ARM architecture ARM: Avoid writing to control register on every exception ARM: 8152/1: Convert pr_warning to pr_warn ARM: remove unused do_unexp_fiq() function ARM: remove extraneous newline in show_regs() ARM: 8150/3: fiq: Replace default FIQ handler ARM: 8140/1: ep93xx: Enable DEBUG_LL_UART_PL01X ARM: 8139/1: versatile: Enable DEBUG_LL_UART_PL01X ARM: 8138/1: drop ISAR0 workaround for B15 ARM: 8136/1: sa1100: add Micro ASIC platform device ARM: 8131/1: arm/smp: Absorb boot_secondary() ARM: 8126/1: crypto: enable NEON SHA-384/SHA-512 for big endian ...
| | \ \
| | \ \
| | \ \
| | \ \
| *---. \ \ Merge branches 'fiq' (early part), 'fixes', 'l2c' (early part) and 'misc' ↵Russell King2014-10-0250-197/+528
| |\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | into for-next
| | | | * | | ARM: 8167/1: extend the reserved memory for initrd to be page alignedYalin Wang2014-10-021-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch extends the start and end address of initrd to be page aligned, so that we can free all memory including the un-page aligned head or tail page of initrd, if the start or end address of initrd are not page aligned, the page can't be freed by free_initrd_mem() function. Signed-off-by: Yalin Wang <yalin.wang@sonymobile.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | * | | ARM: 8168/1: extend __init_end to a page align addressYalin Wang2014-10-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch changes the __init_end address to a page align address, so that free_initmem() can free the whole .init section, because if the end address is not page aligned, it will round down to a page align address, then the tail unligned page will not be freed. Signed-off-by: wang <yalin.wang2010@gmail.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | * | | ARM: 8160/1: drop warning about return_address not using unwind tablesUwe Kleine-König2014-09-261-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The warning was introduced in 2009 (commit 4bf1fa5a34aa ([ARM] 5613/1: implement CALLER_ADDRESSx)). The only "problem" here is that CALLER_ADDRESSx for x > 1 returns NULL which doesn't do much harm. The drawback of implementing a fix (i.e. use unwind tables to implement CALLER_ADDRESSx) is that much of the unwinder code would need to be marked as not traceable. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | * | | ARM: 8161/1: footbridge: select machine dir based on ARCH_FOOTBRIDGEUwe Kleine-König2014-09-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Syntactically FOOTBRIDGE and ARCH_FOOTBRIDGE are identical (the former is defined in an if ARCH_FOOTBRIDGE block and the latter selects the former). Sematically FOOTBRIDGE means "we have a DC21285 (aka footbridge) device in the system" and ARCH_FOOTBRIDGE is the support for boards with a footbridge device, so ARCH_FOOTBRIDGE is the better symbol here. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | * | | ARM: 8158/1: LLVMLinux: use static inline in ARM ftrace.hBehan Webster2014-09-262-6/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With compilers which follow the C99 standard (like modern versions of gcc and clang), "extern inline" does the wrong thing (emits code for an externally linkable version of the inline function). In this case using static inline and removing the NULL version of return_address in return_address.c does the right thing. Signed-off-by: Behan Webster <behanw@converseincode.com> Reviewed-by: Mark Charlebois <charlebm@gmail.com> Acked-by: Steven Rostedt <rostedt@goodmis.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | * | | ARM: 8155/1: place sigpage at a random offset above stackNathan Lynch2014-09-261-1/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sigpage is currently placed alongside shared libraries etc in the address space. Similar to what x86_64 does for its VDSO, place the sigpage at a randomized offset above the stack so that learning the base address of the sigpage doesn't help expose where shared libraries are loaded in the address space (and vice versa). Signed-off-by: Nathan Lynch <nathan_lynch@mentor.com> Reviewed-by: Kees Cook <keescook@chromium.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | * | | ARM: 8154/1: use _install_special_mapping for sigpageNathan Lynch2014-09-261-8/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | _install_special_mapping allows the VMA to be identifed in /proc/pid/maps without the use of arch_vma_name, providing a slight net reduction in object size: text data bss dec hex filename 2996 96 144 3236 ca4 arch/arm/kernel/process.o (before) 2956 104 144 3204 c84 arch/arm/kernel/process.o (after) Signed-off-by: Nathan Lynch <nathan_lynch@mentor.com> Reviewed-by: Kees Cook <keescook@chromium.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | * | | ARM: 8153/1: Enable gcov support on the ARM architectureVincent Sanders2014-09-262-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable gcov support for ARM based on original patches by David Singleton and George G. Davis Riku - updated to patch to current mainline kernel. The patch has been submitted in 2010, 2012 - for symmetry, now in 2014 too. https://lwn.net/Articles/390419/ http://marc.info/?l=linux-arm-kernel&m=133823081813044 v2: remove arch/arm/kernel from gcov disabled files Cc: Andrey Ryabinin <a.ryabinin@samsung.com> Cc: Naresh Kamboju <naresh.kamboju@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Riku Voipio <riku.voipio@linaro.org> Signed-off-by: Vincent Sanders <vincent.sanders@collabora.co.uk> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | * | | ARM: Avoid writing to control register on every exceptionRussell King2014-09-263-8/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If we are not changing the control register value, avoid writing to it. Writes to the control register can be very expensive, taking around a hundred cycles or so. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | * | | ARM: 8152/1: Convert pr_warning to pr_warnJoe Perches2014-09-269-34/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the more common pr_warn. Other miscellanea: o Coalesce formats o Realign arguments Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | * | | ARM: 8140/1: ep93xx: Enable DEBUG_LL_UART_PL01XDaniel Thompson2014-09-161-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This defconfig already enables DEBUG_LL and by default DEBUG_LL_UART_NONE will be selected (but due to some back compability magic I'd like to remove is not actually honoured). DEBUG_LL_UART_PL01X is a much saner default. Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | * | | ARM: 8139/1: versatile: Enable DEBUG_LL_UART_PL01XDaniel Thompson2014-09-161-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This defconfig already enables DEBUG_LL and by default DEBUG_LL_UART_NONE will be selected (but due to some back compability magic I'd like to remove is not actually honoured). DEBUG_LL_UART_PL01X is a much saner default. Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | * | | ARM: 8138/1: drop ISAR0 workaround for B15Brian Norris2014-09-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Brahma-B15's ISAR0 correcty advertises UDIV/SDIV support in both ARM and Thumb2 modes (CPUID_EXT_ISAR0=02101110), so we don't need to manually apply this hwcap. The code in question actually predates the following commit, which made our hwcaps unnecessary: commit 8164f7af88d9ad3a757bd14f634b23997ee77f6b Author: Stephen Boyd <sboyd@codeaurora.org> Date: Mon Mar 18 19:44:15 2013 +0100 ARM: 7680/1: Detect support for SDIV/UDIV from ISAR0 register Signed-off-by: Brian Norris <computersforpeace@gmail.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | * | | ARM: 8136/1: sa1100: add Micro ASIC platform deviceLinus Walleij2014-09-122-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the Atmel Micro ASIC platform device and selects it by default for h3100 and h3600. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | * | | ARM: 8131/1: arm/smp: Absorb boot_secondary()Geert Uytterhoeven2014-08-272-14/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After becoming a mandatory function, boot_secondary() is no longer used outside arch/arm/kernel/smp.c. Hence remove its public prototype, and, as suggested by Arnd, let it be absorbed by its single caller. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | * | | ARM: 8125/1: crypto: enable NEON SHA-1 for big endianArd Biesheuvel2014-08-271-17/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This tweaks the SHA-1 NEON code slightly so it works correctly under big endian, and removes the Kconfig condition preventing it from being selected if CONFIG_CPU_BIG_ENDIAN is set. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | | ARM: 8169/1: l2c: parse cache properties from ePAPR definitionsLinus Walleij2014-10-021-0/+121
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When both 'cache-size' and 'cache-sets' are specified for a L2 cache controller node, parse those properties and set up the set size based on which type of L2 cache controller we are using. Update the L2 cache controller Device Tree binding with the optional 'cache-size', 'cache-sets', 'cache-block-size' and 'cache-line-size' properties. These come from the ePAPR specification. Using the cache size, number of sets and cache line size we can calculate desired associativity of the L2 cache. This is done by the calculation: set size = cache size / sets ways = set size / line size way size = cache size / ways = sets * line size associativity = cache size / way size Example output from the PB1176 DT that look like this: L2: l2-cache { compatible = "arm,l220-cache"; (...) arm,override-auxreg; cache-size = <131072>; // 128kB cache-sets = <512>; cache-line-size = <32>; }; Ends up like this: L2C OF: override cache size: 131072 bytes (128KB) L2C OF: override line size: 32 bytes L2C OF: override way size: 16384 bytes (16KB) L2C OF: override associativity: 8 L2C: DT/platform modifies aux control register: 0x02020fff -> 0x02030fff L2C-220 cache controller enabled, 8 ways, 128 kB L2C-220: CACHE_ID 0x41000486, AUX_CTRL 0x06030fff Which is consistent with the value earlier hardcoded for the PB1176 platform. This patch is an extended version based on the initial patch by Florian Fainelli. Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
OpenPOWER on IntegriCloud