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* Merge branch 'omap-fixes-for-linus' of ↵Linus Torvalds2009-10-157-40/+59
|\ | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6 * 'omap-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6: OMAP2xxx clock: set up clockdomain pointer in struct clk OMAP: Fix race condition with autodeps omap: McBSP: Fix incorrect receiver stop in omap_mcbsp_stop omap: Initialization of SDRC params on Zoom2 omap: RX-51: Drop I2C-1 speed to 2200 omap: SDMA: Fixing bug in omap_dma_set_global_params() omap: CONFIG_ISP1301_OMAP redefined in Beagle defconfig
| * Merge branch '2_6_32rc4_fixes' of git://git.pwsan.com/linux-2.6 into ↵Tony Lindgren2009-10-142-30/+45
| |\ | | | | | | | | | omap-fixes-for-linus
| | * OMAP2xxx clock: set up clockdomain pointer in struct clkPaul Walmsley2009-10-141-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clock24xx.c is missing a omap2_init_clk_clkdm() in its omap2_clk_init() function. Among other bad effects, this causes the OMAP hwmod layer to oops on boot. Thanks to Carlos Aguiar <carlos.aguiar@indt.org.br> and Stefano Panella <Stefano.Panella@csr.com> for reporting this bug. Thanks to Tony Lindgren <tony@atomide.com> for N800 booting advice. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Carlos Aguiar <carlos.aguiar@indt.org.br> Cc: Stefano Panella <Stefano.Panella@csr.com> Cc: Tony Lindgren <tony@atomide.com>
| | * OMAP: Fix race condition with autodepsKalle Jokiniemi2009-10-141-30/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a possible race condition in clockdomain code handling hw supported idle transitions. When multiple autodeps dependencies are being added or removed, a transition of still remaining dependent powerdomain can result in false readings of the state counter. This is especially fatal for off mode state counter, as it could result in a driver not noticing a context loss. Fixed by disabling hw supported state transitions when autodeps are being changed. Signed-off-by: Kalle Jokiniemi <kalle.jokiniemi@digia.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| * | omap: McBSP: Fix incorrect receiver stop in omap_mcbsp_stopJarkko Nikula2009-10-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This small typo written by author causes that McBSP receiver is disabled on OMAP2430 and OMAP3430 even if only transmitter is stopped. This was noted with ALSA SoC where simultaneous recording halted if playback was stopped first. Signed-off-by: Jarkko Nikula <jhnikula@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | omap: Initialization of SDRC params on Zoom2Teerth Reddy2009-10-141-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch initializes the correct SDRC settings required for DVFS on Zoom2. Signed-off-by: Teerth Reddy <teerth@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | omap: RX-51: Drop I2C-1 speed to 2200Aaro Koskinen2009-10-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The I2C-1 bus frequency on RX-51 should be 2.2 MHz. The speed is limited by TWL5030/GAIA; a higher speed could lead to errors on the interface. The maximum speed depends on the system clock for GAIA: 2.2 MHz (if 19.2 MHz), 2.4 MHz (26 MHz) or 2.9 MHz (38.4 MHz). Signed-off-by: Aaro Koskinen <aaro.koskinen@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | omap: SDMA: Fixing bug in omap_dma_set_global_params()Anuj Aggarwal2009-10-141-6/+9
| | | | | | | | | | | | | | | | | | | | | | | | Argument tparams was not being used to program global register GCR.HI_THREAD_RESERVED. This patch fixes the same. Signed-off-by: Anuj Aggarwal <anuj.aggarwal@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | omap: CONFIG_ISP1301_OMAP redefined in Beagle defconfigSanjeev Premi2009-10-141-1/+0
| |/ | | | | | | | | | | | | | | | | | | The symbol CONFIG_ISP1301_OMAP was defined twice in the defconfig. This was causing the warning: arch/arm/configs/omap3_beagle_defconfig:972:warning: override: reassigning to symbol ISP1301_OMAP Signed-off-by: Sanjeev Premi <premi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | ARM: force dcache flush if dcache_dirty bit setNitin Gupta2009-10-121-6/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On ARM, update_mmu_cache() does dcache flush for a page only if it has a kernel mapping (page_mapping(page) != NULL). The correct behavior would be to force the flush based on dcache_dirty bit only. One of the cases where present logic would be a problem is when a RAM based block device[1] is used as a swap disk. In this case, we would have in-memory data corruption as shown in steps below: do_swap_page() { - Allocate a new page (if not already in swap cache) - Issue read from swap disk - Block driver issues flush_dcache_page() - flush_dcache_page() simply sets PG_dcache_dirty bit and does not actually issue a flush since this page has no user space mapping yet. - Now, if swap disk is almost full, this newly read page is removed from swap cache and corrsponding swap slot is freed. - Map this page anonymously in user space. - update_mmu_cache() - Since this page does not have kernel mapping (its not in page/swap cache and is mapped anonymously), it does not issue dcache flush even if dcache_dirty bit is set by flush_dcache_page() above. <user now gets stale data since dcache was never flushed> } Same problem exists on mips too. [1] example: - brd (RAM based block device) - ramzswap (RAM based compressed swap device) Signed-off-by: Nitin Gupta <ngupta@vflare.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | Merge branch 'fix' of ↵Russell King2009-10-1214-164/+237
|\ \ | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6
| * | [ARM] pxa: workaround errata #37 by not using half turbo switchingDennis O'Brien2009-10-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | PXA27x Errata #37 implies system will hang when switching into or out of half turbo (HT bit in CLKCFG) mode, workaround this by not using it. Signed-off-by: Dennis O'Brien <dennis.obrien@eqware.net> Cc: stable-2.6.31 <stable@kernel.org> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
| * | [ARM] pxa/csb726: adjust duplicate structure field initializationJulia Lawall2009-10-121-1/+1
| |/ | | | | | | | | | | | | | | | | | | Currently the irq_type field of the csb726_lan_config structure is initialized twice. The value in the first case, SMSC911X_IRQ_POLARITY_ACTIVE_LOW, is normally stored in the irq_polarity field, so I have renamed the field in the first initialization to that. Signed-off-by: Julia Lawall <julia@diku.dk> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
| * headers: remove sched.h from interrupt.hAlexey Dobriyan2009-10-113-0/+3
| | | | | | | | | | | | | | | | After m68k's task_thread_info() doesn't refer to current, it's possible to remove sched.h from interrupt.h and not break m68k! Many thanks to Heiko Carstens for allowing this. Signed-off-by: Alexey Dobriyan <adobriyan@gmail.com>
| * Merge branch 'for-linus' of ↵Linus Torvalds2009-10-091-39/+39
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input: Input: i8042 - print debug data when testing AUX IRQ delivery Input: libps2 - fix dependancy on i8042 Input: fix rx51 board keymap Input: ad7879 - pass up error codes from probe functions Input: xpad - add BigBen Interactive XBOX 360 Controller Input: rotary_encoder - fix relative axis support Input: sparkspkr - move remove() functions to .devexit.text Input: wistron_btns - add DMI entry for Medion WIM2030 laptop
| | * Input: fix rx51 board keymapAmit Kucheria2009-10-051-39/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The original driver was written with the KEY() macro defined as (col, row) instead of (row, col) as defined by the matrix keypad infrastructure. So the keymap was defined accordingly. Since the driver that was merged upstream uses the matrix keypad infrastructure, modify the keymap accordingly. While we are at it, fix the comments in twl4030.h and define PERSISTENT_KEY as (r,c) instead of (c, r) Tested on a RX51 (N900) device. Signed-off-by: Amit Kucheria <amit.kucheria@verdurent.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Dmitry Torokhov <dtor@mail.ru>
| * | Merge branch 'pm-fixes-32' of ↵Tony Lindgren2009-10-064-95/+137
| |\ \ | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm into omap-fixes-for-linus
| | * | OMAP3: PM: introduce a new powerdomain walk helperArtem Bityutskiy2009-10-053-14/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 'pwrdm_for_each()' function walks powerdomains with a spinlock locked, so the the callbacks cannot do anything which may sleep. This patch introduces a 'pwrdm_for_each_nolock()' helper which does the same, but without the spinlock locked. This fixes the following lockdep warning: [ 0.000000] WARNING: at kernel/lockdep.c:2460 lockdep_trace_alloc+0xac/0xec() [ 0.000000] Modules linked in: (unwind_backtrace+0x0/0xdc) from [<c0045464>] (warn_slowpath_common+0x48/0x60) (warn_slowpath_common+0x48/0x60) from [<c0067dd4>] (lockdep_trace_alloc+0xac/0xec) (lockdep_trace_alloc+0xac/0xec) from [<c009da14>] (kmem_cache_alloc+0x1c/0xd0) (kmem_cache_alloc+0x1c/0xd0) from [<c00b21d8>] (d_alloc+0x1c/0x1a4) (d_alloc+0x1c/0x1a4) from [<c00a887c>] (__lookup_hash+0xd8/0x118) (__lookup_hash+0xd8/0x118) from [<c00a9f20>] (lookup_one_len+0x84/0x94) (lookup_one_len+0x84/0x94) from [<c010d12c>] (debugfs_create_file+0x8c/0x20c) (debugfs_create_file+0x8c/0x20c) from [<c010d320>] (debugfs_create_dir+0x1c/0x20) (debugfs_create_dir+0x1c/0x20) from [<c000e8cc>] (pwrdms_setup+0x60/0x90) (pwrdms_setup+0x60/0x90) from [<c002e010>] (pwrdm_for_each+0x30/0x80) (pwrdm_for_each+0x30/0x80) from [<c000e79c>] (pm_dbg_init+0x7c/0x14c) (pm_dbg_init+0x7c/0x14c) from [<c00232b4>] (do_one_initcall+0x5c/0x1b8) (do_one_initcall+0x5c/0x1b8) from [<c00083f8>] (kernel_init+0x90/0x10c) (kernel_init+0x90/0x10c) from [<c00242c4>] (kernel_thread_exit+0x0/0x8) Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| | * | OMAP3: PM: Enable GPIO module-level wakeupsKevin Hilman2009-10-051-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, only GPIOs in the wakeup domain (GPIOs in bank 0) are enabled as wakups. This patch also enables GPIOs in the PER powerdomain (banks 2-6) to be used as possible wakeup sources. In addition, this patch ensures that all GPIO wakeups can wakeup the MPU using the PM_MPUGRPSEL_<pwrdm> registers. NOTE: this doesn't enable the individual GPIOs as wakeups, this simply enables the per-bank wakeups at the powerdomain level. This problem was discovered by Mike Chan when preventing the CORE powerdomain from going into retention/off. When CORE was allowed to hit retention, GPIO wakeups via IO pad were working fine, but when CORE remained on, GPIO module-level wakeups were not working properly. To test, prevent CORE from going inactive/retention/off, thus preventing the IO chain from being armed: # echo 3 > /debug/pm_debug/core_pwrdm/suspend This ensures that GPIO wakeups happen via module-level wakeups and not via IO pad. Tested on 3430SDP using the touchscreen GPIO (gpio 2, in WKUP) Tested on Zoom2 using the QUART interrup GPIO (gpio 102, in PER) Also, c.f. OMAP PM wiki for troubleshooting GPIO wakeup issues: http://elinux.org/OMAP_Power_Management Reported-by: Mike Chan <mikechan@google.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| | * | OMAP3: PM: USBHOST: clear wakeup events on both hostsVikram Pandita2009-10-051-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | USBHOST module has 2 fclocks (for HOST1 and HOST2), only one iclock and only a single bit in the WKST register to indicate a wakeup event. Because of the single WKST bit, we cannot know whether a wakeup event was on HOST1 or HOST2, so enable both fclocks before clearing the wakeup event to ensure both hosts can properly clear the event. Signed-off-by: Vikram Pandita <vikram.pandita@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| | * | OMAP3: PM: PRCM interrupt: only handle selected PRCM interruptsPaul Walmsley2009-10-051-9/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clearing wakeup sources is now only done when the PRM indicates a wakeup source interrupt. Since we don't handle any other types of PRCM interrupts right now, warn if we get any other type of PRCM interrupt. Either code needs to be added to the PRCM interrupt handler to react to these, or these other interrupts should be masked off at init. Updated after Jon Hunter's PRCM IRQ rework by Kevin Hilman. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| | * | OMAP3: PM: PRCM interrupt: check MPUGRPSEL registerPaul Walmsley2009-10-051-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PM_WKST register contents should be ANDed with the contents of the MPUGRPSEL registers. Otherwise the MPU PRCM interrupt handler could wind up clearing wakeup events meant for the IVA PRCM interrupt handler. A future revision to this code should be to read a cached version of MPUGRPSEL from the powerdomain code, since PRM reads are relatively slow. Updated after Jon Hunter's PRCM IRQ change by Kevin Hilman Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| | * | OMAP3: PM: Prevent hang in prcm_interrupt_handlerJon Hunter2009-10-051-83/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are two scenarios where a race condition could result in a hang in the prcm_interrupt handler. These are: 1). Waiting for PRM_IRQSTATUS_MPU register to clear. Bit 0 of the PRM_IRQSTATUS_MPU register indicates that a wake-up event is pending for the MPU. This bit can only be cleared if the all the wake-up events latched in the various PM_WKST_x registers have been cleared. If a wake-up event occurred during the processing of the prcm interrupt handler, after the corresponding PM_WKST_x register was checked but before the PRM_IRQSTATUS_MPU was cleared, then the CPU would be stuck forever waiting for bit 0 in PRM_IRQSTATUS_MPU to be cleared. 2). Waiting for the PM_WKST_x register to clear. Some power domains have more than one wake-up source. The PM_WKST_x registers indicate the source of a wake-up event and need to be cleared after a wake-up event occurs. When the PM_WKST_x registers are read and before they are cleared, it is possible that another wake-up event could occur causing another bit to be set in one of the PM_WKST_x registers. If this did occur after reading a PM_WKST_x register then the CPU would miss this event and get stuck forever in a loop waiting for that PM_WKST_x register to clear. This patch address the above race conditions that would result in a hang. Signed-off-by: Jon Hunter <jon-hunter@ti.com> Reviewed-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * | | omap: iovmm: Add missing mutex_unlockDaniel Walker2009-10-061-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I was using Coccinelle with the mutex_unlock semantic patch, and it unconvered this problem. It appears to be a valid missing unlock issue. This change should correct it by moving the unlock below the label. This patch is against the mainline kernel. Cc: Julia Lawall <julia@diku.dk> Cc: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> Signed-off-by: Daniel Walker <dwalker@fifo99.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | | omap: iovmm: Fix incorrect spellingHiroshi DOYU2009-10-061-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix incorrect spelling Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | | omap: SRAM: flush the right address after memcpy in omap_sram_pushye janboe2009-10-061-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | the original flush operation is to flush the function address which is copied from. But we do not change the function code and it is not necessary to flush it. Signed-off-by: janboe <janboe.ye@gmail.com> Acked-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | | omap: Lock DPLL5 at bootRajendra Nayak2009-10-051-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Lock DPLL5 at 120MHz at boot. The USBHOST 120MHz f-clock and USBTLL f-clock are the only users of this DPLL, and 120MHz is is the only recommended rate for these clocks. With this patch, the 60 MHz ULPI clock is generated correctly. Tested on an OMAP3430 SDP. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Anand Gadiyar <gadiyar@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | | omap: Fix incorrect 730 vs 850 detectionTony Lindgren2009-10-051-23/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit cd92204924fafbd5c7241dfd12ca3176d542e0c5 added support for omap850. However, the patch accidentally removed the wrong ifdef: # define cpu_is_omap730() 1 # endif #endif +#else +# if defined(CONFIG_ARCH_OMAP850) +# undef cpu_is_omap850 +# define cpu_is_omap850() 1 +# endif +#endif ... void omap2_check_revision(void); #endif /* defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) */ - -#endif Instead of removing removing the #endif at the end of the file, the #endif before #else should have been removed. But we cannot have multiple #else statements as pointed out by Alistair Buxton <a.j.buxton@gmail.com>. So the fix is to: - remove the non-multi-omap special handling, as we need to detect between omap730 and omap850 anyways. - add the missing #endif back to the end of the file Reported-by: Sanjeev Premi <premi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | | | ARM: Add kmap_atomic type debuggingRussell King2009-10-111-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Seemingly this support was missed when highmem was added, so DEBUG_HIGHMEM wouldn't have checked the kmap_atomic type. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | ARM: boolean bit testingJohannes Weiner2009-10-111-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bit testing (test, testset, testclear, testchange) for bit numbers known at compile time returns a word with the tested-for bit set. Change it to return a true boolean value so to make it consistent with the out-of-line path and all the other bitops implementations. Signed-off-by: Johannes Weiner <hannes@cmpxchg.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | ARM: update die() outputRussell King2009-10-111-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make die() better match x86: - add printing of the last accessed sysfs file - ensure console_verbose() is called under the lock - ensure we panic outside of oops_exit() Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | ARM: Dump code/mem oops lines with the appropriate log levelRussell King2009-10-111-16/+17
| | | | | | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | ARM: Dump memory and backtrace as one printk per lineRussell King2009-10-111-19/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dump_mem and dump_backtrace were both using multiple printk statements to print each line. With DEBUG_LL enabled, this causes OOPS to become very difficult to read. Solve this by only using one printk per line. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | ARM: 5756/1: ep93xx: introduce clk parentHartley Sweeten2009-10-101-47/+119
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The clock generation system in the ep93xx uses two external oscillator's and two internal PLLs to derive all the internal clocks. Many of these internal clocks can be stopped to save power. This introduces a "parent" hierarchy for the clocks so that the users count can be correctly tracked for power management. The "parent" for the video clock can either be one of the PLL outputs or the external oscillator. In order to correctly track the "parent" for the video clock calc_clk_div() needed to be modified. It now returns an error code if the desired rate cannot be generated. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Acked-by: Ryan Mallon <ryan@bluewatersys.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | ARM: 5754/1: ep93xx: update i2c supportHartley Sweeten2009-10-104-16/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the ep93xx i2c support: 1) The platform init code passes the configuration data for the i2c-gpio driver. This allows any gpio pin do be used for the sda and scl pins. It also allows the platform to specify the udelay and timeout. 2) Program the gpio configuration register to enable/disable the open drain drivers. Note that this really only works if the sda and scl pins are set to EP93XX_GPIO_LINE_EEDAT and EP93XX_GPIO_LINE_EECLK. 3) Update the edb93xx.c platform init to use the new support. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Acked-by: Ryan Mallon <ryan@bluewatersys.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | ARM: 5753/1: ep93xx: remove old EP93XX_GPIO_* definesHartley Sweeten2009-10-101-12/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most of the EP93XX_GPIO_*_INT_* register defines in ep93xx-regs.h not required due to how the ep93xx core and gpiolib support handle gpio interrupts. Remove the defines to prevent future confusion. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Acked-by: Ryan Mallon <ryan@bluewatersys.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | ARM: 5729/1: ep93xx: define EP93XX_*_PHYS_BASE with macrosHartley Sweeten2009-10-071-8/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change the #define's for the EP93XX_*_PHYS_BASE addresses to use macros for easier readability. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Acked-by: Ryan Mallon <ryan@bluewatersys.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | ARM: 5751/1: ep93xx/micro9: Add Micro9-SlimHubert Feurstein2009-10-072-1/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Contec Micro9-Slim support Cc: Ryan Mallon <ryan@bluewatersys.com> Requires: 5750/1 Signed-off-by: Hubert Feurstein <hubert.feurstein@contec.at> Acked-by: H Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | ARM: 5750/1: ep93xx/micro9: Update platform codeHubert Feurstein2009-10-073-58/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update Contec Micro9 platform code Cc: Ryan Mallon <ryan@bluewatersys.com> Requires: 5749/1 Signed-off-by: Hubert Feurstein <hubert.feurstein@contec.at> Acked-by: H Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | ARM: 5749/1: ep93xx/micro9: Update maintainerHubert Feurstein2009-10-071-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update Contec Micro9 maintainer and add entry in MAINTAINERS Cc: Ryan Mallon <ryan@bluewatersys.com> Requires: 5744/1 Signed-off-by: Hubert Feurstein <hubert.feurstein@contec.at> Acked-by: H Hartley Sweeten <hsweeten@visionengravers.com> Acked-by: Manfred Gruber <m.gruber@tirol.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | ARM: 5752/1: SA1100: fix building of h3100Dmitry Artamonow2009-10-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Both iPaqs h3100 and h3600 currently share the same source file - h3600.c But Makefile builds it only if CONFIG_SA1100_H3600 selected, so selecting just CONFIG_SA1100_H3100 results in "no machine record defined" message and aborted compilation. Fix it. Signed-off-by: Dmitry Artamonow <mad_soft@inbox.ru> Acked-by: Kristoffer Ericson <kristoffer.ericson@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | ARM: 5748/1: bcmring: fix build warning messagesLeo Chen2009-10-072-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the warning messages during kernel build for bcmring. Signed-off-by: Leo Hao Chen <leochen@broadcom.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | ARM: 5747/1: Fix the start_pg value in free_memmap()Catalin Marinas2009-10-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If sparsemem is enabled, the start_pfn passed to the free_memmap() function corresponds to an area of memory not known to the kernel and pfn_to_page returns a wrong value. The (start_pfn - 1), however, is known to the kernel. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | ARM: 5746/1: Handle possible translation errors in ARMv6/v7 coherent_user_rangeCatalin Marinas2009-10-072-4/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is needed because applications using the sys_cacheflush system call can pass a memory range which isn't mapped yet even though the corresponding vma is valid. The patch also adds unwinding annotations for correct backtraces from the coherent_user_range() functions. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | ARM: 5745/1: Change ep93xx gpio_irq static inlines to macrosHartley Sweeten2009-10-071-12/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From: Ryan Mallon <ryan@bluewatersys.com> Change the gpio_to_irq and irq_to_gpio static inline functions to macros so that they can be used in variable initialisers. Signed-off-by: Ryan Mallon <ryan@bluewatersys.com> Acked-by: H Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | ARM: 5744/1: ep93xx: add remaining phys offset selectionsHartley Sweeten2009-10-073-2/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the missing Kconfig options for the first SDRAM bank address on ep93xx boards. Cc: Hubert Feurstein <(address hidden)> Signed-off-by: H Hartley Sweeten <(address hidden)> Acked-by: Ryan Mallon <(address hidden)> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | ARM: 5742/1: ARM: add debug check for invalid kernel page faultsImre Deak2009-10-051-0/+5
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the following in arch/arm/mm/fault.c page faults from kernel mode are invalid if mmap_sem is already held and there is no exception handler defined for the faulting instruction: /* * As per x86, we may deadlock here. However, since the kernel only * validly references user space from well defined areas of the code, * we can bug out early if this is from code which shouldn't. */ if (!down_read_trylock(&mm->mmap_sem)) { if (!user_mode(regs) && !search_exception_tables(regs->ARM_pc)) goto no_context; Since mmap_sem can be held at arbitrary times by another thread this also means that any page faults from kernel mode are invalid if no exception handler is defined for them, regardless whether mmap_sem is held at the time of fault. To easier detect code that can trigger the above error, add a check also for the case where mmap_sem is acquired. As this has an overhead make it a VM debug check. Signed-off-by: Imre Deak <imre.deak@nokia.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | Merge master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2009-10-0256-253/+721
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * master.kernel.org:/home/rmk/linux-2.6-arm: (25 commits) ARM: 5728/1: Proper prefetch abort handling on ARMv6 and ARMv7 ARM: 5727/1: Pass IFSR register to do_PrefetchAbort() ARM: 5740/1: fix valid_phys_addr_range() range check ARM: 5739/1: ARM: allow empty ATAG_CORE ARM: 5735/1: sa1111: CodingStyle cleanups ARM: 5738/1: Correct TCM documentation ARM: 5734/1: arm: fix compilation of entry-common.S for older CPUs ARM: 5733/1: fix bcmring compile error ARM: 5732/1: remove redundant include file ARM: 5731/2: Fix U300 generic GPIO, remove ifdefs from MMCI v3 ARM: Ensure do_cache_op takes mmap_sem ARM: Fix __cpuexit section mismatch warnings ARM: Don't allow highmem on SMP platforms without h/w TLB ops broadcast ARM: includecheck fix: mach-davinci, board-dm365-evm.c ARM: Remove unused CONFIG SA1100_H3XXX ARM: Fix warning: unused variable 'highmem' ARM: Fix warning: #warning syscall migrate_pages not implemented ARM: Fix SA11x0 clocksource warning ARM: Fix SA1100 Neponset serial section mismatch ARM: Fix SA1100 Assabet/Neponset PCMCIA section mismatch warnings ...
| * | | ARM: 5728/1: Proper prefetch abort handling on ARMv6 and ARMv7Kirill A. Shutemov2009-10-021-1/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, on ARMv6 and ARMv7, if an application tries to execute code (or garbage) on non-executable page it hangs. It caused by incorrect prefetch abort handling. Now every prefetch abort processes as a translation fault. To fix this we have to analyze instruction fault status register to figure out reason why we've got the abort and process it accordingly. To make IFSR different from DFSR we set bit 31 which is reserved in both IFSR and DFSR. This patch also tries to protect from future hangs on unexpected exceptions. An application will be killed if unexpected exception type was received. Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | ARM: 5727/1: Pass IFSR register to do_PrefetchAbort()Kirill A. Shutemov2009-10-0233-78/+144
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instruction fault status register, IFSR, was introduced on ARMv6 to provide status information about the last insturction fault. It needed for proper prefetch abort handling. Now we have three prefetch abort model: * legacy - for CPUs before ARMv6. They doesn't provide neither IFSR nor IFAR. We simulate IFSR with section translation fault status for them to generalize code; * ARMv6 - provides IFSR, but not IFAR; * ARMv7 - provides both IFSR and IFAR. Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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