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* davinci: Add I2C0 devices to MityDSP-L138/MityARM-1808 platformMichael Williamson2010-09-241-0/+145
| | | | | | | | | | This patch adds the i2c0 bus and attached devices to the MityDSP-L138 and MityARM-1808 davinci SoM. Included is a TPS65023 voltage regulator needed for power management and a small 24c02 EPROM that contains factory configuration data. Signed-off-by: Michael Williamson <michael.williamson@criticallink.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: add idcode for tnetv107x rev 1.1/1.2Cyril Chemparathy2010-09-241-1/+8
| | | | | | | | This patch adds an entry into the idcode table for tnetv107x silicon revision 1.1 and 1.2 devices. Signed-off-by: Cyril Chemparathy <cyril@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: Initial support for MityDSP-L138/MityARM-1808Michael Williamson2010-09-245-0/+232
| | | | | | | | | | | | | This patch adds initial support for the MityDSP-L138 and MityDSP-1808 system on Module (SOM) under the machine name "mityomapl138". These SOMs are based on the da850 davinci CPU architecture. Information on these SOMs may be found at http://www.mitydsp.com. Basic support for the console UART, NAND, and EMAC (MII interface) is included in this patch. Signed-off-by: Michael Williamson <michael.williamson@criticallink.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: Add CONFIG_REGULATOR_DUMMY to DA8XX defconfig file.Michael Williamson2010-09-241-0/+1
| | | | | | | | | In order to support reference DA8XX machines not providing a voltage regulator control for the core voltage, the REGULATOR_DUMMY option is required. Signed-off-by: Michael Williamson <michael.williamson@criticallink.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: Add machine checks to DA8XX serial console init routinesMichael Williamson2010-09-242-0/+6
| | | | | | | | | | This patch adds machine checks in the serial console init routines for the DA8XX EVM boards. This is needed because there are other DA8XX based machines that use a different UART/tty as the console and may be included in a common kernel build. Signed-off-by: Michael Williamson <michael.williamson@criticallink.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: dm6467t evm: setup NAND flash timingSekhar Nori2010-09-241-0/+14
| | | | | | | | | | | | | | | Setup NAND flash timing on DM6467T EVM. Without the timing setup, the NAND flash on DM6467T RevC EVM reports a number of random bad blocks because of read errors. Also, with this, copying a 100M file on RevB EVM takes ~35 sec against 1 minute 30 seconds earlier. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Acked-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: am18x/da850/omap-l138 evm: setup NAND flash timingSekhar Nori2010-09-241-0/+12
| | | | | | | | | | | | | | | | | | Setup the NAND flash timings for DA850 EVM Before configuring the timing values, throughput calculation using dd command yielded 469 kB/s write and 966 kB/s read speed. After the timing configuration, the throughput was measured to be 2.4 MB/s write and 5 MB/s read. [Mukul Bhatnagar: actual calculation of timing values from the NAND datasheet] Signed-off-by: Sekhar Nori <nsekhar@ti.com> Cc: Mukul Bhatnagar <mbhatnagar@ti.com> Acked-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: am17x/da830/omap-l137 evm: setup NAND flash timingSudhakar Rajashekhara2010-09-241-0/+12
| | | | | | | | | | | | | | | | | | | Setup the NAND flash timings for DA830 EVM. Before configuring the timing values, throughput calculation using dd command yielded 477 kB/s write and 970 kB/s read speed. After the timing configuration, the throughput was measured to be 2.5 MB/s write and 5.1 MB/s read. [Mukul Bhatnagar: actual calculation of timing values from the NAND datasheet] Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Cc: Mukul Bhatnagar <mbhatnagar@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Acked-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: dm644x evm: setup NAND flash timingSekhar Nori2010-09-241-0/+12
| | | | | | | | | | | | | | | | | | The DM644x EVM nand flash timing was earlier being done as a special case in the NAND driver itself. With the NAND driver now capable of progamming the AEMIF interface using timing data passed from the platform, the timing values are being moved into their rightful place in the EVM specific board file. The values being programmed match what was being done earlier and thus do not represent any change in performance/functionality. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Acked-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* nand: davinci: add support for timing configurationSekhar Nori2010-09-241-0/+3
| | | | | | | | | | | | | | | | | | | | | This patch modifies the DaVinci NAND driver to use the new AEMIF timing setup API to configure the NAND access timings. Earlier, AEMIF configuration was being done as a special case for DM644x board, but now more boards emerge which have capability to boot for other media (SPI flash, NOR flash) and have the kernel access NAND flash. This means that kernel cannot always depend on the bootloader to setup the NAND. Also, on platforms such as da850/omap-l138, the aemif input frequency changes as cpu frequency changes; necessiating re-calculation of timimg values as part of cpufreq transtitions. This patch forms the basis for adding that support. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Acked-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com>
* davinci: add support for aemif timing configurationSekhar Nori2010-09-244-4/+170
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support to configure the AEMIF interface with supplied timing values. Since this capability is useful both from NOR and NAND flashes, it is provided as a new interface and in a file of its own. AEMIF timing configuration is required in cases: 1) Where the AEMIF clock rate can change at runtime (a side affect of cpu frequency change). 2) Where U-Boot does not support NAND/NOR but supports other media like SPI Flash or MMC/SD and thus does not care about setting up the AEMIF timing for kernel to use. 3) Where U-Boot just hasn't configured the timing values and cannot be upgraded because the box is already in the field. Since there is now a header file for AEMIF interface, the common (non-NAND specific) defines for AEMIF registers have been moved from nand.h into the newly created aemif.h Signed-off-by: Sekhar Nori <nsekhar@ti.com> Acked-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: dm365 evm: use EDMAQ_3 as the audio DMA queueSekhar Nori2010-09-241-1/+3
| | | | | | | | | | | | | | By default the audio driver uses EDMAQ_0 as the DMA queue, but on DM365 this queue is specially designed for video transfers with a large fifo size. Having both audio and video transfers on the same queue leads to noise on the audio side. This patch changes the audio queue number for DM365 to EDMAQ_3. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* DA850: Add MMCSD1 resources, platform device and convenience registration ↵Juha Kuikka2010-09-242-0/+40
| | | | | | | | | function Add resources, platform device and convenience registration function for DA850's second MMC/SD controller (MMCSD1). Signed-off-by: Juha Kuikka <juha.kuikka@elektrobit.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* DA850: Split MMCSD clock into two to support both MMCSD peripheralsJuha Kuikka2010-09-241-3/+11
| | | | | | | | Split mmcsd_clk into mmcsd0_clk and mmcsd1_clk and add davinci_mmc.1 in preparation for adding support for MMCSD1 peripheral in DA850. Signed-off-by: Juha Kuikka <juha.kuikka@elektrobit.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* DA850: Add LPSC id for MMCSD1 peripheralJuha Kuikka2010-09-241-0/+1
| | | | | | | Add LPSC id for DA850's MMCSD1 peripheral. Signed-off-by: Juha Kuikka <juha.kuikka@elektrobit.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* arm: mach-davinci: check irq2ctlr() resultKulikov Vasiliy2010-09-241-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | If irq2ctlr() fails return IRQ_NONE. Also as it can fail make 'ctlr' signed. The semantic patch that finds this problem (many false-positive results): (http://coccinelle.lip6.fr/) // <smpl> @ r1 @ identifier f; @@ int f(...) { ... } @@ identifier r1.f; type T; unsigned T x; @@ *x = f(...) ... *x > 0 Signed-off-by: Kulikov Vasiliy <segooon@gmail.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* DA850: move MII/RMII pin lists to the board fileSergei Shtylyov2010-09-243-12/+22
| | | | | | | | | | | | The CPGMAC pin list in da850.c was incorrectly split into two MII/RMII mode specific pin lists, while what pin group is used is a function of how the board is wired. Copy the pin lists to board-da850-evm.c, renaming them accordingly, and merge the two lists in da850.c into one, da850_cpgmac_pins[], representing the CPGMAC module as a whole... Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Tested-by: Ben Gardiner <bengardiner@nanometrics.ca> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* DA850: move NAND/NOR pin lists to the board fileSergei Shtylyov2010-09-243-25/+40
| | | | | | | | | | | | | | | The NAND/NOR flash pin lists (da850_nand_pins/da850_nor_pins) are purely board specific and as such shouldn't be in da850.c -- copy them to board-da850-evm.c, renaming to da850_evm_nand_pins/da850_evm_nor_pins respectively, and merge the two lists in da850.c into one, representing the EMIF 2.5 module as a whole, just like we have it in da830.c... While at it, remove the '__init' modifier from da850_evm_setup_nor_nand() as this function is called from non '__init' code... Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Tested-by: Ben Gardiner <bengardiner@nanometrics.ca> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* Davinci: tnetv107x: retain psc reg base after initCyril Chemparathy2010-09-241-1/+1
| | | | | | | | | This is a bugfix for the original tnetv107x submission series. The psc_regs base array was being discarded post-init, and this was causing a crash during post-init clock enable/disable. Signed-off-by: Cyril Chemparathy <cyril@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: am18x/da850/omap-l138: keep async clock constant with cpufreqSekhar Nori2010-09-243-3/+11
| | | | | | | | | Keep PLL0 SYSCLK3 at a constant rate of 100MHz. This enables the AEMIF timing to remain valid even as the PLL0 output is changed by cpufreq driver to save power. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: cpufreq: add support for keeping an additional clock constantSekhar Nori2010-09-241-0/+18
| | | | | | | | | | | | | | | | On OMAP-L138 SoC, some of the sysclks need not be at a fixed ratio to CPU clock and can be kept at a relatively constant rate by adjusting the PLLDIVn ratio even as cpufreq goes ahead and changes the CPU clock. This feature can be used to keep the EMIFA (PLL0 SYSCLK3) clock at a constant rate so that the EMIF timings need not be re-programmed whenever the CPU frequency changes. This patch adds the required suppport to cpufreq driver. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: clock: add support for setting sysclk rateSekhar Nori2010-09-242-0/+78
| | | | | | | | | | | | | | | Setting sysclk rate will be useful in cases where the sysclk is not at a fixed ratio to the PLL output but can asynchronously be changed. This support forms the basis of attempt to keep the AEMIF clock constant on OMAP-L138 even as PLL0 output changes as ARM clock is changed to save power. This patch has been tested on OMAP-L138. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: dm365: disable pulldowns for all MMC/SD1 pins.Sekhar Nori2010-09-241-1/+1
| | | | | | | | | | | | | This patch disables internal pulldowns for all MMC/SD1 pins. Presently only MMCSD1_CMD pin's pull down is disabled, but with this some MMC/SD cards do not get detected on MMC/SD1 slot of the EVM. The problem was reproducible with SanDisk 4GB SDHC card. Reported-by: Stephane Bovagne <s-bovagne@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: am18x/da850/omap-l138: use 'NOM' voltage defined in datasheet as ↵Sekhar Nori2010-09-241-3/+3
| | | | | | | | | | | | | | | | | | min voltage For each DA850 OPP, the normal ('NOM') voltage defined in the tecnical reference manual (TRM) is actually the minimum voltage the frequency is supported at. The minimum ('MIN') voltage defined in TRM is meant to take care of voltage fluctuations and the device should not be run at this voltage for extended periods of time. Fix the OPP definitions to define the cvdd_min as the normal voltage defined in the datasheet. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: introduce support for AM1x ARM9 microprocessorsSekhar Nori2010-09-243-17/+17
| | | | | | | | | | | | | | | | | | | | | | | | | The Sitara AM17x SoCs from TI are an OMAP-L137 pin-to-pin compatible ARM9 microprocessor offering from TI. The Sitara AM18x SoCs from TI are an OMAP-L138 pin-to-pin compatible ARM9 microprocessor offering from TI. More information about these processors available at: www.ti.com/am1x Because of their compatibiliy with OMAP-L1x, the kernel support for OMAP-L1x is fully relevant to AM1x processors. This patch updates the Kconfig prompt and help text to include the AM1x part names to help users select configurations required for these parts easily. Also, the hardware information that shows up in /proc/cpuinfo is updated to show applicability of the respective OMAP-L1x EVMs for AM1x parts. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: clean up inconsistent usage of spaces in KconfigSekhar Nori2010-09-241-16/+16
| | | | | | | | | | | | | In arch/arm/mach-davinci/Kconfig, some of the configuration items are indented with multiple spaces instead of tabs. Also, in couple of places, two spaces are used in the middle of help text where one should do. This patch fixes both issues. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: cpufreq: bailout on regulator errorsSekhar Nori2010-09-242-3/+9
| | | | | | | | | | | | | | | | | | | | | | Current cpufreq code does not consider errors that can occur while changing voltage. Code to increase CPU frequency goes ahead even in the case the regulator has failed to increase the voltage. This leads to hard error since lower voltages cannot support increased frequency. Prevent this by not increasing frequency in case increasing voltage is not successful. Also, do not lower the voltage if changing the cpu frequency has failed for some reason. Note that we do not return error on failure to decrease voltage as that is not a hard error. Build fix for non-cpufreq kernels by Caglar Akyuz. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Cc: Caglar Akyuz <caglar@bilkon-kontrol.com.tr> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: clock: make 'disable unused clocks' printk debug onlyKevin Hilman2010-09-241-1/+1
| | | | | | | The long list of clocks being disabled on boot is noisy and not needed for standard boots. Make this a debug printk instead. Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: da850 evm: sparse cleanup: make file local variables staticSekhar Nori2010-09-241-7/+7
| | | | | | | | | | | | | | | Without this cleanup, sparse checker reports warnings of the type: CHECK arch/arm/mach-davinci/board-da850-evm.c arch/arm/mach-davinci/board-da850-evm.c:112:22: warning: symbol 'da850_evm_nandflash_partition' was not declared. Should it be static? The nand flash partitions and regulator supplies are used within the EVM file and so should have been static This patch has been boot tested on DA830 and DA850 EVMs. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* Merge branch 's5p-fixes-for-linus' of ↵Linus Torvalds2010-09-199-66/+107
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung * 's5p-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: S3C64XX: Add IORESOURCE_IRQ_HIGHLEVEL flag to dm9000 on mach-real6410 ARM: S3C64XX: Fix coding style errors on mach-real6410 ARM: S3C64XX: Prototype SPI devices ARM: S3C64XX: Fix dev-spi build ARM: SAMSUNG: Fix on s5p_gpio_[get,set]_drvstr ARM: SAMSUNG: Fix on drive strength value ARM: S5PV210: Add FIMC clocks ARM: S5PV210: Reduce the iodesc length of systimer ARM: S5PV210: Update I2C-1 Clock Register Property. ARM: S5P: Decrease IO Registers memory region size on FIMC ARM: S5P: Fix DMA coherent mask for FIMC
| * ARM: S3C64XX: Add IORESOURCE_IRQ_HIGHLEVEL flag to dm9000 on mach-real6410Darius Augulis2010-09-181-1/+1
| | | | | | | | | | | | | | | | | | Add IORESOURCE_IRQ_HIGHLEVEL irq flag to dm9000 driver platform data in board mach-real6410. Signed-off-by: Darius Augulis <augulis.darius@gmail.com> [kgene.kim@samsung.com: minor title fix] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * ARM: S3C64XX: Fix coding style errors on mach-real6410Darius Augulis2010-09-181-52/+52
| | | | | | | | | | | | | | | | Fix errors reported by checkpatch.pl script Signed-off-by: Darius Augulis <augulis.darius@gmail.com> [kgene.kim@samsung.com: minor title fix] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * ARM: S3C64XX: Prototype SPI devicesMark Brown2010-09-181-0/+1
| | | | | | | | | | | | | | Avoids build warnings due to the undeclared non-statics. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * ARM: S3C64XX: Fix dev-spi buildMark Brown2010-09-141-1/+1
| | | | | | | | | | | | | | | | The irqs.h usage here got missed in the Samsung platform reorganisation. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: Jassi Brar <jassi.brar@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * ARM: SAMSUNG: Fix on s5p_gpio_[get,set]_drvstrKukjin Kim2010-09-141-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes bug on gpio drive strength helper function. The offset should be like follwoing. - off = chip->chip.base - pin; + off = pin - chip->chip.base; In the s5p_gpio_get_drvstr(), the second line is unnecessary, because overwrite drvstr. drvstr = __raw_readl(reg); - drvstr = 0xffff & (0x3 << shift); And need 2bit masking before return the drvstr value. drvstr = drvstr >> shift; + drvstr &= 0x3; In the s5p_gpio_set_drvstr(), need relevant bit clear. tmp = __raw_readl(reg); + tmp &= ~(0x3 << shift); tmp |= drvstr << shift; Reported-by: Jaecheol Lee <jc.lee@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * ARM: SAMSUNG: Fix on drive strength valueKukjin Kim2010-09-141-5/+5
| | | | | | | | | | | | | | | | | | | | This patch fixes on defined drive strength value for GPIO. According to data sheet, if we want drive strength 1x, the value should be 00(b), if 2x should be 10(b), if 3x should be 01(b), and if 4x should be 11(b). Also fixes comment(from S5C to S5P). Reported-by: Janghyuck Kim <janghyuck.kim@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * ARM: S5PV210: Add FIMC clocksMarek Szyprowski2010-09-141-0/+18
| | | | | | | | | | | | | | | | | | | | These clocks enables FIMC driver to operate on machines, which bootloader power gated FIMC devices to save power on boot. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> [kgene.kim@samsung.com: minor title fix] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * ARM: S5PV210: Reduce the iodesc length of systimerKyungmin Park2010-09-141-1/+1
| | | | | | | | | | | | | | It's enough to use 4KiB. Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * ARM: S5PV210: Update I2C-1 Clock Register Property.MyungJoo Ham2010-09-141-1/+1
| | | | | | | | | | | | | | | | | | | | CLK_GATE_IP3[8] is RESERVED. The port "I2C_HDMI_DDC" of CLK_GATE_IP3[10] is used as another I2C port. Therefore, defined the unused I2C-1 as another I2C there was left undefined but used. Signed-off-by: MyungJoo Ham <myungjoo.ham@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * ARM: S5P: Decrease IO Registers memory region size on FIMCSylwester Nawrocki2010-09-143-3/+3
| | | | | | | | | | | | | | | | | | | | | | IO registers region size of all FIMC versions is less than 1kB so there is no need to reserve 1M. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> [kgene.kim@samsung.com: minor title fix] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * ARM: S5P: Fix DMA coherent mask for FIMCMarek Szyprowski2010-09-143-0/+21
| | | | | | | | | | | | | | | | | | | | FIMC driver uses DMA_coherent allocator, which requires proper dma mask to be set. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> [kgene.kim@samsung.com: minor title fix] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* | arm: fix really nasty sigreturn bugAl Viro2010-09-171-0/+2
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If a signal hits us outside of a syscall and another gets delivered when we are in sigreturn (e.g. because it had been in sa_mask for the first one and got sent to us while we'd been in the first handler), we have a chance of returning from the second handler to location one insn prior to where we ought to return. If r0 happens to contain -513 (-ERESTARTNOINTR), sigreturn will get confused into doing restart syscall song and dance. Incredible joy to debug, since it manifests as random, infrequent and very hard to reproduce double execution of instructions in userland code... The fix is simple - mark it "don't bother with restarts" in wrapper, i.e. set r8 to 0 in sys_sigreturn and sys_rt_sigreturn wrappers, suppressing the syscall restart handling on return from these guys. They can't legitimately return a restart-worthy error anyway. Testcase: #include <unistd.h> #include <signal.h> #include <stdlib.h> #include <sys/time.h> #include <errno.h> void f(int n) { __asm__ __volatile__( "ldr r0, [%0]\n" "b 1f\n" "b 2f\n" "1:b .\n" "2:\n" : : "r"(&n)); } void handler1(int sig) { } void handler2(int sig) { raise(1); } void handler3(int sig) { exit(0); } main() { struct sigaction s = {.sa_handler = handler2}; struct itimerval t1 = { .it_value = {1} }; struct itimerval t2 = { .it_value = {2} }; signal(1, handler1); sigemptyset(&s.sa_mask); sigaddset(&s.sa_mask, 1); sigaction(SIGALRM, &s, NULL); signal(SIGVTALRM, handler3); setitimer(ITIMER_REAL, &t1, NULL); setitimer(ITIMER_VIRTUAL, &t2, NULL); f(-513); /* -ERESTARTNOINTR */ write(1, "buggered\n", 9); return 1; } Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk> Cc: stable@kernel.org Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Merge branch 'at91-fixes-for-linus' of git://github.com/at91linux/linux-2.6-at91Linus Torvalds2010-09-104-19/+36
|\ | | | | | | | | | | | | | | | | | | * 'at91-fixes-for-linus' of git://github.com/at91linux/linux-2.6-at91: AT91: at91sam9261ek: remove C99 comments but keep information AT91: at91sam9261ek board: remove warnings related to use of SPI or SD/MMC AT91: dm9000 initialization update AT91: SAM9G45 - add a separate clock entry for every single TC block AT91: clock: peripheral clocks can have other parent than mck AT91: change dma resource index
| * AT91: at91sam9261ek: remove C99 comments but keep informationNicolas Ferre2010-09-101-4/+2
| | | | | | | | Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
| * AT91: at91sam9261ek board: remove warnings related to use of SPI or SD/MMCNicolas Ferre2010-09-101-11/+19
| | | | | | | | | | | | | | | | | | The sd/mmc data structure is not used if SPI is selected. The configuration of PIO on the board prevent from using both interfaces at the same time (board dependent). Remove the warnings at compilation time adding a preprocessor condition. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
| * AT91: dm9000 initialization updateNicolas Ferre2010-09-101-1/+2
| | | | | | | | | | | | | | | | Add information in dm9000 mac/phy chip initialization: - irq resource details - platform data details Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
| * AT91: SAM9G45 - add a separate clock entry for every single TC blockFabian Godehardt2010-09-092-5/+14
| | | | | | | | | | | | | | | | | | | | | | Without this patch you will not be able to register the first block because of the second association call on at91_add_device_tc(). Signed-off-by: Fabian Godehardt <fg@emlix.com> [nicolas.ferre@atmel.com: change tcb1_clk to fake child clock of tcb0_clk] Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Andrew Victor <linux@maxim.org.za> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
| * AT91: clock: peripheral clocks can have other parent than mckNicolas Ferre2010-09-091-1/+2
| | | | | | | | | | | | | | | | | | | | While registering clock allow to set parent clock other than mck. It is useful for clocks than can be seen as child clock of a peripheral. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Andrew Victor <linux@maxim.org.za>
| * AT91: change dma resource indexNicolas Ferre2010-09-071-1/+1
| | | | | | | | | | Reported-by: Dan Liang <dan.liang@atmel.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
* | ARM: Update mach-typesRussell King2010-09-091-2/+96
| | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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