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* OMAP: Fix IOMEM macro for assemblyTony Lindgren2009-06-231-1/+1
| | | | | | Otherwise IOMEM calculations can fail. Signed-off-by: Tony Lindgren <tony@atomide.com>
* OMAP2/3: Initialize gpio debounce registerjanboe2009-06-231-0/+1
| | | | | | | | | | Some bootloader may initialize debounce register and this will make dbclk not consist with the debounce register after linux kernel boot up. Signed-off-by: janboe <janboe.ye@gmail.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* OMAP: IOMMU: function flush_iotlb_page is not flushing correct entryFernando Guzman Lugo2009-06-231-1/+1
| | | | | | | | | The function flush_iotlb_page is not loading the CAM register with the correct entry to be flushed, so it is flushing other entry Signed-off-by: Fernando Guzman Lugo <x0095840@ti.com> Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* OMAP3: DMA: Enable idlemodes for DMA OCPKalle Jokiniemi2009-06-232-0/+28
| | | | | | | | | This patch enables MStandby smart-idle mode, autoidle smartidle mode, and the autoidle bit for DMA4_OCP_SYSCONFIG. Signed-off-by: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Kevin Hilman <khilman@ti.deeprootsystems.com>
* OMAP3: SRAM size fix for HS/EMU devicesTero Kristo2009-06-231-1/+6
| | | | | | | | SRAM size fix for HS/EMU devices Signed-off-by: Tero Kristo <tero.kristo@nokia.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* OMAP2/3: Add omap_type() for determining GP/EMU/HSKevin Hilman2009-06-231-11/+11
| | | | | | | | | | | | | | | The omap_type() function is added and returns the DEVICETYPE field of the CONTROL_STATUS register. The result can be used for conditional code based on whether device is GP (general purpose), EMU or HS (high security). Also move the type defines so omap1 code compile does not require ifdefs for sections using these defines. This code is needed for the following fix to set the SRAM size correctly for HS omaps. Also at least PM and watchdog code will need this function. Signed-off-by: Kevin Hilman <khilman@ti.deeprootsystems.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* Merge branch 'omap-clock-for-next' of git://git.pwsan.com/linux-2.6 into develRussell King2009-06-202-5/+9
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| * OMAP3: Add support for DPLL3 divisor values higher than 2Tero Kristo2009-06-192-5/+7
| | | | | | | | | | | | Previously only 1 and 2 was supported. This is needed for DVFS VDD2 control. Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
| * OMAP3 clock/SDRC: program SDRC_MR register during SDRC clock changePaul Walmsley2009-06-192-5/+5
| | | | | | | | | | | | | | | | | | Program the SDRC_MR_0 register as well during SDRC clock changes. This register allows selection of the memory CAS latency. Some SDRAM chips, such as the Qimonda HYB18M512160AF6, have a lower CAS latency at lower clock rates. Signed-off-by: Paul Walmsley <paul@pwsan.com>
| * OMAP3 clock: add a short delay when lowering CORE clk ratePaul Walmsley2009-06-192-5/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | When changing the SDRAM clock from 166MHz to 83MHz via the CORE DPLL M2 divider, add a short delay before returning to SDRAM to allow the SDRC time to stabilize. Without this delay, the system is prone to random panics upon re-entering SDRAM. This time delay varies based on MPU frequency. At 500MHz MPU frequency at room temperature, 64 loops seems to work okay; so add another 32 loops for environmental and process variation. Signed-off-by: Paul Walmsley <paul@pwsan.com>
* | Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2009-06-1443-553/+3241
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (417 commits) MAINTAINERS: EB110ATX is not ebsa110 MAINTAINERS: update Eric Miao's email address and status fb: add support of LCD display controller on pxa168/910 (base layer) [ARM] 5552/1: ep93xx get_uart_rate(): use EP93XX_SYSCON_PWRCNT and EP93XX_SYSCON_PWRCN [ARM] pxa/sharpsl_pm: zaurus needs generic pxa suspend/resume routines [ARM] 5544/1: Trust PrimeCell resource sizes [ARM] pxa/sharpsl_pm: cleanup of gpio-related code. [ARM] pxa/sharpsl_pm: drop set_irq_type calls [ARM] pxa/sharpsl_pm: merge pxa-specific code into generic one [ARM] pxa/sharpsl_pm: merge the two sharpsl_pm.c since it's now pxa specific [ARM] sa1100: remove unused collie_pm.c [ARM] pxa: fix the conflicting non-static declarations of global_gpios[] [ARM] 5550/1: Add default configure file for w90p910 platform [ARM] 5549/1: Add clock api for w90p910 platform. [ARM] 5548/1: Add gpio api for w90p910 platform [ARM] 5551/1: Add multi-function pin api for w90p910 platform. [ARM] Make ARM_VIC_NR depend on ARM_VIC [ARM] 5546/1: ARM PL022 SSP/SPI driver v3 ARM: OMAP4: SMP: Update defconfig for OMAP4430 ARM: OMAP4: SMP: Enable SMP support for OMAP4430 ...
| * | ARM: OMAP4: SMP: Add mpu timer support for OMAP4430Santosh Shilimkar2009-06-092-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds SMP platform specific parts for local(mpu) timer support for OMAP4430 platform. Each Cortex-a9 core has it's own local timer in the MPU domain. These timers are not in wakeup domain. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
| * | ARM: OMAP4: SMP: Add OMAP4430 SMP board filesSantosh Shilimkar2009-06-091-0/+51
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds SMP platform files support for OMAP4430SDP. TI's OMAP4430 SOC is based on ARM Cortex-A9 SMP architecture. It's a dual core SOC with GIC used for interrupt handling and SCU for cache coherency. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
| * | [ARM] Kconfig: remove 'default n'Russell King2009-05-311-3/+0
| | | | | | | | | | | | | | | | | | | | | Kconfig entries default to n, so there's no need for this to be explicitly specified. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | Merge branch 'for-next' of ↵Russell King2009-05-2935-550/+834
| |\ \ | | |/ | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6 into devel Conflicts: arch/arm/Makefile
| | * Merge branch 'omap4' into for-nextTony Lindgren2009-05-2823-60/+564
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| | | * ARM: OMAP4: Add support for 4430 SDPSantosh Shilimkar2009-05-281-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch updates the Makefile and Kconfig entries for OMAP4. The OMAP4430 SDP board file supports only minimal set of drivers. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | | * ARM: OMAP4: Clock stubs since CLKDEV not in yet.Santosh Shilimkar2009-05-281-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch update the common clock.c file for OMAP4. The clk_get() and clk_put() functions are moved to common place in arch/arm/common/clkdev.c Since on current OMAP4 platform clk management is still not supported, the platform file is stubbed with those functions. Once the framework is ready, this WILL be replaced with a full clkdev implementation. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | | * ARM: OMAP4: Add minimal support for omap4Santosh Shilimkar2009-05-2821-57/+523
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the support for OMAP4. The platform and machine specific headers and sources updated for OMAP4430 SDP platform. OMAP4430 is Texas Instrument's SOC based on ARM Cortex-A9 SMP architecture. It's a dual core SOC with GIC used for interrupt handling and SCU for cache coherency. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * | Merge branch 'omap3-upstream' into for-nextTony Lindgren2009-05-282-4/+4
| | |\ \ | | | |/ | | | | | | | | | | | | Conflicts: arch/arm/mach-omap2/serial.c
| | | * ARM: OMAP3: Initialize more devices for LDPTony Lindgren2009-05-281-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on an earlier patches by Stanley.Miao <stanley.miao@windriver.com> and Nishant Kamat <nskamat@ti.com>. Note that at the ads7846 support still needs support for vaux_control for the touchscreen to work. Signed-off-by: Tony Lindgren <tony@atomide.com>
| | | * ARM: OMAP2/3: Remove L4_WK_OMAP_BASE, L4_PER_OMAP_BASE, L4_EMU_BASE, ↵Tony Lindgren2009-05-281-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | L3_OMAP_BASE These are not being used right now, and the processor specific defines should be used instead by any code accessing these registers. Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * | Merge branch 'omap-upstream' into for-nextTony Lindgren2009-05-289-46/+142
| | |\ \ | | | |/ | | | | | | | | | | | | Conflicts: arch/arm/mach-omap2/Makefile
| | | * ARM: OMAP1: Make 770 LCD workAndrew de Quincey2009-05-281-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make 770 LCD work by adding clk_add_alias(). Also remove the old unused functions. Note that the clk_add_alias() could probably be moved to arch/arm/clkdev.c later on. Cc: linux-fbdev-devel@lists.sourceforge.net Signed-off-by: Andrew de Quincey <adq_dvb@lidskialf.net> Signed-off-by: Imre Deak <imre.deak@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com
| | | * ARM: OMAP2/3: Add generic smc91x support when connected to GPMCTony Lindgren2009-05-281-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the board-rx51 smc91x code to be generic and make the boards to use it. This allows future recalculation of the timings when the source clock gets scaled. Also correct the rx51 interrupt to be IORESOURCE_IRQ_HIGHLEVEL. Thanks to Paul Walmsley <paul@pwsan.com> for better GPMC timing calculations. Signed-off-by: Tony Lindgren <tony@atomide.com>
| | | * ARM: OMAP2/3: Add generic onenand support when connected to GPMCJuha Yrjola2009-05-281-2/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add generic onenand support when connected to GPMC and make the boards to use it. The patch has been modified to make it more generic to support all the boards with GPMC. The patch also remove unused prototype for omap2_onenand_rephase(void). Note that board-apollon.c is currently using the MTD_ONENAND_GENERIC and setting the GPMC timings in the bootloader. Setting the GPMC timings in the bootloader will not allow supporting frequency scaling for the onenand source clock. Signed-off-by: Tony Lindgren <tony@atomide.com>
| | | * ARM: OMAP2/3: sDMA: Correct omap_request_dma_chain(), v2Santosh Shilimkar2009-05-282-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Original OMAP DMA chaining design had chain_id as one of the callback parameters. Patch 538528de0cb256f65716ab2e9613d9e920f97fe2 changed it to use logical channel instead. Correct the naming for callback to also use logical channel number instead of the chain_id. More details are on this email thread: http://marc.info/?l=linux-omap&m=122961071931459&w=2 Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | | * ARM: OMAP2/3: DMA: implement trans copy and const fillTomi Valkeinen2009-05-282-28/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement transparent copy and constant fill features for OMAP2/3. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | | * ARM: OMAP: Update contact address of I2C registration helperJarkko Nikula2009-05-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This email address is going to expire soon so update it. Signed-off-by: Jarkko Nikula <jarkko.nikula@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | | * ARM: OMAP: McBSP: Fix legacy interrupts to clear their statusEero Nurkkala2009-05-251-6/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If XSYNCERR or RSYNCERR interrupts are enabled, they are never cleared causing the IRQ handler to be continuously called. This patch clears the IRQs in question in the event they are enabled and taken. Signed-off-by: Eero Nurkkala <ext-eero.nurkkala@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | | * ARM: OMAP: Increase VMALLOC_END to allow 256MB RAMMans Rullgard2009-05-252-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This increases VMALLOC_END to 0x18000000, making room for 256MB RAM with the default 128MB vmalloc region. Note that after this patch there's no longer a hole between vmalloc space and the beginning of IO space on omap2 as the first virtual mapping starts at 0xd8000000. Also fold in a related change from Paul Walmsley <paul@pwsan.com> to change the OMAP2_SRAM addresses accordingly. Signed-off-by: Mans Rullgard <mans@mansr.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Acked-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | | * ARM: OMAP: Remove unnecessary omap2_globals.Santosh Shilimkar2009-05-251-9/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes unnecessary omap2_globals and pass the global structures directly as function argument. The proposed cleanup was suggested by Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | | * ARM: OMAP: Remove useless omap_sram_error function.Santosh Shilimkar2009-05-251-20/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes fixes omap_sram_error() function and replace the error paths with BUG_ON. The proposed fix was suggested by Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | | * ARM: OMAP: Remove unwanted type casts and fix the compiler warning.Santosh Shilimkar2009-05-251-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes the compiler warning "assignment from incompatible pointer type" in dmtimer.c and removes the tye casts. These warnings were suppressed by type catsing. The proposed fix was suggested by Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | | * ARM: OMAP2/3: Remove OMAP_CM_REGADDRTony Lindgren2009-05-252-16/+0
| | | | | | | | | | | | | | | | | | | | | | | | Processor specific macros should be used instead. Signed-off-by: Tony Lindgren <tony@atomide.com>
| | | * ARM: OMAP2/3: Remove OMAP2_PRCM_BASETony Lindgren2009-05-251-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | It's currently unused, and processor specific defines should be used instead. Signed-off-by: Tony Lindgren <tony@atomide.com>
| | | * ARM: OMAP2/3: Move define of OMAP2_VA_IC_BASE to be local to entry-macro.STony Lindgren2009-05-253-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | Move define of OMAP2_VA_IC_BASE to be local to entry-macro.S Signed-off-by: Tony Lindgren <tony@atomide.com>
| | | * ARM: OMAP2/3: Remove OMAP_PRM_REGADDR and OMAP2_PRM_BASETony Lindgren2009-05-252-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove OMAP_PRM_REGADDR and use processor specific defines instead. Also fold in a patch from Kevin Hilman to add _OFFSET #defines for the PRCM registers to be used with the prm_[read|write]_* macros. These are used extensively in the forthcoming OMAP PM support. Also remove now unused OMAP2_PRM_BASE. Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | | * ARM: OMAP2/3: Remove OMAP2_32KSYNCT_BASETony Lindgren2009-05-253-14/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use processor specific defines instead. As an extra bonus, this patch fixes the problem of CONFIG_DEBUG_SPINLOCK calling sched_clock before we have things initialized: http://patchwork.kernel.org/patch/15810/ Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * | OMAP3: PM: Ensure MUSB block can idle when driver not loadedPeter 'p2' De Schrijver2009-05-281-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Otherwise, bootloaders may leave MUSB in a state which prevents retention. Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| | * | OMAP3: PM: Add D2D clocks and auto-idle setup to PRCM initKevin Hilman2009-05-281-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add D2D clocks (modem_fck, sad2d_ick, mad2d_ick) to clock framework and ensure that auto-idle bits are set for these clocks during PRCM init. Also add omap3_d2d_idle() function called durint PRCM setup which ensures D2D pins are MUX'd correctly to enable retention for standalone (no-modem) devices. Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| | * | OMAP3: PM: UART: disable clocks when idle and off-mode supportKevin Hilman2009-05-282-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch allows the UART clocks to be disabled when the OMAP UARTs are inactive, thus permitting the chip to hit retention in idle. After the expiration of an activity timer, each UART is allowed to disable its clocks so the system can enter retention. The activity timer is (re)activated on any UART interrupt, UART wake event or any IO pad wakeup. The actual disable of the UART clocks is done in the 'prepare_idle' hook called from the OMAP idle loop. While the activity timer is active, the smart-idle mode of the UART is also disabled. This is due to a "feature" of the UART module that after a UART wakeup, the smart-idle mode may be entered before the UART has communicated the interrupt, or upon TX, an idle mode may be entered before the TX FIFOs are emptied. Upon suspend, the 'prepare_suspend' hook cancels any pending activity timers and allows the clocks to be disabled immediately. In addition, upon disabling clocks the UART state is saved in case of an off-mode transition while clocks are off. Special thanks to Tero Kristo for the initial ideas and first versions of UART idle support, and to Jouni Hogander for extra testing and bugfixes. Tested on OMAP3 (Beagle, RX51, SDP, EVM) and OMAP2 (n810) Cc: Tero Kristo <tero.kristo@nokia.com> Cc: Jouni Hogander <jouni.hogander@nokia.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| | * | OMAP3: PM: Add wake-up bit defintiions for CONTROL_PADCONF_XKevin Hilman2009-05-281-0/+4
| | | | | | | | | | | | | | | | Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| | * | OMAP3: PM: Force IVA2 into idle during bootupKevin Hilman2009-05-281-0/+5
| | | | | | | | | | | | | | | | Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| | * | OMAP: Add new function to check wether there is irq pendingJouni Hogander2009-05-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add common omap2/3 function to check wether there is irq pending. Switch to use it in omap2 pm code instead of its own. Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| | * | OMAP2/3: PM: push core PM code from linux-omapKevin Hilman2009-05-283-347/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is to sync the core linux-omap PM code with mainline. This code has evolved and been used for a while the linux-omap tree, but the attempt here is to finally get this into mainline. Following this will be a series of patches from the 'PM branch' of the linux-omap tree to add full PM hardware support from the linux-omap tree. Much of this PM core code was written by Jouni Hogander with significant contributions from Paul Walmsley as well as many others from Nokia, Texas Instruments and linux-omap community. Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com> Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| | * | Merge branch 'omap-clock-upstream' of git://git.pwsan.com/linux-2.6 into ↵Tony Lindgren2009-05-264-8/+20
| | |\ \ | | | | | | | | | | | | | | | for-next
| | | * | OMAP2xxx clock: rename clk_init_one() to clk_preinit()Paul Walmsley2009-05-122-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename clk_init_one() to clk_preinit() to distinguish its function from clk_init() and the individual struct clk init functions. Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | | * | OMAP3 clock: only unlock SDRC DLL if SDRC clk < 83MHzPaul Walmsley2009-05-122-5/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the 34xx TRM Rev. K section 11.2.4.4.11.1 "Purpose of the DLL/CDL Module," the SDRC delay-locked-loop can be locked at any SDRC clock frequency from 83MHz to 166MHz. CDP code unconditionally unlocked the DLL whenever shifting to a lower SDRC speed, but this seems unnecessary and error-prone, as the DLL is no longer able to compensate for process, voltage, and temperature variations. Instead, only unlock the DLL when the SDRC clock rate would be less than 83MHz. Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | | * | OMAP3 SRAM: mark OCM RAM as Non-cacheable Normal memoryPaul Walmsley2009-05-121-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Mark the SRAM (aka OCM RAM) as Non-cacheable Normal memory[1]. This is to prevent the ARM from evicting existing cache lines to SDRAM while code is executing from the SRAM. Necessary since one of the primary uses for the SRAM is to hold the code and data for the CORE DPLL M2 divider reprogramming code, which must execute while the SDRC is idled. If the ARM attempts to write cache lines back to the while the SRAM code is running, the ARM will stall[2]. TI deals with this problem in the CDP kernel by marking the SRAM as Strongly-ordered memory. Tero Kristo <tero.kristo@nokia.com> caught a bug in an earlier version of this patch - thanks Tero. ... 1. ARMv7 ARM (DDI 0406A) pp. A3-30, A3-31, B3-32. 2. Private communication with Richard Woodruff <r-woodruff2@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Tero Kristo <tero.kristo@nokia.com> Cc: Richard Woodruff <r-woodruff2@ti.com>
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