summaryrefslogtreecommitdiffstats
path: root/arch/arm/mm/proc-v7.S
Commit message (Collapse)AuthorAgeFilesLines
* arm: Use __INIT macro instead of .text.init.Tim Abbott2009-04-271-1/+2
| | | | | | | | | | | | | arm is placing some code in the .text.init section, but it does not reference that section in its linker scripts. This change moves this code from the .text.init section to the .init.text section, which is presumably where it belongs. Signed-off-by: Tim Abbott <tabbott@mit.edu> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Merge branch 'for-rmk' of git://linux-arm.org/linux-2.6 into develRussell King2008-11-271-3/+16
|\
| * Modern processors may need to drain the WB before WFICatalin Marinas2008-11-101-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Since WFI may cause the processor to enter a low-power mode, data may still be in the write buffer. This patch adds a DSB (or DWB) to the cpu_(v6|v7)_do_idle functions before the WFI. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * ARMv7: Add SMP initialisation to proc-v7.SJon Callan2008-11-061-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the SMP/nAMP mode setting to __v7_setup and also sets TTBR to shared page table walks if SMP is enabled. The PTWs are also marked inner cacheable for both SMP and UP modes (setting this is fine even if the CPU doesn't support the feature). Signed-off-by: Jon Callan <Jon.Callan@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * ARMv7: Do not set TTBR0 in __v7_setupCatalin Marinas2008-11-061-1/+0
| | | | | | | | | | | | | | | | | | | | This register is set in __enable_mmu in the head.S file. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* | [ARM] mm: fix page table initializationRussell King2008-11-061-6/+6
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | As a result of the ptebits changes, we ended up marking device mappings as normal memory on ARMv7 CPUs, resulting in undesirable behaviour with serial ports and the like. While reviewing the section mapping table entries, other errors in the memory type settings for devices were detected and confirmed to prevent Xscale3 platforms booting. Tested on: OMAP34xx (ARMv7), OMAP24xx (ARMv6), OMAP16xx (ARM926T, ARMv5), PXA311 (Xscale3), PXA272 (Xscale), PXA255 (Xscale), IXP42x (Xscale), S3C2410 (ARM920T, ARMv4T), ARM720T (ARMv4T) StrongARM-110 (ARMv4) Acked-by: Tony Lindgren <tony@atomide.com> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Tested-by: Mike Rapoport <mike@compulab.co.il> Tested-by: Ben Dooks <ben-linux@fluff.org> Tested-by: Anders Grafström <grfstrm@users.sourceforge.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 5318/1: Swap the PRRR and NMRR values in proc-v7.SCatalin Marinas2008-10-221-2/+2
| | | | | | | | A typo caused these values to be swapped leading to incorrect memory type attributes. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge branch 'ptebits' into develRussell King2008-10-091-17/+12
|\ | | | | | | | | | | Conflicts: arch/arm/Kconfig
| * [ARM] Don't include asm/elf.h in asm codeRussell King2008-10-011-1/+1
| | | | | | | | | | | | asm code really wants asm/hwcap.h, so include that instead. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] Convert ARMv7 to use TEX remappingRussell King2008-10-011-4/+33
| | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] Convert ARMv6 and ARMv7 to use new memory typesRussell King2008-10-011-1/+3
| | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] Convert set_pte_ext implementions to macrosRussell King2008-10-011-37/+1
| | | | | | | | | | | | | | There are actually only four separate implementations of set_pte_ext. Use assembler macros to insert code for these into the proc-*.S files. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] 5229/3: Replace some ARMv7 opcodes with the instruction nameCatalin Marinas2008-10-031-1/+1
| | | | | | | | | | | | | | | | | | These instructions were placed in the code directly as opcodes because early compilers didn't support them. Toolchains supporting ARMv7 understand these instructions and the patch puts the mnemonics back. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] 5227/1: Add the ENDPROC declarations to the .S filesCatalin Marinas2008-09-011-0/+8
|/ | | | | | | | | This declaration specifies the "function" type and size for various assembly functions, mainly needed for generating the correct branch instructions in Thumb-2. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] fix 48d7927bdf071d05cf5d15b816cf06b0937cb84fCatalin Marinas2008-04-241-1/+1
| | | | | | | | | | The proc-*.S files have the _prefetch_abort pointer placed at the end of the processor structure but the cpu-multi32.h defines it in the second position. The patch also fixes the support for XSC3 and the MMU-less CPUs (740, 7tdmi, 940, 946 and 9tdmi). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Add a prefetch abort handlerPaul Brook2008-04-181-0/+1
| | | | | | | | | This patch adds a prefetch abort handler similar to the data abort one and renames the latter for consistency. Initial implementation by Paul Brook with some renaming by Catalin Marinas. Signed-off-by: Paul Brook <paul@codesourcery.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* [ARM] 4503/1: nommu: Add noMMU support for ARMv7Catalin Marinas2007-07-201-11/+14
| | | | | | | | This patch adds the necessary ifdef's to the proc-v7.S code and defines the v7wbi_tlb_fns macro in pgtable-nommu.h Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4498/1: ARMv7: Remove the L2 cache configuration via the aux ctrl registerCatalin Marinas2007-07-201-10/+0
| | | | | | | | | The auxiliary control and the L2 auxiliary control registers are Cortex-A8 specific. They need to be removed from the generic ARMv7 support code. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4394/1: ARMv7: Add the TLB range operationsCatalin Marinas2007-05-301-1/+1
| | | | | | | | | We are currently using the ARMv6 operations but need to duplicate some of the code because of the introduction of the new CPU barrier instructions in ARMv7. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] armv7: add support for ARMv7 cores.Catalin Marinas2007-05-081-0/+262
This patch adds support for the ARMv7 cores. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
OpenPOWER on IntegriCloud