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* ARM: 7661/1: mm: perform explicit branch predictor maintenance when requiredWill Deacon2013-03-031-1/+3
* ARM: 7659/1: mm: make mm->context.id an atomic64_t variableWill Deacon2013-03-031-8/+13
* ARM: 7658/1: mm: fix race updating mm->context.id on ASID rolloverWill Deacon2013-03-031-3/+3
* ARM: 7649/1: mm: mm->context.id fix for big-endianBen Dooks2013-02-161-0/+3
* ARM: 7582/2: rename kvm_seq to vmalloc_seq so to avoid confusion with KVMNicolas Pitre2012-11-261-2/+2
* ARM: mm: use bitmap operations when allocating new ASIDsWill Deacon2012-11-051-19/+35
* ARM: mm: avoid taking ASID spinlock on fastpathWill Deacon2012-11-051-8/+15
* ARM: mm: remove IPI broadcasting on ASID rolloverWill Deacon2012-11-051-100/+86
* ARM: 7502/1: contextidr: avoid using bfi instruction during notifierWill Deacon2012-08-251-3/+4
* ARM: 7445/1: mm: update CONTEXTIDR register to contain PID of current processWill Deacon2012-07-091-0/+35
* ARM: Remove current_mm per-cpu variableCatalin Marinas2012-04-171-11/+1
* ARM: Remove __ARCH_WANT_INTERRUPTS_ON_CTXSW on ASID-capable CPUsCatalin Marinas2012-04-171-2/+2
* ARM: Use TTBR1 instead of reserved context IDWill Deacon2012-04-171-18/+27
* ARM: LPAE: Add context switching supportCatalin Marinas2011-12-081-2/+17
* locking, ARM: Annotate low level hw locks as rawThomas Gleixner2011-09-131-7/+7
* Revert "ARM: 6944/1: mm: allow ASID 0 to be allocated to tasks"Russell King2011-06-091-3/+3
* Revert "ARM: 6943/1: mm: use TTBR1 instead of reserved context ID"Russell King2011-06-091-6/+5
* ARM: 6944/1: mm: allow ASID 0 to be allocated to tasksWill Deacon2011-05-261-3/+3
* ARM: 6943/1: mm: use TTBR1 instead of reserved context IDWill Deacon2011-05-261-5/+6
* ARM: 5905/1: ARM: Global ASID allocation on SMPCatalin Marinas2010-02-151-14/+110
* ARM: Fix errata 411920 workaroundsRussell King2009-10-291-4/+1
* cpumask: use mm_cpumask() wrapper: armRusty Russell2009-09-241-1/+1
*-. Merge branches 'armv7', 'at91', 'misc' and 'omap' into develRussell King2007-05-091-3/+7
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| | * [ARM] Fix ASID version switchRussell King2007-05-081-3/+7
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* | [ARM] armv7: add support for asid-tagged VIVT I-cacheCatalin Marinas2007-05-091-0/+7
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* [ARM] 4128/1: Architecture compliant TTBR changing sequenceCatalin Marinas2007-02-081-2/+10
* [ARM] Move mmu.c out of the wayRussell King2006-09-201-0/+45
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