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* ARM: vexpress/MCPM: fix cache disable sequence when CONFIG_FRAME_POINTER=yNicolas Pitre2013-08-141-4/+12
| | | | | | | | | | | | | | | If CONFIG_FRAME_POINTER=y we get the following error: arch/arm/mach-vexpress/tc2_pm.c: In function 'tc2_pm_down': arch/arm/mach-vexpress/tc2_pm.c:200:1: error: fp cannot be used in asm here Let's fix that by explicitly preserving r11 on the stack and removing it from the clobber list. Reported-by: Russell King <rmk+kernel@arm.linux.org.uk> Reviewed-by: Dave Martin <Dave.Martin@arm.com> Signed-off-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
* ARM: vexpress/dcscb: fix cache disabling sequencesNicolas Pitre2013-07-221-21/+37
| | | | | | | | | Unlike real A15/A7's, the RTSM simulation doesn't appear to hit the cache when the CTRL.C bit is cleared. Let's ensure there is no memory access within the disable and flush cache sequence, including to the stack. Signed-off-by: Nicolas Pitre <nico@linaro.org>
* ARM: vexpress/dcscb: handle platform coherency exit/setup and CCIDave Martin2013-05-291-19/+58
| | | | | | | | | | | | | | | | | Add the required code to properly handle race free platform coherency exit to the DCSCB power down method. The power_up_setup callback is used to enable the CCI interface for the cluster being brought up. This must be done in assembly before the kernel environment is entered. Thanks to Achin Gupta and Nicolas Pitre for their help and contributions. Signed-off-by: Dave Martin <dave.martin@linaro.org> Signed-off-by: Nicolas Pitre <nico@linaro.org> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Pawel Moll <pawel.moll@arm.com>
* ARM: vexpress/dcscb: do not hardcode number of CPUs per clusterNicolas Pitre2013-05-291-4/+10
| | | | | | | | | | | If 4 CPUs are assumed, the A15x1-A7x1 model configuration would never shut down the initial cluster as the 0xf reset bit mask will never be observed. Let's construct this mask based on the provided information in the DCSCB config register for the number of CPUs per cluster. Signed-off-by: Nicolas Pitre <nico@linaro.org> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Pawel Moll <pawel.moll@arm.com>
* ARM: vexpress/dcscb: add CPU use counts to the power up/down API implementationNicolas Pitre2013-05-291-15/+59
| | | | | | | | | | It is possible for a CPU to be told to power up before it managed to power itself down. Solve this race with a usage count to deal with this possibility as mandated by the MCPM API definition. Signed-off-by: nicolas Pitre <nico@linaro.org> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Pawel Moll <pawel.moll@arm.com>
* ARM: vexpress: introduce DCSCB supportNicolas Pitre2013-05-291-0/+164
This adds basic CPU and cluster reset controls on RTSM for the A15x4-A7x4 model configuration using the Dual Cluster System Configuration Block (DCSCB). The cache coherency interconnect (CCI) is not handled yet. Signed-off-by: Nicolas Pitre <nico@linaro.org> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Pawel Moll <pawel.moll@arm.com>
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