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* Merge tag 'tegra-for-3.10-clk' of ↵Arnd Bergmann2013-04-091-0/+3
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/drivers From Stephen Warren <swarren@wwwdotorg.org>: ARM: tegra: clock driver development This branch contains most fixes and enhancements to the Tegra common clock driver. The main new feature is a driver for Tegra114, which coupled with later device tree changes enables many devices on that chip, such as MMC, I2C, etc. This branch depends on a patch in: git://git.linaro.org/people/mturquette/linux.git clk-for-3.10 Mike has stated that this branch is stable, and is aware of this dependency and merge. Mike's branch is based on v3.9-rc3, which includes a USB change which causes problems on Tegra. That problem was fixed in v3.9-rc4. Hence, this branch pulls in v3.9-rc4 to ensure bisectability as much as possible. This branch is based on v3.9-rc4, followed by a merge of previous Tegra "soc" pull request, followed by a merge of clk-for-3.10. * tag 'tegra-for-3.10-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: clk: tegra: fix enum tegra114_clk to match binding clk: tegra: Remove forced clk_enable of uartd ARM: dt: Add references to tegra_car clocks clk: tegra: devicetree match for nvidia,tegra114-car clk: tegra: Implement clocks for Tegra114 ARM: tegra: Define Tegra114 CAR binding clk: tegra: Workaround for Tegra114 MSENC problem clk: tegra: Add flags to tegra_clk_periph() clk: tegra: Add new fields and PLL types for Tegra114 clk: tegra: move from a lock bit idx to a lock mask clk: tegra: Add PLL post divider table clk: tegra: introduce TEGRA_PLL_HAS_LOCK_ENABLE clk: tegra: Add TEGRA_PLL_BYPASS flag clk: tegra: Refactor PLL programming code clk: tegra: provide dummy cpu car ops clk: tegra: defer application of init table clk: tegra: Fix cdev1 and cdev2 IDs clk: tegra: Make gr2d and gr3d clocks children of pll_c clk: tegra: Export peripheral reset functions clk: tegra: Fix periph_clk_to_bit macro Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * clk: tegra: defer application of init tableStephen Warren2013-04-041-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Tegra clock driver is initialized during the ARM machine descriptor's .init_irq() hook. It can't be initialized earlier, since dynamic memory usage is required. It can't be initialized later, since the .init_timer() hook needs the clocks initialized. However, at this time, udelay() doesn't work. The Tegra clock initialization table may enable some PLLs. Enabling a PLL may require usage of udelay(). Hence, this can't happen right when the clock driver is initialized. To solve this, separate the clock driver initialization from the clock table processing, so they can execute at separate times. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | Merge branch 'tegra/soc' into next/driversArnd Bergmann2013-04-0923-354/+775
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | This is a dependency for the tegra/clk branch. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Conflicts: drivers/clocksource/tegra20_timer.c
| * | ARM: tegra: pm: remove duplicated include from pm.cWei Yongjun2013-04-051-1/+0
| |/ | | | | | | | | | | | | Remove duplicated include. Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: cpuidle: remove redundant parameters for powered-down modeJoseph Lo2013-04-034-12/+4
| | | | | | | | | | | | | | | | After the patch series for system suspending support, tegra_idle_lp2_last() no longer uses its parameters cpu_on_time or cpu_off_time, so remove them. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: pm: add platform suspend supportJoseph Lo2013-04-035-17/+146
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding suspend to RAM support for Tegra platform. There are three suspend mode for Tegra. The difference were below. * LP2: CPU voltage off * LP1: CPU voltage off, DRAM in self-refresh * LP0: CPU + Core voltage off, DRAM in self-refresh After this patch, the LP2 suspend mode will be supported. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: dt: tegra: add bindings of power management configurations for PMCJoseph Lo2013-04-032-0/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The PMC mostly controls the entry and exit of the system from different sleep modes. Different platform or system may have different configurations. The power management configurations of PMC is represented as some properties. The system needs to define the properties when the system supports deep sleep mode (i.e. suspend). Cc: Grant Likely <grant.likely@secretlab.ca> Cc: Rob Herring <rob.herring@calxeda.com> Cc: devicetree-discuss@lists.ozlabs.org Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: irq: add wake up handlingJoseph Lo2013-04-033-1/+103
| | | | | | | | | | | | | | | | | | | | | | Add the wake up handling for legacy irq controller, and using IRQCHIP_MASK_ON_SUSPEND for wake irq handling. Based on the work by: Varun Wadekar <vwadekar@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: moving the CPU power timer function to PMC driverJoseph Lo2013-04-034-37/+41
| | | | | | | | | | | | | | | | | | | | | | The CPU power timer set up function was related to PMC register. Now moving it to PMC driver. And it also help to clean up the PM related code later. The timer was calculated based on the input clock of PMC. In this patch, we also get the clock from DT. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: add speedo-based process id for Tegra114Danny Huang2013-03-194-0/+116
| | | | | | | | | | | | | | | | | | | | Add speedo-based process identification for Tegra114. Based on the work by: Alex Frid <afrid@nvidia.com> Signed-off-by: Danny Huang <dahuang@nvidia.com> [swarren: added include of bug.h] Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: expose chip ID and revisionDanny Huang2013-03-151-1/+28
| | | | | | | | | | | | | | | | Expose Tegra chip ID and revision in /sys/devices/soc for user mode usage Signed-off-by: Danny Huang <dahuang@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: bring up secondary CPU for Tegra114Joseph Lo2013-03-111-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | The secondary CPU can be brought up by toggling the power in PMC. Then the flow controller will release CPU to go by clearing the reset and clamp signal automatically. Based on the work by: Bo Yan <byan@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: replace the CPU power on function with PMC callJoseph Lo2013-03-111-12/+7
| | | | | | | | | | | | | | | | | | | | Using the CPU power on function in PMC driver to bring up secondary CPUs, because we are going to re-factor powergate driver to support generic power domain. It will be removed later and added the generic power domain support in PMC driver. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: pmc: add power on function for secondary CPUsJoseph Lo2013-03-112-2/+103
| | | | | | | | | | | | | | | | | | Adding the power on function for secondary CPUs in PMC driver, this can help us to remove legacy powergate driver and add generic power domain support later. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: pmc: convert PMC driver to support DT onlyJoseph Lo2013-03-111-29/+22
| | | | | | | | | | | | | | | | | | | | | | The Tegra kernel only support boot from DT now. Clean up the PMC driver to support DT only, that includes: * remove the ifdef of CONFIG_OF * replace the static mapping of PMC addr to map from DT Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: pmc: add specific compatible DT string for Tegra30 and Tegra114Joseph Lo2013-03-111-0/+2
| | | | | | | | | | | | | | | | The PMC HW is not 100% compatible across all Tegra series. We need to specify each of them in the DT match table. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: refactor tegra{20,30}_boot_secondaryHiroshi Doyu2013-03-111-55/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "tegra_boot_secondary()" has many condition branches for some Tegra SoC generations in a single function so that it's not easy to compile a kernel only for a single SoC if one wants with some reason, debug purpose(?). This patch provides SoC specific version of boot_secondary(), tegra{20,30}_boot_secondary(). This could allow any combination of SoC to be built. Those boot_secondary functions can be preparation when we ntroduce chip specific function pointers in the future without having chip dependent branches around. Also removed unused definition/prototpye. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> [josephl: remove the Tegra114 part of the original patch] Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: Unify Device tree board filesHiroshi Doyu2013-03-114-114/+10
| | | | | | | | | | | | | | Unify board-dt-tegra{30,114} to the Tegra20 DT board file, "tegra.c". Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: Rename board-dt-tegra20.c to tegra.cHiroshi Doyu2013-03-112-1/+1
| | | | | | | | | | | | | | | | This is the preparation to unify "board-dt-tegra{20,30,114}.c" to a single file "tegra.c". Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: Unify tegra{20,30,114}_init_early()Hiroshi Doyu2013-03-117-50/+21
| | | | | | | | | | | | | | | | Refactored tegra{20,30,114}_init_early() so that we have the unified tegra_init_early(). Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: fix ignored return value of regulator_enableStephen Warren2013-03-111-1/+6
| | | | | | | | | | | | | | | | | | | | | | This fixes: arch/arm/mach-tegra/board-harmony-pcie.c: In function ‘harmony_pcie_init’: arch/arm/mach-tegra/board-harmony-pcie.c:65:18: warning: ignoring return value of ‘regulator_enable’, declared with attribute warn_unused_result [-Wunused-result] Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: fix the logical detection of power on sequence of warm boot CPUsJoseph Lo2013-03-111-1/+1
| | | | | | | | | | | | | | | | | | | | The warm boot sequence of Tegra30 secondary CPUs should wait for the power ready then removing the clamps. This did not fix any known or unknown issue, but nice to have this fix. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: Fix unchecked return valueHiroshi Doyu2013-03-111-0/+3
| | | | | | | | | | | | | | | | Check a return value for tegra_powergate_remove_clamping(). Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: don't unlock MMIO access to DBGLARJoseph Lo2013-03-112-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no need to unlock MMIO access to the DBGLAR all the time. Doing so may even cause problems if a SW bug causes writes to that MMIO region. Cortex-A15 processors do not support the CP14 register write the code currently uses to unlock the DBGLAR; the instruction throws an undefined instruction exceptions. This prevents tegra_secondary_startup() from executing on Tegra114, and hence prevents SMP. Remove the code that unlocks this access. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: remove save/restore of CPU diag registerStephen Warren2013-03-112-23/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Prior to this change, {save,restore}_cpu_arch_register() collaborated to maintain the value of the CPU diagnostic register across power cycles. This was required to maintain any CPU errata workaround enable bits in that register. However, now that the Tegra reset vector code always enables all required workarounds, there is no need to save and restore the diagnostic register; it is always explicitly programmed in the required manner. Hence, remove the save/restore logic. This has the advantage that the kernel always directly controls the value of this register every boot, rather than relying on a bootloader or other kernel code having previously written the correct value into it. This makes CPU0 (which was previously saved/restored) and CPUn (which should have been set up by the reset vector) be controlled in exactly the same way, which is easier to debug/find/... In particular, when converting Tegra to a multi-platform kernel, the CPU0 diagnostic register value initially comes from the bootloader. Most Tegra bootloaders don't yet enable all required CPU bug workarounds. The previous commit updates the kernel to do so on any CPU power cycle. However, the save/restore code ends up over-writing the value with the old bootloader-driven value instead of the now more-likely-to-be-correct kernel value! Even irrespective of multi-platform conversion, this change limits the kernel's exposure to any WARs the bootloader didn't enable for CPU0: on the very first LP2 transition (CPU power-saving which power-cycles the CPU), the correct value will be enabled. Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: add CPU errata WARs to Tegra reset handlerStephen Warren2013-03-111-6/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CPU cores in Tegra contain some errata. Workarounds must be applied for these every time a CPU boots. Implement those workarounds directly in the Tegra-specific CPU reset vector. Many of these workarounds duplicate code in the core ARM kernel. However, the core ARM kernel cannot enable those workarounds when building a multi-platform kernel, since they require writing to secure- only registers, and a multi-platform kernel often does not run in secure mode, and also cannot generically/architecturally detect whether it is running in secure mode, and hence cannot either unconditionally or conditionally apply these workarounds. Instead, the workarounds must be applied in architecture-specific reset code, which is able to have more direct knowledge of the secure/normal state. On Tegra, we will be able to detect this using a non-architected register in the future, although we currently assume the kernel runs only in secure mode. Other SoCs may never run the kernel in secure mode, and hence always rely on a secure monitor to enable the workarounds, and hence never implement them in the kernel. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | Merge commit '7185684' into omap-for-v3.10/timerTony Lindgren2013-04-032-4/+4
|\ \ | |/ |/| | | | | | | | | | | Conflicts: arch/arm/plat-omap/dmtimer.c Resolve merge conflict in omap_device.c as per Lothar Waßmann <LW@KARO-electronics.de>.
| * ARM: cleanup: clk_get_sys() error handlingRussell King2013-02-241-1/+1
| | | | | | | | | | | | | | Fix clk_get_sys() error handling; IS_ERR() should be used rather than IS_ERR_OR_NULL() to check for errors. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: cleanup: regulator_get() error handlingRussell King2013-02-241-3/+3
| | | | | | | | | | | | | | | | | | regulator_get() does not return NULL as an error value. Even when it does return an error, the code as written falls out the error path while returning zero (indicating no failure.) Fix this, and use the more correct IS_ERR() macro to check for errors. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | Merge tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds2013-02-2139-7545/+690
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull ARM SoC-specific updates from Arnd Bergmann: "This is a larger set of new functionality for the existing SoC families, including: - vt8500 gains support for new CPU cores, notably the Cortex-A9 based wm8850 - prima2 gains support for the "marco" SoC family, its SMP based cousin - tegra gains support for the new Tegra4 (Tegra114) family - socfpga now supports a newer version of the hardware including SMP - i.mx31 and bcm2835 are now using DT probing for their clocks - lots of updates for sh-mobile - OMAP updates for clocks, power management and USB - i.mx6q and tegra now support cpuidle - kirkwood now supports PCIe hot plugging - tegra clock support is updated - tegra USB PHY probing gets implemented diffently" * tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (148 commits) ARM: prima2: remove duplicate v7_invalidate_l1 ARM: shmobile: r8a7779: Correct TMU clock support again ARM: prima2: fix __init section for cpu hotplug ARM: OMAP: Consolidate OMAP USB-HS platform data (part 3/3) ARM: OMAP: Consolidate OMAP USB-HS platform data (part 1/3) arm: socfpga: Add SMP support for actual socfpga harware arm: Add v7_invalidate_l1 to cache-v7.S arm: socfpga: Add entries to enable make dtbs socfpga arm: socfpga: Add new device tree source for actual socfpga HW ARM: tegra: sort Kconfig selects for Tegra114 ARM: tegra: enable ARCH_REQUIRE_GPIOLIB for Tegra114 ARM: tegra: Fix build error w/ ARCH_TEGRA_114_SOC w/o ARCH_TEGRA_3x_SOC ARM: tegra: Fix build error for gic update ARM: tegra: remove empty tegra_smp_init_cpus() ARM: shmobile: Register ARM architected timer ARM: MARCO: fix the build issue due to gic-vic-to-irqchip move ARM: shmobile: r8a7779: Correct TMU clock support ARM: mxs_defconfig: Select CONFIG_DEVTMPFS_MOUNT ARM: mxs: decrease mxs_clockevent_device.min_delta_ns to 2 clock cycles ARM: mxs: use apbx bus clock to drive the timers on timrotv2 ...
| * \ Merge branch 'socfpga/hw' into next/socOlof Johansson2013-02-111-43/+0
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From Dinh Nguyen, this is a series of patches introducing support for socfpga hardware (Altera Cyclone5). It also includes a cleanup that moves some of the ARMv7 cache maintenance functions to a common location, since three other platforms aready implemented it separately. * socfpga/hw: arm: socfpga: Add SMP support for actual socfpga harware arm: Add v7_invalidate_l1 to cache-v7.S arm: socfpga: Add entries to enable make dtbs socfpga arm: socfpga: Add new device tree source for actual socfpga HW Trivial conflict in arch/arm/mach-tegra/headsmp.S. Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | arm: Add v7_invalidate_l1 to cache-v7.SDinh Nguyen2013-02-111-43/+0
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mach-socfpga is another platform that needs to use v7_invalidate_l1 to bringup additional cores. There was a comment that the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Pavel Machek <pavel@denx.de> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Pavel Machek <pavel@denx.de> Tested-by: Stephen Warren <swarren@nvidia.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Russell King <linux@arm.linux.org.uk> Cc: Olof Johansson <olof@lixom.net> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Magnus Damm <magnus.damm@gmail.com> Signed-off-by: Olof Johansson <olof@lixom.net>
| * | Merge branch 'tegra/t114' into next/socOlof Johansson2013-02-094-13/+22
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a couple of fixes sent via email (via Stephen/Hiroshi). * tegra/t114: ARM: tegra: sort Kconfig selects for Tegra114 ARM: tegra: enable ARCH_REQUIRE_GPIOLIB for Tegra114 ARM: tegra: Fix build error w/ ARCH_TEGRA_114_SOC w/o ARCH_TEGRA_3x_SOC Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | ARM: tegra: sort Kconfig selects for Tegra114Stephen Warren2013-02-091-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Kconfig options selected by ARCH_TEGRA_*_SOC were recently sorted. Update the newly added ARCH_TEGRA_114_SOC's select statements to match. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | ARM: tegra: enable ARCH_REQUIRE_GPIOLIB for Tegra114Stephen Warren2013-02-091-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_ARCH_TEGRA_114_SOC doesn't currently enable gpiolib, which causes numerous build problems building a Tegra kernel with only Tegra114 enabled, and not Tegra20 or Tegra30. Enable ARCH_REQUIRE_GPIOLIB to solve this. However, all Tegra will use gpiolib, so select this option from ARCH_TEGRA rather than each individual ARCH_TEGRA_*_SOC, to prevent this problem for any future chips. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | ARM: tegra: Fix build error w/ ARCH_TEGRA_114_SOC w/o ARCH_TEGRA_3x_SOCOlof Johansson2013-02-093-9/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes the build error when ARCH_TEGRA_114_SOC is enabled and ARCH_TEGRA_3x_SOC is disabled. This provides Tegra114 with its own tegra114_init_early() instead of making use of tegra30_init_early() so that T114 build doesn't depend on T3x anymore. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
| * | | ARM: tegra: Fix build error for gic updateHiroshi Doyu2013-02-051-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix build error in board-dt-tegra114.c(next-20130204) Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Reported-by: Sami Liedes<sliedes@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
| * | | ARM: tegra: remove empty tegra_smp_init_cpus()Olof Johansson2013-02-051-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on two separate cleanup branches, it's now empty and can be removed. Signed-off-by: Olof Johansson <olof@lixom.net> Cc: Stephen Warren <swarren@wwwdotorg.org>
| * | | Merge tag 'tegra-for-3.9-soc-t114' of ↵Olof Johansson2013-02-058-16/+137
| |\ \ \ | | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/soc From Stepen Warren: ARM: tegra: add Tegra114 SoC support This pull request adds initial support for the Tegra114 SoC, which integrates a quad-core ARM Cortex-A15 CPU. I'm proud to observe that we posted the initial versions of these patches before the final official announcement of this chip. These patches are enough to boot with a UART-based console, support the Dalmore and Pluto reference/evaluation boards, instantiate the GPIO and pinctrl drivers, and enable a cpuidle state. As yet, no clocks or storage devices are supported, but patches for those will follow shortly. This pull request is based on (most of) the previous pull request with tag tegra-for-3.9-soc-cpuidle, followed by a merge of the previous pull request with tag tegra-for-3.9-scu-base-rework. * tag 'tegra-for-3.9-soc-t114' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: (24 commits) ARM: DT: tegra114: add pinmux DT entry ARM: DT: tegra114: add GPIO DT entry ARM: tegra114: select PINCTRL for Tegra114 SoC ARM: tegra: add Tegra114 ARM_CPUIDLE_WFI_STATE support ARM: tegra: Add SMMU entry to Tegra114 DT ARM: tegra: add AHB entry to Tegra114 DT ARM: tegra: Add initial support for Tegra114 SoC. ARM: dt: tegra114: Add new board, Pluto ARM: dt: tegra114: Add new board, Dalmore ARM: dt: tegra114: Add new SoC base, Tegra114 SoC ARM: tegra: fuse: Add chip ID Tegra114 0x35 ARM: OMAP: Make use of available scu_a9_get_base() interface ARM: tegra: Skip scu_enable(scu_base) if not Cortex A9 ARM: Add API to detect SCU base address from CP15 ARM: tegra: Use DT /cpu node to detect number of CPU core ARM: tegra: Add CPU nodes to Tegra30 device tree ARM: tegra: Add CPU nodes to Tegra20 device tree ARM: perf: simplify __hw_perf_event_init err handling ARM: perf: remove unnecessary checks for idx < 0 ARM: perf: handle armpmu_register failing ... Signed-off-by: Olof Johansson <olof@lixom.net> Remove/add conflict in arch/arm/mach-tegra/common.c resolved. Remove/remove conflict in arch/arm/mach-tegra/platsmp.c. Leave the empty stub function for now since removing it in the merge commit is confusing; will be cleaned up in a separate commit. # # It looks like you may be committing a merge. # If this is not correct, please remove the file # .git/MERGE_HEAD # and try again.
| | * | ARM: tegra114: select PINCTRL for Tegra114 SoCLaxman Dewangan2013-01-291-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Select PINCTRL and PINCTRL_TEGRA114 for enabling Tegra114 pincontrol driver for Tegra114 SoC. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| | * | ARM: tegra: add Tegra114 ARM_CPUIDLE_WFI_STATE supportJoseph Lo2013-01-294-0/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding the generic ARM_CPUIDLE_WFI_STATE support for Tegra114. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| | * | ARM: tegra: Add initial support for Tegra114 SoC.Hiroshi Doyu2013-01-284-0/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add new Tegra 114 SoC support. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| | * | ARM: tegra: fuse: Add chip ID Tegra114 0x35Hiroshi Doyu2013-01-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add tegra_chip_id TEGRA114 0x35 Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| | * | Merge branch 'for-3.9/scu-base-rework' into for-3.9/soc-t114Stephen Warren2013-01-281-17/+2
| | |\ \ | | | | | | | | | | | | | | | | | | | | Conflicts: arch/arm/mach-tegra/platsmp.c
| | | * | ARM: tegra: Skip scu_enable(scu_base) if not Cortex A9Hiroshi Doyu2013-01-281-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Skip scu_enable(scu_base) if CPU is not Cortex A9 with SCU. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| | | * | ARM: tegra: Use DT /cpu node to detect number of CPU coreHiroshi Doyu2013-01-281-15/+0
| | | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SCU based detection only works with Cortex-A9 MP and it doesn't support ones with multiple clusters. The only way to detect number of CPU core correctly is with DT /cpu node. Tegra SoCs decided to use DT detection as the only way and to not use SCU based detection at all. Even if DT /cpu node based detection fails, it continues with a single core Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | Merge tag 'tegra-for-3.9-soc-cpuidle' of ↵Olof Johansson2013-02-0510-9/+516
| |\ \ \ | | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/soc From Stephen Warren: ARM: tegra: cpuidle enhancements This pull request implements a new "LP2" cpuidle state for Tegra20, which makes use of the couple cpuidle feature. It is based on (most of) the previous pull request, with tag tegra-for-3.9-soc-usb. * tag 'tegra-for-3.9-soc-cpuidle' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: ARM: tegra20: cpuidle: apply coupled cpuidle for powered-down mode ARM: tegra20: flowctrl: add support for cpu_suspend_enter/exit clk: tegra20: Implementing CPU low-power function for tegra_cpu_car_ops ARM: tegra20: cpuidle: add powered-down state for secondary CPU ARM: tegra: add pending SGI checking API Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | ARM: tegra20: cpuidle: apply coupled cpuidle for powered-down modeJoseph Lo2013-01-285-9/+192
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "powered-down" cpuidle mode of Tegra20 needs the CPU0 be the last one core to go into this mode before other core. The coupled cpuidle framework can help to sync the MPCore to coupled state then go into "powered-down" idle mode together. The driver can just assume the MPCore come into "powered-down" mode at the same time. No need to take care if the CPU_0 goes into this mode along and only can put it into safe idle mode (WFI). The powered-down state of Tegra20 requires power gating both CPU cores. When the secondary CPU requests to enter powered-down state, it saves its own contexts and then enters WFI for waiting CPU0 in the same state. When the CPU0 requests powered-down state, it attempts to put the secondary CPU into reset to prevent it from waking up. Then power down both CPUs together and power off the cpu rail. Be aware of that, you may see the legacy power state "LP2" in the code which is exactly the same meaning of "CPU power down". Based on the work by: Colin Cross <ccross@android.com> Gary King <gking@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Colin Cross <ccross@android.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| | * | ARM: tegra20: flowctrl: add support for cpu_suspend_enter/exitJoseph Lo2013-01-282-5/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The flow controller can help CPU to go into suspend mode (powered-down state). When CPU go into powered-down state, it needs some careful settings before getting into and after leaving. The enter and exit functions do that by configuring appropriate mode for flow controller. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| | * | ARM: tegra20: cpuidle: add powered-down state for secondary CPUJoseph Lo2013-01-284-4/+259
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The powered-down state of Tegra20 requires power gating both CPU cores. When the secondary CPU requests to enter powered-down state, it saves its own contexts and then enters WFI. The Tegra20 had a limition to power down both CPU cores. The secondary CPU must waits for CPU0 in powered-down state too. If the secondary CPU be woken up before CPU0 entering powered-down state, then it needs to restore its CPU states and waits for next chance. Be aware of that, you may see the legacy power state "LP2" in the code which is exactly the same meaning of "CPU power down". Based on the work by: Colin Cross <ccross@android.com> Gary King <gking@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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