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* ARM: convert all "mov.* pc, reg" to "bx reg" for ARMv6+Russell King2014-07-181-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARMv6 and greater introduced a new instruction ("bx") which can be used to return from function calls. Recent CPUs perform better when the "bx lr" instruction is used rather than the "mov pc, lr" instruction, and this sequence is strongly recommended to be used by the ARM architecture manual (section A.4.1.1). We provide a new macro "ret" with all its variants for the condition code which will resolve to the appropriate instruction. Rather than doing this piecemeal, and miss some instances, change all the "mov pc" instances to use the new macro, with the exception of the "movs" instruction and the kprobes code. This allows us to detect the "mov pc, lr" case and fix it up - and also gives us the possibility of deploying this for other registers depending on the CPU selection. Reported-by: Will Deacon <will.deacon@arm.com> Tested-by: Stephen Warren <swarren@nvidia.com> # Tegra Jetson TK1 Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> # mioa701_bootresume.S Tested-by: Andrew Lunn <andrew@lunn.ch> # Kirkwood Tested-by: Shawn Guo <shawn.guo@freescale.com> Tested-by: Tony Lindgren <tony@atomide.com> # OMAPs Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com> # Armada XP, 375, 385 Acked-by: Sekhar Nori <nsekhar@ti.com> # DaVinci Acked-by: Christoffer Dall <christoffer.dall@linaro.org> # kvm/hyp Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> # PXA3xx Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> # Xen Tested-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> # ARMv7M Tested-by: Simon Horman <horms+renesas@verge.net.au> # Shmobile Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: OMAP4: sleep: build OMAP4 specific functions only for OMAP4Nishanth Menon2013-07-041-1/+5
| | | | | | | | | | | | | | | | | | | | CPU sleep and resume functions for Cortex-A9 based OMAP4 and Cortex-A15 based OMAP5 are different. Hence, even though we reuse most of the remaining file as part of OMAP4/5 consolidation, build OMAP4 specific sleep/resume operations only for OMAP4. SCU is not used OMAP5. This fixes the following build failure with OMAP5 only build: arch/arm/mach-omap2/built-in.o: In function `scu_gp_set': arch/arm/mach-omap2/sleep44xx.S:132: undefined reference to `scu_power_mode' arch/arm/mach-omap2/built-in.o: In function `scu_gp_clear': arch/arm/mach-omap2/sleep44xx.S:229: undefined reference to `scu_power_mode' Reported-by: Pekon Gupta <pekon@ti.com> Reported-by: Vincent Stehlé <v-stehle@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: OMAP2+: Make omap-secure.h localTony Lindgren2012-09-201-1/+1
| | | | | | This can be local to mach-omap2. Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: OMAP2+ Move SoC specific headers to be local to mach-omap2Tony Lindgren2012-09-121-1/+1
| | | | | | | | | | These can now be moved to be local headers in mach-omap2. Note that this patch removes arch/arm/plat-omap/devices.c as it will get removed anyways with Paul Walmsley's patch "ARM: OMAP: split OMAP1, OMAP2+ RNG device registration". Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: OMAP4: sleep: Save the complete used register stack frameSantosh Shilimkar2012-08-091-2/+6
| | | | | | | | | | | | | | OMAP4 sleep entry code even though itself don't use many CPU registers makes call to the v7_flush_dcache_all() which uses them. Since v7_flush_dcache_all() doesn't make use of stack, the caller must take care of the stack frame. Otherwise it will lead to corrupted stack frame. Fix it by saving used registers. Reported-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: Kevin Hilman <khilman@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
* Disintegrate asm/system.h for ARMDavid Howells2012-03-281-1/+0
| | | | | | | | Disintegrate asm/system.h for ARM. Signed-off-by: David Howells <dhowells@redhat.com> cc: Russell King <linux@arm.linux.org.uk> cc: linux-arm-kernel@lists.infradead.org
* ARM: OMAP4: Fix errata i688 with MPU interconnect barriers.Santosh Shilimkar2011-12-081-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On OMAP4 SOC, intecronnects has many write buffers in the async bridges and they need to be drained before CPU enters into standby state. Patch 'OMAP4: PM: Add CPUX OFF mode support' added CPU PM support but OMAP errata i688 (Async Bridge Corruption) needs to be taken care to avoid issues like system freeze, CPU deadlocks, random crashes with register accesses, synchronisation loss on initiators operating on both interconnect port simultaneously. As per the errata, if a data is stalled inside asynchronous bridge because of back pressure, it may be accepted multiple times, creating pointer misalignment that will corrupt next transfers on that data path until next reset of the system (No recovery procedure once the issue is hit, the path remains consistently broken). Async bridge can be found on path between MPU to EMIF and MPU to L3 interconnect. This situation can happen only when the idle is initiated by a Master Request Disconnection (which is trigged by software when executing WFI on CPU). The work-around for this errata needs all the initiators connected through async bridge must ensure that data path is properly drained before issuing WFI. This condition will be met if one Strongly ordered access is performed to the target right before executing the WFI. In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained. IO barrier ensure that there is no synchronisation loss on initiators operating on both interconnect port simultaneously. Thanks to Russell for a tip to conver assembly function to C fuction there by reducing 40 odd lines of code from the patch. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Richard Woodruff <r-woodruff2@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
* ARM: OMAP4: PM: Add L2X0 cache lowpower supportSantosh Shilimkar2011-12-081-0/+95
| | | | | | | | | | | | When MPUSS hits off-mode, L2 cache is lost. This patch adds L2X0 necessary maintenance operations and context restoration in the low power code. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
* ARM: OMAP4: PM: Add CPUX OFF mode supportSantosh Shilimkar2011-12-081-0/+276
This patch adds the CPU0 and CPU1 off mode support. CPUX close switch retention (CSWR) is not supported by hardware design. The CPUx OFF mode isn't supported on OMAP4430 ES1.0 CPUx sleep code is common for hotplug, suspend and CPUilde. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
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