| Commit message (Collapse) | Author | Age | Files | Lines |
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Signed-off-by: Richard Zhao <richard.zhao@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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1. pll_base address should return right value
2. uart parent clk is from pll3
Signed-off-by: Yong Shen <yong.shen@linaro.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Add iomux, clocks, and memory map for Freescale's MX53 SoC.
Add cpu_is_mx53 function to common.h.
Add 3 more banks of gpio's to mxc_gpio_ports.
Add MX53 phys offset address.
Signed-off-by: Dinh Nguyen <Dinh.Nguyen@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Add basic clock support, cpu identification, I/O mapping, interrupt
controller, serial port and ethernet.
Signed-off-by: Amit Kucheria <amit.kucheria@canonical.com>
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