summaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-msm/timer.c
Commit message (Collapse)AuthorAgeFilesLines
* msm: timer: Use clockevents_config_and_register()Stephen Boyd2011-11-101-10/+1
| | | | | | | | | | | | | | | | | | | | | | | | Don't open code the min/max delta logic. Use the generic version instead. Also expand the number of bits we can handle because there isn't anything that says we can't handle all 32 bits. Before: max_delta_ns: 122880426391799 min_delta_ns: 122070 mult: 140737 shift: 32 After: max_delta_ns: 131071523464981 min_delta_ns: 122069 mult: 70369 shift: 31 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: David Brown <davidb@codeaurora.org>
* msm: timer: Setup interrupt after registering clockeventStephen Boyd2011-11-101-4/+2
| | | | | | | | | | | | | Some bootloaders may leave a pending interrupt for the timer and thus msm_timer_interrupt() has a check for a NULL event handler. Unmask and register for the interrupt after registering the clockevent so that we can get the NULL pointer check out of the fast path. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: David Brown <davidb@codeaurora.org>
* msm: timer: Remove SoC specific #ifdefsStephen Boyd2011-11-101-21/+17
| | | | | | | | | | | | | The timer frequency is currently ifdefed in addition to setting the DGT clock's divider value on SCORPIONMP targets. Setup the frequency dynamically using the existing cpu_is_*() branches and assign a custom clocksource read function for 7x01a to get the shift out of the generic path. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: David Brown <davidb@codeaurora.org>
* msm: timer: Remove msm_clocks[] and simplify codeStephen Boyd2011-11-101-145/+76
| | | | | | | | | | | | | We can simplify the timer code now that we only use the DGT for the clocksource and the GPT for the clockevent. Get rid of the msm_clocks[] array and propagate the changes throughout the code. This reduces the lines of code in this file and improves readability. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: David Brown <davidb@codeaurora.org>
* msm: timer: Fix ONESHOT mode interruptsStephen Boyd2011-11-101-5/+20
| | | | | | | | | | | | | | | | | MSM timers don't support an interrupt enable/disable bit. Therefore, when the timer is free running it's possible for the count to wrap and the match value to match again even though a set_next_event() call hasn't been made since the last match. Workaround the lack of an interrupt enable bit by explicitly stopping the timer in the interrupt handler when the clockevent is in ONESHOT mode. This should prevent any possibility of the timer wrapping and matching more than once per set_next_event(). Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: David Brown <davidb@codeaurora.org>
* msm: timer: Use GPT for clockevents and DGT for clocksourceStephen Boyd2011-11-101-69/+52
| | | | | | | | | | | | | | | | | | The clocksource shouldn't stop ticking when the clockevent stops. This is exactly what happens today with MSM timers. The same hardware is used for both the clockevent and the clocksource because the ratings of the two are the same. Fix this by registering a clockevent based on the GPT and a clocksource based on the DGT. This removes any other possible configuration (e.g. a GPT clocksource and a DGT clockevent) but that shouldn't be a big issue since we want higher precision timing than high precision scheduling interrupts. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: David Brown <davidb@codeaurora.org>
* msm: timer: Cleanup #includes and #definesStephen Boyd2011-11-101-19/+7
| | | | | | | | Remove unused/unnecessary #defines, #includes, and use the BIT macro appropriately. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org>
* msm: timer: Tighten #ifdef for local timer supportStephen Boyd2011-11-101-3/+2
| | | | | | | | It is more correct to only define the local timer support code when CONFIG_LOCAL_TIMERS=y. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org>
* ARM: gic, local timers: use the request_percpu_irq() interfaceMarc Zyngier2011-10-231-29/+40
| | | | | | | | | | | | | | | | | | | | This patch remove the hardcoded link between local timers and PPIs, and convert the PPI users (TWD, MCT and MSM timers) to the new *_percpu_irq interface. Also some collateral cleanup (local_timer_ack() is gone, and the interrupt handler is strictly private to each driver). PPIs are now useable for more than just the local timers. Additional testing by David Brown (msm8250 and msm8660) and Shawn Guo (imx6q). Cc: David Brown <davidb@codeaurora.org> Cc: Thomas Gleixner <tglx@linutronix.de> Acked-by: David Brown <davidb@codeaurora.org> Tested-by: David Brown <davidb@codeaurora.org> Tested-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* msm: timer: Fix DGT rate on 8960 and 8660Stephen Boyd2011-06-201-2/+4
| | | | | | | The DGT runs at 27 MHz divided by 4 on 8660 and 8960. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org>
* msm: timer: compensate for timer shift in msm_read_timer_countJeff Ohlstein2011-06-171-1/+5
| | | | | | | | | | | Some msm targets have timers whose lower bits are unreliable. So, we present our timers as lower frequency than they actually are, and ignore the bottom 5 bits on such targets. This compensation was erroneously removed from the msm_read_timer_count function, so restore it. This was broken by 94790ec25 "msm: timer: SMP timer support for msm". Signed-off-by: Jeff Ohlstein <johlstei@codeaurora.org>
* msm: timer: Fix SMP build errorStephen Boyd2011-05-311-0/+2
| | | | | | | | | | | | Fix build breakage on SMP=y builds due to 0f7b332 (ARM: consolidate SMP cross call implementation, 2011-04-03) arch/arm/mach-msm/timer.c: In function 'local_timer_setup': arch/arm/mach-msm/timer.c:295: error: implicit declaration of function 'gic_enable_ppi' Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org>
* msm: timer: fix missing return valueDavid Brown2011-03-311-1/+1
| | | | | | | | | | | | | | Change af90f10d38 "ARM: 6759/1: smp: Select local timers vs broadcast timer support runtime" missed a return statement, causing a compile warning: arch/arm/mach-msm/timer.c:272: warning: 'return' with no value, in function returning non-void Trivially return 0 for success when running on cpu 0 (to match the comment and previous behavior). Signed-off-by: David Brown <davidb@codeaurora.org>
* Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2011-03-231-1/+2
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (35 commits) ARM: Update (and cut down) mach-types ARM: 6771/1: vexpress: add support for multiple core tiles ARM: 6797/1: hw_breakpoint: Fix newlines in WARNings ARM: 6751/1: vexpress: select applicable errata workarounds in Kconfig ARM: 6753/1: omap4: Enable ARM local timers with OMAP4430 es1.0 exception ARM: 6759/1: smp: Select local timers vs broadcast timer support runtime ARM: pgtable: add pud-level code ARM: 6673/1: LPAE: use phys_addr_t instead of unsigned long for start of membanks ARM: Use long long format when printing meminfo physical addresses ARM: integrator: add Integrator/CP sched_clock support ARM: realview/vexpress: consolidate SMP bringup code ARM: realview/vexpress: consolidate localtimer support ARM: integrator/versatile: consolidate FPGA IRQ handling code ARM: rationalize versatile family Kconfig/Makefile ARM: realview: remove old AMBA device DMA definitions ARM: versatile: remove old AMBA device DMA definitions ARM: vexpress: use new init_early for clock tree and sched_clock init ARM: realview: use new init_early for clock tree and sched_clock init ARM: versatile: use new init_early for clock tree and sched_clock init ARM: integrator: use new init_early for clock tree init ...
| * ARM: 6759/1: smp: Select local timers vs broadcast timer support runtimeSantosh Shilimkar2011-02-231-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current code support of dummy timers in absence of local timer is compile time. This is an attempt to convert it to runtime so that on few SOC version if the local timers aren't supported kernel can switch to dummy timers. OMAP4430 ES1.0 does suffer from this limitation. This patch should not have any functional impact on affected files. Cc: Daniel Walker <dwalker@codeaurora.org> Cc: Bryan Huntsman <bryanh@codeaurora.org> Cc: Tony Lindgren <tony@atomide.com> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Magnus Damm <magnus.damm@gmail.com> Cc: Colin Cross <ccross@android.com> Cc: Erik Gilling <konkers@android.com> Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Cc: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: David Brown <davidb@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | msm: timer: Timer support for MSM8960Stepan Moskovchenko2011-01-211-2/+3
| | | | | | | | | | | | | | | | Modify the macros in the MSM timer driver to support the MSM8960 chip. Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org>
* | msm: Generalize timer register mappingsDavid Brown2011-01-211-18/+25
|/ | | | | | | | | Allow the timer register to be determined dynamically instead of at compile time. Use common virtual addresses for the registers across all MSM chips, and select the register mappings based on the detected CPU. Signed-off-by: David Brown <davidb@codeaurora.org>
* msm: timer: SMP timer support for msmJeff Ohlstein2011-01-071-23/+102
| | | | | | | | | | The msm provides timer hardware that is private to each core. Each timer has separate counter and match registers, so we create separate clock_event_devices for each core. For the global clocksource, use cpu 0's counter. Signed-off-by: Jeff Ohlstein <johlstei@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org>
* ARM: MSM: update clock source registrationRussell King2010-12-221-4/+1
| | | | | | | | | | In d7e81c2 (clocksource: Add clocksource_register_hz/khz interface) new interfaces were added which simplify (and optimize) the selection of the divisor shift/mult constants. Switch over to using this new interface. Tested-By: Jeff Ohlstein <johlstei@codeaurora.org> Acked-by: David Brown <davidb@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* msm: timer: Decrease shift on timer clocksourceJeff Ohlstein2010-10-271-1/+1
| | | | | | | | The shift of 24 causes the shift and multiply operation to sometimes overflow, resulting in incorrect timer values and poor performance. Signed-off-by: Jeff Ohlstein <johlstei@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
* msm: timer: support 8x60 timersJeff Ohlstein2010-10-081-2/+21
| | | | | Signed-off-by: Jeff Ohlstein <johlstei@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
* msm: timer: allow MSM_DGT_BASE to be overridenDaniel Walker2010-05-131-0/+2
| | | | | | | | Some SoC need to redefine MSM_DGT_BASE from it's default. This allows it to be defined in a header to override the default value. Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
* clocksource: pass clocksource to read() callbackMagnus Damm2009-04-211-2/+2
| | | | | | | | | | | | | | Pass clocksource pointer to the read() callback for clocksources. This allows us to share the callback between multiple instances. [hugh@veritas.com: fix powerpc build of clocksource pass clocksource mods] [akpm@linux-foundation.org: cleanup] Signed-off-by: Magnus Damm <damm@igel.co.jp> Acked-by: John Stultz <johnstul@us.ibm.com> Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Hugh Dickins <hugh@veritas.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* cpumask: convert struct clock_event_device to cpumask pointers.Rusty Russell2008-12-131-1/+1
| | | | | | | | | | | | | Impact: change calling convention of existing clock_event APIs struct clock_event_timer's cpumask field gets changed to take pointer, as does the ->broadcast function. Another single-patch change. For safety, we BUG_ON() in clockevents_register_device() if it's not set. Signed-off-by: Rusty Russell <rusty@rustcorp.com.au> Cc: Ingo Molnar <mingo@elte.hu>
* [ARM] msm: clean up iomap and devicesBrian Swetland2008-10-221-1/+1
| | | | | | | | | | | | | - Add some more peripherals (sdcc, etc) to the iomap. - Remove virtual base addresses for devices that we should be passing physical addresses to drivers via resources and ioremap()ing. - don't try to use uarts for ll debug once the mmu is enabled due to problems with the peripheral window - make base addresses void __iomem * and fixup irq.c and timer.c - Remove common.c and bring in devices.c/devices.h similar to the PXA architecture. Signed-off-by: Brian Swetland <swetland@google.com>
* [ARM] Convert asm/io.h to linux/io.hRussell King2008-09-061-2/+1
| | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Move include/asm-arm/arch-* to arch/arm/*/include/machRussell King2008-08-071-1/+1
| | | | | | This just leaves include/asm-arm/plat-* to deal with. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] msm: irq and timer support for ARCH_MSM7X00AArve Hjønnevåg2008-01-261-0/+205
- Vectored Interrupt Controller support - Timer support using the GPT and DGT timers Signed-off-by: Brian Swetland <swetland@google.com>
OpenPOWER on IntegriCloud