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* [ARM] Kirkwood: clarify PCIe MEM bus/physical address distinctionLennert Buytenhek2009-11-071-1/+1
| | | | | Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
* [ARM] kirkwood: fix PCI I/O port assignmentLennert Buytenhek2009-11-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | Instead of allocating PCI devices I/O port bus addresses from the 000xxxxx I/O port range as intended, due to a bus versus physical address mixup, the Kirkwood PCIe handling code inadvertently allocated I/O port bus addresses from the f20xxxxx address range (which is the physical address range of the PCIe I/O mapping window), but then direct all I/O port accesses to bus addresses 000xxxxx, which would then not be decoded at all. Fix this by setting the base address of the PCIe I/O space struct resource to KIRKWOOD_PCIE_IO_BUS_BASE instead of the incorrect KIRKWOOD_PCIE_IO_PHYS_BASE, and fix up __io() to expect addresses offsetted by the former instead of the latter. (The suggested fix of directing I/O port accesses from the host to bus addresses f20xxxxx instead has the problem that assigning full 32bit I/O port bus addresses (f20xxxxx) doesn't work on all PCI devices, as not all PCI devices implement full 32 bit BAR registers for I/O ports. We should really try to allocate I/O port bus addresses that fit in 16 bits.) Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
* [ARM] kirkwood: fix section mismatchLi Jie2009-11-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | kirkwood_timer_init() and kirkwood_pcie_setup() lack of __init which causes following warnings: WARNING: vmlinux.o(.text+0x9568): Section mismatch in reference from the function kirkwood_timer_init() to the function .init.text:kirkwood_find_tclk() The function kirkwood_timer_init() references the function __init kirkwood_find_tclk(). This is often because kirkwood_timer_init lacks a __init annotation or the annotation of kirkwood_find_tclk is wrong. WARNING: vmlinux.o(.text+0x979c): Section mismatch in reference from the function kirkwood_pcie_setup() to the function .init.text:orion_pcie_setup() The function kirkwood_pcie_setup() references the function __init orion_pcie_setup(). This is often because kirkwood_pcie_setup lacks a __init annotation or the annotation of orion_pcie_setup is wrong. Signed-off-by: lijie <eltshanli@gmail.com> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
* [ARM] Kirkwood: clock gating for unused peripheralsRabeeh Khoury2009-06-081-0/+4
| | | | | | | | | | | To save power: 1. Enabling clock gating of unused peripherals 2. PLL and PHY of the units are also disabled (when possible. Signed-off-by: Rabeeh Khoury <rabeeh@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
* [ARM] 5359/1: Kirkwood: fix compilation errorNicolas Pitre2009-01-081-0/+1
| | | | | | | Commit ba84be2338d3 broke the build. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Kirkwood: add support for newer SoC modelsRonen Shitrit2008-09-251-0/+6
| | | | | | | | | | | | Add support to the Kirkwood port for newer device models and silicon revisions. Instead of looking at the DEVICE_ID register, the device version is now determined by looking at the PCI-Express device ID and revision registers, as it is done for orion5x, and this information is used to determine the TCLK frequency, again, as it is done for orion5x. Signed-off-by: Ronen Shitrit <rshitrit@marvell.com> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
* [ARM] Move include/asm-arm/plat-orion to arch/arm/plat-orion/include/platLennert Buytenhek2008-08-091-1/+1
| | | | | | | This patch performs the equivalent include directory shuffle for plat-orion, and fixes up all users. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
* [ARM] add Marvell Kirkwood (88F6000) SoC supportSaeed Bishara2008-06-221-0/+180
The Marvell Kirkwood (88F6000) is a family of ARM SoCs based on a Shiva CPU core, and features a DDR2 controller, a x1 PCIe interface, a USB 2.0 interface, a SPI controller, a crypto accelerator, a TS interface, and IDMA/XOR engines, and depending on the model, also features one or two Gigabit Ethernet interfaces, two SATA II interfaces, one or two TWSI interfaces, one or two UARTs, a TDM/SLIC interface, a NAND controller, an I2S/SPDIF interface, and an SDIO interface. This patch adds supports for the Marvell DB-88F6281-BP Development Board and the RD-88F6192-NAS and the RD-88F6281 Reference Designs, enabling support for the PCIe interface, the USB interface, the ethernet interfaces, the SATA interfaces, the TWSI interfaces, the UARTs, and the NAND controller. Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
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