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* [ARM] 5431/1: scoop: completely drop old-style SCOOP GPIO accessorsDmitry Baryshkov2009-03-251-2/+0
| | | | | | | | Now, as all places that use Scoop GPIO have been converted to use GPIO API, drop old-style accessors completely. Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge branch 'highmem' into develRussell King2009-03-245-4/+97
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| * [ARM] Feroceon: add highmem support to L2 cache handling codeNicolas Pitre2009-03-151-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The choice is between looping over the physical range and performing single cache line operations, or to map highmem pages somewhere, as cache range ops are possible only on virtual addresses. Because L2 range ops are much faster, we go with the later by factoring the physical-to-virtual address conversion and use a fixmap entry for it in the HIGHMEM case. Possible future optimizations to avoid the pte setup cost: - do the pte setup for highmem pages only - determine a threshold for doing a line-by-line processing on physical addresses when the range is small Signed-off-by: Nicolas Pitre <nico@marvell.com>
| * [ARM] make page_to_dma() highmem awareNicolas Pitre2009-03-152-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If a machine class has a custom __virt_to_bus() implementation then it must provide a __arch_page_to_dma() implementation as well which is _not_ based on page_address() to support highmem. This patch fixes existing __arch_page_to_dma() and provide a default implementation otherwise. The default implementation for highmem is based on __pfn_to_bus() which is defined only when no custom __virt_to_bus() is provided by the machine class. That leaves only ebsa110 and footbridge which cannot support highmem until they provide their own __arch_page_to_dma() implementation. But highmem support on those legacy platforms with limited memory is certainly not a priority. Signed-off-by: Nicolas Pitre <nico@marvell.com>
| * [ARM] introduce dma_cache_maint_page()Nicolas Pitre2009-03-152-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | This is a helper to be used by the DMA mapping API to handle cache maintenance for memory identified by a page structure instead of a virtual address. Those pages may or may not be highmem pages, and when they're highmem pages, they may or may not be virtually mapped. When they're not mapped then there is no L1 cache to worry about. But even in that case the L2 cache must be processed since unmapped highmem pages can still be L2 cached. Signed-off-by: Nicolas Pitre <nico@marvell.com>
| * [ARM] kmap supportNicolas Pitre2009-03-152-3/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The kmap virtual area borrows a 2MB range at the top of the 16MB area below PAGE_OFFSET currently reserved for kernel modules and/or the XIP kernel. This 2MB corresponds to the range covered by 2 consecutive second-level page tables, or a single pmd entry as seen by the Linux page table abstraction. Because XIP kernels are unlikely to be seen on systems needing highmem support, there shouldn't be any shortage of VM space for modules (14 MB for modules is still way more than twice the typical usage). Because the virtual mapping of highmem pages can go away at any moment after kunmap() is called on them, we need to bypass the delayed cache flushing provided by flush_dcache_page() in that case. The atomic kmap versions are based on fixmaps, and __cpuc_flush_dcache_page() is used directly in that case. Signed-off-by: Nicolas Pitre <nico@marvell.com>
| * [ARM] fixmap supportNicolas Pitre2009-03-151-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the minimum fixmap interface expected to be implemented by architectures supporting highmem. We have a second level page table already allocated and covering 0xfff00000-0xffffffff because the exception vector page is located at 0xffff0000, and various cache tricks already use some entries above 0xffff0000. Therefore the PTEs covering 0xfff00000-0xfffeffff are free to be used. However the XScale cache flushing code already uses virtual addresses between 0xfffe0000 and 0xfffeffff. So this reserves the 0xfff00000-0xfffdffff range for fixmap stuff. The Documentation/arm/memory.txt information is updated accordingly, including the information about the actual top of DMA memory mapping region which didn't match the code. Signed-off-by: Nicolas Pitre <nico@marvell.com>
* | Merge branch 'devel' of ↵root2009-03-242-0/+16
|\ \ | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6 into devel
| * | [ARM] pxa: add base support for Marvell's PXA168 processor lineEric Miao2009-03-232-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | """The Marvell® PXA168 processor is the first in a family of application processors targeted at mass market opportunities in computing and consumer devices. It balances high computing and multimedia performance with low power consumption to support extended battery life, and includes a wealth of integrated peripherals to reduce overall BOM cost .... """ See http://www.marvell.com/featured/pxa168.jsp for more information. 1. Marvell Mohawk core is a hybrid of xscale3 and its own ARM core, there are many enhancements like instructions for flushing the whole D-cache, and so on 2. Clock reuses Russell's common clkdev, and added the basic support for UART1/2. 3. Devices are a bit different from the 'mach-pxa' way, the platform devices are now dynamically allocated only when necessary (i.e. when pxa_register_device() is called). Description for each device are stored in an array of 'struct pxa_device_desc'. Now that: a. this array of device description is marked with __initdata and can be freed up system is fully up b. which means board code has to add all needed devices early in his initializing function c. platform specific data can now be marked as __initdata since they are allocated and copied by platform_device_add_data() 4. only the basic UART1/2/3 are added, more devices will come later. Signed-off-by: Jason Chagas <chagas@marvell.com> Signed-off-by: Eric Miao <eric.miao@marvell.com>
* | | [ARM] pass reboot command line to arch_reset()Russell King2009-03-191-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OMAP wishes to pass state to the boot loader upon reboot in order to instruct it whether to wait for USB-based reflashing or not. There is already a facility to do this via the reboot() syscall, except we ignore the string passed to machine_restart(). This patch fixes things to pass this string to arch_reset(). This means that we keep the reboot mode limited to telling the kernel _how_ to perform the reboot which should be independent of what we request the boot loader to do. Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | Merge branch 'for-russell' of ↵Russell King2009-03-171-0/+1
|\ \ \ | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/chris/linux-2.6 into devel
| * | | IXP4xx: workaround for PCI prefetch problems near 64 MB boundary.Krzysztof Hałasa2009-03-171-0/+1
| | |/ | |/| | | | | | | | | | | | | | | | Map unused registers at the end of DMA region at 64 MB to allow PCI masters to cross the boundary when prefetching data from SDRAM. Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
* | | [ARM] 5422/1: ARM: MMU: add a Non-cacheable Normal executable memory typePaul Walmsley2009-03-121-0/+1
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a Non-cacheable Normal ARM executable memory type, MT_MEMORY_NONCACHED. On OMAP3, this is used for rapid dynamic voltage/frequency scaling in the VDD2 voltage domain. OMAP3's SDRAM controller (SDRC) is in the VDD2 voltage domain, and its clock frequency must change along with voltage. The SDRC clock change code cannot run from SDRAM itself, since SDRAM accesses are paused during the clock change. So the current implementation of the DVFS code executes from OMAP on-chip SRAM, aka "OCM RAM." If the OCM RAM pages are marked as Cacheable, the ARM cache controller will attempt to flush dirty cache lines to the SDRC, so it can fill those lines with OCM RAM instruction code. The problem is that the SDRC is paused during DVFS, and so any SDRAM access causes the ARM MPU subsystem to hang. TI's original solution to this problem was to mark the OCM RAM sections as Strongly Ordered memory, thus preventing caching. This is overkill: since the memory is marked as non-bufferable, OCM RAM writes become needlessly slow. The idea of "Strongly Ordered SRAM" is also conceptually disturbing. Previous LAKML list discussion is here: http://www.spinics.net/lists/arm-kernel/msg54312.html This memory type MT_MEMORY_NONCACHED is used for OCM RAM by a future patch. Cc: Richard Woodruff <r-woodruff2@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | Merge branch 'dma' into develRussell King2009-02-212-44/+37
|\ \ | | | | | | | | | | | | | | | Conflicts: arch/arm/plat-mxc/dma-mx1-mx2.c
| * | [ARM] dma: move IOMD and floppy DMA structures to RiscPC DMA codeRussell King2009-02-211-13/+0
| | | | | | | | | | | | | | | | | | | | | There's no point these being in a generic include file when they're only used in arch/arm/mach-rpc/dma.c. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | [ARM] dma: remove dmamode_t typedefRussell King2009-01-022-7/+2
| | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | [ARM] dma: make DMA_MODE_xxx reflect ISA DMA settingsRussell King2009-01-021-5/+8
| | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | [ARM] dma: constify dma controller name and dma opsRussell King2008-12-111-2/+2
| | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | [ARM] dma: move RiscPC specific DMA data out of dma_structRussell King2008-12-111-5/+13
| | | | | | | | | | | | | | | | | | | | | Separate the RiscPC specific (IOMD and floppy FIQ) data out of the core DMA structure by making the IOMD and floppy DMA supersets. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | [ARM] dma: rejig DMA initializationRussell King2008-12-111-5/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than having the central DMA multiplexer call the architecture specific DMA initialization function, have each architecture DMA initialization function use core_initcall(), and register each DMA channel separately with the multiplexer. This removes the array of dma structures in the central multiplexer, replacing it with an array of pointers instead; this is more flexible since it allows the drivers to wrap the DMA structure (eventually allowing us to transition non-ISA DMA drivers away.) Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | [ARM] dma: remove dmach_t typedefRussell King2008-12-082-23/+21
| | | | | | | | | | | | | | | | | | Remove a pointless integer typedef. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | [ARM] 5384/1: unwind: Add stack unwinding support for loadable modulesCatalin Marinas2009-02-192-5/+18
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds ELF section parsing for the unwinding tables in loadable modules together with the PREL31 relocation symbol resolving. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | [ARM] 5383/2: unwind: Add core support for ARM stack unwindingCatalin Marinas2009-02-191-0/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the main functionality for parsing the stack unwinding information generated by the ARM EABI toolchains. The unwinding information consists of an index with a pair of words per function and a table with unwinding instructions. For more information, see "Exception Handling ABI for the ARM Architecture" at: http://infocenter.arm.com/help/topic/com.arm.doc.subset.swdev.abi/index.html Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | [ARM] 5382/1: unwind: Reorganise the stacktrace supportCatalin Marinas2009-02-122-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch changes the walk_stacktrace and its callers for easier integration of stack unwinding. The arch/arm/kernel/stacktrace.h file is also moved to arch/arm/include/asm/stacktrace.h. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | [ARM] 5381/1: unwind: Reorganise the traps.c codeCatalin Marinas2009-02-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | This patch moves code around in the arch/arm/kernel/traps.c file for easier integration of the stack unwinding support. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | [ARM] 5388/1: Add hwcap bits for VFPv3 and VFPv3D16Catalin Marinas2009-02-121-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The VFPv3D16 is a VFPv3 CPU configuration where only 16 double registers are present, as the VFPv2 configuration. This patch adds the corresponding hwcap bits so that applications or debuggers have more information about the supported features. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | [ARM] 5387/1: Add ptrace VFP support on ARMCatalin Marinas2009-02-123-0/+13
| |/ |/| | | | | | | | | | | | | | | | | | | | | This patch adds ptrace support for setting and getting the VFP registers using PTRACE_SETVFPREGS and PTRACE_GETVFPREGS. The user_vfp structure defined in asm/user.h contains 32 double registers (to cover VFPv3 and Neon hardware) and the FPSCR register. Cc: Paul Brook <paul@codesourcery.com> Cc: Daniel Jacobowitz <dan@codesourcery.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | byteorder: make swab.h include asm/swab.h like a regular headerHarvey Harrison2009-01-142-3/+0
| | | | | | | | | | | | | | | | | | Add swab.h to kbuild.asm and remove the individual entries from each arch, mark as unifdef as some arches have some kernel-only bits inside. Signed-off-by: Harvey Harrison <harvey.harrison@gmail.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | NOMMU: Make VMAs per MM as for MMU-mode linuxDavid Howells2009-01-081-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make VMAs per mm_struct as for MMU-mode linux. This solves two problems: (1) In SYSV SHM where nattch for a segment does not reflect the number of shmat's (and forks) done. (2) In mmap() where the VMA's vm_mm is set to point to the parent mm by an exec'ing process when VM_EXECUTABLE is specified, regardless of the fact that a VMA might be shared and already have its vm_mm assigned to another process or a dead process. A new struct (vm_region) is introduced to track a mapped region and to remember the circumstances under which it may be shared and the vm_list_struct structure is discarded as it's no longer required. This patch makes the following additional changes: (1) Regions are now allocated with alloc_pages() rather than kmalloc() and with no recourse to __GFP_COMP, so the pages are not composite. Instead, each page has a reference on it held by the region. Anything else that is interested in such a page will have to get a reference on it to retain it. When the pages are released due to unmapping, each page is passed to put_page() and will be freed when the page usage count reaches zero. (2) Excess pages are trimmed after an allocation as the allocation must be made as a power-of-2 quantity of pages. (3) VMAs are added to the parent MM's R/B tree and mmap lists. As an MM may end up with overlapping VMAs within the tree, the VMA struct address is appended to the sort key. (4) Non-anonymous VMAs are now added to the backing inode's prio list. (5) Holes may be punched in anonymous VMAs with munmap(), releasing parts of the backing region. The VMA and region structs will be split if necessary. (6) sys_shmdt() only releases one attachment to a SYSV IPC shared memory segment instead of all the attachments at that addresss. Multiple shmat()'s return the same address under NOMMU-mode instead of different virtual addresses as under MMU-mode. (7) Core dumping for ELF-FDPIC requires fewer exceptions for NOMMU-mode. (8) /proc/maps is now the global list of mapped regions, and may list bits that aren't actually mapped anywhere. (9) /proc/meminfo gains a line (tagged "MmapCopy") that indicates the amount of RAM currently allocated by mmap to hold mappable regions that can't be mapped directly. These are copies of the backing device or file if not anonymous. These changes make NOMMU mode more similar to MMU mode. The downside is that NOMMU mode requires some extra memory to track things over NOMMU without this patch (VMAs are no longer shared, and there are now region structs). Signed-off-by: David Howells <dhowells@redhat.com> Tested-by: Mike Frysinger <vapier.adi@gmail.com> Acked-by: Paul Mundt <lethal@linux-sh.org>
* | PCI: arm: use generic INTx swizzle from PCI coreBjorn Helgaas2009-01-071-1/+1
| | | | | | | | | | | | | | Use the generic pci_common_swizzle() instead of arch-specific code. Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | arm: introduce asm/swab.hHarvey Harrison2009-01-063-32/+52
| | | | | | | | | | Signed-off-by: Harvey Harrison <harvey.harrison@gmail.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | atomic_t: unify all arch definitionsMatthew Wilcox2009-01-061-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | The atomic_t type cannot currently be used in some header files because it would create an include loop with asm/atomic.h. Move the type definition to linux/types.h to break the loop. Signed-off-by: Matthew Wilcox <willy@linux.intel.com> Cc: Huang Ying <ying.huang@intel.com> Cc: <linux-arch@vger.kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | Merge branch 'next-merged' of git://aeryn.fluff.org.uk/bjdooks/linux into develRussell King2008-12-181-4/+6
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| * | [ARM] VIC: Update asm/hardware/vic.h with PL192 informationBen Dooks2008-12-151-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The original arch/arm/include/asm/hardware/vic.h was written for the PL190 ARM VIC implementation, and as such does not have any information about the PL192 version. Add details about the PL192 and PL190 specific registers and any changes between the two units. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
* | | Merge branch 'omap3-upstream' of ↵Russell King2008-12-152-7/+11
|\ \ \ | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6 into devel
| * | | [ARM] 5340/1: fix stack placement after noexecstack changesLennert Buytenhek2008-12-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 8ec53663d2698076468b3e1edc4e1b418bd54de3 ("[ARM] Improve non-executable support") added support for detecting non-executable stack binaries. One of the things it does is to make READ_IMPLIES_EXEC be set in ->personality if we are running on a CPU that doesn't support the XN ("Execute Never") page table bit or if we are running a binary that needs an executable stack. This exposed a latent bug in ARM's asm/processor.h due to which we'll end up placing the stack at a very low address, where it will bump into the heap on any application that uses significant amount of stack or heap or both, causing many interesting crashes. Fix this by testing the ADDR_LIMIT_32BIT bit in ->personality instead of testing for equality against PER_LINUX_32BIT. Reviewed-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | [ARM] 5339/1: fix __fls() on ARMNicolas Pitre2008-12-041-6/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 0c65f459ce6c intended to fix truncation issues with fls() on ARMv5+ by renaming it to __fls() and wrapping it into a C function. However that didn't take into account the fact that __fls() already already had different semantics in the kernel. Let's move the __fls() code into fls() function directly, and redefine __fls() with the appropriate semantics. While at it, bring a generic __fls() definition for pre ARMv5 too. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | [ARM] move asm/xip.h's mach/hardware.h include to mach/xip.hRussell King2008-12-141-1/+0
| |/ / |/| | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | [ARM] dma: correct dma_supported() implementationRussell King2008-12-131-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dma_supported() is supposed to indicate whether the system can support the DMA mask it was passed, which depends on the maximal address which can be returned for DMA allocations. If the mask is smaller than that, we are unable to guarantee that the driver can reliably obtain suitable memory. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | Merge branch 'for-rmk-realview' of git://linux-arm.org/linux-2.6 into develRussell King2008-12-011-3/+3
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| * | | RealView: Use only the shadow mapping of ARM11MPCore local timersCatalin Marinas2008-12-011-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All the cases where the local timer for a CPU is accessed happen on the corresponding current CPU, hence no need to access the per-CPU local timer mappings. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* | | | [ARM] Add a common typesafe __io implementationRussell King2008-11-301-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As Al did for Versatile in 2ad4f86b60b649fd7428265c08d73a3bd360c81b, add a typesafe __io implementation for platforms to use. Convert platforms to use this new simple typesafe implementation. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | [ARM] give RiscPC a NR_IRQS definition and remove defaultRussell King2008-11-291-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RiscPC is the only platform using the default setting for NR_IRQS, so the default NR_IRQS doesn't really make sense; remove it and make RiscPC provide such a definition. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | [ARM] Remove linux/sched.h from asm/cacheflush.h and asm/uaccess.hRussell King2008-11-293-2/+3
| |_|/ |/| | | | | | | | | | | | | | | | | ... and fix those drivers that were incorrectly relying upon that include. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | [ARM] Rename ISA mach/dma.h header to mach/isa-dma.hRussell King2008-11-291-1/+1
| | | | | | | | | | | | | | | | | | | | | This avoids confusion with platform specific DMA implementations in mach/dma.h Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | [ARM] Hide ISA DMA API when ISA_DMA_API is unsetRussell King2008-11-291-7/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When ISA_DMA_API is unset, we're not implementing the ISA DMA API, so there's no point in publishing the prototypes via asm/dma.h, nor including the machine dependent parts of that API. This allows us to remove a lot of mach/dma.h files which don't contain any useful code. Unfortunately though, some platforms put their own private non-ISA definitions into mach/dma.h, so we leave these behind and fix the appropriate #include statments. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | [ARM] move MAX_DMA_ADDRESS to mach/memory.hRussell King2008-11-291-0/+1
| | | | | | | | | | | | | | | | | | | | | Move the definition of MAX_DMA_ADDRESS from mach/dma.h to mach/memory.h, thereby placing it along side its relative, ISA_DMA_THRESHOLD. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | [ARM] asm/system.h does not require asm/memory.hRussell King2008-11-281-2/+0
| | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | Merge branch 'highmem' into develRussell King2008-11-283-16/+27
|\ \ \ | | | | | | | | | | | | | | | | | | | | Conflicts: arch/arm/mach-clps7500/include/mach/memory.h
| * | | [ARM] remove a common set of __virt_to_bus definitionsNicolas Pitre2008-11-281-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Let's provide an overridable default instead of having every machine class define __virt_to_bus and __bus_to_virt to the same thing. What most platforms are using is bus_addr == phys_addr so such is the default. One exception is ebsa110 which has no DMA what so ever, so the actual definition is not important except only for proper compilation. Also added a comment about the special footbridge bus translation. Let's also remove comments alluding to set_dma_addr which is not (and should not) be commonly used. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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