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* ARM: 6741/1: errata: pl310 cache sync operation may be faultySrinidhi Kasagar2011-02-191-0/+1
| | | | | | | | | | | | | | | | | | | | | | The effect of cache sync operation is to drain the store buffer and wait for all internal buffers to be empty. In normal conditions, store buffer is able to merge the normal memory writes within its 32-byte data buffers. Due to this erratum present in r3p0, the effect of cache sync operation on the store buffer still remains when the operation completes. This means that the store buffer is always asked to drain and this prevents it from merging any further writes. This can severely affect performance on the write traffic esp. on Normal memory NC one. The proposed workaround is to replace the normal offset of cache sync operation(0x730) by another offset targeting an unmapped PL310 register 0x740. Signed-off-by: srinidhi kasagar <srinidhi.kasagar@stericsson.com> Acked-by: Linus Walleij <linus.walleij@stericsson.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2x0: Add aux control register bitfieldsSantosh Shilimkar2010-12-181-1/+11
| | | | | | | | | | This patch adds the PL310 Auxiliary Control Register bitfields so that SOC's can use these bit fields to construct the AUXCTRL value to be passed/programmed instead of hardcoding it. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* Merge branch 'l2x0-pull-rmk' of ↵Russell King2010-10-281-3/+6
|\ | | | | | | git://dev.omapzoom.org/pub/scm/santosh/kernel-omap4-base into devel-stable
| * ARM: l2x0: Determine the cache sizeSantosh Shilimkar2010-10-261-0/+1
| | | | | | | | | | | | | | | | | | The cache size is needed for to optimise range based maintainance operations Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Linus Walleij <linus.walleij@stericsson.com>
| * ARM: l2x0: Fix coding-style in the cache-l2x0.hSantosh Shilimkar2010-10-261-3/+5
| | | | | | | | | | | | | | | | | | Replace tab with space after #define to be consisten with other define in the file. Also move the bit mask below the register offsets. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Linus Walleij <linus.walleij@stericsson.com>
* | ARM: Add L2X0 PREFETCH and POWER control registerKyungmin Park2010-10-251-0/+4
|/ | | | | | | | This patch adds L2X0 Prefetch and Power control register. Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* ARM: 6094/1: Extend cache-l2x0 to support the 16-way PL310Jason McMullan2010-05-151-0/+3
| | | | | | | | | | | | | | | | The L310 cache controller's interface is almost identical to the L210. One major difference is that the PL310 can have up to 16 ways. This change uses the cache's part ID and the Associativity bits in the AUX_CTRL register to determine the number of ways. Also, this version prints out the CACHE_ID and AUX_CTRL registers. Acked-by: Will Deacon <will.deacon@arm.com> Acked-by: Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Jason S. McMullan <jason.mcmullan@netronome.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* RealView: Add support for the RealView/PBX platformColin Tuckley2009-05-301-0/+2
| | | | | | | | | This is a RealView platform supporting core tiles with ARM11MPCore, Cortex-A8 or Cortex-A9 (multicore) processors. It has support for MMC, CompactFlash, PCI-E. Signed-off-by: Colin Tuckley <colin.tuckley@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* [ARM] move include/asm-arm to arch/arm/include/asmRussell King2008-08-021-0/+56
Move platform independent header files to arch/arm/include/asm, leaving those in asm/arch* and asm/plat* alone. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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