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* Merge tag 'tegra-for-3.15-dt' of ↵Olof Johansson2014-03-201-1/+5
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt Merge "ARM: tegra: device tree changes for 3.15" from Stephen Warren: This enables: - host1x and eDP support on Tegra124. - LCD panel support for a few Tegra20 devices and Venice2. - Enables power down, SPI flash, and USB on Venice2. - Documents which Dalmore revision is supported. - Adds an I2C bus mux to Cardhu. Additionally, Tegra124 is converted to use #address-cells=<2> since the HW suports more than 32-bits of address space, and various cleanups are included. * tag 'tegra-for-3.15-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (21 commits) ARM: dts: tegra: add PCIe interrupt mapping properties ARM: tegra: use 2 address cells for Tegra124 DT ARM: tegra: Rename as3722 node to pmic ARM: tegra: Fix whitespace around '=' ARM: tegra: Enable USB on Venice2 ARM: tegra: Add Tegra124 USB support ARM: tegra: Enable eDP for Venice2 ARM: tegra: Add Tegra124 eDP support ARM: tegra: Add Tegra124 host1x support ARM: tegra: Hook up SDMMC3 power-supply on Venice2 ARM: tegra: Overhaul Venice2 regulators ARM: tegra: Combine VBUS enable pins into one node ARM: tegra: Use "disabled" for status property ARM: tegra: add SPI flash to Venice2 DT ARM: tegra: enable PCA9546 on Cardhu ARM: tegra: enable LCD panel on Ventana ARM: tegra: enable LCD panel on Seaboard ARM: tegra: add system-power-controller property for PMIC node ARM: tegra: document which Dalmore revisions are supported ARM: tegra: Properly sort clocks property ... Signed-off-by: Olof Johansson <olof@lixom.net>
| * ARM: dts: tegra: add PCIe interrupt mapping propertiesLucas Stach2014-03-061-0/+4
| | | | | | | | | | | | | | | | Those are defined by the common PCI binding. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: Properly sort clocks propertyThierry Reding2014-02-051-1/+1
| | | | | | | | | | | | | | | | Other files and nodes list the resets property after the clocks property so do the same here for consistency. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra: Add head numbers to display controllersThierry Reding2014-02-181-0/+4
|/ | | | | | | | | | The number of the head specifies the index of the display controller unit and is required to properly configure outputs so that they receive video data from the correct source. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
* ARM: tegra: modify Tegra30 USB2 default phy_type to UTMIEric Brower2013-12-201-5/+16
| | | | | | | | | | | Modify Tegra30 default USB2 phy_type to UTMI; this matches power-on-reset defaults and is expected to be the common case. The current implementation is likely an incorrect carry-over from Tegra20, where USB2 does default to ULPI. Signed-off-by: Eric Brower <ebrower@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: convert dts files of Tegra30 platforms to use pinctrl definesLaxman Dewangan2013-12-161-0/+1
| | | | | | | | Use Tegra pinconrol dt-binding macro to set the values of different pinmux properties of Tegra30 platforms. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: add missing unit addresses to DTStephen Warren2013-12-161-25/+25
| | | | | | | | | | DT node names should include a unit address iff the node has a reg property. For Tegra DTs at least, we were previously applying a different rule, namely that node names only needed to include a unit address if it was required to make the node name unique. Consequently, many unit addresses are missing. Add them. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: remove legacy DMA entries from DTStephen Warren2013-12-111-12/+0
| | | | | | | | | Now that all Tegra drivers have been converted to use DMA APIs which retrieve DMA channel information from standard DMA DT properties, we can remove all the legacy DT DMA-related properties. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
* ARM: tegra: remove legacy clock entries from DTStephen Warren2013-12-111-15/+3
| | | | | | | | | Now that all Tegra drivers have been converted to use the common reset framework, we can remove all the legacy DT clocks/clock-names entries for "clocks" that were only used with the old custom Tegra module reset API. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
* ARM: tegra: update DT files to add DMA propertiesStephen Warren2013-12-111-0/+39
| | | | | | | | | This patch switches the Tegra DT files to use the standard DMA DT bindings rather than custom properties. Note that the legacy properties are not yet removed; the drivers must be updated to use the new properties first. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
* ARM: tegra: update DT files to add reset propertiesStephen Warren2013-12-111-0/+104
| | | | | | | | | | | | An earlier patch updated the Tegra DT bindings to require resets and reset-names properties to be filled in. This patch updates the DT files to include those properties. Note that any legacy clocks and clock-names entries that are replaced by reset properties are not yet removed; the drivers must be updated to use the new resets and reset-names properties first. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: add missing clock documentation to DT bindingsStephen Warren2013-12-111-2/+2
| | | | | | | | | | | | | Many of the Tegra DT binding documents say nothing about the clocks or clock-names properties, yet those are present and required in DT files. This patch simply updates the documentation file to match the implicit definition of the binding, based on real-world DT content. All Tegra bindings that mention clocks are updated to have consistent wording and formatting of the clock-related properties. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-By: Terje Bergstrom <tbergstrom@nvidia.com>
* ARM: tegra: Use symbolic names for gr3d clocksThierry Reding2013-10-171-1/+2
| | | | | | | | | Commit 05849c9381354be4bd4a2a878b5ecb12d375a1a0 (ARM: tegra30: convert device tree files to use CLK defines) updated the Tegra30 device tree to use symbolic clock names but forgot to update this node. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: Mark Tegra30 display controller compatible with Tegra20Thierry Reding2013-10-171-1/+1
| | | | | | | | The display controller found on Tegra30 SoCs is backwards-compatible with the one on Tegra20 SoCs. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: add USB DT entries for Tegra30Tuomas Tynkkynen2013-08-131-0/+86
| | | | | | | | | | | | Add device tree entries for the 3 USB controllers and PHYs and enable the third controller on Cardhu and Beaver boards. Fix VBUS regulator entries on Beaver. The GPIO pins were wrong. Also, internal pullups need to be enabled on those pins. Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: dts: tegra: Increase prefetchable PCI memory spaceJay Agarwal2013-08-121-2/+2
| | | | | | | | | | | | | Instead of evenly splitting the 512 MiB area between prefetchable and non-prefetchable memory spaces, increase the prefetchable memory space to 384 MiB while at the same time decreasing the non-prefetchable memory space to 128 MiB. This is a more useful default as most PCIe devices require more prefetchable than non-prefetchable memory. Signed-off-by: Jay Agarwal <jagarwal@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: Add Tegra30 PCIe supportThierry Reding2013-08-121-0/+70
| | | | | | | | | Add the top-level pcie-controller node for the Tegra30 SoC. Tegra30 has three root ports that can use different lane layouts. Signed-off-by: Jay Agarwal <jagarwal@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra30: convert device tree files to use CLK definesHiroshi Doyu2013-05-281-47/+63
| | | | | | | | | | | | Use the Tegra30 CAR binding header (tegra30-car.h) to replace magic numbers in the device tree. For example, - clocks = <&tegra_car 28>; + clocks = <&tegra_car CLK_HOST1X>; Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> [swarren, updated since tegra30-car.h moved for consistency] Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: convert device tree files to use IRQ definesStephen Warren2013-05-281-86/+88
| | | | | | Use the GIC and standard IRQ binding defines in all IRQ specifiers. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: convert device tree files to use GPIO definesStephen Warren2013-05-281-0/+2
| | | | | | | Use TEGRA_GPIO() macro to name all GPIOs referenced by GPIO properties, and some interrupts properties. Use standard GPIO flag defines too. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: use #include for all device treesStephen Warren2013-05-281-1/+1
| | | | | | | | | | | | | Replace /include/ (dtc) with #include (C pre-processor) for all Tegra DT files, so that gcc -E handles the entire include tree, and hence any of those files can #include some other file e.g. for constant definitions. This allows future use of #defines and header files in order to define names for various constants, such as the IDs and flags in GPIO specifiers. Use of those features will increase the readability of the device tree files. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Merge tag 'tegra-for-3.10-dt' of ↵Arnd Bergmann2013-04-091-0/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/dt2 From Stephen Warren <swarren@wwwdotorg.org>: ARM: tegra: device tree changes This branch contains the majority of the device tree changes for Tegra. Highlights include: * Many changes for Tegra114, and the Dalmore board, to enable pinctrl, SDHCI/MMC, PWM, DMA, I2C, KBC, SPI, battery, regulators. * Adding or enabling suspend wakeup sources on many boards, and adding suspend timing parameters, to support the system suspend patches. * Adding clocks to the audio-related nodes, so that in 3.11, the audio driver can pull these clocks from device tree rather than hard-coding clock names. * Some small DT fixes/cleanup. This branch is based on the previous clk pull request. * tag 'tegra-for-3.10-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: (25 commits) clk: tegra: Fix cdev1 and cdev2 IDs ARM: dts: tegra: add the PM configurations of PMC ARM: tegra: add non-removable and keep-power-in-suspend property for MMC ARM: tegra: whistler: add wakeup source for KBC ARM: tegra: add power gpio keys to DT ARM: tegra: keep power on to SD slot on Dalmore ARM: tegra: add clocks property to AC'97 sound nodes ARM: tegra: add clocks property to sound nodes ARM: tegra: dalmore: add fixed regulator node ARM: tegra: dalmore: add TPS65090 node ARM: tegra: dalmore: add cpu regulator node ARM: tegra: Add sbs-battery node to Dalmore ARM: tegra: add DT binding for i2c-tegra ARM: tegra: add SPI nodes to Tegra114 DT ARM: tegra: add KBC nodes to Tegra114 DT ARM: tegra: add aliases and DMA requestor for serial nodes of Tegra114 ARM: tegra: add I2C nodes to Tegra114 DT ARM: tegra: add APB DMA nodes to Tegra114 DT ARM: tegra: add PWM nodes to Tegra114 DT ARM: tegra: fix the status of PWM DT nodes ... Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * ARM: tegra: fix the status of PWM DT nodesAndrew Chew2013-04-041-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We should be defining the PWM nodes with status as "disabled" in the chip-specific dtsi file, since we don't know whether specific boards will use the PWM or not. This patch fixes the PWM node status for Tegra20 and Tegra30. Also fixed the one user of PWM, which is the Tegra20 medcom-wide board, so that PWM is set to "okay" in the board-specific dts file. Signed-off-by: Andrew Chew <achew@nvidia.com> [swarren: in medcom-wide: fixed node sort order, removed duplicate pwm: label, fixed syntax error] Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | Merge branch 'tegra/clk' into next/dt2Arnd Bergmann2013-04-091-1/+5
|\ \ | |/ | | | | | | | | | | | | | | This is a dependency for the tegra/dt branch. Conflicts: drivers/clocksource/tegra20_timer.c Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * Merge branch 'for-3.10/soc' into for-3.10/clkStephen Warren2013-04-041-1/+5
| |\
| | * ARM: tegra: add clock source of PMC to device treesJoseph Lo2013-04-031-0/+2
| | | | | | | | | | | | | | | | | | | | | Adding the bindings of the clock source of PMC in DT. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| | * ARM: tegra: fix the PMC compatible string in DTJoseph Lo2013-03-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The PMC HW is not 100% compatible across all Tegra series. We need to specify them in DT. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| | * clocksource: tegra: move to of_clk_getPeter De Schrijver2013-03-111-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new clockframework introduced DT IDs for each clock. To be able to remove the device registrations, this driver needs to be updated to use the DT IDs. Note that the actual removal of the clk_register_clkdev() calls will be done in a later series. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | | ARM: tegra: fix register address of slink controllerLaxman Dewangan2013-03-221-1/+1
|/ / | | | | | | | | | | | | | | | | | | Fix typo on register address of slink3 controller where register address is wrongly set as 0x7000d480 but it is 0x7000d800. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Cc: <stable@vger.kernel.org> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* | ARM: Tegra: Add clock entry for smp_twd clockPrashant Gaikwad2013-03-041-0/+1
|/ | | | | | | | | | | | | As DT support for clocks and smp_twd is enabled, add clock entry for smp_twd clock to DT. This fixes the following error while booting the kernel: smp_twd: clock not found -2 Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> [swarren: include kernel log spew that this fixes] Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
* ARM: tegra: remove clock-frequency properties from serial nodesStephen Warren2013-02-131-5/+0
| | | | | | | | | | | | | Currently, the serial nodes define both a clock-frequency and a clocks property. We should not provide both, since they might conflict. In practice, this also causes problems since the of_serial driver uses the clock-frequency property in preference to the clocks property, and hence doesn't clk_prepare_enable() the clock, which may then leave it with no known users, and hence the common clock framework will disable it, thus breaking the port, which is usually the console. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: dt: tegra30: Rename "smmu" to "iommu"Hiroshi Doyu2013-01-291-1/+1
| | | | | | | Use functional name for DT entry instead of h/w name. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: move serial clock-frequency attr into the Tegra30 dtsiStephen Warren2013-01-281-0/+5
| | | | | | | | No Tegra30 Platform is running PLL_P at another rate than 408MHz, nor is any using any other PLL as UART source clock. Move attribute into SoC level dtsi file to slim down board DT files. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: add DT entry for KBC controllerLaxman Dewangan2013-01-281-0/+8
| | | | | | | | | | | | NVIDIA's Tegra SoCs have the matrix keyboard controller which supports 16x8 type of matrix. The number of rows and columns are configurable. Add DT entry for KBC controller. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> [swarren: added clocks property] Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: swap cache-/interrupt-ctrlr nodes in DTStephen Warren2013-01-281-9/+9
| | | | | | | | | | | | This ensures nodes are sorted in order of reg address. This makes it easier to compare against e.g. the U-Boot device trees, and is simply consistent and clean. While we're at it, remove the unit address from the cache-controller node name, since it's unique without it. Reported-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: dts: add aliases and DMA requestor for serial controllerLaxman Dewangan2013-01-281-5/+26
| | | | | | | | | | | | | Add APB DMA requestor and serial aliases for serial controller. There will be two serial driver i.e. 8250 based simple serial driver and APB DMA based serial driver for higher baudrate and performace. The simple serial driver get enabled with compatible nvidia,tegra20-uart and APB DMA based driver will get enabled with compatible nvidia,tegra20-hsuart. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra30: tegra30 gpio is not compatible with tegra20 gpioLaxman Dewangan2013-01-281-1/+1
| | | | | | | | | | tegra30 gpio controller is not compatible with the tegra20 due to their bank stride i.e. Tegra20 bank stride is 0x80 where Tegra30 bank stride is 0x100. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> [swarren: fixed typo syntax error] Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Merge branch 'for-3.9/scu-base-rework' into for-3.9/soc-t114Stephen Warren2013-01-281-0/+29
|\ | | | | | | | | Conflicts: arch/arm/mach-tegra/platsmp.c
| * ARM: tegra: Add CPU nodes to Tegra30 device treeHiroshi Doyu2013-01-281-0/+29
| | | | | | | | | | | | | | | | Add CPU node for Tegra30. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Reviewed-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra: add clock properties to Tegra30 DTPrashant Gaikwad2013-01-281-1/+55
| | | | | | | | | | | | | | | | Add clock information to device nodes. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> [swarren: added second clock to 3d node] Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra: define Tegra30 CAR bindingPrashant Gaikwad2013-01-281-0/+6
|/ | | | | | | | | The device tree binding models Tegra30 CAR (Clock And Reset) as a single monolithic clock provider. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> [swarren: fixed typo in binding doc] Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Merge tag 'multiplatform' of ↵Linus Torvalds2012-12-131-0/+23
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC multiplatform conversion patches from Olof Johansson: "Here are more patches in the progression towards multiplatform, sparse irq conversions in particular. Tegra has a handful of cleanups and general groundwork, but is not quite there yet on full enablement. Platforms that are enabled through this branch are VT8500 and Zynq. Note that i.MX was converted in one of the earlier cleanup branches as well (before we started a separate topic for multiplatform). And both new platforms for this merge window, sunxi and bcm, were merged with multiplatform support enabled." Fix up conflicts mostly as per Olof. * tag 'multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (29 commits) ARM: zynq: Remove all unused mach headers ARM: zynq: add support for ARCH_MULTIPLATFORM ARM: zynq: make use of debug_ll_io_init() ARM: zynq: remove TTC early mapping ARM: tegra: move debug-macro.S to include/debug ARM: tegra: don't include iomap.h from debug-macro.S ARM: tegra: decouple uncompress.h and debug-macro.S ARM: tegra: simplify DEBUG_LL UART selection options ARM: tegra: select SPARSE_IRQ ARM: tegra: enhance timer.c to get IO address from device tree ARM: tegra: enhance timer.c to get IRQ info from device tree ARM: timer: fix checkpatch warnings ARM: tegra: add TWD to device tree ARM: tegra: define DT bindings for and instantiate RTC ARM: tegra: define DT bindings for and instantiate timer clocksource/mtu-nomadik: use apb_pclk clk: ux500: Register mtu apb_pclocks ARM: plat-nomadik: convert platforms to SPARSE_IRQ mfd/db8500-prcmu: use the irq_domain_add_simple() mfd/ab8500-core: use irq_domain_add_simple() ...
| * ARM: tegra: add TWD to device treeStephen Warren2012-11-161-0/+6
| | | | | | | | | | | | | | This will allow timer.c to use twd_local_timer_of_register(), and hence not need to hard-code the TWD address or IRQ. Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: define DT bindings for and instantiate RTCStephen Warren2012-11-161-0/+6
| | | | | | | | | | | | | | | | | | | | | | The Tegra RTC maintains seconds and milliseconds counters, and five alarm registers. The alarms and other interrupts may wake the system from low-power state. Define a DT binding for this HW module, and add the module into the Tegra device tree files. Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: define DT bindings for and instantiate timerStephen Warren2012-11-161-0/+11
| | | | | | | | | | | | | | | | | | | | | | The Tegra timer provides a number of 29-bit timer channels, a single 32-bit free running counter, and in the Tegra30 variant, 5 watchdog modules. The first two channels may also trigger a legacy watchdog reset. Define a DT binding for this HW module, and add the module into the Tegra device tree files. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | Merge tag 'orion_dt_for_3.8' of git://git.infradead.org/users/jcooper/linux ↵Olof Johansson2012-11-261-2/+2
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into next/dt From Jason Cooper: orion dt for v3.8 - ehci-orion dt binding - gpio-poweroff - use dt regulators - move mpp to DT/pinctrl Depends on: - orion/boards - merge conflicts - keep all 'select's in Kconfig - remove all #includes in board-*.c - pinctrl/devel up to: - 06763c7 pinctrl: mvebu: move to its own directory * tag 'orion_dt_for_3.8' of git://git.infradead.org/users/jcooper/linux: (211 commits) ARM: Kirkwood: remove kirkwood_ehci_init() from new boards ARM: Kirkwood: Add support LED of OpenBlocks A6 ARM: Kirkwood: Convert to EHCI via DT for OpenBlocks A6 ARM: kirkwood: Add NAND partiton map for OpenBlocks A6 ARM: kirkwood: Add support second I2C bus and RTC on OpenBlocks A6 ARM: kirkwood: Add support DT of second I2C bus ARM: kirkwood: Convert mplcec4 board to pinctrl ARM: Kirkwood: Convert km_kirkwood to pinctrl ARM: Kirkwood: support 98DX412x kirkwoods with pinctrl ARM: Kirkwood: Convert IX2-200 to pinctrl. ARM: Kirkwood: Convert lsxl boards to pinctrl. ARM: Kirkwood: Convert ib62x0 to pinctrl. ARM: Kirkwood: Convert GoFlex Net to pinctrl. ARM: Kirkwood: Convert dreamplug to pinctrl. ARM: Kirkwood: Convert dockstar to pinctrl. ARM: Kirkwood: Convert dnskw to pinctrl ARM: Kirkwood: Convert iConnect to pinctrl. ARM: Kirkwood: Convert TS219 to pinctrl. ARM: Kirkwood: Add DTSI files for pinctrl ARM: Kirkwood: Make use of mvebu pincltl and gpio drivers ... Signed-off-by: Olof Johansson <olof@lixom.net>
| * ARM: dt: tegra: fix length of pad control and mux registersPritesh Raithatha2012-10-301-2/+2
| | | | | | | | | | | | | | | | | | The reg property contains <base length> not <base last_offset>. Fix the length values to be length not last_offset. Cc: stable@vger.kernel.org Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra: Add Tegra30 host1x supportThierry Reding2012-11-151-0/+87
| | | | | | | | | | | | | | | | | | Add the host1x node along with its children to the Tegra30 DTSI. Board- specific DTS files are expected to enable the available outputs and complement the device tree with data specific to the hardware. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra: dts: add slink controller dt entryLaxman Dewangan2012-11-151-0/+60
| | | | | | | | | | | | | | | | Add slink controller details in the dts file of Tegra20 and Tegra30. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra: dt: add L2 cache controllerJoseph Lo2012-11-051-0/+9
|/ | | | | | | Add L2 cache controller binding into DT for Tegra. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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