| Commit message (Collapse) | Author | Age | Files | Lines |
|
|
|
|
|
|
|
|
|
|
|
| |
As explained by commit 9c0da3cc61f1233c ("ARM: dts: explicitly mark
skeleton.dtsi as deprecated"), including skeleton.dtsi is deprecated.
This fixes the following warning with W=1:
Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
|
|
|
|
|
|
|
|
|
| |
This patch adds the missing reg properties for the MXS GPIO banks
in order to fix the dtc warnings.
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
|
|
|
|
|
| |
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
|
|
|
|
|
|
|
|
| |
Change iio_hwmon nodes to use hypen in node names instead of
underscore.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
|
|
|
|
|
|
|
| |
Add auart4 2-pin configuration on auart0 rts/cts pads.
Signed-off-by: Mans Rullgard <mans@mansr.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
|
|
|
|
|
|
|
|
|
| |
This patch enables On Chip OTP support for i.MX23 and i.MX28 SoCs,
but keeps the old compatible string.
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
|
|
|
|
|
|
|
|
|
|
|
| |
Fix a typo in the TX DMA interrupt name for AUART4.
This patch makes AUART4 operational again.
Signed-off-by: Marek Vasut <marex@denx.de>
Fixes: f30fb03d4d3a ("ARM: dts: add generic DMA device tree binding for mxs-dma")
Cc: stable@vger.kernel.org
Acked-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
|
|
|
|
| |
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The chipidea driver adds an extra line of spam to the log when a
host-only chipidea instance is left set to the default of a dual role
controller.
[ 2.010873] ci_hdrc ci_hdrc.1: doesn't support gadget
Set the dr_mode property to host on all the host-only nodes
to avoid this warning.
Signed-off-by: Matt Porter <mporter@konsulko.com>
Acked-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
|
|
|
|
| |
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
|
|
|
|
|
|
|
| |
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
[ukl: rebase from ancient kernel version]
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
|
|
|
|
|
|
| |
Signed-off-by: Michael Heimpold <mhei@heimpold.de>
Acked-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
|
|
|
|
|
|
|
|
| |
We need to use controller id to access different register regions
for mxs phy.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
|
|
|
|
|
|
|
|
| |
This allows to read the SoC on-die temperature sensor available on the LRADC by
using:
cat /sys/class/hwmon/hwmon0/device/temp1_input
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
|
|
|
|
|
|
|
| |
Adding #io-channel-cells property to lradc allows us to use the lradc as
an iio provider.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
|
|
|
|
|
|
|
| |
The pins have nothing todo with the phy layer. We better rename them, so
it gets clear they are routed to the ehci core not to any phy.
Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: devicetree@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: Eric Bénard <eric@eukrea.com>
Signed-off-by: Denis Carikli <denis@eukrea.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: devicetree@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: Eric Bénard <eric@eukrea.com>
Signed-off-by: Denis Carikli <denis@eukrea.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
|
|
|
|
|
|
| |
Add auart2 pins configuration on its main pads
Signed-off-by: Aida Mynzhasova <aida.mynzhasova@skitlab.ru>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
|
|
|
|
|
|
|
|
|
|
| |
Enable the DCP by default on both i.MX23 and i.MX28.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: David S. Miller <davem@davemloft.net>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
|
|\
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC DT updates from Olof Johansson:
"Most of this branch consists of updates, additions and general churn
of the device tree source files in the kernel (arch/arm/boot/dts).
Besides that, there are a few things to point out:
- Lots of platform conversion on OMAP2+, with removal of old board
files for various platforms.
- Final conversion of a bunch of ux500 (ST-Ericsson) platforms as
well
- Some updates to pinctrl and other subsystems. Most of these are
for DT-enablement of the various platforms and acks have been
collected"
* tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (385 commits)
ARM: dts: bcm11351: Use GIC/IRQ defines for sdio interrupts
ARM: dts: bcm: Add missing UARTs for bcm11351 (bcm281xx)
ARM: dts: bcm281xx: Add card detect GPIO
ARM: dts: rename ARCH_BCM to ARCH_BCM_MOBILE (dt)
ARM: bcm281xx: Add device node for the GPIO controller
ARM: mvebu: Add Netgear ReadyNAS 104 board
ARM: tegra: fix Tegra114 IOMMU register address
ARM: kirkwood: add support for OpenBlocks A7 platform
ARM: dts: omap4-panda: add DPI pinmuxing
ARM: dts: AM33xx: Add RNG node
ARM: dts: AM33XX: Add hwspinlock node
ARM: dts: OMAP5: Add hwspinlock node
ARM: dts: OMAP4: Add hwspinlock node
ARM: dts: use 'status' property for PCIe nodes
ARM: dts: sirf: add missed address-cells and size-cells for prima2 I2C
ARM: dts: sirf: add missed cell, cs and dma channel for SPI nodes
ARM: dts: sirf: add missed graphics2d iobg in atlas6 dts
ARM: dts: sirf: add missed chhifbg node in prima2 and atlas6 dts
ARM: dts: sirf: add missed memcontrol-monitor node in prima2 and atlas6 dts
ARM: mvebu: Add the core-divider clock to Armada 370/XP
...
|
| |
| |
| |
| |
| |
| |
| | |
Add pinmux for 4-bit SD card connected to SSP2.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
| |
| |
| |
| |
| |
| |
| |
| | |
This pin definition had been added after the initial patch to use
symbolic pin names in DTS files.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
| |
| |
| |
| |
| |
| |
| |
| | |
Convert mx23/mx28 dts files to use the padconfig defintions from
mxs-pinfunc.h.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
Convert mx23/mx28 dts filed to use the pinctrl header files.
NOTE: During automatic conversion of these files to use the pinconfig
definitions an inconsistency has been found in:
arch/arm/boot/dts/imx28-apx4devkit.dts
According to the comment the function for pad SSP2_SS0 should have
been MX28_PAD_SSP2_SS0__GPIO_2_19, while the given value 0x2131
represents: MX28_PAD_SSP2_SS0__AUART3_TX
I used the later (though probably wrong) definition because that's
what is actually being used in the DTB.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
Testing g_ether results in the following:
[ 1.648022] using random self ethernet address
[ 1.652778] using random host ethernet address
[ 1.660504] usb0: HOST MAC c6:28:6a:81:dc:ff
[ 1.666360] usb0: MAC 7e:81:54:16:c0:c6
[ 1.670504] using random self ethernet address
[ 1.675842] using random host ethernet address
[ 1.682655] g_ether gadget: Ethernet Gadget, version: Memorial Day 2008
[ 1.689332] g_ether gadget: g_ether ready
[ 3.328974] irq 237: nobody cared (try booting with the "irqpoll" option)
[ 3.335831] CPU: 0 PID: 1 Comm: swapper Not tainted 3.11.0-rc6-next-20130819 #1035
[ 3.343500] [<c0014258>] (unwind_backtrace+0x0/0xf0) from [<c0011b20>] (show_stack+0x10/0x14)
[ 3.352098] [<c0011b20>] (show_stack+0x10/0x14) from [<c006af4c>] (__report_bad_irq+0x20/0xc0)
[ 3.360763] [<c006af4c>] (__report_bad_irq+0x20/0xc0) from [<c006b3f4>] (note_interrupt+0x1d4/0x234)
[ 3.369943] [<c006b3f4>] (note_interrupt+0x1d4/0x234) from [<c0069754>] (handle_irq_event_percpu+0xc4/0x268)
[ 3.379815] [<c0069754>] (handle_irq_event_percpu+0xc4/0x268) from [<c0069934>] (handle_irq_event+0x3c/0x5c)
[ 3.389686] [<c0069934>] (handle_irq_event+0x3c/0x5c) from [<c006bb78>] (handle_level_irq+0x8c/0xe8)
[ 3.398865] [<c006bb78>] (handle_level_irq+0x8c/0xe8) from [<c0068ff0>] (generic_handle_irq+0x20/0x30)
[ 3.408213] [<c0068ff0>] (generic_handle_irq+0x20/0x30) from [<c000fc9c>] (handle_IRQ+0x30/0x84)
[ 3.417040] [<c000fc9c>] (handle_IRQ+0x30/0x84) from [<c0012564>] (__irq_svc+0x44/0x54)
[ 3.425094] [<c0012564>] (__irq_svc+0x44/0x54) from [<c0020244>] (__do_softirq+0x90/0x268)
[ 3.433400] [<c0020244>] (__do_softirq+0x90/0x268) from [<c00207d4>] (irq_exit+0x9c/0xd8)
[ 3.441619] [<c00207d4>] (irq_exit+0x9c/0xd8) from [<c000fca0>] (handle_IRQ+0x34/0x84)
[ 3.449577] [<c000fca0>] (handle_IRQ+0x34/0x84) from [<c0012564>] (__irq_svc+0x44/0x54)
[ 3.457629] [<c0012564>] (__irq_svc+0x44/0x54) from [<c04602b0>] (_raw_spin_unlock_irqrestore+0x34/0x44)
[ 3.467164] [<c04602b0>] (_raw_spin_unlock_irqrestore+0x34/0x44) from [<c0348298>] (input_register_handler+0x98/0xb4)
[ 3.477835] [<c0348298>] (input_register_handler+0x98/0xb4) from [<c064bc10>] (mousedev_init+0x30/0x60)
[ 3.487275] [<c064bc10>] (mousedev_init+0x30/0x60) from [<c00088ac>] (do_one_initcall+0xe8/0x154)
[ 3.496198] [<c00088ac>] (do_one_initcall+0xe8/0x154) from [<c062aabc>] (kernel_init_freeable+0xf0/0x1b4)
[ 3.505810] [<c062aabc>] (kernel_init_freeable+0xf0/0x1b4) from [<c0456550>] (kernel_init+0x8/0xe4)
[ 3.514899] [<c0456550>] (kernel_init+0x8/0xe4) from [<c000ee60>] (ret_from_fork+0x14/0x34)
[ 3.523263] handlers:
[ 3.525578] [<c0339d14>] ci_irq
[ 3.528757] Disabling IRQ #237
Provide the USB0_ID pin in the usb0 node, so that g_ether can operate
correctly.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
|/
|
|
|
|
|
|
|
|
|
|
| |
The delay units inside the LRADC depend on the presence of a 2 kHz clock.
This change enables the clock to be able to use the delay unit for the
touchscreen part of the driver.
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Tested-by: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
Tested-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
|
|
|
|
|
| |
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
|
|
|
|
| |
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
|
|
|
|
| |
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
|
|
|
|
| |
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
|
|
|
|
| |
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
After providing spi alias, we can get the following message during probe:
m25p80 spi1.0: sst25vf016b (2048 Kbytes)
,which looks better than the original one:
m25p80 spi32766.0: sst25vf016b (2048 Kbytes)
While at it, keep the alias entries in alphabetical order.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
|
|
|
|
|
|
|
|
|
|
| |
After mxs-dma driver adopts generic DMA device tree binding, channel
interrupt number is defined in DMA controller node, and channel ID is
listed in "dmas" property. So the DMA channel interrupt number in
client nodes' "interrupts" property and fsl,<module>-dma-channel which
are used by old customized DMA binding can be removed now.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
|
|
|
|
|
|
|
|
| |
These systems all use saif0 as the mclock provider to codec sgtl5000.
Reflect that in device tree source, so that sgtl5000 can find the clock
by calling clk_get().
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
|\
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
Pull crypto update from Herbert Xu:
- Do not idle omap device between crypto operations in one session.
- Added sha224/sha384 shims for SSSE3.
- More optimisations for camellia-aesni-avx2.
- Removed defunct blowfish/twofish AVX2 implementations.
- Added unaligned buffer self-tests.
- Added PCLMULQDQ optimisation for CRCT10DIF.
- Added support for Freescale's DCP co-processor
- Misc fixes.
* git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (44 commits)
crypto: testmgr - test hash implementations with unaligned buffers
crypto: testmgr - test AEADs with unaligned buffers
crypto: testmgr - test skciphers with unaligned buffers
crypto: testmgr - check that entries in alg_test_descs are in correct order
Revert "crypto: twofish - add AVX2/x86_64 assembler implementation of twofish cipher"
Revert "crypto: blowfish - add AVX2/x86_64 implementation of blowfish cipher"
crypto: camellia-aesni-avx2 - tune assembly code for more performance
hwrng: bcm2835 - fix MODULE_LICENSE tag
hwrng: nomadik - use clk_prepare_enable()
crypto: picoxcell - replace strict_strtoul() with kstrtoul()
crypto: dcp - Staticize local symbols
crypto: dcp - Use NULL instead of 0
crypto: dcp - Use devm_* APIs
crypto: dcp - Remove redundant platform_set_drvdata()
hwrng: use platform_{get,set}_drvdata()
crypto: omap-aes - Don't idle/start AES device between Encrypt operations
crypto: crct10dif - Use PTR_RET
crypto: ux500 - Cocci spatch "resource_size.spatch"
crypto: sha256_ssse3 - add sha224 support
crypto: sha512_ssse3 - add sha384 support
...
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
This patch enables the DCP crypto functionality on imx28.
Currently, only aes-128-cbc is supported.
Moreover, the dcpboot misc-device, which is used by Freescale's
SDK tools and uses a non-software-readable OTP-key, is added.
Changes of v2:
- ring buffer for hardware-descriptors
- use of ablkcipher walk
- OTP key encryption/decryption via misc-device
(compatible to Freescale-SDK)
- overall cleanup
The DCP is also capable of sha1/sha256 but I won't be able to add
that anytime soon.
Tested with built-in runtime-self-test, tcrypt and openssl via
cryptodev 1.6 on imx28-evk and a custom built imx28-board.
Signed-off-by: Tobias Rauter <tobias.rauter@gmail.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
|
|\ \
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
into next/dt
From Shawn Guo:
mxs device tree changes for 3.11:
* A couple of new board support, cfa10055 and cfa10057
* A few updates on cfa10036 device tree source
* Some auart pinctrl data addition
* Adopt soc bus infrastructure for mach-mxs
* tag 'mxs-dt-3.11' of git://git.linaro.org/people/shawnguo/linux-2.6:
ARM: mxs: dt: Add Crystalfontz CFA-10057 device tree
ARM: mxs: dt: Add the Crystalfontz CFA-10055 device tree
ARM: cfa10049: Switch the chip select pin of the LCD controller
ARM: cfa10036: Add USB0 OTG port
ARM: dts: apf28dev: Add touchscreen support for APF28dev
ARM: mxs: Fix UARTs on M28EVK
ARM: cfa10036: dt: Change i2c0 clock frequency
ARM: dts: cfa10036: Change the OLED display to SSD1306
ARM: mx28: add auart4 2 pins pinmux to imx28.dtsi
ARM: mx28: add auart3 2 pins pinmux to imx28.dtsi
ARM: mx28: add auart2 2 pins pinmux to imx28.dtsi
ARM: mxs: Use soc bus infrastructure
ARM: dts: mx28: Adjust the digctl compatible string
ARM: mxs: Remove init_irq declaration in machine description
Includes an update to 3.10-rc6
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
Add auart4 2 pins configuration on SSP3 pads
Signed-off-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
Add auart3 2 pins configuration on its main pads
Signed-off-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
Add auart2 2 pins configuration on its main pads
Signed-off-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
| |/
| |
| |
| |
| |
| |
| |
| | |
MX28 has the same DIGCTL block as MX23, so adjust the compatible string to
reflect that.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
|/
|
|
|
|
|
|
| |
This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
|
|
|
|
|
|
|
|
|
|
|
|
| |
Add generic DMA device tree binding for mxs-dma. The changes include:
* Add channel interrupts into DMA controller nodes
* Add properties '#dma-cells' and 'dma-channels' for DMA controller nodes
* And properties 'dmas' and 'dma-names' for DMA client nodes
* Update mxs-dma device tree binding doc
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
|
|
|
|
|
|
|
|
|
|
| |
Put the clock to the devicetree, so the driver can take care of it
later. Then, we don't have to do the enabling as a workaround in board
init.
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
[shawn.guo: add enet_out into imx28.dtsi and overwrite it for m28evk]
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
|
|
|
|
|
|
| |
Instead of using the static definitions, get ocotp base address from
device tree with mapping.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
|
|
|
|
|
|
|
|
|
|
|
| |
Instead of using static address definition, get reset address from
device tree with mapping, so that core_initcall mxs_arch_reset_init()
can be killed.
The "rtc" clock code in mxs_arch_reset_init() seems to be zombie, since
there is no clk lookup defined in clock driver at all. Remove it
together.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
|
|
|
|
|
|
|
|
|
|
| |
Instead of using the static definitions, get clkctrl and digctl base
addresses with mapping from device tree.
Use macro on variable is not nice, but it's done here to save huge
pointless diff stat.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
|
|
|
|
|
|
|
|
| |
Change call clk_get_sys() to of_clk_get() to look up timrot clock from
device tree, so that the clk_register_clkdev() call for timrot can be
saved in clock driver.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
|
|
|
|
| |
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|