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* ARM: dts: BCM63xx: Add ARMPLL device tree nodesFlorian Fainelli2015-12-061-8/+28
| | | | | | | | | | Add the ARM PLL controller which comes standard with the Cortex-A9 found on the BCM63138 SoCs. This is the same controller as the one found in the Broadcom iProc architecture, however, we have a separate compatible string to indicate the integration difference, since the hardware is different. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* ARM: dts: BCM63xx: re-parent NAND controller nodeFlorian Fainelli2015-05-271-11/+11
| | | | | | | | | | | The NAND controller is a child node of the UBUS (legacy) bus, not the AXI (new) bus, re-parent the NAND controller node accordingly. This was a mistake introduced by a failed merge of this NAND node with other changes (PMB). Fixes: b5762cacc411 ("ARM: bcm63138: add NAND DT support") Reported-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* ARM: dts: BCM63xx: Add timer and syscon-reboot nodesFlorian Fainelli2015-05-131-0/+12
| | | | | | | Add a "brcm,bcm6328-timer" and "syscon-reboot" nodes to allow the generic syscon-reboot driver to reset a BCM63138 SoC. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* ARM: bcm63138: add NAND DT supportBrian Norris2015-05-131-0/+11
| | | | | | | Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Tested-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* ARM: dts: BCM63xx: Add SMP nodes and required propertiesFlorian Fainelli2015-05-131-0/+8
| | | | | | | | | | | Update bcm63138.dtsi with the following: - enable-method for both CPU nodes - brcm,bcm63138-bootlut node - resets properties to point to the correct PMB controller to release the secondary CPU from reset Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* ARM: dts: BCM63xx: Add PMB busses nodesFlorian Fainelli2015-05-131-0/+12
| | | | | | | Add the two BCM63138 PMB busses nodes found on this System-on-a-Chip as described in their corresponding binding document. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* ARM: dts: BCM63xx: fix L2 cache propertiesFlorian Fainelli2015-02-161-2/+3
| | | | | | | | | | The L2 cache properties were completely off with respect to what the hardware is configured for. Fix the cache-size, cache-line-size and cache-sets to reflect the L2 cache controller we have: 512KB, 16 ways and 32 bytes per cache-line. Fixes: 46d4bca0445a0 ("ARM: BCM63XX: add BCM63138 minimal Device Tree") Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* ARM: dts: bcm63138: change "interupts" to "interrupts"Radek Dostal2014-11-201-1/+1
| | | | | | | | | all other nodes in bcm63138.dtsi use "interrupts", this had to be just a typo which never got noticed, even it may have quite some consequences. Signed-off-by: Radek Dostal <radek.dostal@streamunlimited.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
* ARM: BCM63XX: add BCM63138 minimal Device TreeFlorian Fainelli2014-09-171-0/+134
Add a very minimalistic BCM63138 Device Tree include file which describes the BCM63138 SoC with only the basic set of required peripherals: - Cortex A9 CPUs - ARM GIC - ARM SCU - PL310 Level-2 cache controller - ARM TWD & Global timers - ARM TWD watchdog - legacy MIPS bus (UBUS) - BCM6345-style UARTs (disabled by default) Since the PL310 L2 cache controller does not come out of reset with correct default values, we need to override the 'cache-sets' and 'cache-size' properties to get its geometry right. Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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