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| * ARM: mvebu: add Device Tree description of AHCI interfaces on Armada 38xThomas Petazzoni2014-04-261-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | The Marvell Armada 38x processors contain two AHCI compatible interfaces. This commit adds the Device Tree description of those interfaces at the SoC level, and also enables them on the Armada 385 DB platform, which allows access to both interfaces through SATA ports. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1397574006-5868-4-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * ARM: mvebu: enable the SDHCI interface on Armada 385Thomas Petazzoni2014-04-251-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In commit "mmc: sdhci-pxav3: add support for the Armada 38x SDHCI controller", the sdhci-pxav3 driver has been extended to also be usable on Armada 38x platforms. Therefore, this commit adds the necessary Device Tree informations to declare this SDHCI interface in the Armada 38x SoC, and also in the Armada 385 Development Board. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Andrew Lunn <andrew@lunn.ch> Link: https://lkml.kernel.org/r/1397486478-16991-2-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * ARM: mvebu: add SMP support in the Armada 38x device treeThomas Petazzoni2014-04-241-0/+10
| | | | | | | | | | | | | | | | | | | | | | This commit improves the Armada 38x Device Tree to add the CPU reset and PMSU Device Tree nodes as well as the declaration of the enabling method for the CPUs. These are needed to get SMP working on Armada 38x platforms. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1397483648-26611-12-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * ARM: mvebu: enable the coherency fabric on Armada 38xThomas Petazzoni2014-04-241-0/+10
| | | | | | | | | | | | | | | | | | This commit adds the necessary Device Tree information to enable the coherency fabric on Armada 38x. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1397483228-25625-11-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * ARM: mvebu: Enable Armada 380/385 watchdog in the devicetreeEzequiel Garcia2014-04-241-0/+7
| | | | | | | | | | | | | | | | | | | | Add the DT nodes to enable the watchdog support available on Armada 380/385 SoC. Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1397481813-4962-9-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* | ARM: mvebu: ensure the mdio node has a clock reference on Armada 38xThomas Petazzoni2014-04-071-0/+1
|/ | | | | | | | | | | | | | | The mvmdio driver accesses some register of the Ethernet unit. It therefore takes a reference and enables a clock. However, on Armada 38x, no clock specification was given in the Device Tree, which leads the mvmdio driver to fail when being used as a module and loaded before the mvneta driver: it tries to access a register from a hardware unit that isn't clocked. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1395790439-21332-3-git-send-email-thomas.petazzoni@free-electrons.com Acked-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: mvebu: Add support for NAND controller in Armada 38x SoCEzequiel Garcia2014-03-131-0/+10
| | | | | | | | | | The Armada 38x SoC family has a NAND controller, compatible with the controller in Armada 370/375/XP SoCs. Add support for it in the devicetree file. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1394742273-5113-5-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: mvebu: Add the Core Divider clock to Armada 38x SoCsEzequiel Garcia2014-03-131-0/+8
| | | | | | | | | | The Armada 38x SoC family has a clock provider called "Core Divider", derived from the fixed 2 GHz main PLL clock. This is similar to the one on A370, A375 and AXP. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1394742273-5113-4-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: mvebu: Add a 2 GHz fixed-clock on Armada 38x SoCsEzequiel Garcia2014-03-131-0/+7
| | | | | | | | | | Armada 38x SoCs have a 2 GHz fixed main PLL that is used to feed other clocks. This commit adds a DT representation of this clock through a fixed-clock compatible node. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1394742273-5113-3-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: mvebu: use macros for interrupt flags on Armada 375/38xThomas Petazzoni2014-02-221-20/+25
| | | | | | | | | | | Instead of hardcoding the values of the interrupt flags, use the macros provided by <include/dt-bindings/interrupt-controller/irq.h> and <include/dt-bindings/interrupt-controller/arm-gic.h> for the Armada 375 and Armada 38x Device Tree files. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: mvebu: use GIC_{SPI,PPI} in Armada 375/38x DTsThomas Petazzoni2014-02-221-20/+21
| | | | | | | | | | Instead of hardcoding 0 and 1 to indicate SPI and PPI GIC interrupts, use the definitions of <dt-bindings/interrupt-controller/arm-gic.h> to clarify the Device Tree code. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: mvebu: add Device Tree description of the Armada 380/385 SoCsThomas Petazzoni2014-02-171-0/+345
The Armada 380 and 385 SoCs are new SoCs from Marvell, based on a Cortex-A9 cores (single core for 380, dual core for 385) and a number of hardware blocks that are common with earlier SoCs from the mvebu family. The provided Device Tree describes the following parts of the SoC: * CPU * Device Bus * Clocks * Interrupt controllers: GIC and MPIC * GPIO controllers * I2C buses * L2 cache * MBus controller * Pinctrl * Serial * SPI buses * System controller (for reboot) * Timer * XOR engines * PCIe controllers * Network interfaces Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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