summaryrefslogtreecommitdiffstats
path: root/Documentation/devicetree/bindings/phy
Commit message (Collapse)AuthorAgeFilesLines
...
| * | | dt-bindings: phy-pxa-usb: add bindingsLubomir Rintel2019-06-211-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the PHY chip for USB OTG on PXA platforms. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Acked-by: Pavel Machek <pavel@ucw.cz> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| * | | dt-bindings: phy: Add binding for Qualcomm PCIe2 PHYBjorn Andersson2019-05-311-0/+42
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | The Qualcomm PCIe2 PHY is a Synopsys based PCIe PHY found in a number of Qualcomm platforms, add a binding to describe this. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* | | Merge tag 'phy-for-5.2-rc_v2' of ↵Greg Kroah-Hartman2019-07-011-0/+12
|\ \ \ | |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into usb-next Kishon writes: phy: for 5.2-rc *) Move Tegra124 PLL power supplies to be enabled by xusb-tegra124 *) Move Tegra210 PLL power supplies to be enabled by xusb-tegra210 *) Minor fixes: fix memory leaks at error path and addresses coverity. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> * tag 'phy-for-5.2-rc_v2' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy: phy: tegra: xusb: Add Tegra210 PLL power supplies phy: tegra: xusb: Add Tegra124 PLL power supplies dt-bindings: phy: tegra-xusb: List PLL power supplies phy: usb: phy-brcm-usb: Remove sysfs attributes upon driver removal phy: renesas: rcar-gen2: Fix memory leak at error paths phy: qcom-qusb2: fix missing assignment of ret when calling clk_prepare_enable
| * | dt-bindings: phy: tegra-xusb: List PLL power suppliesThierry Reding2019-06-121-0/+12
| |/ | | | | | | | | | | | | | | | | | | | | | | | | These power supplies provide power for various PLLs that are set up and driven by the XUSB pad controller. These power supplies were previously improperly added to the PCIe and XUSB controllers, but depending on the driver probe order, power to the PLLs will not be supplied soon enough and cause initialization to fail. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* | dt-bindings: rcar-gen3-phy-usb2: Add r7s9210 supportChris Brandt2019-05-211-4/+6
| | | | | | | | | | | | | | | | | | | | Document RZ/A2 (R7S9210) SoC bindings. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | dt-bindings: rcar-gen3-phy-usb2: Document dr_modeChris Brandt2019-05-211-0/+3
|/ | | | | | | | | | Document the optional dr_mode property Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* dt-bindings: phy-qcom-qmp: Tweak qcom,msm8998-qmp-ufs-phyMarc Gonzalez2019-04-221-1/+2
| | | | | | | | Fixup MSM8998 UFS binding now that Evan's reset series has landed. https://lore.kernel.org/lkml/20190321171800.104681-1-evgreen@chromium.org/ Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* dt-bindings: phy-qcom-qmp: Add qcom,msm8998-qmp-pcie-phyMarc Gonzalez2019-04-181-0/+5
| | | | | | | Add compatible string for QMP PCIe phy on msm8998. Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* dt-bindings: phy: Add support for HiSilicon's hi3660 USB PHYYu Chen2019-04-181-0/+26
| | | | | | | | | | | | | This patch adds binding documentation for supporting the hi3660 usb phy on boards like the HiKey960. Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: John Stultz <john.stultz@linaro.org> Cc: Binghui Wang <wangbinghui@hisilicon.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Yu Chen <chenyu56@huawei.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* dt-bindings: phy-imx8mq-usb: add optional vbus supply regulatorLucas Stach2019-04-181-0/+3
| | | | | | | | Add a vbus supply regulator phandle, so the PHY can enable the VBUS voltage rail when powering up. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* dt-bindings: phy: ti: Add dt binding documentation for SERDES in AM654x SoCKishon Vijay Abraham I2019-04-171-0/+82
| | | | | | | | | | | | | | | | | | | | | | | | AM654x has two SERDES instances. Each instance has three input clocks (left input, externel reference clock and right input) and two output clocks (left output and right output) in addition to a PLL mux clock which the SERDES uses for Clock Multiplier Unit (CMU refclock). The PLL mux clock can select from one of the three input clocks. The right output can select between left input and external reference clock while the left output can select between the right input and external reference clock. The left and right input reference clock of SERDES0 and SERDES1 respectively are connected to the SoC clock. In the case of two lane SERDES personality card, the left input of SERDES1 is connected to the right output of SERDES0 in a chained fashion. See section "Reference Clock Distribution" of AM65x Sitara Processors TRM (SPRUID7 – April 2018) for more details. Add dt-binding documentation in order to represent all these different configurations in device tree. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* dt-bindings: phy: rcar-gen3-phy-usb2: Revise #phy-cells propertyYoshihiro Shimoda2019-04-171-1/+7
| | | | | | | | To have the detailed property on each PHY specifier, this patch revises the #phy-cells property. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* dt-bindings: rcar-gen3-phy-usb2: Add r8a77470 supportBiju Das2019-04-171-2/+4
| | | | | | | | | | | | Document RZ/G1C (R8A77470) SoC bindings. For RZ/G1C, this driver is used to enable interrupt generation and initializing timing registers which is part of phy_init code. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* dt-bindings: phy: rcar-gen2: Add r8a77470 supportBiju Das2019-04-171-4/+53
| | | | | | | | | | | | | | Add USB PHY support for r8a77470 SoC. Renesas RZ/G1C (R8A77470) USB PHY is similar to the R-Car Gen2 family, but has the below feature compared to other RZ/G1 and R-Car Gen2/3 SoCs It has a shared pll reset for usbphy0/usbphy1 and this register reside in usbphy0 block. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* dt-bindings: phy: Add document for phy-mtk-ufsStanley Chu2019-04-171-0/+38
| | | | | | | | Add UFS M-PHY node document for MediaTek SoC chips. Signed-off-by: Stanley Chu <stanley.chu@mediatek.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* dt-bindings: phy: Add a new property drive-impedance-ohm for RK's emmc PHYChristoph Muellner2019-04-171-2/+6
| | | | | | | | | This patch documents the new proprty drive-impedance-ohm for Rockchip's eMMC PHY node. Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* dt-bindings: phy-qcom-qmp: Add UFS PHY resetEvan Green2019-04-171-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | Add a required reset to the SDM845 UFS phy to express the PHY reset bit inside the UFS controller register space. Before this change, this reset was not expressed in the DT, and the driver utilized two different callbacks (phy_init and phy_poweron) to implement a two-phase initialization procedure that involved deasserting this reset between init and poweron. This abused the two callbacks and diluted their purpose. That scheme does not work as regulators cannot be turned off in phy_poweroff because they were turned on in init, rather than poweron. The net result is that regulators are left on in suspend that shouldn't be. This new scheme gives the UFS reset to the PHY, so that it can fully initialize itself in a single callback. We can then turn regulators on during poweron and off during poweroff. Signed-off-by: Evan Green <evgreen@chromium.org> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* dt-bindings: phy: Add Amlogic G12A USB3+PCIE Combo PHY BindingsNeil Armstrong2019-04-171-0/+22
| | | | | | | | | | | Add the Amlogic G12A Family USB3 + PCIE Combo PHY Bindings. This PHY can provide exclusively USB3 or PCIE support on shared I/Os. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* dt-bindings: phy: Add Amlogic G12A USB2 PHY BindingsNeil Armstrong2019-04-171-0/+22
| | | | | | | | | | | | | Add the Amlogic G12A Family USB2 OTG PHY Bindings The PHY can work in host or peripheral modes depending on it's position. Configuration of the mode is part of the USBCTRL registers which are outside of the PHY registers. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* dt-bindings: phy: Add Stingray USB PHY binding documentSrinath Mannam2019-04-171-0/+32
| | | | | | | | Add DT binding document for Stingray USB PHY. Signed-off-by: Srinath Mannam <srinath.mannam@broadcom.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* dt-bindings: phy: tegra: Add Tegra186 supportThierry Reding2019-04-171-0/+9
| | | | | | | | | | | | | Extend the bindings to cover the set of features found in Tegra186. Note that, technically, there are four more supplies connected to the XUSB pad controller (DVDD_PEX, DVDD_PEX_PLL, HVDD_PEX and HVDD_PEX_PLL), but the power sequencing requirements of Tegra186 require these to be under the control of the PMIC. Reviewed-by: JC Kuo <jckuo@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* Merge tag 'usb-5.1-rc1' of ↵Linus Torvalds2019-03-068-12/+126
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb Pull USB/PHY updates from Greg KH: "Here is the big USB/PHY driver pull request for 5.1-rc1. The usual set of gadget driver updates, phy driver updates, xhci updates, and typec additions. Also included in here are a lot of small cleanups and fixes and driver updates where needed. All of these have been in linux-next for a while with no reported issues" * tag 'usb-5.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (167 commits) wusb: Remove unnecessary static function ckhdid_printf usb: core: make default autosuspend delay configurable usb: core: Fix typo in description of "authorized_default" usb: chipidea: Refactor USB PHY selection and keep a single PHY usb: chipidea: Grab the (legacy) USB PHY by phandle first usb: chipidea: imx: set power polarity dt-bindings: usb: ci-hdrc-usb2: add property power-active-high usb: chipidea: imx: remove unused header files usb: chipidea: tegra: Fix missed ci_hdrc_remove_device() usb: core: add option of only authorizing internal devices usb: typec: tps6598x: handle block writes separately with plain-I2C adapters usb: xhci: Fix for Enabling USB ROLE SWITCH QUIRK on INTEL_SUNRISEPOINT_LP_XHCI usb: xhci: fix build warning - missing prototype usb: xhci: dbc: Fixing typo error. usb: xhci: remove unused member 'parent' in xhci_regset struct xhci: tegra: Prevent error pointer dereference USB: serial: option: add Telit ME910 ECM composition usb: core: Replace hardcoded check with inline function from usb.h usb: core: skip interfaces disabled in devicetree usb: typec: mux: remove redundant check on variable match ...
| * dt-bindings: phy-qcom-qmp: Add qcom,msm8998-qmp-ufs-phyMarc Gonzalez2019-02-121-0/+4
| | | | | | | | | | | | | | Add compatible string for QMP UFS phy on msm8998. Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| * dt-bindings: phy: Move the Cadence D-PHY bindingsMaxime Ripard2019-02-071-0/+20
| | | | | | | | | | | | | | | | | | | | The Cadence D-PHY bindings was defined as part of the DSI block so far. However, since it's now going to be a separate driver, we need to move the binding to a file of its own. Acked-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| * dt-bindings: phy: mvebu-utmi: add UTMI PHY bindingsMiquel Raynal2019-02-071-0/+38
| | | | | | | | | | | | | | | | Add bindings for Marvell Armada 3700 USB2 UTMI+ PHY. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| * dt-bindings: phy: mvebu-comphy: extend the file to describe a3700 bindingsMiquel Raynal2019-02-071-12/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current file describe COMPHY bindings for the IP available on the CP110 of Armada 7k/8k. Bindings are very close (and serve the same purpose) as the new Armada 3700 COMPHY driver so update this file to describe both. Also add an example of how to use this second compatible (same as for the ESPRESSObin). While doing so, enhance a bit the file by adding upper case where needed. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| * dt-bindings: phy-qcom: Add support for msm8998 usbJeffrey Hugo2019-02-072-0/+6
| | | | | | | | | | | | | | | | USB on msm8998 utilizes the QUSB2 and QMP phys, similar to sdm845. Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| * dt-bindings: phy-rockchip-inno-usb2: add documentation for extcon propertyEnric Balletbo i Serra2019-02-071-0/+2
| | | | | | | | | | | | | | | | | | | | | | Commit 98898f3bc83c8 ("phy: rockchip-inno-usb2: support otg-port for rk3399") introduces the extcon property that is used to detect the cable-state. Document this property in the documentation binding. Fixes: 98898f3bc83c8 ("phy: rockchip-inno-usb2: support otg-port for rk3399") Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| * dt-bindings: phy: ti: Add support for AM654x USB2 PHYRoger Quadros2019-02-071-0/+1
| | | | | | | | | | | | | | | | | | Add support for USB2 PHY on AM654x SoC. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| * dt-bindings: rcar-gen3-phy-usb2: Add r8a774c0 supportFabrizio Castro2019-02-071-0/+2
| | | | | | | | | | | | | | | | | | | | Document RZ/G2E (R8A774C0) SoC bindings. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* | dt-bindings: phy: Armada 38x common phy bindingsRussell King2019-02-071-0/+40
|/ | | | | | | Add the Marvell Armada 38x common phy bindings. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
* dt-bindings: phy-qcom-qmp: Move #clock-cells to childEvan Green2018-12-121-6/+5
| | | | | | | | | | | | | | | | | The phy-qcom-qmp bindings specified #clock-cells as 1. This was never used because of_clk_add_provider() was never called, so there was no way anybody could reference these clocks from DT. Furthermore, even if they could be accessed, the bindings never specified what should go in that additional cell. Fix these incomplete and broken bindings. Move the #clock-cells into the child node, since that is the actual clock provider, and not all instances of qcom-qmp-phy are clock providers. Also set #clock-cells to zero, since there's nothing to pass to it. Signed-off-by: Evan Green <evgreen@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* dt-bindings: phy-qcom-qmp: Fix register underspecificationEvan Green2018-12-121-8/+62
| | | | | | | | | | | | | | | | Add register regions for the second lane of dual-lane nodes. This additional specification is needed so that the driver can stop reaching beyond the tx and rx register allocations to get at the second lane registers in a dual-lane PHY. While in there, document #clock-cells as optional for PHYs that don't provide a pipe clock. Also, document the pcs_misc register region, which was being quietly supplied and used. Signed-off-by: Evan Green <evgreen@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* dt-bindings: phy: add binding for Freescale i.MX8MQ USB3 PHYLucas Stach2018-12-121-0/+17
| | | | | | | | This adds the binding for the USB3 PHY found on the i.MX8M SoC. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* dt-bindings: phy: add cpsw port interface mode selection phy bindingsGrygorii Strashko2018-12-121-0/+68
| | | | | | | | | | Add CPSW Port's Interface Mode Selection PHY (phy-gmii-sel) DT Bindings Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Tony Lindgren <tony@atomide.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* dt-bindings: phy: Document cadence Sierra PHY bindingsAlan Douglas2018-12-121-0/+67
| | | | | | | | | | | | | | | | | | | | | Add DT binding documentation for Sierra PHY. The PHY supports a number of different protocols, including PCIe and USB. The PHY lanes may be configured as single or multi-lane links. Each link is treated as a separate sub-node. For example, if there are 4 lanes in total the first 2 might be configured as a multi-lane PCIe link while the other two are single lane USB links, and in this case there would be 3 sub-nodes. There are two resets for the PHY block (one for APB register access, one for the PHY link) and separate resets for each link. For multi-lane links, the reset corresponds to the reset line on the master lane, the resets on other lanes have no effect. Signed-off-by: Alan Douglas <adouglas@cadence.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* dt-bindings: phy: add binding for Allwinner H6 USB2 PHYIcenowy Zheng2018-12-121-3/+5
| | | | | | | | | | | | The USB2.0 PHY on Allwinner H6 is similar to the ones on the ones on older SoCs, but with holes in PHY number (USB1 and USB2 are missing, in which USB1 is a USB3 PHY). Add binding for the PHY. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* dt-bindings: phy-qcom-qmp: Fix several mistakes from prior commitsDouglas Anderson2018-11-121-8/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Digging through the "phy-qcom-qmp" showed me many inconsistencies between the bindings and the reality of the driver. Let's fix them all. * In commit 2d66eab18375 ("dt-bindings: phy: qmp: Add support for QMP phy in IPQ8074") we probably should have explicitly listed that there are no clocks for this PHY and also added the reset names in alphabetical order. You can see that there are no clocks in the driver where "clk_list" is NULL. * In commit 8587b220f05e ("dt-bindings: phy-qcom-qmp: Update bindings for QMP V3 USB PHY") we probably should have listed the resets for this new PHY and also removed the "(Optional)" marking for the "cfg" reset since PHYs that need "cfg" really do need it. It's just that not all PHYs need it. * In commit 7f0802074120 ("dt-bindings: phy-qcom-qmp: Update bindings for sdm845") we forgot to update one instance of the string "qcom,qmp-v3-usb3-phy" to be "qcom,sdm845-qmp-usb3-phy". Let's fix that. We should also have added "qcom,sdm845-qmp-usb3-uni-phy" to the clock-names and reset-names lists. * In commit 99c7c7364b71 ("dt-bindings: phy-qcom-qmp: Add UFS phy compatible string for sdm845") we should have added the set of clocks and resets for "qcom,sdm845-qmp-ufs-phy". These were taken from the driver. * Cleanup the wording for what properties child nodes have to make it more obvious which types of PHYs need clocks and resets. This was sorta implicit in the "-names" description but I found myself confused. * As per the code not all "pcie qmp phys" have resets. Specifically note that the "has_lane_rst" property in the driver is false for "ipq8074-qmp-pcie-phy". Thus make it clear exactly which PHYs need child nodes with resets. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* Merge tag 'devicetree-for-4.20' of ↵Linus Torvalds2018-10-261-0/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux Pull Devicetree updates from Rob Herring: "A bit bigger than normal as I've been busy this cycle. There's a few things with dependencies and a few things subsystem maintainers didn't pick up, so I'm taking them thru my tree. The fixes from Johan didn't get into linux-next, but they've been waiting for some time now and they are what's left of what subsystem maintainers didn't pick up. Summary: - Sync dtc with upstream version v1.4.7-14-gc86da84d30e4 - Work to get rid of direct accesses to struct device_node name and type pointers in preparation for removing them. New helpers for parsing DT cpu nodes and conversions to use the helpers. printk conversions to %pOFn for printing DT node names. Most went thru subystem trees, so this is the remainder. - Fixes to DT child node lookups to actually be restricted to child nodes instead of treewide. - Refactoring of dtb targets out of arch code. This makes the support more uniform and enables building all dtbs on c6x, microblaze, and powerpc. - Various DT binding updates for Renesas r8a7744 SoC - Vendor prefixes for Facebook, OLPC - Restructuring of some ARM binding docs moving some peripheral bindings out of board/SoC binding files - New "secure-chosen" binding for secure world settings on ARM - Dual licensing of 2 DT IRQ binding headers" * tag 'devicetree-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (78 commits) ARM: dt: relicense two DT binding IRQ headers power: supply: twl4030-charger: fix OF sibling-node lookup NFC: nfcmrvl_uart: fix OF child-node lookup net: stmmac: dwmac-sun8i: fix OF child-node lookup net: bcmgenet: fix OF child-node lookup drm/msm: fix OF child-node lookup drm/mediatek: fix OF sibling-node lookup of: Add missing exports of node name compare functions dt-bindings: Add OLPC vendor prefix dt-bindings: misc: bk4: Add device tree binding for Liebherr's BK4 SPI bus dt-bindings: thermal: samsung: Add SPDX license identifier dt-bindings: clock: samsung: Add SPDX license identifiers dt-bindings: timer: ostm: Add R7S9210 support dt-bindings: phy: rcar-gen2: Add r8a7744 support dt-bindings: can: rcar_can: Add r8a7744 support dt-bindings: timer: renesas, cmt: Document r8a7744 CMT support dt-bindings: watchdog: renesas-wdt: Document r8a7744 support dt-bindings: thermal: rcar: Add device tree support for r8a7744 Documentation: dt: Add binding for /secure-chosen/stdout-path dt-bindings: arm: zte: Move sysctrl bindings to their own doc ...
| * dt-bindings: phy: rcar-gen2: Add r8a7744 supportBiju Das2018-10-151-0/+1
| | | | | | | | | | | | | | | | | | | | Add USB PHY support for r8a7744 SoC. Renesas RZ/G1N (R8A7744) USB PHY is identical to the R-Car Gen2 family. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Rob Herring <robh@kernel.org>
* | Merge tag 'usb-4.20-rc1' of ↵Linus Torvalds2018-10-2610-16/+304
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb Pull USB/PHY updates from Greg KH: "Here is the big USB/PHY driver patches for 4.20-rc1 Lots of USB changes in here, primarily in these areas: - typec updates and new drivers - new PHY drivers - dwc2 driver updates and additions (this old core keeps getting added to new devices.) - usbtmc major update based on the industry group coming together and working to add new features and performance to the driver. - USB gadget additions for new features - USB gadget configfs updates - chipidea driver updates - other USB gadget updates - USB serial driver updates - renesas driver updates - xhci driver updates - other tiny USB driver updates All of these have been in linux-next for a while with no reported issues" * tag 'usb-4.20-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (229 commits) usb: phy: ab8500: silence some uninitialized variable warnings usb: xhci: tegra: Add genpd support usb: xhci: tegra: Power-off power-domains on removal usbip:vudc: BUG kmalloc-2048 (Not tainted): Poison overwritten usbip: tools: fix atoi() on non-null terminated string USB: misc: appledisplay: fix backlight update_status return code phy: phy-pxa-usb: add a new driver usb: host: add DT bindings for faraday fotg2 usb: host: ohci-at91: fix request of irq for optional gpio usb/early: remove set but not used variable 'remain_length' usb: typec: Fix copy/paste on typec_set_vconn_role() kerneldoc usb: typec: tcpm: Report back negotiated PPS voltage and current USB: core: remove set but not used variable 'udev' usb: core: fix memory leak on port_dev_path allocation USB: net2280: Remove ->disconnect() callback from net2280_pullup() usb: dwc2: disable power_down on rockchip devices usb: gadget: udc: renesas_usb3: add support for r8a77990 dt-bindings: usb: renesas_usb3: add bindings for r8a77990 usb: gadget: udc: renesas_usb3: Add r8a774a1 support USB: serial: cypress_m8: remove set but not used variable 'iflag' ...
| * | dt-bindings: phy-qcom-qmp: Add UFS phy compatible string for sdm845Can Guo2018-09-251-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | Update the compatible string for UFS QMP PHY on SDM845. Signed-off-by: Can Guo <cang@codeaurora.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| * | dt-bindings: rcar-gen3-phy-usb2: add no-otg-pins propertyYoshihiro Shimoda2018-09-251-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds a new optional property "renesas,no-otg-pins" which a board does not provide proper otg pins. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| * | dt-bindings: phy: Document BCM63138 compatible stringFlorian Fainelli2018-09-251-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Document the compatible string "brcm,bcm63138-sata-phy" as a valid compatible string describing the standard Broadcom SATA PHY block. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| * | dt-bindings: phy: add UniPhier PCIe PHY descriptionKunihiko Hayashi2018-09-251-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add DT bindings for PHY interface built into PCIe controller implemented in UniPhier SoCs. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| * | dt-bindings: rcar-gen3-phy-usb3: Add r8a774a1 supportFabrizio Castro2018-09-251-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Document RZ/G2M (R8A774A1) SoC bindings. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| * | dt-bindings: rcar-gen3-phy-usb2: Add r8a774a1 supportFabrizio Castro2018-09-251-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Document RZ/G2M (R8A774A1) SoC bindings. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| * | dt-bindings: add binding for Rockchip hdmi phy using an Innosilicon IPZheng Yang2018-09-101-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | The phy is used so far in two Rockchip socs the rk3228 and the rk3328. Signed-off-by: Zheng Yang <zhengyang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| * | dt-bindings: phy: add DT bindings for UniPhier USB2 PHY driverKunihiko Hayashi2018-09-101-0/+45
| | | | | | | | | | | | | | | | | | | | | | | | Add DT bindings for PHY interface built into USB2 controller implemented on Socionext UniPhier SoCs. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| * | dt-bindings: phy: add DT bindings for UniPhier USB3 PHY driverKunihiko Hayashi2018-09-102-0/+126
| | | | | | | | | | | | | | | | | | | | | | | | Add DT bindings for PHY interface built into USB3 controller implemented in UniPhier SoCs. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
OpenPOWER on IntegriCloud