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| * | drm/amd/display: Block immediate flips for non-fast updatesNicholas Kazlauskas2019-08-062-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] Underflow can occur in the case where we change buffer pitch, DCC state, rotation or mirroring for a plane while also performing an immediate flip. It can also generate a p-state warning stack trace on DCN1 which is typically observed during the cursor handler pipe locking because of how frequent cursor updates can occur. [How] Store the update type on each CRTC - every plane will have access to the CRTC state if it's flipping. If the update type is not UPDATE_TYPE_FAST then the immediate flip should be disallowed. No changes to the target vblank sequencing need to be done, we just need to ensure that the surface registers do a double buffered update. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: David Francis <david.francis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Validate dc_plane_info and dc_plane_size in atomic checkNicholas Kazlauskas2019-08-061-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] Pitch, DCC, rotation and mirroring can result in updates that are not UPDATE_TYPE_FAST but UPDATE_TYPE_MED instead. DC needs dc_plane_info and dc_plane_size to make this determination and we aren't currently passing this into DC during atomic check. Underflow (visible or non-visible) can occur if we don't validate this correctly. This also will generally trigger p-state warnings, typically via the cursor handler when locking. [How] Get the framebuffer tiling flags and generate the required structures for DC in dm_determine_update_type_for_commit. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: David Francis <david.francis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: enable Navi12 kfd support for amdgpushaoyunl2019-08-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Navi12 has the same interface as Navi10 Signed-off-by: shaoyunl <shaoyun.liu@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Add missing NV12 asic IDsRoman Li2019-08-021-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | Add missing navi12 asic ids. Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: Add nv12 DC ip blockLeo Li2019-08-022-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Load DC and amdgpu display manager Signed-off-by: Leo Li <sunpeng.li@amd.com> Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Add ASICREV_IS_NAVI macrosLeo Li2019-08-021-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | They are used by DC to determine ASIC revs. Signed-off-by: Leo Li <sunpeng.li@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: enable DPG mode for Navi12Boyuan Zhang2019-08-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Enable Dynamic Power Gating VCN for Navi12. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: add VCN ip block for Navi12Boyuan Zhang2019-08-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Add VCN2 ip block for Navi12 Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: add Navi12 VCN firmware supportBoyuan Zhang2019-08-021-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | Add Navi12 to VCN family Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: add psp ip block for navi12Xiaojie Yuan2019-08-021-0/+1
| | | | | | | | | | | | | | | | | | Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: add smu ip block for navi12Xiaojie Yuan2019-08-021-0/+6
| | | | | | | | | | | | | | | | | | Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: start autoload till RLCG fw for navi12Xiaojie Yuan2019-08-021-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | rlc save restore list is not ready yet for navi12 Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu/psp11: add psp support for navi12Xiaojie Yuan2019-08-022-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | Same as other navi asics. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu/smu11: add smu support for navi12Xiaojie Yuan2019-08-022-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | Same as other Navi asics. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: correct smu rlc handshake enablement bitJack Xiao2019-08-021-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Correct the enablement bit of SMU RLC handshake. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: add CGTT_GS_NGG_CLK_CTRL register to gc headerXiaojie Yuan2019-08-022-0/+41
| | | | | | | | | | | | | | | | | | | | | gc 10.1.2 introduced this new register Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu/sdma5: add golden settings for navi12 (v2)Xiaojie Yuan2019-08-021-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | common golden settings are put in golden_settings_sdma_5 array v2: update settings (Alex) Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu/gfx10: add golden settings for navi12 (v2)Xiaojie Yuan2019-08-021-5/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add initial golden settings for navi12 gfx. v2: update settings Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: enable virtual display for navi12Xiaojie Yuan2019-08-022-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Virtual display is a sw display interface for bring up and virtualization or for cards without display hardware. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu/gfx10: set tcp harvest for navi12Xiaojie Yuan2019-08-021-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | Same as navi10. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: add ip blocks for navi12Xiaojie Yuan2019-08-021-0/+7
| | | | | | | | | | | | | | | | | | Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu/gmc10: set gart size and vm size for navi12Xiaojie Yuan2019-08-021-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | Same as other navi asics. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu/sdma5: add placeholder for navi12 golden settingsXiaojie Yuan2019-08-021-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | None yet. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu/sdma5: declare sdma firmwares for navi12Xiaojie Yuan2019-08-021-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | Declare the firmwares and load the proper ones for navi12. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu/gfx10: set rlc funcs for navi12Xiaojie Yuan2019-08-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Same as other navi asics. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu/gfx10: set number of me(c)/pipe/queue for navi12Xiaojie Yuan2019-08-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Same as other navi asics. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu/gfx10: add placeholder for navi12 golden settingsXiaojie Yuan2019-08-021-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | Not used yet. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu/gfx10: declare cp/rlc firmwares for navi12Xiaojie Yuan2019-08-021-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | Set the name properly to load the right ucode. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu/gfx10: add gfx config for navi12Xiaojie Yuan2019-08-021-8/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | got from mmCP_MAX_CONTEXT and mmPA_SC_FIFO_SIZE v2: squash all navi asics together because the settings are the same. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu/gfx10: set gfx cg for navi12Xiaojie Yuan2019-08-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Same as other navi asics. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: set nbio/hdp cg for navi12Xiaojie Yuan2019-08-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Same as navi10. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: initialize cg/pg flags and external rev id for navi12Xiaojie Yuan2019-08-021-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | don't enable any cg/pg features yet. v2: calculate external revision id from revision id so that we can differentiate navi12 A0 from A1 directly. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: use front door firmware loading for navi12Xiaojie Yuan2019-08-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Same as other navi asics. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: set asic family and ip blocks for navi12Xiaojie Yuan2019-08-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | same with navi10 Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: add gpu_info firmware for navi12Xiaojie Yuan2019-08-021-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | gpu_info firmare store asic configuration details. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: add navi12 asic typeXiaojie Yuan2019-08-022-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Add asic type. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: initialize reg base for navi12Xiaojie Yuan2019-08-024-1/+58
| | | | | | | | | | | | | | | | | | | | | | | | Set up the register offset map for navi12. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: add ip offset header for navi12 (v2)Xiaojie Yuan2019-08-021-0/+1119
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the absolute offsets of each IP regiser block. v2: Squash in MP1 update Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: update SDMA V4 microcode initJohn Clements2019-08-021-35/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | Removed loading duplicate instances of SDMA FW for Arcturus. We use a single image for all instances. Signed-off-by: John Clements <john.clements@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: extend PSP FW loading support to 8 SDMA instancesJohn Clements2019-08-023-3/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | Arcturus has 8 instances of SDMA. Update host to PSP interface to handle it. Signed-off-by: John Clements <john.clements@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: disable MEC2 JT context init for ArcturusJohn Clements2019-08-021-5/+11
| | | | | | | | | | | | | | | | | | | | | | | | We don't need to handle it like other asics. Signed-off-by: John Clements <john.clements@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: update PSP CMD fail response status printJohn Clements2019-08-021-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Print the response in hex with the apprpriate mask. Signed-off-by: John Clements <john.clements@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: add PSP KDB loading support for ArcturusJohn Clements2019-08-023-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the arcturus specific psp metadata to the amdgpu firmware and properly parse it when loading it. Signed-off-by: John Clements <john.clements@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: add PSP SW init support for ArcturusJohn Clements2019-08-022-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | Add arcturus cases to psp init sewquence. Signed-off-by: John Clements <john.clements@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: removed duplicate lineJohn Clements2019-08-021-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | Remove duplicate break. Signed-off-by: John Clements <john.clements@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/powerplay: correct navi10 vcn powergateEvan Quan2019-08-023-9/+19
| | | | | | | | | | | | | | | | | | | | | | | | vcn dpm on is a prerequisite for vcn power gate control. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/powerplay: enable SW SMU power profile switch support in KFDEvan Quan2019-08-023-2/+45
| | | | | | | | | | | | | | | | | | | | | | | | Hook up the SW SMU power profile switch in KFD routine. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/powerplay: support power profile retrieval and setting on arcturusEvan Quan2019-08-021-0/+74
| | | | | | | | | | | | | | | | | | | | | | | | Enable arcturus power profile retrieval and setting. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/powerplay: guard consistency between CPU copy and local VRAMEvan Quan2019-08-025-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | This can prevent CPU to use the out-dated copy. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: replace AMDGPU_RAS_UE with AMDGPU_RAS_SUCCESSTao Zhou2019-08-024-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ce can also trigger interrupt, and even both ce and ue error can be found in one ras query, distinguishing between ce and ue in interrupt handler is uncessary. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Suggested-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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