summaryrefslogtreecommitdiffstats
Commit message (Expand)AuthorAgeFilesLines
* drm/i915: add render state initializationMika Kuoppala2014-05-148-0/+286
* drm/i915: Only do gtt cleanup in vma_unbind for the global vmaDaniel Vetter2014-05-141-5/+7
* drm/i915: Don't drop pinned fencesDaniel Vetter2014-05-141-0/+3
* drm/i915: use dev_priv directly in i915_driver_unloadDaniel Vetter2014-05-141-1/+1
* drm/i915: Use the connector name in fbdev debug messagesChris Wilson2014-05-141-10/+14
* drm/i915: Use for_each_crtc() when iterating through the CRTCsDamien Lespiau2014-05-144-16/+16
* drm/i915: Introduce a for_each_crtc() macroDamien Lespiau2014-05-141-0/+3
* drm/i915: Use for_each_intel_crtc() when iterating through intel_crtcsDamien Lespiau2014-05-143-38/+25
* drm/i915: Introduce a for_each_intel_crtc() macroDamien Lespiau2014-05-141-0/+3
* drm/i915: Use ilk_wm_max_level() in latency debugfs filesDamien Lespiau2014-05-133-3/+4
* drm/i915: Don't cast void* pointersDamien Lespiau2014-05-131-37/+37
* drm/i915: Work-around garbage DR4 from UXADaniel Vetter2014-05-131-0/+5
* drm/i915: WARN_ON fence pin leaksDaniel Vetter2014-05-132-20/+28
* drm/i915: Kill vblank waits after pipe enable on gmch platformsVille Syrjälä2014-05-131-4/+0
* drm/i915: Disable/enable planes as the first/last thing during modeset on gmc...Ville Syrjälä2014-05-131-6/+6
* drm/i915: Ringbuffer signal func for the second BSD ringOscar Mateo2014-05-131-0/+1
* x86/gpu: Sprinkle const, __init and __initconst to stolen memory quirksVille Syrjälä2014-05-131-10/+10
* x86/gpu: Implement stolen memory size early quirk for CHVDamien Lespiau2014-05-131-1/+27
* drm/i915/chv: Implement stolen memory size detectionDamien Lespiau2014-05-131-2/+36
* drm/i915/chv: CHV doesn't have CRT outputVille Syrjälä2014-05-131-1/+1
* drm/i915/chv: Add DPLL state readout supportVille Syrjälä2014-05-131-1/+33
* drm/i915/chv: Pipe select change for DP and HDMIChon Ming Lee2014-05-124-2/+20
* drm/i915/chv: Add phy supports for CherryviewChon Ming Lee2014-05-122-2/+270
* drm/i915/chv: Add update and enable pll for CherryviewChon Ming Lee2014-05-122-2/+202
* drm/i915/chv: find the best divisor for the target clock v4Chon Ming Lee2014-05-122-0/+107
* drm/i915/chv: Trigger phy common lane resetChon Ming Lee2014-05-122-15/+65
* drm/i915/chv: Add vlv_pipe_to_channelChon Ming Lee2014-05-121-0/+14
* drm/i915/chv: Update Cherryview DPLL changes to support Port D. v2Chon Ming Lee2014-05-123-2/+16
* drm/i915/chv: Add DPIO offset for Cherryview. v3Chon Ming Lee2014-05-123-2/+13
* drm/i915/chv: Add DDL register defines for CherryviewVille Syrjälä2014-05-121-0/+29
* srm/i915/chv: Add Cherryview PCI IDsVille Syrjälä2014-05-122-1/+17
* drm/i915/chv: Initial clock gating support for CherryviewVille Syrjälä2014-05-121-0/+13
* drm/i915/chv: Add Cherryview interrupt registers into debugfsVille Syrjälä2014-05-121-1/+41
* drm/i915: Drop unecessary casts in i915_irq.cDaniel Vetter2014-05-121-6/+6
* drm/i915/chv: Preliminary interrupt support for CherryviewVille Syrjälä2014-05-121-1/+224
* drm/i915: Use hash tables for the command parserBrad Volkin2014-05-124-38/+140
* drm/i915: Convert gmch platforms over to ilk_crtc_{enable, disable}_planes()Ville Syrjälä2014-05-121-78/+56
* drm/i915: Flush request queue when waiting for ring spaceChris Wilson2014-05-083-27/+16
* drm/i915: Improve fallback ring waitingChris Wilson2014-05-081-6/+16
* drm/i915: Make aliasing a 2nd class VMBen Widawsky2014-05-071-0/+4
* drm/i915: Use topdown allocation for PPGTT PDEs on gen6/7Ben Widawsky2014-05-071-2/+1
* drm/i915: vlv: enable runtime PMImre Deak2014-05-071-1/+1
* drm/i915: vlv: add runtime PM supportImre Deak2014-05-072-0/+389
* drm/i915: propagate the error code from runtime PM callbacksImre Deak2014-05-071-15/+42
* drm/i915: add various missing GTI/Gunit register definitionsImre Deak2014-05-071-1/+40
* drm/i915/chv: Add DPINVGTT registers defines for CherryviewVille Syrjälä2014-05-061-1/+11
* drm/i915/chv: Add display interrupt registers bits for CherryviewVille Syrjälä2014-05-061-1/+20
* drm/i915/chv: Add DPFLIPSTAT register bits for CherryviewVille Syrjälä2014-05-061-0/+7
* drm/i915/chv: Add PIPESTAT register bits for CherryviewVille Syrjälä2014-05-061-0/+8
* drm/i915/chv: Enable aliasing PPGTT for CHVVille Syrjälä2014-05-061-3/+4
OpenPOWER on IntegriCloud