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* MIPS: Replace obsolete strict_strto call with kstrtoDaniel Walter2014-06-042-3/+3
| | | | | | | | Signed-off-by: Daniel Walter <dwalter@google.com> Cc: linux-kernel@vger.kernel.org Cc: richard@nod.at Cc: akpm@linux-foundation.org Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BFP: Simplify code slightly.Ralf Baechle2014-06-041-4/+4
| | | | | | | This keeps the if condition slightly simpler - it's going to become ore complication. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* mips: Update the email address of Geert UytterhoevenGeert Uytterhoeven2014-06-024-8/+3
| | | | | | | | | All my Sony addresses are defunct. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6817/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add minimal defconfig for mips_paravirtAndreas Herrmann2014-06-021-0/+103
| | | | | | | | | | Signed-off-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com> Cc: linux-mips@linux-mips.org Cc: David Daney <ddaney.cavm@gmail.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7008/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Enable build for new system 'paravirt'David Daney2014-06-022-0/+20
| | | | | | | | | | Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com> Cc: linux-mips@linux-mips.org Cc: James Hogan <james.hogan@imgtec.com> Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7015/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: paravirt: Add pci controller for virtioDavid Daney2014-06-024-1/+139
| | | | | | | | | | Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com> Cc: linux-mips@linux-mips.org Cc: James Hogan <james.hogan@imgtec.com> Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7011/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add code for new system 'paravirt'David Daney2014-06-0211-6/+777
| | | | | | | | | | | | | For para-virtualized guests running under KVM or other equivalent hypervisor. Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com> Cc: linux-mips@linux-mips.org Cc: James Hogan <james.hogan@imgtec.com> Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7004/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add functions for hypervisor callDavid Daney2014-05-303-1/+117
| | | | | | | | | | | | | | | | | | Introduce kvm_hypercall[0-3]. Define three new hypercalls for MIPS: GET_CLOCK_FREQ, EXIT_VM, and CONSOLE_OUTPUT. [andreas.herrmann: * Properly define hypercalls and HC numbers for MIPS in kvm_para.h header files] Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com> Cc: linux-mips@linux-mips.org Cc: James Hogan <james.hogan@imgtec.com> Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7005/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: OCTEON: Add OCTEON3 to __get_cpu_typeAndreas Herrmann2014-05-301-0/+1
| | | | | | | | | | | | Otherwise __builtin_unreachable might be called. Signed-off-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com> Cc: linux-mips@linux-mips.org Cc: David Daney <ddaney.cavm@gmail.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7014/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add function get_ebase_cpunumDavid Daney2014-05-302-1/+10
| | | | | | | | | | | | This returns the CPUNum from the low order Ebase bits. Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com> Cc: linux-mips@linux-mips.org Cc: James Hogan <james.hogan@imgtec.com> Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7012/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add minimal support for OCTEON3 to c-r4k.cDavid Daney2014-05-302-4/+46
| | | | | | | | | | | | These are needed to boot a generic mips64r2 kernel on OCTEONIII. Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com> Cc: linux-mips@linux-mips.org Cc: James Hogan <james.hogan@imgtec.com> Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7003/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Don't build fast TLB refill handler with 32-bit kernelsDavid Daney2014-05-301-2/+6
| | | | | | | | | | | | The fast handler only supports 64-bit kernels. Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com> Cc: linux-mips@linux-mips.org Cc: James Hogan <james.hogan@imgtec.com> Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7010/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Don't use RI/XI with 32-bit kernels on 64-bit CPUsDavid Daney2014-05-301-1/+8
| | | | | | | | | | | | The TLB handlers cannot handle this case, so disable it for now. Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com> Cc: linux-mips@linux-mips.org Cc: James Hogan <james.hogan@imgtec.com> Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7007/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: OCTEON: Move CAVIUM_OCTEON_CVMSEG_SIZE to CPU_CAVIUM_OCTEONDavid Daney2014-05-301-12/+11
| | | | | | | | | | | | | CVMSEG is related to the CPU core not the SoC system. So needs to be configurable there. Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com> Cc: linux-mips@linux-mips.org Cc: James Hogan <james.hogan@imgtec.com> Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7013/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Move system level config items from CPU_CAVIUM_OCTEON to CAVIUM_OCTEON_SOCDavid Daney2014-05-301-5/+5
| | | | | | | | | | | | They are a property of the SoC not the CPU itself. Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com> Cc: linux-mips@linux-mips.org Cc: James Hogan <james.hogan@imgtec.com> Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7009/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: OCTEON: Enable use of FPUDavid Daney2014-05-306-27/+75
| | | | | | | | | | | | | | | | | | | | Some versions of the assembler will not assemble CFC1 for OCTEON, so override the ISA for these. Add r4k_fpu.o to handle low level FPU initialization. Modify octeon_switch.S to save the FPU registers. And include r4k_switch.S to pick up more FPU support. Get rid of "#define cpu_has_fpu 0" Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com> Cc: linux-mips@linux-mips.org Cc: James Hogan <james.hogan@imgtec.com> Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7006/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Malta: support powering downPaul Burton2014-05-301-0/+4
| | | | | | | | | | | | | | This patch powers down the Malta in response to a power off command (eg. poweroff or shutdown -P). It may then be powered back up by pressing the "ON/NMI" button (S4) on the board. In cases where the power off state cannot be entered (eg. because the required PCI support is disabled) the current reset behaviour will be used as a fallback. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Tested-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6907/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Malta: hang on haltPaul Burton2014-05-301-4/+6
| | | | | | | | | | | | | | When the system is halted it makes little sense to reset it. Instead, hang by executing an infinite loop. [ralf@linux-mips.org: Remove printk from mips_machine_halt() - this is not the place to communicate with the user.] Suggested-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6906/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Malta: Let PIIX4 respond to PCI special cyclesPaul Burton2014-05-301-0/+6
| | | | | | | | | | | | This patch enables the PIIX4 to respond to special cycles on the PCI bus. One such special cycle must be used in order to enter a suspend state, and if response to it is not enabled then the suspend state will never be entered. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6904/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Malta: add suspend state entry codePaul Burton2014-05-304-0/+141
| | | | | | | | | | | | | This patch introduces code which will enter a suspend state via the PIIX4. This can only be done when PCI support is enabled since it requires access to PCI I/O space and the generation of a special cycle on the PCI bus. In cases where PCI is disabled the mips_pm_suspend function will simply always return an error. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6905/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Define some more PIIX4 registers & valuesPaul Burton2014-05-301-0/+12
| | | | | | | | | | | This patch simply adds definitions for some I/O registers in the PIIX4 PM device, and the magic data for a special cycle which must occur on the PCI bus in order for the PIIX4 to enter a suspend state. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6903/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: DEC: Remove the Halt button interrupt on R4k systemsMaciej W. Rozycki2014-05-301-0/+5
| | | | | | | | | | | | | | On R4k DECstations the Halt button is wired to the NMI processor input rather than an ordinary interrupt input such as on R3k DECstations. This is possible with a different design of the CPU daughtercard that routes the Halt button line from the baseboard connector. Additionally the interrupt input has been reused for a different purpose on the KN04 and KN05 R4k CPU daughtercards so it is better kept masked. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6705/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: DEC: Only select the R4k clock event/source on R4k systemsMaciej W. Rozycki2014-05-301-2/+2
| | | | | | | | | | R3k systems have no R4k timer so there's no point in pulling code that's going to be dead. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6704/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: __delay ABI-dependent subtraction simplificationMaciej W. Rozycki2014-05-301-5/+3
| | | | | | | | | | | | This small update to the previous fix to __delay removes a conditional around the ABI-dependent subtraction operation within an inline asm in favor to the standard <asm/asm.h> LONG_SUBU macro. No change in code produced. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6703/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Implement random_get_entropy with CP0 RandomMaciej W. Rozycki2014-05-302-18/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update to commit 9c9b415c50bc298ac61412dff856eae2f54889ee [MIPS: Reimplement get_cycles().] On systems were for whatever reasons we can't use the cycle counter, fall back to the c0_random register as an entropy source. It has however a very small range that makes it suitable for random_get_entropy only and not get_cycles. This optimised version compiles to 8 instructions in the fast path even in the worst case of all the conditions to check being variable (including a MFC0 move delay slot that is only required for very old processors): 828: 8cf90000 lw t9,0(a3) 828: R_MIPS_LO16 jiffies 82c: 40057800 mfc0 a1,c0_prid 830: 3c0200ff lui v0,0xff 834: 00a21024 and v0,a1,v0 838: 1040007d beqz v0,a30 <add_interrupt_randomness+0x22c> 83c: 3c030000 lui v1,0x0 83c: R_MIPS_HI16 cpu_data 840: 40024800 mfc0 v0,c0_count 844: 00000000 nop 848: 00409021 move s2,v0 84c: 8ce20000 lw v0,0(a3) 84c: R_MIPS_LO16 jiffies On most targets the sequence will be shorter and on some it will reduce to a single `MFC0 <reg>,c0_count', as all MIPS architecture (i.e. non-legacy MIPS) processors require the CP0 Count register to be present. The only known exception that reports MIPS architecture compliance, but contrary to that lacks CP0 Count is the Ingenic JZ4740 thingy. For broken platforms like that this code requires cpu_has_counter to be hardcoded to 0 (i.e. no variable setting is permitted) so as not to penalise all the other good platforms out there. The asm barrier is required so that the compiler does not pull any potentially costly (cold cache!) `cpu_data' variable access into the fast path. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: Theodore Ts'o <tytso@mit.edu> Cc: John Crispin <blogic@openwrt.org> Cc: Andrew McGregor <andrewmcgr@gmail.com> Cc: Dave Taht <dave.taht@bufferbloat.net> Cc: Felix Fietkau <nbd@nbd.name> Cc: Simon Kelley <simon@thekelleys.org.uk> Cc: Jim Gettys <jg@freedesktop.org> Cc: David Daney <ddaney@caviumnetworks.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6702/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Netlogic: XLP9XX on-chip SATA supportGanesan Ramalingam2014-05-302-0/+378
| | | | | | | | | | | | The XLP9XX SoC has an on-chip SATA controller with two ports. Add ahci-init-xlp2.c to initialize the controller, setup the glue logic registers, fixup PCI quirks and setup interrupt ack logic. Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6913/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Netlogic: Support for XLP3XX on-chip SATAGanesan Ramalingam2014-05-302-0/+210
| | | | | | | | | | | | XLP3XX includes an on-chip SATA controller with 4 ports. The controller needs glue logic initialization and PCI fixup before it can be used with the standard AHCI driver. Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6872/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add MSI support for XLP9XXGanesan Ramalingam2014-05-304-51/+156
| | | | | | | | | | | | | | | In XLP9XX, the interrupt routing table for MSI-X has been moved to the PCIe controller's config space from PIC. There are also 32 MSI-X interrupts available per link on XLP9XX. Update XLP MSI/MSI-X code to handle this. Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: g@linux-mips.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6912/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Netlogic: Add support for XLP5XXYonghong Song2014-05-308-4/+23
| | | | | | | | | | | Add support for the XLP5XX processor which is an 8 core variant of the XLP9XX. Add XLP5XX cases to code which earlier handled XLP9XX. Signed-off-by: Yonghong Song <ysong@broadcom.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6871/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Netlogic: Update XLP9XX/2XX core freq calculationJayachandran C2014-05-302-18/+73
| | | | | | | | | | Calculate XLP 9XX and 2XX core frequency from the per-core PLL. This should give the correct value for all board configurations. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6870/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Netlogic: PIC freq calculation for XLP 9XX/2XXGanesan Ramalingam2014-05-304-34/+114
| | | | | | | | | | | | Update PIC frequency calculation for XLP9XX and 2XX processors using the correct PLL registers. This should work for all possible board configurations. Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6876/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Netlogic: Fix XLP9XX pic entryJayachandran C2014-05-301-2/+3
| | | | | | | | | | Add the compatible property to the PIC entry. Also fix up the nodename to use the correct address. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6869/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Netlogic: Use PRID_IMP_MASK macroJayachandran C2014-05-306-9/+10
| | | | | | | | | | Use PRID_IMP_MASK macro instead of 0xff00 to extract the processor type. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6868/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Netlogic: IRQ mapping for some more SoC blocksJayachandran C2014-05-303-35/+69
| | | | | | | | | | | Add IRQ to IRT (PIC interupt table index) mapping for SATA, GPIO, NAND and SPI interfaces on the XLP SoC. Fix offsets for few blocks and add device IDs for a few blocks. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6911/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Netlogic: Enable access to more than 64GBJayachandran C2014-05-301-0/+15
| | | | | | | | | | | The ELPA bit needs to be set in the PAGEGRAIN register to enable access to >64GB physical address. Update reset.S to do this from every hardware thread. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6866/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Netlogic: Reduce size of reset codeJayachandran C2014-05-302-11/+16
| | | | | | | | | | | Update thread wakeup function to use scratch registers for saving SP and RA. Move the register restore code needed for thread 0 to the calling function. This reduces the size of code copied to the reset vector. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6910/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Netlogic: Use cpumask_scnprintf for wakeup_maskJayachandran C2014-05-301-3/+4
| | | | | | | | | | | Use standard function to print cpumask. Also fixup a typo in the same file. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: g@linux-mips.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6909/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Netlogic: Warn on invalid irqJayachandran C2014-05-301-0/+2
| | | | | | | | | Warn and return if invalid IRQ is passed to nlm_set_pic_extra_ack. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6862/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Netlogic: Move coremask setup to nlm_node_initJayachandran C2014-05-302-4/+2
| | | | | | | | | This is needed for nlm_node_present(0) to work on uniprocessor compile. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6861/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Netlogic: Fix uniprocessor compilationJayachandran C2014-05-301-0/+2
| | | | | | | | | | The macros in topology.h need CONFIG_SMP, and the uniprocessor compilation fails due to this. Wrap the macros in an ifdef so that uniprocessor works. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6863/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Support upto 256 CPUsJayachandran C2014-05-301-2/+2
| | | | | | | | | This is needed for two node XLP9xx configurations. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6860/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Enable the BPF_JIT symbol for MIPSMarkos Chandras2014-05-301-0/+1
| | | | | | | Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6743/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: net: Add BPF JITMarkos Chandras2014-05-304-0/+1447
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds initial support for BPF-JIT on MIPS Tested on mips32 LE/BE and mips64 BE/n64 using dhcp, ping and various tcpdump filters. Benchmarking: Assuming the remote MIPS target uses 192.168.154.181 as its IP address, and the local host uses 192.168.154.136, the following results can be obtained using the following tcpdump filter (catches no frames) and a simple 'time ping -f -c 1000000' command. [root@(none) ~]# tcpdump -p -n -s 0 -i eth0 net 10.0.0.0/24 -d (000) ldh [12] (001) jeq #0x800 jt 2 jf 8 (002) ld [26] (003) and #0xffffff00 (004) jeq #0xa000000 jt 16 jf 5 (005) ld [30] (006) and #0xffffff00 (007) jeq #0xa000000 jt 16 jf 17 (008) jeq #0x806 jt 10 jf 9 (009) jeq #0x8035 jt 10 jf 17 (010) ld [28] (011) and #0xffffff00 (012) jeq #0xa000000 jt 16 jf 13 (013) ld [38] (014) and #0xffffff00 (015) jeq #0xa000000 jt 16 jf 17 (016) ret #65535 - BPF-JIT Disabled real 1m38.005s user 0m1.510s sys 0m6.710s - BPF-JIT Enabled real 1m35.215s user 0m1.200s sys 0m4.140s [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: uasm: Add lb uasm instructionMarkos Chandras2014-05-304-8/+12
| | | | | | | | It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: uasm: Add mflo uasm instructionMarkos Chandras2014-05-305-5/+11
| | | | | | | | It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: uasm: Add mul uasm instructionMarkos Chandras2014-05-305-1/+6
| | | | | | | | | | | It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6736/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: uasm: Add lh uam instructionMarkos Chandras2014-05-304-6/+10
| | | | | | | | | | | It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6733/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: uasm: Add wsbh uasm instructionMarkos Chandras2014-05-305-1/+16
| | | | | | | | | | | It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6732/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: uasm: Add sltu uasm instructionMarkos Chandras2014-05-305-1/+6
| | | | | | | | | | | It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6731/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: uasm: Add sltiu uasm instructionMarkos Chandras2014-05-304-4/+8
| | | | | | | | | | | It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6730/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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