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* spi: imx: Switch to SPDX identifierFabio Estevam2018-05-031-19/+3
| | | | | | | | Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: omap2-mcspi: Idle hardware during suspend and resumeTony Lindgren2018-05-021-10/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We currently are calling mcspi suspend and resume without considering that mcspi might provide resources for other device driver such as regulators. This means resume can fail and will produce -EACCES if errors if anything calls mcspi functions between device_prepare() and device_complete(). To fix the issue, let's do the following changes: 1. Let's add checking for return values for pm_runtime_get calls, and call pm_runtime_put_noidle() on errors. Things still fail after this change, but at least we see something is wrong as we now see -EACCES errors on resume. 2. Let's use noirq level for suspend and resume as other drivers can still call SPI related functions on suspend and resume. This still won't fix the -EACCES issue, but gets us to something a bit saner. 3. Finally, let's modify suspend and resume to call to make sure the device is idled properly on suspend. We have device_prepare() call pm_runtime_get_noresume() that won't get released until in device_complete() when it calls pm_runtime_put(). So if SPI is still active on entering suspend, it will never get idled unless we add calls to pm_runtime_force_suspend() and resume. This also fixes the -EACCES errors on resume together with changes 1 and 2 above. And since we're already rewriting suspend resume functions, let's arrange the order of suspend and resume functions to be like they usually are with suspend first. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: omap2-mcspi: Restore context always in runtime_resumeTony Lindgren2018-05-021-45/+30
| | | | | | | | | | | We can have the SoC enter off mode also during idle, not just during suspend. Currently we are handling the CS restore properly for unused CS only for resume and not for runtime resume. Let's just move all the context related restore to runtime_resume(). Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: meson-spicc: Fix error handling in meson_spicc_probe()Alexey Khoroshilov2018-05-021-3/+8
| | | | | | | | | | | If devm_spi_register_master() fails in meson_spicc_probe(), spicc->core is left undisabled. The patch fixes that. Found by Linux Driver Verification project (linuxtesting.org). Signed-off-by: Alexey Khoroshilov <khoroshilov@ispras.ru> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: mpc52xx: Use gpio_is_valid()Arvind Yadav2018-04-271-1/+1
| | | | | | | | Replace the manual validity checks for the GPIO with the gpio_is_valid(). Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: Check presence the of ->transfer[_xxx]() before registering a controllerBoris Brezillon2018-04-261-0/+21
| | | | | | | | | | | | Right now, no checks are done on the presence of a ->transfer[_xxx]() method, which can lead to a NULL pointer dereference when someone starts sending something on the bus. Do the check at registration time and refuse to add the controller if all ->transfer[_xxx]() pointers are NULL. Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi/bcm63xx-hspi: Enable the clock before calling clk_get_rate().Stefan Potyra2018-04-261-8/+17
| | | | | | | | | | | | | | Enable the clock prior to calling clk_get_rate(), because clk_get_rate() should only be called if the clock is enabled. Additionally, prepare/enable the pll_clk before calling clk_get_rate() for the same reason. Found by Linux Driver Verification project (linuxtesting.org). Fixes: 142168eba9dc ("spi: bcm63xx-hsspi: add bcm63xx HSSPI driver") Signed-off-by: Stefan Potyra <Stefan.Potyra@elektrobit.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: s3c64xx: samsung: Remove support for Exynos5440Krzysztof Kozlowski2018-04-251-12/+0
| | | | | | | | | | The Exynos5440 is not actively developed, there are no development boards available and probably there are no real products with it. Remove wide-tree support for Exynos5440. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: Add an helper to flush the message queueBoris Brezillon2018-04-232-0/+18
| | | | | | | | | | This is needed by the spi-mem logic to force all messages that have been queued before a memory operation to be sent before we start the memory operation. We do that in order to guarantee that spi-mem operations do not preempt regular SPI transfers. Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: Expose spi_{map,unmap}_buf() for internal useBoris Brezillon2018-04-232-18/+48
| | | | | | | | | | | | | spi_{map,unmap}_buf() are needed by the spi-mem logic that is about to be introduced to prepare data buffer for DMA operations. Remove the static specifier on these functions and add their prototypes to drivers/spi/internals.h. We do not export the symbols here because both SPI_MEM and SPI can't be enabled as modules and we'd like to prevent controller/device drivers from using these functions. Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: simplify getting .drvdataWolfram Sang2018-04-202-8/+4
| | | | | | | | | We should get drvdata from struct device directly. Going via platform_device is an unneeded step back and forth. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: pxa2xx: Allow 64-bit DMAAndy Shevchenko2018-04-191-1/+1
| | | | | | | | | | | | | | Currently the 32-bit device address only is supported for DMA. However, starting from Intel Sunrisepoint PCH the DMA address of the device FIFO can be 64-bit. Change the respective variable to be compatible with DMA engine expectations, i.e. to phys_addr_t. Fixes: 34cadd9c1bcb ("spi: pxa2xx: Add support for Intel Sunrisepoint") Cc: Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: spi-s3c64xx: Allow higher transfer lengths in polling IO modeSylwester Nawrocki2018-04-181-33/+66
| | | | | | | | | | | | Some variants of the SPI controller have no DMA support, in such case SPI transfers longer than the FIFO length are not currently properly handled by the driver. Fix it by doing multiple transfers in the s3c64xx_spi_transfer_one() function if the SPI transfer length exceeds the FIFO size. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Andi Shyti <andi@etezian.org> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: spi-s3c64xx: Use local variable for FIFO lengthSylwester Nawrocki2018-04-181-3/+3
| | | | | | | | More references to fifo_len are added in subsequent patch. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Andi Shyti <andi@etezian.org> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: pxa2xx: pxa2xx_spi_transfer_one() can be statickbuild test robot2018-04-181-3/+3
| | | | | | | Fixes: d5898e19c0d7 ("spi: pxa2xx: Use core message processing loop") Signed-off-by: Fengguang Wu <fengguang.wu@intel.com> Reviewed-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: spi-s3c64xx: Add missing s3c64xx_ prefix to function namesSylwester Nawrocki2018-04-181-12/+12
| | | | | | | | | Add a s3c64xx_ prefix to remaining generic function names so it is clear the code is part of the driver when grepping or looking at debug logs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Andi Shyti <andi@etezian.org> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: spi-s3c64xx: Drop unused enable_datapath() function argumentSylwester Nawrocki2018-04-181-3/+2
| | | | | | | | The spi pointer argument is not used now so remove it. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Andi Shyti <andi@etezian.org> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: Remove depends on HAS_DMA in case of platform dependencyGeert Uytterhoeven2018-04-181-9/+3
| | | | | | | | | | | | | | | | | | | Remove dependencies on HAS_DMA where a Kconfig symbol depends on another symbol that implies HAS_DMA, and, optionally, on "|| COMPILE_TEST". In most cases this other symbol is an architecture or platform specific symbol, or PCI. Generic symbols and drivers without platform dependencies keep their dependencies on HAS_DMA, to prevent compiling subsystems or drivers that cannot work anyway. This simplifies the dependencies, and allows to improve compile-testing. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by: Mark Brown <broonie@kernel.org> Acked-by: Robin Murphy <robin.murphy@arm.com> Acked-by: Mark Brown <broonie@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: pxa2xx: Use core message processing loopJarkko Nikula2018-04-173-185/+89
| | | | | | | | | | Convert the pump_transfers() transfer tasklet to transfer_one() hook the SPI core calls to process single transfer instead of handling message processing and chip select handling in the driver. This not only simplifies the driver but also brings transfer statistics from the core. Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: pxa2xx: Remove pump_transfers string from dev_ printsJarkko Nikula2018-04-171-6/+4
| | | | | | | | | | | We are going to rename and modify pump_transfers(). Prepare for it by removing the string "pump_transfers:" from error and warning prints. While at it make these user-visible strings single line in sources as it helps source grepping from error reports. Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: pxa2xx: Remove unused argument from pxa2xx_spi_dma_prepare()Jarkko Nikula2018-04-173-3/+3
| | | | | | | | | Current DMA engine implementation of pxa2xx_spi_dma_prepare() don't use the dma_burst argument. Remove it since it became unused after commit 6356437e65c2 ("spi: spi-pxa2xx: remove legacy PXA DMA bits"). Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: spi-s3c64xx: Fix indentation in the register offset definitionsSylwester Nawrocki2018-04-171-8/+8
| | | | | | | | | | Change indentation so register address offset and register bit definitions are aligned to same column. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Andi Shyti <andi@etezian.org> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: spi-s3c64xx: Do not ignore timeout errors in polling I/O modeSylwester Nawrocki2018-04-171-0/+2
| | | | | | | | | | | Currently timeout errors in polling I/O mode transfer are silently ignored. Fix it by returning an error when we time out waiting on the RX FIFO level to reach the transfer length. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Andi Shyti <andi@etezian.org> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: spi-s3c64xx: Remove unused s3c64xx_spi_hwinit() function argumentSylwester Nawrocki2018-04-171-3/+3
| | | | | | | | | | The channel argument is not used and anyway it could be retrieved from the passed driver data structure. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Andi Shyti <andi@etezian.org> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: spi-s3c64xx: Remove unused driver data structure tgl_spi fieldSylwester Nawrocki2018-04-171-2/+0
| | | | | | | | | The tgl_spi pointer is now unused so remove it. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Andi Shyti <andi@etezian.org> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: zynqmp: Add pm runtime supportNaga Sureshkumar Relli2018-04-171-16/+70
| | | | | | | | This patch adds runtime pm functions. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: sh-msiof: Simplify calculation of divisors for transfer rateVladimir Zapolskiy2018-04-171-32/+35
| | | | | | | | | | | | | | | | | The change updates sh_msiof_spi_set_clk_regs() function by iterating over BRDV power values. Note that the change is a functional one, namely prescaler output x 1/1 set in BRDV bit field (0b111) for MSO division rate set to 2 is substituted by BRDV = 0b000 and BRPS = 0b0, in terms of written values to TSCR setting of 0x0107 is substituted by 0x0000, and for all input parameter cases this is the only functional change, which touches the controller. As a result of the rework the function is supposed to be slightly more efficient and more readable and maintainable in case of any further extensions. Signed-off-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: stm32: Fix error handling in stm32_spi_probe()Alexey Khoroshilov2018-04-171-1/+1
| | | | | | | | | | | clk_get_rate() is below clk_prepare_enable(), so its error should lead to goto err_clk_disable, not to err_master_put. Found by Linux Driver Verification project (linuxtesting.org). Signed-off-by: Alexey Khoroshilov <khoroshilov@ispras.ru> Reviewed-by: Amelie Delaunay <amelie.delaunay@st.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: sh-msiof: Fix bit field overflow writes to TSCR/RSCRVladimir Zapolskiy2018-04-161-0/+1
| | | | | | | | | | | | | | | | | | | | | The change fixes a bit field overflow which allows to write to higher bits while calculating SPI transfer clock and setting BRPS and BRDV bit fields, the problem is reproduced if 'parent_rate' to 'spi_hz' ratio is greater than 1024, for instance p->min_div = 2, MSO rate = 33333333, SPI device rate = 10000 results in k = 5, i.e. BRDV = 0b100 or 1/32 prescaler output, BRPS = 105, TSCR value = 0x6804, thus MSSEL and MSIMM bit fields are non-zero. Fixes: 65d5665bb260 ("spi: sh-msiof: Update calculation of frequency dividing") Signed-off-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: imx: Update MODULE_DESCRIPTION to "SPI Controller driver"wangbo2018-04-131-1/+1
| | | | | | | | Now i.MX SPI controller can work in Slave mode. Update MODULE_DESCRIPTION to "SPI Controller driver". Signed-off-by: wangbo <wang.bo116@zte.com.cn> Signed-off-by: Mark Brown <broonie@kernel.org>
* Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhostLinus Torvalds2018-04-112-1/+9
|\ | | | | | | | | | | | | | | Pull virtio update from Michael Tsirkin: "This adds reporting hugepage stats to virtio-balloon" * tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost: virtio_balloon: export hugetlb page allocation counts
| * virtio_balloon: export hugetlb page allocation countsJonathan Helman2018-04-102-1/+9
| | | | | | | | | | | | | | | | | | | | | | Export the number of successful and failed hugetlb page allocations via the virtio balloon driver. These 2 counts come directly from the vm_events HTLB_BUDDY_PGALLOC and HTLB_BUDDY_PGALLOC_FAIL. Signed-off-by: Jonathan Helman <jonathan.helman@oracle.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Jason Wang <jasowang@redhat.com>
* | Merge tag 'iommu-updates-v4.17' of ↵Linus Torvalds2018-04-1125-853/+1008
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu Pull IOMMU updates from Joerg Roedel: - OF_IOMMU support for the Rockchip iommu driver so that it can use generic DT bindings - rework of locking in the AMD IOMMU interrupt remapping code to make it work better in RT kernels - support for improved iotlb flushing in the AMD IOMMU driver - support for 52-bit physical and virtual addressing in the ARM-SMMU - various other small fixes and cleanups * tag 'iommu-updates-v4.17' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (53 commits) iommu/io-pgtable-arm: Avoid warning with 32-bit phys_addr_t iommu/rockchip: Support sharing IOMMU between masters iommu/rockchip: Add runtime PM support iommu/rockchip: Fix error handling in init iommu/rockchip: Use OF_IOMMU to attach devices automatically iommu/rockchip: Use IOMMU device for dma mapping operations dt-bindings: iommu/rockchip: Add clock property iommu/rockchip: Control clocks needed to access the IOMMU iommu/rockchip: Fix TLB flush of secondary IOMMUs iommu/rockchip: Use iopoll helpers to wait for hardware iommu/rockchip: Fix error handling in attach iommu/rockchip: Request irqs in rk_iommu_probe() iommu/rockchip: Fix error handling in probe iommu/rockchip: Prohibit unbind and remove iommu/amd: Return proper error code in irq_remapping_alloc() iommu/amd: Make amd_iommu_devtable_lock a spin_lock iommu/amd: Drop the lock while allocating new irq remap table iommu/amd: Factor out setting the remap table for a devid iommu/amd: Use `table' instead `irt' as variable name in amd_iommu_update_ga() iommu/amd: Remove the special case from alloc_irq_table() ...
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| *-------------. \ Merge branches 'x86/amd', 'x86/vt-d', 'arm/rockchip', 'arm/omap', ↵Joerg Roedel2018-03-291654-11836/+19064
| |\ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'arm/mediatek', 'arm/exynos', 'arm/renesas', 'arm/smmu' and 'core' into next
| | | | | | | | | * | iommu/dma: Add HW MSI(GICv3 ITS) address regions reservationShameer Kolothum2018-02-141-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Modified iommu_dma_get_resv_regions() to include GICv3 ITS region on ACPI based ARM platfiorms which may require HW MSI reservations. Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> Reviewed-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
| | | | | | | | | * | ACPI/IORT: Add msi address regions reservation helperShameer Kolothum2018-02-143-5/+116
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On some platforms msi parent address regions have to be excluded from normal IOVA allocation in that they are detected and decoded in a HW specific way by system components and so they cannot be considered normal IOVA address space. Add a helper function that retrieves ITS address regions - the msi parent - through IORT device <-> ITS mappings and reserves it so that these regions will not be translated by IOMMU and will be excluded from IOVA allocations. The function checks for the smmu model number and only applies the msi reservation if the platform requires it. Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> Reviewed-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> [For the ITS part] Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
| | | | | | | | | * | iommu/io-pgtable: Use size_t return type for all foo_unmapVivek Gautam2018-02-133-24/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unmap returns a size_t all throughout the IOMMU framework. Make io-pgtable match this convention. Moreover, there isn't a need to have a signed int return type as we return 0 in case of failures. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Acked-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
| | | | | | | | | * | iommu: Do not return error code for APIs with size_t return typeSuravee Suthikulpanit2018-02-133-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, iommu_unmap, iommu_unmap_fast and iommu_map_sg return size_t. However, some of the return values are error codes (< 0), which can be misinterpreted as large size. Therefore, returning size 0 instead to signify failure to map/unmap. Cc: Joerg Roedel <joro@8bytes.org> Cc: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
| | | | | | | | * | | iommu/io-pgtable-arm: Avoid warning with 32-bit phys_addr_tRobin Murphy2018-03-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's not entirely unreasonable for io-pgtable-arm to be built for configurations with 32-bit phys_addr_t, where the compiler rightly raises a warning about the 36-bit shift. That particular code path should never actually *run* on those systems, but we still want it to compile cleanly, which is easily done by using an unambiguous u64 as the intermediate type instead. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
| | | | | | | | * | | Merge branch 'for-joerg/arm-smmu/updates' of ↵Joerg Roedel2018-03-292-317/+292
| | | | | | | | |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/will/linux into arm/smmu
| | | | | | | | | * | | iommu/arm-smmu-v3: Support 52-bit virtual addressRobin Murphy2018-03-271-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Stage 1 input addresses are effectively 64-bit in SMMUv3 anyway, so really all that's involved is letting io-pgtable know the appropriate upper bound for T0SZ. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| | | | | | | | | * | | iommu/arm-smmu-v3: Support 52-bit physical addressRobin Murphy2018-03-271-15/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement SMMUv3.1 support for 52-bit physical addresses. Since a 52-bit OAS implies 64KB translation granule support, permitting level 1 block entries there is simple, and the rest is just extending address fields. Tested-by: Nate Watterson <nwatters@codeaurora.org> Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| | | | | | | | | * | | iommu/io-pgtable-arm: Support 52-bit physical addressRobin Murphy2018-03-271-18/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bring io-pgtable-arm in line with the ARMv8.2-LPA feature allowing 52-bit physical addresses when using the 64KB translation granule. This will be supported by SMMUv3.1. Tested-by: Nate Watterson <nwatters@codeaurora.org> Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| | | | | | | | | * | | iommu/arm-smmu-v3: Clean up queue definitionsRobin Murphy2018-03-271-73/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As with registers and tables, use GENMASK and the bitfield accessors consistently for queue fields, to save some lines and ease maintenance a little. This now leaves everything in a nice state where all named field definitions expect to be used with bitfield accessors (although since single-bit fields can still be used directly we leave some of those uses as-is to avoid unnecessary churn), while the few remaining *_MASK definitions apply exclusively to in-place values. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| | | | | | | | | * | | iommu/arm-smmu-v3: Clean up table definitionsRobin Murphy2018-03-271-90/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As with registers, use GENMASK and the bitfield accessors consistently for table fields, to save some lines and ease maintenance a little. This also catches a subtle off-by-one wherein bit 5 of CD.T0SZ was missing. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| | | | | | | | | * | | iommu/arm-smmu-v3: Clean up register definitionsRobin Murphy2018-03-271-97/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The FIELD_{GET,PREP} accessors provided by linux/bitfield.h allow us to define multi-bit register fields solely in terms of their bit positions via GENMASK(), without needing explicit *_SHIFT and *_MASK definitions. As well as the immediate reduction in lines of code, this avoids the awkwardness of values sometimes being pre-shifted and sometimes not, which means we can factor out some common values like memory attributes. Furthermore, it also makes it trivial to verify the definitions against the architecture spec, on which note let's also fix up a few field names to properly match the current release (IHI0070B). Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| | | | | | | | | * | | iommu/arm-smmu-v3: Clean up address maskingRobin Murphy2018-03-271-32/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before trying to add the SMMUv3.1 support for 52-bit addresses, make things bearable by cleaning up the various address mask definitions to use GENMASK_ULL() consistently. The fact that doing so reveals (and fixes) a latent off-by-one in Q_BASE_ADDR_MASK only goes to show what a jolly good idea it is... Tested-by: Nate Watterson <nwatters@codeaurora.org> Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| | | | | | | | | * | | iommu/arm-smmu-v3: limit reporting of MSI allocation failuresNate Watterson2018-03-271-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the arm-smmu-v3 driver expects to allocate MSIs for all SMMUs with FEAT_MSI set. This results in unwarranted "failed to allocate MSIs" warnings being printed on systems where FW was either deliberately configured to force the use of SMMU wired interrupts -or- is altogether incapable of describing SMMU MSI topology (ACPI IORT prior to rev.C). Remedy this by checking msi_domain before attempting to allocate SMMU MSIs. Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Nate Watterson <nwatters@codeaurora.org> Signed-off-by: Sinan Kaya <okaya@codeaurora.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
| | | | | | | | | * | | iommu/arm-smmu-v3: Warn about missing IRQsRobin Murphy2018-03-271-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is annoyingly non-obvious when DMA transactions silently go missing due to undetected SMMU faults. Help skip the first few debugging steps in those situations by making it clear when we have neither wired IRQs nor MSIs with which to raise error conditions. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| | | | | | | * | | | | dt-bindings: iommu: ipmmu-vmsa: Add device tree support for r8a774[35]Biju Das2018-03-201-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Document r8a774[35] specific compatible strings. The Renesas RZ/G1[ME] (r8a774[35]) IPMMU are identical to the R-Car Gen2 family. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Chris Paterson <chris.paterson2@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Joerg Roedel <jroedel@suse.de>
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