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* Merge tag 'fixes-nc-for-linus' of ↵Linus Torvalds2013-05-0279-279/+321
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC non-critical fixes from Olof Johansson: "Here is a collection of fixes (and some intermixed cleanups) that were considered less important and thus not included in the later parts of the 3.9-rc cycle. It's a bit all over the map, contents wise. A series of ux500 fixes and cleanups, a bunch of various fixes for OMAP and tegra, and some for Freescale i.MX and even Qualcomm MSM. Note that there's also a patch on this branch to globally turn off -Wmaybe-uninitialized when building with -Os. It's been posted several times by Arnd and no dissent was raised, but nobody seemed interested to pick it up. So here it is, as the topmost patch." * tag 'fixes-nc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (70 commits) Turn off -Wmaybe-uninitialized when building with -Os ARM: orion5x: include linux/cpu.h ARM: tegra: call cpu_do_idle from C code ARM: u300: fix ages old copy/paste bug ARM: OMAP2+: add dependencies on ARCH_MULTI_V6/V7 ARM: tegra: solve adr range issue with THUMB2_KERNEL enabled ARM: tegra: fix relocation truncated error when THUMB2_KERNEL enabled ARM: tegra: fix build error when THUMB2_KERNEL enabled ARM: msm: Fix uncompess.h tx underrun check ARM: vexpress: Remove A9 PMU compatible values for non-A9 platforms ARM: cpuimx27 and mbimx27: prepend CONFIG_ to Kconfig macro ARM: OMAP2+: fix typo "CONFIG_BRIDGE_DVFS" ARM: OMAP1: remove "config MACH_OMAP_HTCWIZARD" ARM: mach-imx: mach-imx6q: Fix sparse warnings ARM: mach-imx: src: Include "common.h ARM: mach-imx: gpc: Include "common.h" ARM: mach-imx: avic: Staticize *avic_base ARM: mach-imx: tzic: Staticize *tzic_base ARM: mach-imx: clk: Include "clk.h" ARM: mach-imx: clk-busy: Staticize clk_busy_mux_ops ...
| * Turn off -Wmaybe-uninitialized when building with -OsArnd Bergmann2013-04-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gcc-4.7 and higher add a lot of false positive warnings about potential uses of uninitialized warnings, but only when optimizing for size (-Os). This is the default when building allyesconfig, which turns on CONFIG_CC_OPTIMIZE_FOR_SIZE. In order to avoid getting a lot of patches that initialize such variables and accidentally hide real errors along the way, let's just turn off this warning on the respective gcc versions when building with size optimizations. The -Wmaybe-uninitialized option was introduced in the same gcc version (4.7) that is now causing the false positives, so there is no effect on older compilers. A side effect is that when building with CONFIG_CC_OPTIMIZE_FOR_SIZE, we might now see /fewer/ warnings about possibly uninitialized warnings than with -O2, but that is still much better than seeing warnings known to be bogus. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * ARM: orion5x: include linux/cpu.hArnd Bergmann2013-04-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | The linux/cpu.h header is no longer implictly included in this file, so we need to an #include statement to avoid this build warning: arch/arm/mach-orion5x/common.c:339:3: error: implicit declaration of function 'cpu_idle_poll_ctrl' [-Werror=implicit-function-declaration] Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Jason Cooper <jason@lakedaemon.net> Cc: Andrew Lunn <andrew@lunn.ch>
| * ARM: tegra: call cpu_do_idle from C codeArnd Bergmann2013-04-292-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | When building a kernel for multiple CPU architecture levels, cpu_do_idle() is a macro for an indirect function call, which cannot be called from assembly code as Tegra does. Adding a trivial C wrapper for this function lets us build a tegra kernel with ARMv6 support enabled. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Joseph Lo <josephl@nvidia.com> Cc: Stephen Warren <swarren@nvidia.com>
| * ARM: u300: fix ages old copy/paste bugLinus Walleij2013-04-261-1/+1
| | | | | | | | | | | | | | | | | | The UART1 is on the fast AHB bridge, not on the slow bus. Cc: stable@vger.kernel.org Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
| * ARM: OMAP2+: add dependencies on ARCH_MULTI_V6/V7Arnd Bergmann2013-04-231-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_ARCH_OMAP2PLUS depends on (ARCH_MULTI_V6 || ARCH_MULTI_V7) as of a0694861 "ARM: OMAP2+: Enable ARCH_MULTIPLATFORM support", but the individual OMAP2/3/4/5 and AM33XX platforms can all be selected independent of what we are building for, which is a bug and prevents us from easily building e.g. an ARMv7-only defconfig. This makes ARCH_OMAP2 depend on ARCH_MULTI_V6 and the others depend on ARCH_MULTI_V7, to ensure we really only build the platforms for the CPUs we have enabled in the global multiplatform configuration step. Cc: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * ARM: tegra: solve adr range issue with THUMB2_KERNEL enabledStephen Warren2013-04-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When building the kernel with CONFIG_THUMB2_KERNEL enabled, older assemblers may emit the following error: reset-handler.S:78: Error: invalid immediate for address calculation (value = 0x00000004) Using an explicit adr.w instruction will solve this. Newer assemblers do this automatically. Use the W() macro to do this under Thumb mode only. Inspired-by: Joseph Lo <josephl@nvidia.com> Suggested-by: Dave Martin <dave.martin@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
| * ARM: tegra: fix relocation truncated error when THUMB2_KERNEL enabledJoseph Lo2013-04-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The conditional branch instruction in Thumb2 only available to short range. The linker will fail when the conditional branch over the range. Then resulting in link error when generating kernel image. e.g.: arch/arm/mach-tegra/reset-handler.S:47:(.text+0xf8e): relocation truncated to fit: R_ARM_THM_JUMP19 against symbol `cpu_resume' defined in .data section in arch/arm/kernel/built-in.o This patch using a Thumb2 instruction IT (if-then) to have a longer branch range. Reported-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Dave Martin <dave.martin@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
| * ARM: tegra: fix build error when THUMB2_KERNEL enabledJoseph Lo2013-04-181-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fix the build failure when CONFIG_THUBM2_KERNEL enabled. You clould see the error message below: arch/arm/mach-tegra/sleep-tegra30.S:69: Error: shift must be constant -- `orr r12,r12,r4,lsl r3' Reported-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Dave Martin <dave.martin@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
| * Merge tag 'msm-fix-3.10' of ↵Olof Johansson2013-04-142-2/+5
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/davidb/linux-msm into next/fixes-non-critical From David Brown: Some minor fixes for MSM for 3.10 - Fix a timer problem that causes missed ticks and hangs. - Fix a problem with the decompressor UART dropping characters. * tag 'msm-fix-3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/davidb/linux-msm: ARM: msm: Fix uncompess.h tx underrun check ARM: msm: Stop counting before reprogramming clockevent Signed-off-by: Olof Johansson <olof@lixom.net>
| | * ARM: msm: Fix uncompess.h tx underrun checkStephen Boyd2013-04-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bit 3 of the SR register is set if there is a tx underrun. If this bit isn't set, we should loop on the tx ready bit until we can transmit again. Otherwise we should skip the loop and transmit immediately. The code is doing the opposite though, checking for an underrun and then looping on the tx ready bit causing us to never loop on the tx read bit when the tx buffer may not be ready. This doesn't seem to affect my 8960 device too often, but in some cases I see a lost character or two from the decompressor prints. This also matches what we do in the assembly in debug-macro.S. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org>
| * | Merge tag 'imx-noncritical-fixes-3.10' of ↵Olof Johansson2013-04-1117-32/+19
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.linaro.org/people/shawnguo/linux-2.6 into next/fixes-non-critical From Shawn Guo: The imx noncritical fixes for 3.10: * A bunch of fixes for sparse warings * One fix for the typo in use of Kconfig symbol MACH_EUKREA_CPUIMX27_USEUART4 * tag 'imx-noncritical-fixes-3.10' of git://git.linaro.org/people/shawnguo/linux-2.6: ARM: cpuimx27 and mbimx27: prepend CONFIG_ to Kconfig macro ARM: mach-imx: mach-imx6q: Fix sparse warnings ARM: mach-imx: src: Include "common.h ARM: mach-imx: gpc: Include "common.h" ARM: mach-imx: avic: Staticize *avic_base ARM: mach-imx: tzic: Staticize *tzic_base ARM: mach-imx: clk: Include "clk.h" ARM: mach-imx: clk-busy: Staticize clk_busy_mux_ops ARM: mach-imx: irq-common: Remove imx_irq_set_priority() ARM: mach-imx: clk-gate2: Include "clk.h" ARM: mach-imx: clk-pllv2: Staticize clk_pllv2_ops ARM: mach-imx: clk-pllv1: Staticize clk_pllv1_ops ARM: mach-imx: cpu-imx5: Include "common.h" ARM: mach-imx: iomux-imx31: Staticize mxc_pin_alloc_map ARM: mach-imx: mm-imx3: Staticize imx3_init_l2x0() ARM: mach-imx: cpu: Include "common.h" Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | ARM: cpuimx27 and mbimx27: prepend CONFIG_ to Kconfig macroPaul Bolle2013-04-032-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 2d66c7803595da0d4bcd949825d598575f5de9e6 ("cpuimx27 and mbimx27: allow fine control of UART4 and SDHC2 usage") added the Kconfig symbol MACH_EUKREA_CPUIMX27_USEUART4. But it forgot to prepend CONFIG_ to the use of its macro. Add that prefix now. Signed-off-by: Paul Bolle <pebolle@tiscali.nl> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * | ARM: mach-imx: mach-imx6q: Fix sparse warningsFabio Estevam2013-04-011-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the following sparse warnings: arch/arm/mach-imx/mach-imx6q.c:60:6: warning: symbol 'imx6q_restart' was not declared. Should it be static? arch/arm/mach-imx/mach-imx6q.c:223:24: warning: symbol 'imx6q_cpufreq_pdev' was not declared. Should it be static? Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * | ARM: mach-imx: src: Include "common.hFabio Estevam2013-04-011-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the following sparse warnings: arch/arm/mach-imx/src.c:28:6: warning: symbol 'imx_enable_cpu' was not declared. Should it be static? arch/arm/mach-imx/src.c:39:6: warning: symbol 'imx_set_cpu_jump' was not declared. Should it be static? arch/arm/mach-imx/src.c:46:6: warning: symbol 'imx_src_prepare_restart' was not declared. Should it be static? arch/arm/mach-imx/src.c:59:13: warning: symbol 'imx_src_init' was not declared. Should it be static? Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * | ARM: mach-imx: gpc: Include "common.h"Fabio Estevam2013-04-011-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the following sparse warnings: arch/arm/mach-imx/gpc.c:29:6: warning: symbol 'imx_gpc_pre_suspend' was not declared. Should it be static? arch/arm/mach-imx/gpc.c:43:6: warning: symbol 'imx_gpc_post_resume' was not declared. Should it be static? arch/arm/mach-imx/gpc.c:71:6: warning: symbol 'imx_gpc_mask_all' was not declared. Should it be static? arch/arm/mach-imx/gpc.c:83:6: warning: symbol 'imx_gpc_restore_all' was not declared. Should it be static? arch/arm/mach-imx/gpc.c:122:13: warning: symbol 'imx_gpc_init' was not declared. Should it be static? Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * | ARM: mach-imx: avic: Staticize *avic_baseFabio Estevam2013-04-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the following sparse warning: arch/arm/mach-imx/avic.c:54:14: warning: symbol 'avic_base' was not declared. Should it be static? Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * | ARM: mach-imx: tzic: Staticize *tzic_baseFabio Estevam2013-04-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the following sparse warning: arch/arm/mach-imx/tzic.c:52:14: warning: symbol 'tzic_base' was not declared. Should it be static? Also, remove the comment, as it does not apply for kernels newer than 3.2. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * | ARM: mach-imx: clk: Include "clk.h"Fabio Estevam2013-04-011-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the following sparse warning: arch/arm/mach-imx/clk.c:3:1: warning: symbol 'imx_ccm_lock' was not declared. Should it be static? Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * | ARM: mach-imx: clk-busy: Staticize clk_busy_mux_opsFabio Estevam2013-04-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the following sparse warning: arch/arm/mach-imx/clk-busy.c:150:16: warning: symbol 'clk_busy_mux_ops' was not declared. Should it be static? Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * | ARM: mach-imx: irq-common: Remove imx_irq_set_priority()Fabio Estevam2013-04-011-19/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | imx_irq_set_priority() is not used anywhere, so remove it. This fixes the following sparse warnings: arch/arm/mach-imx/irq-common.c:24:5: warning: symbol 'imx_irq_set_priority' was not declared. Should it be static? Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * | ARM: mach-imx: clk-gate2: Include "clk.h"Fabio Estevam2013-04-011-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the following sparse warning: arch/arm/mach-imx/clk-gate2.c:86:12: warning: symbol 'clk_register_gate2' was not declared. Should it be static? Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * | ARM: mach-imx: clk-pllv2: Staticize clk_pllv2_opsFabio Estevam2013-04-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the following sparse warning: rch/arm/mach-imx/clk-pllv2.c:232:16: warning: symbol 'clk_pllv2_ops' was not declared. Should it be static? Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * | ARM: mach-imx: clk-pllv1: Staticize clk_pllv1_opsFabio Estevam2013-04-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the following sparse warning: arch/arm/mach-imx/clk-pllv1.c:81:16: warning: symbol 'clk_pllv1_ops' was not declared. Should it be static? Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * | ARM: mach-imx: cpu-imx5: Include "common.h"Fabio Estevam2013-04-011-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the following sparse warnings: arch/arm/mach-imx/cpu-imx5.c:65:12: warning: symbol 'mx51_neon_fixup' was not declared. Should it be static? arch/arm/mach-imx/cpu-imx5.c:99:5: warning: symbol 'mx53_revision' was not declared. Should it be static? Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * | ARM: mach-imx: iomux-imx31: Staticize mxc_pin_alloc_mapFabio Estevam2013-04-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the following sparse warning: arch/arm/mach-imx/iomux-imx31.c:43:15: warning: symbol 'mxc_pin_alloc_map' was not declared. Should it be static? Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * | ARM: mach-imx: mm-imx3: Staticize imx3_init_l2x0()Fabio Estevam2013-04-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the following sparse warning: arch/arm/mach-imx/mm-imx3.c:85:13: warning: symbol 'imx3_init_l2x0' was not declared. Should it be static? Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * | ARM: mach-imx: cpu: Include "common.h"Fabio Estevam2013-04-011-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the following sparse warnings: arch/arm/mach-imx/cpu.c:10:6: warning: symbol 'mxc_set_cpu_type' was not declared. Should it be static? arch/arm/mach-imx/cpu.c:15:6: warning: symbol 'imx_print_silicon_rev' was not declared. Should it be static? arch/arm/mach-imx/cpu.c:24:13: warning: symbol 'imx_set_aips' was not declared. Should it be static? Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | | ARM: vexpress: Remove A9 PMU compatible values for non-A9 platformsPawel Moll2013-04-113-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ARM perf core code used to rely on the pmu node being compatible with "arm,cortex-a9-pmu", even when the PMUs of the different Cortex-A processors are not really compatible... This is no longer required and actually became harmful, so remove all the offending values from Versatile Express DTS files. Signed-off-by: Pawel Moll <pawel.moll@arm.com> Signed-off-by: Olof Johansson <olof@lixom.net>
| * | | Merge tag 'tegra-for-3.10-fixes' of ↵Arnd Bergmann2013-04-0919-82/+67
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/fixes-non-critical From Stephen Warren <swarren@wwwdotorg.org>: ARM: tegra: minor fixes This branch contains a variety of small build and run-time fixes that weren't important enough for 3.9. * Enable CPU errata WARs in secondary reset handler as a preparation for multi-platform support, and a related fix. * Don't touch DBLGAR in reset/resume handlers, so enable the code to run on A15 cores. * Minor build fixes. * A fix to the Tegra clock driver. * Some error-handling fixes. This branch is based on the previous fixes-for-mmc pull request. * tag 'tegra-for-3.10-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: ARM: tegra: powergate: Don't error out if new state == old state ARM: tegra: Export tegra_powergate_sequence_power_up() memory: tegra30: Fix build error w/o PM ARM: tegra: fix ignored return value of regulator_enable ARM: tegra: fix the logical detection of power on sequence of warm boot CPUs ARM: tegra: Fix unchecked return value ARM: tegra: don't unlock MMIO access to DBGLAR clk: tegra: No 7.1 super clk dividers on Tegra20 ARM: tegra: remove save/restore of CPU diag register ARM: tegra: add CPU errata WARs to Tegra reset handler ARM: dts: tegra: fix the activate polarity of cd-gpio in mmc host Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| | * | | ARM: tegra: powergate: Don't error out if new state == old stateThierry Reding2013-03-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Don't treat it as an error if a partition is already in the same power state when a user wants to power it on or off. This allows code to proceed if no state change is required. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| | * | | ARM: tegra: Export tegra_powergate_sequence_power_up()Thierry Reding2013-03-291-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This function can be used by drivers to enable power to the hardware blocks that they drive. Most of the drivers can be built as a module and therefore require this function to be exported. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| | * | | memory: tegra30: Fix build error w/o PMHiroshi Doyu2013-03-151-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make this depend on CONFIG_PM. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Reviewed-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| | * | | ARM: tegra: fix ignored return value of regulator_enableStephen Warren2013-03-111-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes: arch/arm/mach-tegra/board-harmony-pcie.c: In function ‘harmony_pcie_init’: arch/arm/mach-tegra/board-harmony-pcie.c:65:18: warning: ignoring return value of ‘regulator_enable’, declared with attribute warn_unused_result [-Wunused-result] Signed-off-by: Stephen Warren <swarren@nvidia.com>
| | * | | ARM: tegra: fix the logical detection of power on sequence of warm boot CPUsJoseph Lo2013-03-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The warm boot sequence of Tegra30 secondary CPUs should wait for the power ready then removing the clamps. This did not fix any known or unknown issue, but nice to have this fix. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| | * | | ARM: tegra: Fix unchecked return valueHiroshi Doyu2013-03-111-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Check a return value for tegra_powergate_remove_clamping(). Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| | * | | ARM: tegra: don't unlock MMIO access to DBGLARJoseph Lo2013-03-112-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no need to unlock MMIO access to the DBGLAR all the time. Doing so may even cause problems if a SW bug causes writes to that MMIO region. Cortex-A15 processors do not support the CP14 register write the code currently uses to unlock the DBGLAR; the instruction throws an undefined instruction exceptions. This prevents tegra_secondary_startup() from executing on Tegra114, and hence prevents SMP. Remove the code that unlocks this access. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| | * | | clk: tegra: No 7.1 super clk dividers on Tegra20Peter De Schrijver2013-03-111-34/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unlike Tegra30, Tegra20 does not have a 7.1 divider for the CPU superclk. Remove the clocks related to the divider. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| | * | | ARM: tegra: remove save/restore of CPU diag registerStephen Warren2013-03-112-23/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Prior to this change, {save,restore}_cpu_arch_register() collaborated to maintain the value of the CPU diagnostic register across power cycles. This was required to maintain any CPU errata workaround enable bits in that register. However, now that the Tegra reset vector code always enables all required workarounds, there is no need to save and restore the diagnostic register; it is always explicitly programmed in the required manner. Hence, remove the save/restore logic. This has the advantage that the kernel always directly controls the value of this register every boot, rather than relying on a bootloader or other kernel code having previously written the correct value into it. This makes CPU0 (which was previously saved/restored) and CPUn (which should have been set up by the reset vector) be controlled in exactly the same way, which is easier to debug/find/... In particular, when converting Tegra to a multi-platform kernel, the CPU0 diagnostic register value initially comes from the bootloader. Most Tegra bootloaders don't yet enable all required CPU bug workarounds. The previous commit updates the kernel to do so on any CPU power cycle. However, the save/restore code ends up over-writing the value with the old bootloader-driven value instead of the now more-likely-to-be-correct kernel value! Even irrespective of multi-platform conversion, this change limits the kernel's exposure to any WARs the bootloader didn't enable for CPU0: on the very first LP2 transition (CPU power-saving which power-cycles the CPU), the correct value will be enabled. Signed-off-by: Stephen Warren <swarren@nvidia.com>
| | * | | ARM: tegra: add CPU errata WARs to Tegra reset handlerStephen Warren2013-03-111-6/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CPU cores in Tegra contain some errata. Workarounds must be applied for these every time a CPU boots. Implement those workarounds directly in the Tegra-specific CPU reset vector. Many of these workarounds duplicate code in the core ARM kernel. However, the core ARM kernel cannot enable those workarounds when building a multi-platform kernel, since they require writing to secure- only registers, and a multi-platform kernel often does not run in secure mode, and also cannot generically/architecturally detect whether it is running in secure mode, and hence cannot either unconditionally or conditionally apply these workarounds. Instead, the workarounds must be applied in architecture-specific reset code, which is able to have more direct knowledge of the secure/normal state. On Tegra, we will be able to detect this using a non-architected register in the future, although we currently assume the kernel runs only in secure mode. Other SoCs may never run the kernel in secure mode, and hence always rely on a secure monitor to enable the workarounds, and hence never implement them in the kernel. Signed-off-by: Stephen Warren <swarren@nvidia.com>
| | * | | ARM: dts: tegra: fix the activate polarity of cd-gpio in mmc hostJoseph Lo2013-03-1110-10/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GPIO pin of SD slot card detection should active low. Signed-off-by: Joseph Lo <josephl@nvidia.com> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | Merge tag 'omap-for-v3.10/fixes-non-critical-signed' of ↵Arnd Bergmann2013-04-08888-4815/+8893
| |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/fixes-non-critical From Tony Lindgren <tony@atomide.com>: Non critical omap fixes for v3.10 merge window. A big chunk of these fixes are needed to support omap5 es2 version that includes PM features while the earlier version es1 did not. * tag 'omap-for-v3.10/fixes-non-critical-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: OMAP2+: fix typo "CONFIG_BRIDGE_DVFS" ARM: OMAP1: remove "config MACH_OMAP_HTCWIZARD" ARM: OMAP: dpll: enable bypass clock only when attempting dpll bypass ARM: OMAP2+: powerdomain: avoid testing whether an unsigned char is less than 0 ARM: OMAP2+: hwmod: Remove unused _HWMOD_WAKEUP_ENABLED flag ARM: OMAP2+: am335x: Change the wdt1 func clk src to per_32k clk ARM: OMAP2+: AM33xx: hwmod: Add missing sysc definition to wdt1 entry Contains an update to 3.9-rc5 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| | * \ \ \ Merge branch 'for_3.10/omap5_generic_updates' of ↵Tony Lindgren2013-04-0110-24/+48
| | |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux into omap-for-v3.10/fixes-non-critical
| | | * | | | ARM: OMAP5: clock: No Freqsel on OMAP5 devices tooRajendra Nayak2013-03-191-6/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OMAP5 does not have freqsel either, so checks needs to be extended. Infact only OMAP343X devices has the freqsel support, so fix the check accordingly so that future patching can be avoided. Reported-by: Archit Taneja <archit@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
| | | * | | | ARM: OMAP5: Make errata i688 workaround availableSantosh Shilimkar2013-03-192-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Errata i688 is also applicable for OMAP5 based devices. Update the code so that it can be enabled on OMAP5 devices. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
| | | * | | | ARM: OMAP5: Update SAR memory layout for WakeupGenSantosh Shilimkar2013-03-191-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On OMAP5 es2 WakeupGen SAR register layout offset have changed. Update the layout accordingly. Reported-by: Menon, Nishanth <nm@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
| | | * | | | ARM: OMAP5: Update SAR RAM base addressSantosh Shilimkar2013-03-192-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update SAR RAM base address for OMAP5 based devices. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
| | | * | | | ARM: OMAP5: Reuse prm read_inst/write_instTero Kristo2013-03-191-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make use of 'prm_base' so that prm read_inst/write_inst can work on OMAP5 devices. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
| | | * | | | ARM: OMAP5: prm: Allow prm init to succeedSantosh Shilimkar2013-03-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow prm init to succeed on OMAP5 SOCs. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
| | | * | | | ARM: OMAP5: timer: Update the clocksource name as per clock dataSantosh Shilimkar2013-03-191-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OMAP5 clockdata has different sys clock node name. Fix the timer code to take care of it. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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