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* MIPS: Netlogic: Add irq mapping and setup for XHCI port 3Ganesan Ramalingam2015-04-013-1/+12
| | | | | | | | | | Add support for third XHCI port in XLPII processors. Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8895/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Netlogic: Do not enable SUE for coreJayachandran C2015-04-011-1/+1
| | | | | | | | | | | Enabling the SUE bit for core can can result in rare cache errors which are difficult to track down, so do not enable it. This can cause a minor performance loss in some tests. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8894/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Netlogic: Handle XLP hardware errataJayachandran C2015-04-012-0/+22
| | | | | | | | | | Core configuration register IFU_BRUB_RESERVE has to be setup to handle a silicon errata which can result in a CPU hang. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8902/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Netlogic: Update function to read DRAM BARsJayachandran C2015-04-013-7/+9
| | | | | | | | | | | | Change name of xlp_get_dram_map to nlm_get_dram_map to be consistent with the rest of the functions in the file. Pass the the size of the array 'dram_map' to the function, and ensure that it does not write past the end of the array. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8892/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Netlogic: Added HugeTLB as defaultPrem Mallappa2015-04-011-0/+1
| | | | | | | | | | Enable CPU_SUPPORTS_HUGEPAGES for XLP processors. Signed-off-by: Prem Mallappa <pmallapp@broadcom.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8891/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Netlogic: nlm_core_id for xlp9xxJayachandran C2015-04-011-1/+7
| | | | | | | | | | XLP9XX has 5 bits that specify the core in the EBASE register. XLP5XX case added as well for completeness. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8890/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Netlogic: Move cores per node out of multi-node.hJayachandran C2015-04-016-36/+43
| | | | | | | | | | | | Use the current_cpu_data package field to get the node of the current CPU. This allows us to remove xlp_cores_per_node and move nlm_threads_per_node() and nlm_cores_per_node() to netlogic/common.h, which simplifies code. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8889/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Netlogic: Use MIPS topology.hJayachandran C2015-04-012-15/+1
| | | | | | | | | | | | | | | commit bda4584cd943 ("MIPS: Support CPU topology files in sysfs") added topology related macros for all MIPS platforms and commit bbbf6d8768f5 ("MIPS: NL: Fix nlm_xlp_defconfig build error") removed most of the contents from mach-netlogic/topology.h. The netlogic specific topology is not needed anymore, we just need to setup the package field in current_cpu_data. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8888/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: MSI: Update MSI handling for XLPJayachandran C2015-04-011-9/+10
| | | | | | | | | | | | | The per-cpu interrupt ACK using EIRR has to be done just once after all the bits in the status register are processed. PIC ack has to be done once in case of MSI, and for every interrupt in case of MSI-X Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8887/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Netlogic: Fix frequency calculation registerGanesan Ramalingam2015-04-012-4/+7
| | | | | | | | | | | | | Change the PIC frequency calculation to use the register that has the current configuration. The existing code used the register that is written to change frequency, which can have an invalid value if the firmware did not set it up correctly. Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8885/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Netlogic: Disable writing IRT for disabled blocksJayachandran C2015-04-011-9/+16
| | | | | | | | | | If the device header of a block is not present, return invalid IRT value so that we do not program an incorrect offset. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8882/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Netlogic: Fix cop0 prid check in AHCI initGanesan Ramalingam2015-04-011-1/+1
| | | | | | | | | | PRID register should be masked with IMP_MASK to get processor ID. Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8883/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Netlogic: Fix nlm_xlp2_get_pic_frequency to use ref_divQingmin Liu2015-04-011-1/+1
| | | | | | | | | | | | The variable ref_div is initialized to the correct divisor but not used in the frequency calculation. This caused incorrect frequency to be reported when the clock divisor is not 3. Signed-off-by: Qingmin Liu <qingmin@broadcom.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8884/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Netlogic: Fix wait for slave CPUsShanghui Liu2015-04-011-1/+1
| | | | | | | | | | | | For core 0, the condition of "cpu == bootcpu" is always true, so it does not wait for other three threads to become ready. Fix this by using correct check. Signed-off-by: Shanghui Liu <shliu@broadcom.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8881/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: LLVMLinux: Silence variable self-assignment warnings.Toma Tabacu2015-04-014-20/+0
| | | | | | | | | | | | | | Remove variable self-assignments. This silences a bunch of -Wself-assign warnings reported by clang. The changed code can be compiled without warnings by both gcc and clang. Signed-off-by: Toma Tabacu <toma.tabacu@imgtec.com> Signed-off-by: Daniel Sanders <daniel.sanders@imgtec.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9314/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: LLVMLinux: Fix an 'inline asm input/output type mismatch' error.Daniel Sanders2015-04-011-2/+4
| | | | | | | | | | | | | | | | | | | | | | | Replace incorrect matching constraint that caused the error with an alternative that still has the required constraints on the inline assembly. This is the error message reported by clang: arch/mips/include/asm/checksum.h:285:27: error: unsupported inline asm: input with type '__be32' (aka 'unsigned int') matching output with type 'unsigned short' "0" (htonl(len)), "1" (htonl(proto)), "r" (sum)); ^~~~~~~~~~~~ The changed code can be compiled successfully by both gcc and clang. Signed-off-by: Daniel Sanders <daniel.sanders@imgtec.com> Signed-off-by: Toma Tabacu <toma.tabacu@imgtec.com> Suggested-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9313/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: LLVMLinux: Fix a 'cast to type not present in union' error.Toma Tabacu2015-04-011-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | Remove a cast to the 'mips16e_instruction' union inside an if condition and instead do an assignment to a local 'union mips16e_instruction' variable's 'full' member before the if statement and use this variable in the if condition. This is the error message reported by clang: arch/mips/kernel/branch.c:38:8: error: cast to union type from type 'unsigned short' not present in union if (((union mips16e_instruction)inst).ri.opcode ^ ~~~~ The changed code can be compiled successfully by both gcc and clang. Signed-off-by: Toma Tabacu <toma.tabacu@imgtec.com> Signed-off-by: Daniel Sanders <daniel.sanders@imgtec.com> Cc: Andreas Herrmann <andreas.herrmann@caviumnetworks.com> Cc: David Daney <david.daney@cavium.com> Cc: Manuel Lauss <manuel.lauss@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9312/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Changed current_thread_info() to an equivalent supported by both clang ↵Daniel Sanders2015-04-011-2/+2
| | | | | | | | | | | | | | | | | | | | | | | and GCC Without this, a 'break' instruction is executed very early in the boot and the boot hangs. The problem is that clang doesn't honour named registers on local variables and silently treats them as normal uninitialized variables. However, it does honour them on global variables. Signed-off-by: Daniel Sanders <daniel.sanders@imgtec.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Cc: David Daney <ddaney.cavm@gmail.com> Acked-by: Behan Webster <behanw@converseincode.com> Patchwork: https://patchwork.linux-mips.org/patch/9311/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: XPA: Add new configuration file.Steven J. Hill2015-04-011-0/+439
| | | | | | | | | Add in new config files for enabling a XPA platform. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9354/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: OCTEON: Use correct CSR to soft resetChandrakala Chavva2015-04-011-1/+4
| | | | | | | | | | | | | | | This fixes reboot for Octeon III boards [ralf@linux-mips.org: Dropped segment for function cvmx_reset_octeon() which was removed by the preceeding commit.] Signed-off-by: Chandrakala Chavva <cchavva@caviumnetworks.com> Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com> Cc: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9464/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Remove unused function cvmx_reset_octeon().Ralf Baechle2015-04-011-8/+0
| | | | | | As suggested by David Daney. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: OCTEON: Use device tree to probe for flash chips.David Daney2015-04-011-5/+37
| | | | | | | | | | | | Don't assume they are there, the device tree will tell us. Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com> Tested-by: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9461/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: OCTEON: Protect accesses to bootbus flash with octeon_bootbus_sem.David Daney2015-04-012-1/+42
| | | | | | | | | | | Without this, we get bus errors. Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9460/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: OCTEON: Add semaphore to serialize bootbus accesses.David Daney2015-04-012-0/+5
| | | | | | | | | | | | | | | | | | | | | Some hardware blocks attached to the OCTEON bootbus run asynchronously to accesses from the CPUs. These include MMC/SD host, CF(when using DMA), and NAND controller. A bus error, or corrupt data may occur if a CPU is trying to access a bootbus connected device at the same time the bus is running asynchronous operations. To work around these problems we add this semaphore that must be acquired before initiating bootbus activity. Subsequent patches will add users for this. Signed-off-by: David Daney <david.daney@cavium.com> [aleksey.makarov@auriga.com: combine the patches] Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com> Signed-off-by: Chandrakala Chavva <cchavva@caviumnetworks.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9459/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BMIPS: Add DTS files for several platformsKevin Cernekee2015-04-0123-1/+1992
| | | | | | | | | | | | | | | | | | | | | | Most of the supported chips use legacy (non-DT) bootloaders, so they will need to select an appropriate builtin DTB at compile time until the bootloader is updated. Provide suitable DTS files, and a means to compile one of them into the kernel image. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com> Cc: f.fainelli@gmail.com Cc: abrestic@chromium.org Cc: tglx@linutronix.de Cc: jason@lakedaemon.net Cc: jogo@openwrt.org Cc: arnd@arndb.de Cc: computersforpeace@gmail.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8858/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BMIPS: Update DT bindings to reflect new SoC supportKevin Cernekee2015-04-012-11/+12
| | | | | | | | | | | | | | | | | | | Add an entry for each supported Broadcom SoC. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com> Cc: f.fainelli@gmail.com Cc: abrestic@chromium.org Cc: tglx@linutronix.de Cc: jason@lakedaemon.net Cc: jogo@openwrt.org Cc: arnd@arndb.de Cc: computersforpeace@gmail.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8857/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BMIPS: Refresh BCM3384 DTS filesKevin Cernekee2015-04-013-117/+127
| | | | | | | | | | | | | | | | | | | | | The DT bindings for this platform have changed as the bootloader and product requirements evolved. In particular, there are both Linux-on-Zephyr and Linux-on-Viper configurations. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: jaedon.shin@gmail.com Cc: abrestic@chromium.org Cc: tglx@linutronix.de Cc: jason@lakedaemon.net Cc: jogo@openwrt.org Cc: arnd@arndb.de Cc: computersforpeace@gmail.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8856/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BMIPS: Enable additional peripheral and CPU support in defconfigKevin Cernekee2015-04-013-6/+109
| | | | | | | | | | | | | | | | | | | | Also, add an LE defconfig for set-top box (BCM7xxx). This will allow the BMIPS kernel to run on several non-BCM3384 platforms. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com> Cc: f.fainelli@gmail.com Cc: abrestic@chromium.org Cc: tglx@linutronix.de Cc: jason@lakedaemon.net Cc: jogo@openwrt.org Cc: arnd@arndb.de Cc: computersforpeace@gmail.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8855/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BMIPS: Use a non-default FIXADDR_TOP settingKevin Cernekee2015-04-011-0/+18
| | | | | | | | | | | | | | | | | | | This will be required to support BMIPS3300 platforms. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: jaedon.shin@gmail.com Cc: abrestic@chromium.org Cc: tglx@linutronix.de Cc: jason@lakedaemon.net Cc: jogo@openwrt.org Cc: arnd@arndb.de Cc: computersforpeace@gmail.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8854/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BMIPS: Delete the irqchip driver from irq.cKevin Cernekee2015-04-012-209/+17
| | | | | | | | | | | | | | | | | | | | | | | BCM3384/BCM63xx can use the common drivers/irqchip/irq-bcm7120-l2.c for this purpose; BCM7xxx will use drivers/irqchip/irq-bcm7038-l1.c. We no longer need this code under arch/mips. [ralf@linux-mips.org: Fix conflicts.] Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: jaedon.shin@gmail.com Cc: abrestic@chromium.org Cc: tglx@linutronix.de Cc: jason@lakedaemon.net Cc: jogo@openwrt.org Cc: arnd@arndb.de Cc: computersforpeace@gmail.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8853/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BMIPS: Add quirks for several Broadcom platformsKevin Cernekee2015-04-011-2/+99
| | | | | | | | | | | | | | | | | | | | | A couple of chips require special handling in order to make SMP secondary boot and/or exception vectors work correctly. Take care of these in setup.c. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: jaedon.shin@gmail.com Cc: abrestic@chromium.org Cc: tglx@linutronix.de Cc: jason@lakedaemon.net Cc: jogo@openwrt.org Cc: arnd@arndb.de Cc: computersforpeace@gmail.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8852/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BMIPS: Remove bogus bus nameKevin Cernekee2015-04-011-1/+1
| | | | | | | | | | | | | | | | | | | There is no "bcm3384" bus so let's just remove it to avoid confusion. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: jaedon.shin@gmail.com Cc: abrestic@chromium.org Cc: tglx@linutronix.de Cc: jason@lakedaemon.net Cc: jogo@openwrt.org Cc: arnd@arndb.de Cc: computersforpeace@gmail.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8851/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BMIPS: Rewrite DMA code to use "dma-ranges" propertyKevin Cernekee2015-04-011-32/+68
| | | | | | | | | | | | | | | | | | | | This is a more standardized way of handling DMA remapping, and it is suitable for the memory map found on BCM3384. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: jaedon.shin@gmail.com Cc: abrestic@chromium.org Cc: tglx@linutronix.de Cc: jason@lakedaemon.net Cc: jogo@openwrt.org Cc: arnd@arndb.de Cc: computersforpeace@gmail.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8850/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BMIPS: Document the firmware->kernel DTB interfaceKevin Cernekee2015-04-011-0/+28
| | | | | | | | | | | | | | | | | | | Add a new section covering the Generic BMIPS machine type. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: jaedon.shin@gmail.com Cc: abrestic@chromium.org Cc: tglx@linutronix.de Cc: jason@lakedaemon.net Cc: jogo@openwrt.org Cc: arnd@arndb.de Cc: computersforpeace@gmail.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8849/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Reorder MIPS_L1_CACHE_SHIFT prioritiesKevin Cernekee2015-04-011-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enabling support for more than one BMIPS CPU in the same build may result in different L1_CACHE_SHIFT values, e.g. CPU_BMIPS5000 selects MIPS_L1_CACHE_SHIFT_7 CPU_BMIPS4380 selects MIPS_L1_CACHE_SHIFT_6 anything else defaults to MIPS_L1_CACHE_SHIFT_5 Ensure that if more than one MIPS_L1_CACHE_SHIFT_x option is selected, Kconfig sets CONFIG_MIPS_L1_CACHE_SHIFT to the highest value. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: jaedon.shin@gmail.com Cc: abrestic@chromium.org Cc: tglx@linutronix.de Cc: jason@lakedaemon.net Cc: jogo@openwrt.org Cc: arnd@arndb.de Cc: computersforpeace@gmail.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8847/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Let __dt_register_buses accept a single bus typeKevin Cernekee2015-04-011-1/+4
| | | | | | | | | | | | | | | | | | | Some machines only have one bus type to register (e.g. "simple-bus"). Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: jaedon.shin@gmail.com Cc: abrestic@chromium.org Cc: tglx@linutronix.de Cc: jason@lakedaemon.net Cc: jogo@openwrt.org Cc: arnd@arndb.de Cc: computersforpeace@gmail.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8845/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* IRQCHIP: Add new driver for BCM7038-style level 1 interrupt controllersKevin Cernekee2015-04-014-0/+393
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the main peripheral IRQ controller on the BCM7xxx MIPS chips; it has the following characteristics: - 64 to 160+ level IRQs - Atomic set/clear registers - Reasonably predictable register layout (N status words, then N mask status words, then N mask set words, then N mask clear words) - SMP affinity supported on most systems - Typically connected to MIPS IRQ 2,3,2,3 on CPUs 0,1,2,3 This driver registers one IRQ domain and one IRQ chip to cover all instances of the block. Up to 4 instances of the block may appear, as it supports 4-way IRQ affinity on BCM7435. The same block exists on the ARM BCM7xxx chips, but typically the ARM GIC is used instead. So this driver is primarily intended for MIPS STB chips. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: jaedon.shin@gmail.com Cc: abrestic@chromium.org Cc: tglx@linutronix.de Cc: jason@lakedaemon.net Cc: jogo@openwrt.org Cc: arnd@arndb.de Cc: computersforpeace@gmail.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8844/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* IRQCHIP: bcm7120-l2: Add support for BCM3380-style controllersKevin Cernekee2015-04-012-4/+92
| | | | | | | | | | | | | | | | | | | | | These controllers support multiple enable/status pairs (64+ IRQs), can put the enable/status words at different offsets, and do not support multiple parent IRQs. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: jaedon.shin@gmail.com Cc: abrestic@chromium.org Cc: tglx@linutronix.de Cc: jason@lakedaemon.net Cc: jogo@openwrt.org Cc: arnd@arndb.de Cc: computersforpeace@gmail.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8843/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* IRQCHIP: bcm7120-l2: Split STB-specific logic into its own functionKevin Cernekee2015-04-012-64/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The BCM7xxx instances of this block (listed in the register manual as simply "IRQ0") all have the following items in common: - brcm,int-map-mask: for routing different bits in the L2 to different parent IRQs - brcm,int-fwd-mask: for hardwiring certain IRQs to bypass the L2 and use dedicated L1 lines - one enable/status pair (32 bits only) Much of the driver code can be shared with BCM3380-style controllers, but in order to do this cleanly, let's split out the BCM7xxx-specific logic first. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: jaedon.shin@gmail.com Cc: abrestic@chromium.org Cc: tglx@linutronix.de Cc: jason@lakedaemon.net Cc: jogo@openwrt.org Cc: arnd@arndb.de Cc: computersforpeace@gmail.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8842/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* IRQCHIP: bcm7120-l2: Refactor driver for arbitrary IRQEN/IRQSTAT offsetsKevin Cernekee2015-04-011-13/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the driver assumes that REG_BASE+0x00 is the IRQ enable mask, and REG_BASE+0x04 is the IRQ status mask. This is true on BCM3384 and BCM7xxx, but it is not true for some of the controllers found on BCM63xx chips. So we will change a couple of key assumptions: - Don't assume that both the IRQEN and IRQSTAT registers will be covered by a single ioremap() operation. - Don't assume any particular ordering (IRQSTAT might show up before IRQEN on some chips). - For an L2 controller with >=64 IRQs, don't assume that every IRQEN/IRQSTAT pair will use the same register spacing. This patch changes the "plumbing" but doesn't yet provide a way for users to instantiate a controller with arbitrary IRQEN/IRQSTAT offsets. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: jaedon.shin@gmail.com Cc: abrestic@chromium.org Cc: tglx@linutronix.de Cc: jason@lakedaemon.net Cc: jogo@openwrt.org Cc: computersforpeace@gmail.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8841/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* IRQCHIP: brcmstb-l2: don't clear wakeable interrupts at init timeBrian Norris2015-04-011-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Wakeable interrupts might be pending at boot/init time, because wakeup interrupts might have triggered a resume from S5. So don't clear such wakeups. This means that any driver which requests a wakeable interrupt bit should be prepared to handle an interrupt as soon as they call request_irq(). (This is technically already the correct development practice, but some drivers probably expect not to receive interrupts until they have performed some I/O.) Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: jaedon.shin@gmail.com Cc: abrestic@chromium.org Cc: tglx@linutronix.de Cc: jason@lakedaemon.net Cc: jogo@openwrt.org Cc: arnd@arndb.de Cc: computersforpeace@gmail.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8840/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* IRQCHIP: Update docs regarding irq_domain_add_tree()Kevin Cernekee2015-04-011-2/+1
| | | | | | | | | | | | | | | | | | | Several drivers now use this API, including the ARM GIC driver, so remove the outdated comment. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: jaedon.shin@gmail.com Cc: abrestic@chromium.org Cc: tglx@linutronix.de Cc: jason@lakedaemon.net Cc: jogo@openwrt.org Cc: computersforpeace@gmail.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8839/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: bcm3384: Rename "bcm3384" target to "bmips"Kevin Cernekee2015-04-0111-20/+20
| | | | | | | | | | | | | | | | | | | | | | This platform is configured primarily through device tree, and we can reuse the same code to support a bunch of other chips. Change the name to reflect this. [ralf@linux-mips.org: Fix conflicts with other patches.] Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: jaedon.shin@gmail.com Cc: abrestic@chromium.org Cc: tglx@linutronix.de Cc: jason@lakedaemon.net Cc: jogo@openwrt.org Cc: computersforpeace@gmail.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8838/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add dtbs_install targetAndrew Bresticker2015-04-011-0/+5
| | | | | | | | | | | | | | | | | | | | Add the dtbs_install Makefile target to install the dtb files into $INSTALL_DTBS_PATH. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Tested-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: jaedon.shin@gmail.com Cc: tglx@linutronix.de Cc: jason@lakedaemon.net Cc: jogo@openwrt.org Cc: arnd@arndb.de Cc: computersforpeace@gmail.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8836/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Move device-trees into vendor sub-directoriesAndrew Bresticker2015-04-0127-22/+73
| | | | | | | | | | | | | | | | | | | Move the MIPS device-trees into the appropriate vendor sub-directories. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Tested-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: jaedon.shin@gmail.com Cc: tglx@linutronix.de Cc: jason@lakedaemon.net Cc: jogo@openwrt.org Cc: arnd@arndb.de Cc: computersforpeace@gmail.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8835/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add support for fine granularity task level IRQ time accountingDeng-Cheng Zhu2015-04-011-0/+1
| | | | | | | | | | | | With sched_clock being ready, it makes sense to add the option of IRQ time accounting -- When we have a fast enough sched_clock, IRQ time accounting will be enabled (see sched_clock_register). Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Cc: linux-mips@linux-mips.org Cc: macro@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9489/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: csrc-sb1250: Implement read_sched_clockDeng-Cheng Zhu2015-04-011-0/+8
| | | | | | | | | | | Use sb1250 hpt for sched_clock source. This implementation will give high resolution cputime accounting. Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Cc: linux-mips@linux-mips.org Cc: macro@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9488/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: csrc-sb1250: Remove FSF mail address from GPL noticeDeng-Cheng Zhu2015-04-011-4/+0
| | | | | | | | | | | | | | | | This is to make checkpatch.pl happy for the next patch. It would otherwise say -- ERROR: Do not include the paragraph about writing to the Free Software Foundation's mailing address from the sample GPL notice. The FSF has changed addresses in the past, and may do so again. Linux already includes a copy of the GPL. Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Cc: linux-mips@linux-mips.org Cc: macro@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9487/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: csrc-sb1250: Extract hpt cycle acquisition from sb1250_hpt_readDeng-Cheng Zhu2015-04-011-2/+9
| | | | | | | | | | | This is to prepare for the upcoming read_sched_clock implementation, which will also need to get cycles from the high precision timer. Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Cc: linux-mips@linux-mips.org Cc: macro@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9486/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: jz4740: Implement read_sched_clockDeng-Cheng Zhu2015-04-011-0/+8
| | | | | | | | | | | Use jz4740 timer counter for sched_clock source. This implementation will give high resolution cputime accounting. Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Cc: linux-mips@linux-mips.org Cc: macro@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9485/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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