| Commit message (Collapse) | Author | Age | Files | Lines |
|---|
| |
|
|
|
|
|
|
|
|
|
| |
CPUs can be in either the legacy 29-bit or 32-bit physical addressing
modes. This follows the x86 approach of tracking the phys bits in cpuinfo
and exposing it to userspace through procfs.
This change was requested to permit kexec-tools to detect the physical
addressing mode in order to determine the appropriate address mangling.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
|
| |\
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
* 'for-next' of git://android.git.kernel.org/kernel/tegra:
spi: tegra: fix error setting on timeout
spi: add spi_tegra driver
tegra: harmony: enable PCI Express
tegra: add PCI Express support
tegra: add PCI Express clocks
[ARM] tegra: Add APB DMA support
[ARM] tegra: Add cpufreq support
[ARM] tegra: common: Update common clock init table
[ARM] tegra: clock: Add dvfs support, bug fixes, and cleanups
[ARM] tegra: Add support for reading fuses
[ARM] tegra: gpio: Add suspend and wake support
[ARM] tegra: pinmux: add safe values, move tegra2, add suspend
[ARM] tegra: add suspend and mirror irqs to legacy controller
[ARM] tegra: Add legacy irq support
[ARM] tegra: update iomap
|
| | |
| |
| |
| |
| |
| |
| | |
avoids derefencing an uninitialized pointer
Change-Id: Icf528441ae481e9f6f5ddc0be32c7c217fa49701
Signed-off-by: Erik Gilling <konkers@android.com>
|
| | |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
v2 changes:
from Thierry Reding:
* add "select TEGRA_SYSTEM_DMA" to Kconfig
from Grant Likely:
* add oneline description to header
* inline references to DRIVER_NAME
* inline references to BUSY_TIMEOUT
* open coded bytes_per_word()
* spi_readl/writel -> spi_tegra_readl/writel
* move transfer validation to spi_tegra_transfer
* don't request_mem_region iomem as platform bus does that for us
* __exit -> __devexit
v3 changes:
from Russell King:
* put request_mem_region back int
from Grant Likely:
* remove #undef DEBUG
* add SLINK_ to register bit defines
* remove unused bytes_per_word
* make spi_tegra_readl/writel static linine
* various refactoring for clarity
* mark err if BSY bit is not cleared after 1000 retries
* move spinlock to protect setting of RDY bit
* subsys_initcall -> module_init
v3 changes:
from Grant Likely:
* update spi_tegra to use PTR_ERRless dma API
v4 changes:
from Grant Likely:
* remove empty spi_tegra_cleanup fucntion
* allow device ids of -1
Signed-off-by: Erik Gilling <konkers@android.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Cc: Thierry Reding <thierry.reding@avionic-design.de>
Cc: Russell King <linux@arm.linux.org.uk>
spi: tegra: cleanups from upstream review
Change-Id: Icecf7e64efcb39de072a15234ba1faa4bad40d25
Signed-off-by: Erik Gilling <konkers@android.com>
|
| | |
| |
| |
| |
| |
| |
| | |
Signed-off-by: Mike Rapoport <mike@compulab.co.il>
CC: Olof Johansson <olof@lixom.net>
CC: Gary King <GKing@nvidia.com>
Signed-off-by: Colin Cross <ccross@android.com>
|
| | |
| |
| |
| |
| |
| |
| |
| |
| | |
Change-Id: Ibd0bcd46895eb88952b9db29e1f68572d39aae01
Signed-off-by: Mike Rapoport <mike@compulab.co.il>
Acked-by: Arnd Bergmann <arnd@arndb.de>
CC: Russell King <linux@arm.linux.org.uk>
CC: Gary King <GKing@nvidia.com>
Signed-off-by: Colin Cross <ccross@android.com>
|
| | |
| |
| |
| |
| |
| | |
Signed-off-by: Mike Rapoport <mike@compulab.co.il>
CC: Gary King <GKing@nvidia.com>
Signed-off-by: Colin Cross <ccross@android.com>
|
| | |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
The APB DMA block handles DMA transfers to and from some peripherals
in the Tegra SOC. It reads from sequential addresses on the memory
bus, and writes repeatedly to the same address on the APB bus.
Two transfer modes are supported, oneshot for transferring a known
size to or from a peripheral, and continuous for streaming data.
In continuous mode, a callback occurs when the buffer is half full
to allow the existing data to be handled and a new request queued.x
v2 changes:
dma API no longer uses PTR_ERR
Signed-off-by: Erik Gilling <konkers@android.com>
Signed-off-by: Colin Cross <ccross@android.com>
|
| | |
| |
| |
| |
| |
| |
| |
| |
| | |
Implement cpufreq support for the Tegra SOC. DVFS is handled by the
core virtual cpu clock. The frequencies of the two cores are tied
together, the highest frequency requested by either core determines
the actual frequency.
Signed-off-by: Colin Cross <ccross@android.com>
|
| | |
| |
| |
| |
| |
| | |
Renames clocks in the clock init table to match the datasheet names
Signed-off-by: Colin Cross <ccross@android.com>
|
| | |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
- Add drivers to clock lookup table
- Add new pll_m entries
- Support I2C U16 divider
- Fix rate reporting on 32.768kHz clock
- Call propagate rate only if set_rate succeeds
- Add support for audio_sync clock
- Add 24MHz to PLLA frequency list
- Correct i2s1/2/spdifout mux
- Add suspend support
- Fix enable/disable parent clocks in set_parent
- Add max_rate parameter to all clocks
- DVFS support
- Add virtual cpu clock with dvfs
- Support clk_round_rate
- Fix requesting very high periph frequencies
- Add quirks for PLLU:
PLLU is slightly different from the rest of the PLLs. The
lock enable bit is at bit 22 instead of 18 in the MISC
register, and the post divider field is a single bit with
reversed values from other PLLs.
- Simplify recalculating clock rates
- Fix UART divider flags
- Remove unused clock ops
Signed-off-by: Colin Cross <ccross@android.com>
|
| | |
| |
| |
| |
| |
| |
| |
| | |
The Tegra SOC contains fuses to identify the CPU type and
bin, and a unique id. The CPU info is required to determine
the correct voltages for each cpu and core frequency.
Signed-off-by: Colin Cross <ccross@android.com>
|
| | |
| |
| |
| |
| |
| |
| | |
Includes checkpatch fixes and TEGRA_NR_GPIOS changes from
Mike Rapoport <mike@compulab.co.il>
Signed-off-by: Colin Cross <ccross@android.com>
|
| | |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
- the reset values for some pin groups in the tegra pin mux can result in
functional errors due to conflicting with actively-configured pin groups
muxing from the same controller. this change adds a known safe, non-
conflicting mux for every pin group, which can be used on platforms
where the pin group is not routed to any peripheral
- also add each pin group's I/O voltage rail, to enable platform code to
map from the pin groups used by each interface to the regulators used
for dynamic voltage control
- add routines to individually configure the tristate, pin mux and pull-
ups for a pingroup_config array, so that it is possible to program
individual values at run-time without modifying other values.
this allows driver power-management code to reprogram individual
interfaces into lower power states during idle / suspend, or to
reprogram the pin mux to support multiple physical busses per
internal controller (e.g., sharing a single I2C or SPI controller
across multiple pin groups)
- move chip-specific data like pingroups and drive-pingroups
out of the common code and into chip-specific code
- fix debug output for group with no pullups
- add a TEGRA_MUX_SAFE function. Setting a pingroup to TEGRA_MUX_SAFE
will automatically select a mux setting that is guaranteed not to
conflict with any of the hardware blocks.
Signed-off-by: Gary King <gking@nvidia.com>
|
| | |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
mirror IRQ enable and disable operations on the legacy PPI system
interrupt controller, since the legacy controller is responsible
for responding to wakeup interrupts when the CPU is in LP2 idle mode
save the irq controller state on suspend and restore on resume
Signed-off-by: Gary King <gking@nvidia.com>
|
| | |
| |
| |
| |
| |
| |
| |
| | |
The "legacy irq controller" duplicates the functionality of the GIC,
but remains powered during the cpu suspend and idle modes that power
down the CPU and the GIC.
Signed-off-by: Colin Cross <ccross@android.com>
|
| | |
| |
| |
| |
| |
| |
| |
| | |
Add missing io address map entries from datasheet.
Add the IRAM area to the statically mapped io regions.
Correct the onewire, USB, and statmon addresses
Signed-off-by: Colin Cross <ccross@android.com>
|
| |\ \
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin:
Blackfin: fix inverted anomaly 05000481 logic
Blackfin: drop unused irq_panic()/DEBUG_ICACHE_CHECK
Blackfin: ppi/spi/twi headers: add missing __BFP undef
Blackfin: update defconfigs
Blackfin: bfin_twi.h: start a common TWI header
netdev: bfin_mac: push settings to platform resources
|
| | | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
No one uses these MMRs so we didn't notice when the anomaly handling
logic was inverted.
Reported-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
|
| | | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
This code was useful during early port development when our icache code
wasn't solid, but that ship has sailed long ago, and no code calls this
function anymore (irq_panic). So punt it.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
|
| | | |
| | |
| | |
| | | |
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
|
| | | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
- enable pm for ADI boards
- drop security option as no one uses it
- enable uninitialized mmap for everyone
- disable wireless by default as no one uses it
- disable cfq io sched as noop is fine
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
|
| | | |
| | |
| | |
| | |
| | |
| | | |
Start one place for TWI definitions.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
|
| | | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
Move all the pin settings out of the Kconfig and into the platform
resources (MII vs RMII). This clean up also lets us push out the
phy settings so that board porters may control the layout.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Acked-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
|
| |\ \ \
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
* 'next' of git://git.monstr.eu/linux-2.6-microblaze: (42 commits)
microblaze: Fix build with make 3.82
fbdev/xilinxfb: Microblaze driver support
microblaze: Support C optimized lib functions for little-endian
microblaze: Separate library optimized functions
microblaze: Support timer on AXI lite
microblaze: Add support for little-endian Microblaze
microblaze: KGDB little endian support
microblaze: Add PVR for endians plus detection
net: emaclite: Add support for little-endian platforms
microblaze: trivial: Add comment for AXI pvr
microblaze: pci-common cleanup
microblaze: Support early console on uart16550
microblaze: Do not compile early console support for uartlite if is disabled
microblaze: Setup early console dynamically
microblaze: Rename all uartlite early printk functions
microblaze: remove early printk uarlite console dependency from header
microblaze: Remove additional compatible properties
microblaze: Remove hardcoded asm instraction for PVR loading
microblaze: Use static const char * const where possible
microblaze: Define VMALLOC_START/END
...
|
| | | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
When running make headers_install_all on x86_64 and make 3.82 I hit this:
arch/microblaze/Makefile:80: *** mixed implicit and normal rules. Stop.
make: *** [headers_install_all] Error 2
So split the rules to satisfy make 3.82.
Signed-off-by: Thomas Backlund <tmb@mandriva.org>
Cc: Stable <stable@kernel.org>
Signed-off-by: Michal Simek <monstr@monstr.eu>
|
| | | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
DCR bus is natively used for PowerPC. Microblaze has
no infrastructure for compile DCR that's why is necessary
to exclude it.
Signed-off-by: Michal Simek <monstr@monstr.eu>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
CC: Andrei Konovalov <akonovalov@ru.mvista.com>
CC: "David S. Miller" <davem@davemloft.net>
CC: linux-kernel@vger.kernel.org
|
| | | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
Optimized C library functions can rapidly speedup the kernel.
memset doesn't need to be optimized because there is no difference
in behavior on little/big endian cpu.
Signed-off-by: Michal Simek <monstr@monstr.eu>
|
| | | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
memcpy/memmove/memset
Signed-off-by: Michal Simek <monstr@monstr.eu>
|
| | | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
New microblaze systems uses two buses. One for memories
and flashes and the second for low-speed peripherals
which can run on different CLK. This is the reason
why the kernel is trying to read clock-frequency
directly from node. If there is then the kernel will
work with it. If not then cpu CLK is used.
Signed-off-by: Michal Simek <monstr@monstr.eu>
|
| | | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
Microblaze little-endian toolchain exports __MICROBLAZEEL__
which is used in the kernel to identify little/big endian.
The most of the changes are in loading values from DTB which
is always big endian.
Little endian platforms are based on new AXI bus which has
impact to early uartlite initialization.
Signed-off-by: Michal Simek <monstr@monstr.eu>
|
| | | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
Just need to use little-endian opcode for brki r16, 0x18
Signed-off-by: Michal Simek <monstr@monstr.eu>
CC: Jason Wessel <jason.wessel@windriver.com>
|
| | | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
Upcomming microblaze version will support little-endian.
Signed-off-by: Michal Simek <monstr@monstr.eu>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
|
| | | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
Upcomming Microblaze is little endian that's why is necessary
to fix protocol and length loading.
Signed-off-by: Michal Simek <monstr@monstr.eu>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Acked-by: David S. Miller <davem@davemloft.net>
CC: Eric Dumazet <eric.dumazet@gmail.com>
CC: netdev@vger.kernel.org
CC: linux-kernel@vger.kernel.org
CC: devicetree-discuss@lists.ozlabs.org
|
| | | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
AXI and OPB share some PVR macros.
Signed-off-by: Michal Simek <monstr@monstr.eu>
|
| | | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
Use set_dma_ops and remove now used-once oddly named temp pointer sd.
Signed-off-by: Milton Miller <miltonm@bga.com>
Signed-off-by: Nishanth Aravamudan <nacc@us.ibm.com>
Signed-off-by: Michal Simek <monstr@monstr.eu>
|
| | | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
Early console support reuse setting from U-BOOT that's why
it is not necessary to setup baudrates, etc.
Signed-off-by: Michal Simek <monstr@monstr.eu>
|
| | | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
Kconfig blocks to select any other early console support that's why
this patch has no real impact on current kernel version. But it is done
because of uart16550.
Signed-off-by: Michal Simek <monstr@monstr.eu>
|
| | | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
Just setup pointer early console in run time.
Signed-off-by: Michal Simek <monstr@monstr.eu>
|
| | | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
This is done because of uart16550 early printk support
Signed-off-by: Michal Simek <monstr@monstr.eu>
|
| | | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
This dependency is resolved in menuconfig.
Signed-off-by: Michal Simek <monstr@monstr.eu>
|
| | | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
Device-tree BSP generates longer compatible properties
that's why we can remove extra/old one.
Signed-off-by: Michal Simek <monstr@monstr.eu>
|
| | | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
It comes from past where pvr wasn't supported in msr instruction.
Signed-off-by: Michal Simek <monstr@monstr.eu>
|
| | | | |
| | | |
| | | |
| | | |
| | | | |
Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: Michal Simek <monstr@monstr.eu>
|
| | | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
per cpu changes requires VMALLOC_START/END to be
define even for noMMU systems.
Signed-off-by: Michal Simek <monstr@monstr.eu>
|
| | | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
Several kernel modules requires empty_zero_page and mbc
to be exported.
Signed-off-by: Michal Simek <monstr@monstr.eu>
|
| | | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
Replaced libgcc functions with asm optimized implementation.
Signed-off-by: Michal Simek <monstr@monstr.eu>
|
| | | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
gpiolib returns -ENXIO if struct gpio_chip::to_irq isn't set, so it's
safe to always call.
Based on PPC patch
"powerpc/gpio: support gpio_to_irq()"
78331aded913d76c7ff996a1a0747d54b057460b
Signed-off-by: Michal Simek <monstr@monstr.eu>
|
| | | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
mmiowb is required by any driver.
Signed-off-by: Michal Simek <monstr@monstr.eu>
|
| | | | |
| | | |
| | | |
| | | | |
Signed-off-by: Michal Simek <monstr@monstr.eu>
|
