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* Documentation/pwm: Update supported SoC name for pwm-samsungSachin Kamat2013-11-111-1/+1
| | | | | | | | Updated supported SoC name for pwm-samsung. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
* pwm: samsung: Fix kernel warning while unexporting a channelSachin Kamat2013-11-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | PWM channel data was set to NULL before freeing it. This caused the following kernel warning while unexporting the channel. Set the channel data to NULL after freeing it. [ 70.495000] WARNING: CPU: 0 PID: 1 at drivers/base/devres.c:805 pwm_put+0x48/0x80() [ 70.505000] Modules linked in: [ 70.505000] CPU: 0 PID: 1 Comm: sh Not tainted 3.12.0-rc6-next-20131024-00012-gd4aec04-dirty #58 [ 70.515000] [<c0014ddc>] (unwind_backtrace+0x0/0xf4) from [<c0011784>] (show_stack+0x10/0x14) [ 70.525000] [<c0011784>] (show_stack+0x10/0x14) from [<c03a3cbc>] (dump_stack+0x7c/0xb0) [ 70.530000] [<c03a3cbc>] (dump_stack+0x7c/0xb0) from [<c001de68>] (warn_slowpath_common+0x6c/0x88) [ 70.540000] [<c001de68>] (warn_slowpath_common+0x6c/0x88) from [<c001df20>] (warn_slowpath_null+0x1c/0x24) [ 70.550000] [<c001df20>] (warn_slowpath_null+0x1c/0x24) from [<c01d1af8>] (pwm_put+0x48/0x80) [ 70.560000] [<c01d1af8>] (pwm_put+0x48/0x80) from [<c01d21c8>] (pwm_unexport_store+0x94/0xac) [ 70.565000] [<c01d21c8>] (pwm_unexport_store+0x94/0xac) from [<c010991c>] (sysfs_write_file+0x148/0x1d8) [ 70.575000] [<c010991c>] (sysfs_write_file+0x148/0x1d8) from [<c00b2a80>] (vfs_write+0xb4/0x1a0) [ 70.585000] [<c00b2a80>] (vfs_write+0xb4/0x1a0) from [<c00b3068>] (SyS_write+0x3c/0x78) [ 70.595000] [<c00b3068>] (SyS_write+0x3c/0x78) from [<c000e2e0>] (ret_fast_syscall+0x0/0x30) Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Reviewed-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
* MAINTAINERS: Move PWM subsystem tree to kernel.orgThierry Reding2013-11-011-2/+1
| | | | | | | The PWM subsystem tree is now located on kernel.org. This will hopefully make it more reliably accessible. Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
* Documentation/pwm: Fix trivial typosSachin Kamat2013-10-241-2/+2
| | | | | | | Fixes some trivial typos to improve readability. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
* pwm-backlight: Remove unused variableThierry Reding2013-10-221-1/+1
| | | | | | | | I forgot to remove this during earlier cleanup patches and only checked various builds for errors, not warnings. Reported-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
* pwm_backlight: avoid short blank screen while doing hibernationHuayi Li2013-10-221-2/+8
| | | | | | | | | | | | | | | | | | Use SIMPLE_DEV_PM_OPS macro will initialize the member "freeze" and "thaw" of pwm_backlight_pm_ops as below, .freeze = suspend_fn, .thaw = resume_fn, then during the process of making hibernation snapshot, screen will be blank at the moment of freezing, and then light at the moment of thawing. this is not the right user experience for suspending to disk. so this patch drops freeze and thaw callback, make the LCD is always lighting before the final shutdown. Signed-off-by: Huayi Li <huayi.li@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
* pwm-backlight: Fix brightness adjustmentThierry Reding2013-10-181-12/+18
| | | | | | | | | Split adjustment of the brightness (by changing the PWM duty cycle) from the power on sequence. This fixes an issue where the brightness can no longer be updated once the backlight has been enabled. Reported-by: Marc Dietrich <marvin24@gmx.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
* pwm: add ep93xx PWM supportH Hartley Sweeten2013-10-176-300/+240
| | | | | | | | | | | | | | | Remove the non-standard EP93xx PWM driver in drivers/misc and add a new driver for the PWM controllers on the EP93xx platform based on the PWM framework. These PWM controllers each support 1 PWM channel with programmable duty cycle, frequency, and polarity inversion. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Cc: Ryan Mallon <rmallon@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
* pwm-backlight: Allow for non-increasing brightness levelsMike Dunn2013-10-161-14/+15
| | | | | | | | | | | | | Currently the driver assumes that the values specified in the brightness-levels device tree property increase as they are parsed from left to right. But boards that invert the signal between the PWM output and the backlight will need to specify decreasing brightness-levels. This patch removes the assumption that the last element of the array is the maximum value, and instead searches the array for the maximum value and uses that in the duty cycle calculation. Signed-off-by: Mike Dunn <mikedunn@newsguy.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* pwm-backlight: Add power supply supportThierry Reding2013-10-162-0/+15
| | | | | | | Backlights require a power supply to work properly. This commit adds a regulator to power up and power down the backlight. Signed-off-by: Thierry Reding <treding@nvidia.com>
* pwm-backlight: Use new enable_gpio fieldThierry Reding2013-10-162-7/+55
| | | | | | | | | Make use of the new enable_gpio field and allow it to be set from DT as well. Now that all legacy users of platform data have been converted to initialize this field to an invalid value, it is safe to use the field from the driver. Signed-off-by: Thierry Reding <treding@nvidia.com>
* unicore32: Initialize PWM backlight enable_gpio fieldThierry Reding2013-10-161-0/+1
| | | | | | | The GPIO API defines 0 as being a valid GPIO number, so this field needs to be initialized explicitly. Signed-off-by: Thierry Reding <treding@nvidia.com>
* ARM: shmobile: Initialize PWM backlight enable_gpio fieldThierry Reding2013-10-161-0/+1
| | | | | | | | The GPIO API defines 0 as being a valid GPIO number, so this field needs to be initialized explicitly. Acked-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Thierry Reding <treding@nvidia.com>
* ARM: SAMSUNG: Initialize PWM backlight enable_gpio fieldThierry Reding2013-10-1611-0/+15
| | | | | | | The GPIO API defines 0 as being a valid GPIO number, so this field needs to be initialized explicitly. Signed-off-by: Thierry Reding <treding@nvidia.com>
* ARM: pxa: Initialize PWM backlight enable_gpio fieldThierry Reding2013-10-1617-34/+19
| | | | | | | | | | | The GPIO API defines 0 as being a valid GPIO number, so this field needs to be initialized explicitly. A special case is the Palm Tungsten|C board. Since it doesn't use any quirks that would require the existing .init() or .exit() hooks it can simply use the new enable_gpio field. Signed-off-by: Thierry Reding <treding@nvidia.com>
* ARM: OMAP: Initialize PWM backlight enable_gpio fieldThierry Reding2013-10-161-0/+1
| | | | | | | The GPIO API defines 0 as being a valid GPIO number, so this field needs to be initialized explicitly. Signed-off-by: Thierry Reding <treding@nvidia.com>
* pwm-backlight: Add optional enable GPIOThierry Reding2013-10-161-0/+5
| | | | | | | | | | | | | | To support a wider variety of backlight setups, introduce an optional enable GPIO. Legacy users of the platform data already have a means of supporting GPIOs by using the .init(), .exit() and .notify() hooks. DT users however cannot use those, so an alternative method is required. In order to ease the introduction of the optional enable GPIO, make it available in the platform data first, so that existing users can be converted. Once that has happened a second patch will add code to make use of it in the driver. Signed-off-by: Thierry Reding <treding@nvidia.com>
* pwm-backlight: Track enable stateThierry Reding2013-10-161-0/+11
| | | | | | | | | Follow up patches will add support for more complex means of powering the backlight on and off such as using a regulator. To prevent calls to the regulator API from becoming unbalanced, keep track of the enabled state internally. Signed-off-by: Thierry Reding <treding@nvidia.com>
* pwm-backlight: Refactor backlight power on/offThierry Reding2013-10-161-22/+31
| | | | | | | | In preparation for adding an optional regulator and enable GPIO to the driver, split the power on and power off sequences into separate functions to reduce code duplication at the multiple call sites. Signed-off-by: Thierry Reding <treding@nvidia.com>
* pwm-backlight: Improve readabilityThierry Reding2013-10-161-1/+6
| | | | | | | Add more blank lines to increase readability. While at it, remove a trailing blank line at the end of the file. Signed-off-by: Thierry Reding <treding@nvidia.com>
* pwm: don't use devm_pinctrl_get_select_default() in probeWolfram Sang2013-10-152-12/+0
| | | | | | | | | Since commit ab78029 (drivers/pinctrl: grab default handles from device core), we can rely on device core for setting the default pins. Compile tested only. Acked-by: Linus Walleij <linus.walleij@linaro.org> (personally at LCE13) Signed-off-by: Wolfram Sang <wsa@the-dreams.de> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
* pwm: imx: Remove redundant of_match_ptrSachin Kamat2013-10-081-1/+1
| | | | | | | | | The data structure of_match_ptr() protects is always compiled in. Hence of_match_ptr() is not needed. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
* pwm: lpc32xx: Remove redundant of_match_ptrSachin Kamat2013-10-081-1/+1
| | | | | | | | | The data structure of_match_ptr() protects is always compiled in. Hence of_match_ptr() is not needed. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Cc: Alexandre Pereira da Silva <aletes.xgr@gmail.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
* pwm: mxs: Remove redundant of_match_ptrSachin Kamat2013-10-081-1/+1
| | | | | | | | | The data structure of_match_ptr() protects is always compiled in. Hence of_match_ptr() is not needed. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
* pwm: twl: Include linux/of.h headerSachin Kamat2013-10-081-0/+1
| | | | | | | 'of_match_ptr' is defined in linux/of.h. Include it explicitly. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
* pwm: twl-led: Include linux/of.h headerSachin Kamat2013-10-081-0/+1
| | | | | | | 'of_match_ptr' is defined in linux/of.h. Include it explicitly. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
* pwm: samsung: Include linux/of.h headerSachin Kamat2013-10-081-0/+1
| | | | | | | 'of_match_ptr' is defined in linux/of.h. Include it explicitly. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
* pwm: imx: Include linux/of.h headerSachin Kamat2013-10-081-0/+1
| | | | | | | 'of_match_ptr' is defined in linux/of.h. Include it explicitly. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
* pwm: atmel-tcb: fix max time computation for slow clk sourceBoris BREZILLON2013-09-191-1/+1
| | | | | | | | | Use the the tcb counter width to compute the maximum time that can be represented using the slow clock source instead of the static 16 bit width. Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
* pwm: atmel-tcb: add missing clk source configBoris BREZILLON2013-09-191-0/+2
| | | | | | | | | Clock source changes are never applied to the CMR register. This may lead to wrong period/duty cycle configuration. Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
* Linux 3.12-rc1v3.12-rc1Linus Torvalds2013-09-161-3/+3
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* Merge branch 'timers/core' of ↵Linus Torvalds2013-09-168-128/+164
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull timer code update from Thomas Gleixner: - armada SoC clocksource overhaul with a trivial merge conflict - Minor improvements to various SoC clocksource drivers * 'timers/core' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: clocksource: armada-370-xp: Add detailed clock requirements in devicetree binding clocksource: armada-370-xp: Get reference fixed-clock by name clocksource: armada-370-xp: Replace WARN_ON with BUG_ON clocksource: armada-370-xp: Fix device-tree binding clocksource: armada-370-xp: Introduce new compatibles clocksource: armada-370-xp: Use CLOCKSOURCE_OF_DECLARE clocksource: armada-370-xp: Simplify TIMER_CTRL register access clocksource: armada-370-xp: Use BIT() ARM: timer-sp: Set dynamic irq affinity ARM: nomadik: add dynamic irq flag to the timer clocksource: sh_cmt: 32-bit control register support clocksource: em_sti: Convert to devm_* managed helpers
| * clocksource: armada-370-xp: Add detailed clock requirements in devicetree ↵Ezequiel Garcia2013-09-021-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | binding Specifies the required clock inputs for each supported compatible. Armada 370 requires a single clock phandle, and Armada XP requires two clock phandles with clock-names "nbclk" and "fixed". Cc: devicetree@vger.kernel.org Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Jason Cooper <jason@lakedaemon.net> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| * clocksource: armada-370-xp: Get reference fixed-clock by nameEzequiel Garcia2013-09-021-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | The Armada XP timer has two mandatory clock inputs: nbclk and refclk, as specified by the device-tree binding. This commit fixes the clock selection. Instead of hard-coding the clock rate for the 25 MHz reference fixed-clock, obtain the clock by its name. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Jason Cooper <jason@lakedaemon.net> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| * clocksource: armada-370-xp: Replace WARN_ON with BUG_ONEzequiel Garcia2013-09-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | If the clock fails to be obtained and the timer fails to be properly registered, the kernel will freeze real soon. Instead, let's BUG() where the actual problem is located. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Jason Cooper <jason@lakedaemon.net> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| * clocksource: armada-370-xp: Fix device-tree bindingEzequiel Garcia2013-09-021-5/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit fixes the DT binding for the Armada 370/XP SoC timer. The previous "marvell,armada-370-xp-timer" compatible is removed and two new compatible strings are introduced: "marvell,armada-xp-timer" and "marvell,armada-370-timer". The rationale behind this change is that the Armada 370 SoC and the Armada XP SoC timers are not really compatible: * Armada 370 has no 25 MHz fixed timer. * Armada XP cannot work properly without such 25 MHz fixed timer as doing otherwise leads to using a clocksource whose frequency varies when doing cpufreq frequency changes. This commit also removes the "marvell,timer-25Mhz" property, given it's now meaningless. Cc: devicetree@vger.kernel.org Acked-by: Jason Cooper <jason@lakedaemon.net> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
| * clocksource: armada-370-xp: Introduce new compatiblesEzequiel Garcia2013-09-021-15/+39
| | | | | | | | | | | | | | | | | | | | | | | | The Armada XP SoC clocksource driver cannot work without the 25 MHz fixed timer. Therefore it's appropriate to introduce a new compatible string and use it to set the 25 MHz fixed timer. The 'marvell,timer-25MHz' property will be marked as deprecated. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch>
| * clocksource: armada-370-xp: Use CLOCKSOURCE_OF_DECLAREEzequiel Garcia2013-09-023-23/+5
| | | | | | | | | | | | | | | | | | | | This is almost cosmetic: we achieve a bit of consistency with other clocksource drivers by using the CLOCKSOURCE_OF_DECLARE macro for the boilerplate code. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch>
| * clocksource: armada-370-xp: Simplify TIMER_CTRL register accessEzequiel Garcia2013-09-021-39/+30
| | | | | | | | | | | | | | | | | | | | | | | | This commit creates two functions to access the TIMER_CTRL register: one for global one for the per-cpu. This makes the code much more readable. In addition, since the TIMER_CTRL register is also used for watchdog, this is preparation work for future thread-safe improvements. Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
| * clocksource: armada-370-xp: Use BIT()Ezequiel Garcia2013-09-021-6/+6
| | | | | | | | | | | | | | | | | | This is a purely cosmetic commit: we replace hardcoded values that representing bits by BIT(), which is slightly more readable. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch>
| * ARM: timer-sp: Set dynamic irq affinityViresh Kumar2013-08-221-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When a cpu goes to a deep idle state where its local timer is shutdown, it notifies the time frame work to use the broadcast timer instead. Unfortunately, the broadcast device could wake up any CPU, including an idle one which is not concerned by the wake up at all. This implies, in the worst case, an idle CPU will wake up to send an IPI to another idle cpu. This patch fixes this for ARM platforms using timer-sp, by setting CLOCK_EVT_FEAT_DYNIRQ feature. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
| * ARM: nomadik: add dynamic irq flag to the timerDaniel Lezcano2013-08-221-1/+2
| | | | | | | | | | | | | | | | Add the dynamic irq affinity feature to the timer clock device. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Vincent Guittot <vincent.guittot@linaro.org> Acked-by: Rickard Andersson <rickard.andersson@stericsson.com>
| * clocksource: sh_cmt: 32-bit control register supportMagnus Damm2013-08-221-14/+36
| | | | | | | | | | | | | | | | | | | | | | Add support for CMT hardware with 32-bit control and counter registers, as found on r8a73a4 and r8a7790. To use the CMT with 32-bit hardware a second I/O memory resource needs to point out the CMSTR register and it needs to be 32 bit wide. Signed-off-by: Magnus Damm <damm@opensource.se> Reviewed-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * clocksource: em_sti: Convert to devm_* managed helpersLaurent Pinchart2013-08-221-35/+14
| | | | | | | | | | | | | | | | Replace kzalloc, clk_get, ioremap and request_irq by their managed counterparts to simplify error paths. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Daniel Lezcano <daniel.lezcano@linaro.org>
* | Merge branch 'for-next' of git://git.samba.org/sfrench/cifs-2.6Linus Torvalds2013-09-162-36/+21
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull CIFS fixes from Steve French: "Two minor cifs fixes and a minor documentation cleanup for cifs.txt" * 'for-next' of git://git.samba.org/sfrench/cifs-2.6: cifs: update cifs.txt and remove some outdated infos cifs: Avoid calling unlock_page() twice in cifs_readpage() when using fscache cifs: Do not take a reference to the page in cifs_readpage_worker()
| * | cifs: update cifs.txt and remove some outdated infosBjörn Jacke2013-09-131-31/+11
| | | | | | | | | | | | | | | | | | Acked-by: Jeff Layton <jlayton@redhat.com> Signed-off-by: Björn JACKE <bj@sernet.de> Signed-off-by: Steve French <smfrench@gmail.com>
| * | cifs: Avoid calling unlock_page() twice in cifs_readpage() when using fscacheSachin Prabhu2013-09-131-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When reading a single page with cifs_readpage(), we make a call to fscache_read_or_alloc_page() which once done, asynchronously calls the completion function cifs_readpage_from_fscache_complete(). This completion function unlocks the page once it has been populated from cache. The module then attempts to unlock the page a second time in cifs_readpage() which leads to warning messages. In case of a successful call to fscache_read_or_alloc_page() we should skip the second unlock_page() since this will be called by the cifs_readpage_from_fscache_complete() once the page has been populated by fscache. With the modifications to cifs_readpage_worker(), we will need to re-grab the page lock in cifs_write_begin(). The problem was first noticed when testing new fscache patches for cifs. https://bugzilla.redhat.com/show_bug.cgi?id=1005737 Signed-off-by: Sachin Prabhu <sprabhu@redhat.com> Reviewed-by: Jeff Layton <jlayton@redhat.com> Signed-off-by: Steve French <smfrench@gmail.com>
| * | cifs: Do not take a reference to the page in cifs_readpage_worker()Sachin Prabhu2013-09-131-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We do not need to take a reference to the pagecache in cifs_readpage_worker() since the calling function will have already taken one before passing the pointer to the page as an argument to the function. Signed-off-by: Sachin Prabhu <sprabhu@redhat.com> Reviewed-by: Jeff Layton <jlayton@redhat.com> Signed-off-by: Steve French <smfrench@gmail.com>
* | | Merge tag 'upstream-3.12-rc1' of git://git.infradead.org/linux-ubiLinus Torvalds2013-09-162-4/+4
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull UBI fixes from Artem Bityutskiy: "Just a single fastmap fix plus a regression fix" * tag 'upstream-3.12-rc1' of git://git.infradead.org/linux-ubi: UBI: Fix invalidate_fastmap() UBI: Fix PEB leak in wear_leveling_worker()
| * | | UBI: Fix invalidate_fastmap()Richard Weinberger2013-08-201-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Onging tests uncovered that invalidate_fastmap() is broken. It must not call ubi_wl_put_fm_peb() because all PEBs used by the old fastmap have already been put back. Signed-off-by: Richard Weinberger <richard@nod.at> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
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