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* drm/i915: Fix current tiling check for relaxed fencingChris Wilson2010-11-151-8/+14
| | | | | | | | As we may bind an object with the correct alignment, but with an invalid size, it may pass the current checks on whether the object may be reused with a fence. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: fix relaxed tiling for gen <= 3 && !g33Daniel Vetter2010-11-151-3/+40
| | | | | | | | | g33/pineview doesn't have any alignment constrains for unfenced tiled buffers. But older chips have. Fix this. Problem introduced in a00b10c360b35d6431a94cbf130a4e162870d661. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Remove the definitions for Primary Ring BufferChris Wilson2010-11-114-25/+27
| | | | | | | | | | We only ever used the PRB0, neglecting the secondary ring buffers, and now with the advent of multiple engines with separate ring buffers we need to excise the anachronisms from our code (and be explicit about which ring we mean where). This is doubly important in light of the FORCEWAKE required to read ring buffer registers on SandyBridge. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* Revert "drm/i915/ringbuffer: Ignore failure to setup the ring on Sandybridge"Chris Wilson2010-11-111-24/+8
| | | | This reverts commit 629e894173c9de589913cf649deaadec4b0579bd.
* drm/i915/ringbuffer: set FORCE_WAKE bit before reading ring registerZou Nan hai2010-11-114-86/+106
| | | | | | | | | Before reading ring register, set FORCE_WAKE bit to prevent GT core power down to low power state, otherwise we may read stale values. Signed-off-by: Zou Nan hai <nanhai.zou@intel.com> [ickle: added a udelay which seemed to do the trick on my SNB] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Remove the global irq wait queueChris Wilson2010-11-113-9/+3
| | | | | | ... as it has been replaced by per-ring waiters. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Only add the lazy request if we end up waiting for it.Chris Wilson2010-11-102-7/+4
| | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Unconditionally get the fence reg when pinning scanoutChris Wilson2010-11-101-2/+1
| | | | | | | | We use i915_gem_object_get_fence_reg() to do LRU tracking of the fence registers, so stop trying to be too clever when pinning the fb->obj. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Fix unload after failed initialisationChris Wilson2010-11-081-9/+12
| | | | | | | If modeset init failed we attempted to unload the module, before we finished setting it up and so triggered various oopses. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: POSTING_READs are simply flushes and so irrelevant to tracingChris Wilson2010-11-082-5/+7
| | | | | | | | | As we use POSTING_READ to flush the write to the register before proceeding, we do not care what the return value is and similar we do not care for the read to be recorded whilst tracing register read/writes. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: filter out the read/write of GPIO registers from debug tracingYuanhan Liu2010-11-081-12/+13
| | | | | | | | | These registers are written very frequently, are timing sensitive, and not particularly relevant to any debugging, so remove the tracepoints from these. Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Add untraced register read/write interfaceYuanhan Liu2010-11-081-0/+5
| | | | | | | | This will be used later to hide the frequently written registers from debug traces in order to increase the signal-to-noise. Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: trace down all the register write and readYuanhan Liu2010-11-082-8/+76
| | | | | | | | Add two tracepoints at I915_WRITE/READ for tracing down all the register write and read. Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Apply display workaround required according to the B-Spec.Eric Anholt2010-11-082-0/+6
| | | | | | | Not known to fix any current bugs. Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Apply B-spec mandated workaround for read flushes on Ironlake.Eric Anholt2010-11-082-0/+19
| | | | | | | | This is not known to fix any particular bugs we have, but the spec says to do it, and the BIOS hadn't already set it up on my system. Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915/ringbuffer: Ignore failure to setup the ring on SandybridgeChris Wilson2010-11-071-8/+24
| | | | | | | | | The ring buffer registers return 0 whilst idle (for some values of idle) on early Sandybridge hw. Persevere even when all appears hopeless... Fortunately the head auto-reporting prevents most hangs. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=31370 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915/ringbuffer: Be consistent in use of ring->size when initialisingChris Wilson2010-11-071-1/+1
| | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Handle GPU hangs during fault gracefully.Chris Wilson2010-11-071-1/+2
| | | | | | | Instead of killing the process, just return no page found and reschedule the process giving the GPU some time to (hopefully) recover. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: kill mappable/fenceable disdinctionDaniel Vetter2010-11-045-55/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | a00b10c360b35d6431a "Only enforce fence limits inside the GTT" also added a fenceable/mappable disdinction when binding/pinning buffers. This only complicates the code with no pratical gain: - In execbuffer this matters on for g33/pineview, as this is the only chip that needs fences and has an unmappable gtt area. But fences are only possible in the mappable part of the gtt, so need_fence implies need_mappable. And need_mappable is only set independantly with relocations which implies (for sane userspace) that the buffer is untiled. - The overlay code is only really used on i8xx, which doesn't have unmappable gtt. And it doesn't support tiled buffers, currently. - For all other buffers it's a bug to pass in a tiled bo. In short, this disdinction doesn't have any practical gain. I've also reverted mapping the overlay and context pages as possibly unmappable. It's not worth being overtly clever here, all the big gains from unmappable are for execbuf bos. Also add a comment for a clever optimization that confused me while reading the original patch by Chris Wilson. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: revert pageflip/mappable related abi breakageDaniel Vetter2010-11-041-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | In a00b10c360b35d6431a "Only enforce fence limits inside the GTT" Chris Wilson implemented an optimization to only pin framebuffers as mappable for crtc_set_base (but not for pageflips). This breaks the abi, eg: A double buffering mesa client might leave the last framebuffer in unmappable space on close. A subsequent glReadPix by a frontbuffer rendering client then goes boom. My pretty anal mappable/unmappable consistency checking detected this, see https://bugs.freedesktop.org/show_bug.cgi?id=31286 Chris Wilson tried to fix this in 085ce2643713830cf772c by pinning tiled framebuffers into mappable space. This a) renders the original optimization of not forcing framebuffers for pageflipping clients into mappable pointless because all our scanout buffers are tiled by default. b) doesn't solve the problem for untiled framebuffers. So kill this. Emperically it's no gain anyway because framebuffers are being reused by the ddx and hence there's no chance for them to get constanly bounced between mappable and unmappable. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson2010-11-044-25/+42
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| * agp/intel: fix cache control for sandybridgeZhenyu Wang2010-11-041-2/+2
| | | | | | | | | | | | | | | | | | This is broken from 97ef1bdd0bc75bce7b2058e9c432b6c277dcf4d3. Let's set the correct bit for LLC+MLC and LLC only. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Cc: stable@kernel.org Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * agp/intel: restore cache behavior on sandybridgeZhenyu Wang2010-11-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This restores cache behavior for default AGP_USER_MEMORY as uncached, and leave default AGP_USER_CACHED_MEMORY as LLC only. I've seen different cache behavior on one sandybridge desktop CPU vs. another mobile CPU. Until we figure out how to detect the real cache config, restore back to the original behavior now. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Cc: stable@kernel.org Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * drm/i915; Don't apply Ironlake FDI clock workaround to SandybridgeZhenyu Wang2010-11-042-3/+5
| | | | | | | | | | | | Signed-off-by: Zhenyu Wang <zhenyu.z.wang@intel.com> Cc: stable@kernel.org Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * drm/i915: Fix KMS regression on Sandybridge/CPTZhenyu Wang2010-11-041-21/+33
| | | | | | | | | | | | | | | | | | | | We should enable FDI normal training on Sandybridge/CPT system as well. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> [ickle: removed unrelated chunks] Cc: stable@kernel.org Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * i915: reprogram power monitoring registers on resumeKyle McMartin2010-11-032-1/+4
| | | | | | | | | | | | | | | | | | | | | | Fixes issue where i915_gfx_val was reporting values several orders of magnitude higher than physically possible (without leaving scorch marks on my thighs at least.) Signed-off-by: Kyle McMartin <kyle@redhat.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Cc: stable@kernel.org Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | drm/i915: Ensure that if we ever try to pin+fence it is mappable.Chris Wilson2010-11-032-1/+3
| | | | | | | | | | | | | | | | | | | | When merging Daniel's full-gtt patches I had a set of tweaks which I thought I had undone. I was half right... Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=31286 Reported-by: jinjin.wang@intel.com Reported-by: Alexey Fisher <bug-track@fisher-privat.net> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | drm/i915: Drop the iomem accessors when writing to the kmapped blt batchChris Wilson2010-11-021-3/+3
| | | | | | | | | | | | | | | | | | | | I presumed that we would be writing to the batch through the GTT having bound it, so I converted it to use iomem. Even later as I spotted that we didn't even move the batch to the GTT (now an issue since we default to uncached memory on SNB) I still didn't realise that using iomem for kmapped memory was incorrect. Fix it. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson2010-11-022-6/+5
|\ \ | |/ | | | | | | | | | | | | | | Immediate merge to resolve conflicts from applying a stability fix to both branches. Conflicts: drivers/gpu/drm/i915/intel_ringbuffer.c drivers/gpu/drm/i915/intel_ringbuffer.h
| * drm/i915: SNB BLT workaroundChris Wilson2010-11-022-3/+116
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On some stepping of SNB cpu, the first command to be parsed in BLT command streamer should be MI_BATCHBUFFER_START otherwise the GPU may hang. (cherry picked from commit 8d19215be8254f4f75e9c5a0d28345947b0382db) Conflicts: drivers/gpu/drm/i915/intel_ringbuffer.c drivers/gpu/drm/i915/intel_ringbuffer.h Signed-off-by: Zou Nan hai <nanhai.zou@intel.com> Cc: stable@kernel.org Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * drm/i915: Fix the graphics frequency clamping at init and when IPS is active.Jesse Barnes2010-11-021-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Part of the issue here was that Eric slipped in a debug hack for testing the i915 IPS code before the intel_ips.c driver had landed. This caused the driver to always use the full range of frequencies, which is only legal when IPS tells us we have the headroom. Once that hack was removed, there was confusion about the driver's frequency clamping variables: max_delay is the driver's current limit on the highest frequency the IPS driver wants us to use, while dev_priv->fmax is the hardware-reported limit that the IPS driver can increase up to. Tested with IPS driver loaded or not. Note that on Ironlake systems without the IPS driver loaded this will result in a performance reduction, and the inital warmup of frequency limits can impact benchmarking on systems with IPS loaded. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net> [ickle: demoted a debugging printk] Cc: stable@kernel.org Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * drm/i915: Allow powersave modparam to be adjusted at runtime.Chris Wilson2010-11-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | 2.6.36 appears to respect the 0400 mode we assigned to the parameter preventing it from being adjusted after loading. However, this is safe to adjust at runtime. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=31311 Reported-by: Fernando Lemos <fernandotcl@gmail.com> Cc: stable@kernel.org Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | drm/i915: SNB BLT workaroundZou Nan hai2010-11-022-3/+123
| | | | | | | | | | | | | | | | | | | | On some stepping of SNB cpu, the first command to be parsed in BLT command streamer should be MI_BATCHBUFFER_START otherwise the GPU may hang. Signed-off-by: Zou Nan hai <nanhai.zou@intel.com> [ickle: rebased for -next] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | agp/intel: restore cache behavior on sandybridgeZhenyu Wang2010-11-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | This restores cache behavior for default AGP_USER_MEMORY as uncached, and leave default AGP_USER_CACHED_MEMORY as LLC only. I've seen different cache behavior on one sandybridge desktop CPU vs. another mobile CPU. Until we figure out how to detect the real cache config, restore back to the original behavior now. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | agp/intel: fix cache control for sandybridgeZhenyu Wang2010-11-021-2/+2
| | | | | | | | | | | | | | | | This is broken from 97ef1bdd0bc75bce7b2058e9c432b6c277dcf4d3. Let's set the correct bit for LLC+MLC and LLC only. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | Revert "drm/i915: add MMIO debug output"Chris Wilson2010-11-021-28/+2
| | | | | | | | | | | | | | | | | | | | We can use mmiotrace instead of our own debug printks. This reverts commit be282fd48e7492812402a22d73a348c44bf95b63. Conflicts: drivers/gpu/drm/i915/i915_drv.h
* | Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson2010-11-014-9/+7
|\ \ | |/ | | | | | | | | Conflicts: drivers/gpu/drm/i915/i915_gem.c drivers/gpu/drm/i915/i915_gem_evict.c
| * drm/i915: Apply big hammer to serialise buffer access between ringsChris Wilson2010-11-011-28/+52
| | | | | | | | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org
| * drm/i915: opregion_setup: iounmap correct addressChristoph Fritz2010-11-011-1/+1
| | | | | | | | | | | | | | | | | | In case of an opregion signature mismatch in intel_opregion_setup(), iounmap the correct address. Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com> Cc: stable@kernel.org Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * drm/i915: Flush read-only buffers from the active list upon idle as wellChris Wilson2010-10-282-13/+5
| | | | | | | | | | | | | | | | | | | | It is possible for the active list to only contain a read-only buffer so that the ring->gpu_write_list remains entry. This leads to an inconsistency between i915_gpu_is_active() and i915_gpu_idle() causing an infinite spin during the shrinker and an assertion failure that i915_gpu_idle() does indeed flush all buffers from the active lists. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * i915: signedness bug in check_overlay_src()Dan Carpenter2010-10-271-1/+3
| | | | | | | | | | | | | | | | | | | | | | "depth" should be signed in case packed_depth_bytes() returns -EINVAL. This probably doesn't make a difference at runtime. In the original code we would return -EINVAL later if (rec->offset_Y % 4294967274) is non-zero. Signed-off-by: Dan Carpenter <error27@gmail.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | drm/i915: Move the invalidate|flush information out of the device structChris Wilson2010-11-013-26/+23
| | | | | | | | | | | | | | ... and into a local structure scoped for the single function in which it is used. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | drm/i915: Apply big hammer to serialise buffer access between ringsChris Wilson2010-11-011-23/+52
| | | | | | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | drm/i915/debugfs: Report ring in error stateChris Wilson2010-11-013-28/+36
| | | | | | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | agp/intel: the GMCH is always enabled for integrated processor graphicsChris Wilson2010-10-311-16/+27
| | | | | | | | | | | | | | | | | | | | ... and trying to set the bit is ineffectual. Fixes the regression from e380f60 which detected that we were trying to do undefined operations on the I830_GMCH_CTRL. Reported-by: Alexey Fisher <bug-track@fisher-privat.net> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | drm/i915: Evict just the purgeable GTT entries on the first passChris Wilson2010-10-313-40/+25
| | | | | | | | | | | | | | | | | | | | Take two passes to evict everything whilst searching for sufficient free space to bind the batchbuffer. After searching for sufficient free space using LRU eviction, evict everything that is purgeable and try again. Only then if there is insufficient free space (or the GTT is too badly fragmented) evict everything from the aperture and try one last time. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | drm/i915: Fix typo from e5281ccd in i915_gem_attach_phys_object()Chris Wilson2010-10-301-1/+1
| | | | | | | | | | | | | | | | Accessing the uninitialised obj->pages instead of the local page lead to an OOPs. Reported-by: Xavier Chantry <chantry.xavier@gmail.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | drm/i915: Record BSD engine error stateChris Wilson2010-10-294-0/+24
| | | | | | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | drm/i915/ringbuffer: Use the HEAD auto-reporting mechanismChris Wilson2010-10-291-1/+12
| | | | | | | | | | | | | | | | | | My Sandybridge only reports 0 for the ring buffer registers, causing it to hang as soon as we exhaust the available ring. As a workaround, take advantage of our huge ring buffers and use the auto-reporting mechanism to update the status page with the HEAD location every 64 KiB. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | drm/i915: Check if the GPU hung whilst waiting for the ring to clearChris Wilson2010-10-291-0/+2
| | | | | | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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