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* clk: turn rate change failed warning into pr_debugSascha Hauer2014-03-201-1/+1
| | | | | | | | | | If a rate change failed it's the opportunity of the caller to handle this. Do not spam the log with a message. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Mike Turquette <mturquette@linaro.org>
* MAINTAINERS: use LKML for common clk frameworkMike Turquette2014-03-191-1/+1
| | | | | | | Framework is not ARM specific and used by many architectures. Change ML from LAKML to LKML. Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: respect the clock dependencies in of_clk_initGregory CLEMENT2014-03-191-4/+79
| | | | | | | | | | | | | | | | | | | | | Until now the clock providers were initialized in the order found in the device tree. This led to have the dependencies between the clocks not respected: children clocks could be initialized before their parent clocks. Instead of forcing each platform to manage its own initialization order, this patch adds this work inside the framework itself. Using the data of the device tree the of_clk_init function now delayed the initialization of a clock provider if its parent provider was not ready yet. The strict dependency check (all parents of a given clk must be initialized) was added by Boris BREZILLON Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: mpc85xx: Update the driver to align to new clock bindingsTang Yuantian2014-03-191-22/+48
| | | | | | | | | | | | The clock bindings for Freescale CoreNet platform are updated. So, the driver needs to be updated accordingly. The main changes include: - Added a new node to present the input system clock - Changed PLL and MUX's compatible string Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: at91: optimization of the set_rate callbackJean-Jacques Hiblot2014-03-191-30/+8
| | | | | | Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@traphandler.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: at91: fix programmable clk irq handlingJean-Jacques Hiblot2014-03-192-93/+89
| | | | | | | | | | The PCKRDY bit is not set until the system clock is enabled. This patch moves the management of the ready status in the system clock driver. Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@traphandler.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: at91: propagate rate change on system clksBoris BREZILLON2014-03-191-1/+1
| | | | | | | | System clks are just gates, and thus do not provide any rate operations. Authorize clk rate change to be propagated to system clk parents. Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: at91: replace prog clk round_rate with determine_rateBoris BREZILLON2014-03-191-28/+28
| | | | | | | | Implement the determine_rate callback to choose the best parent clk that fulfills the requested rate. Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* Documentation: clk: Add locking documentationLaurent Pinchart2014-03-191-0/+34
| | | | | | | | Briefly document the common clock framework locking scheme from a clock driver point of view. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* Merge tag 'clk-hisi' of ↵Mike Turquette2014-03-197-39/+164
|\ | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/hzhuang1/linux into clk-next-hisilcon updating clock drivers for Hisilicon
| * clk: hisi: remove static variableHaojian Zhuang2014-03-194-42/+72
| | | | | | | | | | | | | | Remove the static variable. So these common clock register helper could be used in more SoCs. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
| * clk: hip04: add clock driverHaojian Zhuang2014-03-194-1/+94
| | | | | | | | | | | | Now only fixed rate clocks are appended into the clock driver. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
| * clk: hisi: assign missing clk to tableHaojian Zhuang2014-03-191-0/+2
| | | | | | | | | | | | The fixed rate and fixed factor clock isn't registered to clk table. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
* | clk: sunxi: fix thinko in commentEmilio López2014-03-191-1/+1
| | | | | | | | | | | | | | | | This should read MOD0 and not MMC; MMC is just one example of a MOD0 clock. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | clk: sunxi: fix some calculationsEmilio López2014-03-191-3/+3
| | | | | | | | | | | | | | | | | | | | Some divisor calculations were misrounded, causing higher than requested rates on some clocks. Fix them up using DIV_ROUND_UP, and replace one homebrew instance of it as well with the right macro. Reported-by: Boris BREZILLON <b.brezillon.dev@gmail.com> Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | clk: sunxi: fix A20 PLL4 calculationEmilio López2014-03-191-0/+7
| | | | | | | | | | | | | | | | | | Allwinner actually reworked the PLL4 on A20; now it's compatible with the sun4i PLL5/6 design previous to any divisions, as well as to the new PLL8 in sun7i. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | Merge tag 'sunxi-clk-for-3.15' of https://bitbucket.org/emiliolopez/linux ↵Mike Turquette2014-03-192-48/+344
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into clk-next-sunxi Allwinner sunXi SoCs clock changes This adds support for the new, more correct clock node naming and gets the A10 compatibles in line with the rest of the other SoCs. It also adds support for the USB, GMAC and A31's PLL6 clocks. Some of these changes also require DT modifications that will be merged via arm-soc.
| * | clk: sunxi: Add new clock compatiblesMaxime Ripard2014-02-182-33/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Allwinner A10 compatibles were following a slightly different compatible patterns than the rest of the SoCs for historical reasons. Add compatibles matching the other pattern to the clock driver for consistency, and keep the older one for backward compatibility. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Emilio López <emilio@elopez.com.ar>
| * | clk: sunxi: Add Allwinner A20/A31 GMAC clock unitChen-Yu Tsai2014-02-182-0/+126
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Allwinner A20/A31 clock module controls the transmit clock source and interface type of the GMAC ethernet controller. Model this as a single clock for GMAC drivers to use. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Emilio López <emilio@elopez.com.ar>
| * | clk: sunxi: Add support for PLL6 on the A31Maxime Ripard2014-02-182-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | The A31 has a slightly different PLL6 clock. Add support for this new clock in our driver. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Emilio López <emilio@elopez.com.ar>
| * | clk: sunxi: Add USB clock register defintionsRoman Byshko2014-02-182-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add register definitions for the usb-clk register found on sun4i, sun5i and sun7i SoCs. Signed-off-by: Roman Byshko <rbyshko@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Emilio López <emilio@elopez.com.ar>
| * | clk: sunxi: Add support for USB clock-register reset bitsHans de Goede2014-02-181-0/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The usb-clk register is special in that it not only contains clk gate bits, but also has a few reset bits. This commit adds support for this by allowing gates type sunxi clks to also register a reset controller. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Emilio López <emilio@elopez.com.ar>
| * | clk: sunxi: get divs parent clock name from parent factor clockChen-Yu Tsai2014-02-031-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Divs clocks consist of a parent factor clock with multiple outputs, and seperate clocks for each output. Get the name of the parent clock from the parent factor clock, instead of the DT node name. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
| * | clk: sunxi: add names for pll5, pll6 parent clocks to factors_dataChen-Yu Tsai2014-02-031-9/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some factor clocks, such as the parent clock of pll5 and pll6, have multiple output names. Add the corresponding names to factors_data tied to compatible string. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
| * | clk: sunxi: update clock-output-names dt binding documentationChen-Yu Tsai2014-02-031-6/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | clock-output-names is now required for most of sunxi clock nodes, to provide the name of the corresponding clock. Add the new requirements, exceptions, as well as examples. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
| * | clk: sunxi: add clock-output-names dt property supportChen-Yu Tsai2014-02-031-0/+6
| |/ | | | | | | | | | | | | | | | | | | | | | | sunxi clock drivers use dt node name as clock name, but clock nodes should be named clk@X, so the names would be the same. Let the drivers read clock names from dt clock-output-names property. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
* | clk: socfpga: Fix section mismatch warningDinh Nguyen2014-03-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | WARNING: drivers/clk/socfpga/built-in.o(.data+0xc0): Section mismatch in reference from the variable socfpga_child_clocks to the function .init.text:socfpga_pll_init() The variable socfpga_child_clocks references the function __init socfpga_pll_init() If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console WARNING: drivers/clk/socfpga/built-in.o(.data+0x184): Section mismatch in reference from the variable socfpga_child_clocks to the function .init.text:socfpga_periph_init() The variable socfpga_child_clocks references the function __init socfpga_periph_init() If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console WARNING: drivers/clk/socfpga/built-in.o(.data+0x248): Section mismatch in reference from the variable socfpga_child_clocks to the function .init.text:socfpga_gate_init() The variable socfpga_child_clocks references the function __init socfpga_gate_init() If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console Reported-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | Merge tag 'clk-mvebu-3xx-3.15-2' of git://git.infradead.org/linux-mvebu into ↵Mike Turquette2014-03-182-2/+28
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clk-next-mvebu clock: mvebu new SoC changes for v3.15 (incremental pull #2) - mvebu (Armada 375) - fix ratio register offest - mvebu (Armada 380) - expand core divider clock driver to support 380 SoC (enables nand support)
| * | clk: mvebu: Update binding documentation for the core divider clockEzequiel Garcia2014-03-131-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | The Core Divider clock support two new compatible strings for Armada 375 and Armada 380 SoCs. Add the compatible strings to the documentation. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1394742273-5113-7-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * | clk: mvebu: Support Armada 380 SoC on the core divider clockEzequiel Garcia2014-03-131-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds support for the Core Divider clocks of the Armada 380 SoCs. Similarly to Armada 370 and XP, the Core Divider clocks of the 380 have gate capabilities. The only difference is the register layout. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1394742273-5113-2-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * | clk: mvebu: Fix ratio register offset on A375 SoCEzequiel Garcia2014-03-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | This commit fixes the ratio register offset which is 0x4, as per the Armada 375 SoC specification. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1394638901-13368-2-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* | | clk: clk-s2mps11: Add support for clocks in S5M8767 MFDTushar Behera2014-03-182-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since clock operation within S2MPS11 and S5M8767 are similar, we can support both the devices within a single driver. Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Reviewed-by: Yadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | | clk: clk-s2mps11: Refactor for including support for other MFD clocksTushar Behera2014-03-181-4/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The clocks in S2MPS11 and S5M8767 are managed in the same way, baring a difference in the register offset. It would be better to update existing S2MPS11 driver to support the clocks in S5M8767, rather than creating an almost duplicate driver altogether. Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Reviewed-by: Yadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | | clk: add MOXA ART SoCs clock driverJonas Jensen2014-03-183-0/+146
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MOXA ART SoCs allow to determine PLL output and APB frequencies by reading registers holding multiplier and divisor information. Add a clock driver for this SoC. Signed-off-by: Jonas Jensen <jonas.jensen@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | | Merge branch 'clk-fixes' into clk-nextMike Turquette2014-02-262-1/+4
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| * | | clk:at91: Fix memory leak in of_at91_clk_master_setup()Masanari Iida2014-02-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | cppcheck detected following error [clk-master.c:245]: (error) Memory leak: characteristics The original code forgot to free characteristics when irq_of_parse_and_map() failed. Signed-off-by: Masanari Iida <standby24x7@gmail.com> Acked-by Boris BREZILLON <b.brezillon@overkiz.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | | clk: nomadik: fix multiplatform problemLinus Walleij2014-02-261-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Nomadik debugfs screws up multiplatform boots if debugfs is enabled on the multiplatform image, since it's a simple initcall that is unconditionally executed and reads from certain memory locations. Fix this by checking that the driver has been properly initialized, so a base offset to the Nomadik SRC controller exists, before proceeding to register debugfs files. Reported-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | | | clk: ti/divider: fix rate calculation for fractional ratesTomi Valkeinen2014-02-261-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ti/clk-divider.c does not calculate the rates consistently at the moment. As an example, on OMAP3 we have a clock divider with a source clock of 864000000 Hz. With dividers 6, 7 and 8 the theoretical rates are: 6: 144000000 7: 123428571.428571... 8: 108000000 Calling clk_round_rate() with the rate in the first column will give the rate in the second column: 144000000 -> 144000000 143999999 -> 123428571 123428572 -> 123428571 123428571 -> 108000000 Note how clk_round_rate() returns 123428571 for rates from 123428572 to 143999999, which is mathematically correct, but when clk_round_rate() is called with 123428571, the returned value is surprisingly 108000000. This means that the following code works a bit oddly: rate = clk_round_rate(clk, 123428572); clk_set_rate(clk, rate); As clk_set_rate() also does clock rate rounding, the result is that the clock is set to the rate of 108000000, not 123428571 returned by the clk_round_rate. This patch changes the ti/clk-divider.c to use DIV_ROUND_UP when calculating the rate. This gives the following behavior which fixes the inconsistency: 144000000 -> 144000000 143999999 -> 123428572 123428572 -> 123428572 123428571 -> 108000000 Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | | | clk: divider: fix rate calculation for fractional ratesTomi Valkeinen2014-02-261-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clk-divider.c does not calculate the rates consistently at the moment. As an example, on OMAP3 we have a clock divider with a source clock of 864000000 Hz. With dividers 6, 7 and 8 the theoretical rates are: 6: 144000000 7: 123428571.428571... 8: 108000000 Calling clk_round_rate() with the rate in the first column will give the rate in the second column: 144000000 -> 144000000 143999999 -> 123428571 123428572 -> 123428571 123428571 -> 108000000 Note how clk_round_rate() returns 123428571 for rates from 123428572 to 143999999, which is mathematically correct, but when clk_round_rate() is called with 123428571, the returned value is surprisingly 108000000. This means that the following code works a bit oddly: rate = clk_round_rate(clk, 123428572); clk_set_rate(clk, rate); As clk_set_rate() also does clock rate rounding, the result is that the clock is set to the rate of 108000000, not 123428571 returned by the clk_round_rate. This patch changes the clk-divider.c to use DIV_ROUND_UP when calculating the rate. This gives the following behavior which fixes the inconsistency: 144000000 -> 144000000 143999999 -> 123428572 123428572 -> 123428572 123428571 -> 108000000 Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | | | clk: axi-clkgen: Add support for v2Lars-Peter Clausen2014-02-262-44/+270
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the new v2 version of the axi-clkgen core. Unfortunately the method of accessing the registers is quite different on v2, while the content still stays largely the same. So the patch adds a small abstraction layer which implements the specific read and write functions for v1 and v2 in callback functions. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
* | | | clk: hisilicon: add hi3620_mmc_clksZhangfei Gao2014-02-264-0/+294
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Suggest by Arnd: abstract mmc tuning as clock behavior, also because different soc have different tuning method and registers. hi3620_mmc_clks is added to handle mmc clock specifically on hi3620. Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | | | clk: socfpga: Support multiple parents for the pll clocksDinh Nguyen2014-02-261-4/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PLLs can be from 3 different sources: osc1, osc2, or the f2s_ref_clk. Update the clock driver to be able to get the correct parent. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Cc: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | | | clk: socfpga: Fix integer overflow in clock calculationDinh Nguyen2014-02-261-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use 64-bit integer for calculating clock rate. Also use do_div for the 64-bit division. Signed-off-by: Graham Moore <grmoore@altera.com> Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Cc: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | | | clk: zynq: Use clk_readl/clk_writel helper functionMichal Simek2014-02-252-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Do not use readl/writel directly because the whole clk subsystem is using clk_readl/clk_writel functions. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | | | clk: shmobile: div6: use proper description in kernel docWolfram Sang2014-02-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These variable clocks have nothing to do with MSTP gating, probably a copy&paste leftover. Signed-off-by: Wolfram Sang <wsa@sang-engineering.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | | | Merge branch 'clk-fixes' into clk-nextMike Turquette2014-02-24391-2289/+3592
|\ \ \ \ | |/ / /
| * | | Merge branch 'clocks/fixes/drivers' of git://linuxtv.org/pinchartl/fbdev ↵Mike Turquette2014-02-24375-2197/+3482
| |\ \ \ | | | | | | | | | | | | | | | into clk-fixes
| | * | | clk: shmobile: Fix typo in MSTP clock DT bindingsLaurent Pinchart2014-02-241-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DT bindings document a renesas,indices property, while the code, the DT example and the DT sources all use renesas,clock-indices. Fix the documentation. The shmobile mstp DT bindings have been merged in v3.14-rc1 with a bug in the DT ABI, a fix during the -rc series is appropriate. Reported-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Simon Horman <horms@verge.net.au>
| | * | | clk: shmobile: rcar-gen2: Fix qspi divisorLaurent Pinchart2014-02-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The qspi clock divisor is incorrectly set to twice the value it should have, possibly because it has been computed based on PLL1 as the clock parent instead of PLL1 / 2 (the datasheets specifies the qspi nominal frequencies, not the divisor values). Fix it. This bug introduced in v3.14-rc1 breaks various devices on the Lager and Kolesh shmobile boards and should thus be considered as a regression for which a fix during the -rc series is appropriate. Reported-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Simon Horman <horms+renesas@verge.net.au>
| | * | | clk: shmobile: rcar-gen2: Fix clock parent for all non-PLL clocksLaurent Pinchart2014-02-241-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The lb, qspi, sdh, sd0 and sd1 clocks have the PLL1 (divided by 2) as their parent, not the main clock. Fix it. This bug introduced in v3.14-rc1 breaks various devices on the Lager and Kolesh shmobile boards and should thus be considered as a regression for which a fix during the -rc series is appropriate. Reported-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Simon Horman <horms+renesas@verge.net.au>
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