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* [PATCH] x86_64: Allow modular build of ia32 aout loaderAndi Kleen2005-11-145-5/+12
| | | | | Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86_64: Force correct address space size for MTRR on some 64bit ↵Shaohua Li2005-11-142-0/+13
| | | | | | | | | | | | | | | | Intel Xeons They report 40bit, but only have 36bits of physical address space. This caused problems with setting up the correct masks for MTRR. CPUID workaround for steppings 0F33h(supporting x86) and 0F34h(supporting x86 and EM64T). Detail info can be found at: http://download.intel.com/design/Xeon/specupdt/30240216.pdf http://download.intel.com/design/Pentium4/specupdt/30235221.pdf Signed-off-by: Shaohua Li<shaohua.li@intel.com> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] AGP: Make gart iterator in K8 AGP driver SMP safeAndi Kleen2005-11-141-2/+3
| | | | | | | | Ugh! Cc: davej@redhat.com Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] AGP: Try unsupported AGP chipsets on x86-64 by defaultAndi Kleen2005-11-141-1/+1
| | | | | | | | | | | | | So far all new ones have worked and there isn't much variation because the CPU does all the interesting bits. So enable try unsupported by default. Can be still disabled with try_unsupported=0 (module) or amd64.try_unsupported=0 (boot option) Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] AGP: Support ULI/ALI 1689 bridge on AMD64Andi Kleen2005-11-141-0/+10
| | | | | | | | (no name because I'm not sure of the correct name) Cc: davej@redhat.com Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86_64: Optimize NUMA node hash functionEric Dumazet2005-11-141-24/+43
| | | | | | | | | | | | | | | | | | | | | | | | Compute the highest possible value for memnode_shift, in order to reduce footprint of memnodemap[] to the minimum, thus making all users (phys_to_nid(), kfree()), more cache friendly. Before the patch : Node 0 MemBase 0000000000000000 Limit 00000001ffffffff Node 1 MemBase 0000000200000000 Limit 00000003ffffffff Using 23 for the hash shift. Max adder is 3ffffffff After the patch : Node 0 MemBase 0000000000000000 Limit 00000001ffffffff Node 1 MemBase 0000000200000000 Limit 00000003ffffffff Using 33 for the hash shift. In this case, only 2 bytes of memnodemap[] are used, instead of 2048 Signed-off-by: Eric Dumazet <dada1@cosmosbay.com> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86_64: Save/restore CS in 64bit signal handlers and force __USER_CS ↵Bryan Ford2005-11-141-0/+17
| | | | | | | | | | for CS This allows to run 64bit signal handlers in 64bit processes that run small code snippets in compat mode. Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86_64: New heuristics to find out hotpluggable CPUs.Andi Kleen2005-11-144-5/+47
| | | | | | | | | | | | | | | | | | | | | | | | | With a NR_CPUS==128 kernel with CPU hotplug enabled we would waste 4MB on per CPU data of all possible CPUs. The reason was that HOTPLUG always set up possible map to NR_CPUS cpus and then we need to allocate that much (each per CPU data is roughly ~32k now) The underlying problem is that ACPI didn't tell us how many hotplug CPUs the platform supports. So the old code just assumed all, which would lead to this memory wastage. This implements some new heuristics: - If the BIOS specified disabled CPUs in the ACPI/mptables assume they can be enabled later (this is bending the ACPI specification a bit, but seems like a obvious extension) - The user can overwrite it with a new additionals_cpus=NUM option - Otherwise use half of the available CPUs or 2, whatever is more. Cc: ashok.raj@intel.com Cc: len.brown@intel.com Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86_64: Use int operations in spinlocks to support more than 128 ↵Andi Kleen2005-11-141-6/+6
| | | | | | | | | CPUs spinning. Pointed out by Eric Dumazet Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86_64: Some clarifications for Documention/x86_64/mm.txtAndi Kleen2005-11-141-1/+5
| | | | | | | I got some questions on this, so just fix up the documentation. Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86_64: Replace swiotlb extern with includeAndi Kleen2005-11-141-4/+1
| | | | | | | Minor victory on the continuous quest against all stray extern. Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86_64: Replace cpu_pda extern with includeAndi Kleen2005-11-141-2/+0
| | | | | | | Minor cleanup - remove obsolete extern Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86_64: Only use asm/sections.h to declare section symbolsAndi Kleen2005-11-146-16/+8
| | | | | | | | | Adding __initdata_* to asm-generic/sections.h Replaces a lot of open coded externs in arch/x86_64/* I had to change __bss_end to __bss_stop to match the other architectures. Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86_64: Don't apply __PHYSICAL_MASK to page frame numbersAndi Kleen2005-11-142-3/+3
| | | | | | | | | | | It is for physical addresses, not for PFNs. Pointed out by Tejun Heo. Cc: htejun@gmail.com Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86_64: Unmap NULL during early bootupSiddha, Suresh B2005-11-1411-32/+56
| | | | | | | | | | | | | | | | | | We should zap the low mappings, as soon as possible, so that we can catch kernel bugs more effectively. Previously early boot had NULL mapped and didn't trap on NULL references. This patch introduces boot_level4_pgt, which will always have low identity addresses mapped. Druing boot, all the processors will use this as their level4 pgt. On BP, we will switch to init_level4_pgt as soon as we enter C code and zap the low mappings as soon as we are done with the usage of identity low mapped addresses. On AP's we will zap the low mappings as soon as we jump to C code. Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Signed-off-by: Ashok Raj <ashok.raj@intel.com> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86_64: Speed up numa_node_id by putting it directly into the PDAAndi Kleen2005-11-147-5/+18
| | | | | | | | | | | | Not go from the CPU number to an mapping array. Mode number is often used now in fast paths. This also adds a generic numa_node_id to all the topology includes Suggested by Eric Dumazet Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86_64: Fix gcc 4 warning in aperture.cAndi Kleen2005-11-141-1/+1
| | | | | | | | | | Fix arch/x86_64/kernel/aperture.c: In function #iommu_hole_init#: arch/x86_64/kernel/aperture.c:199: warning: #aper_order# may be used uninitialized in this function Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86-64/i386: Fix CPU model for family 6Suresh Siddha2005-11-142-4/+4
| | | | | | | | | | | According to cpuid instruction in IA32 SDM-Vol2, when computing cpu model, we need to consider extended model ID for family 0x6 also. AK: Also added fixes/simplifcation from Petr Vandrovec Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86_64: Remove duplicate __cpuinit defineAshok Raj2005-11-141-2/+0
| | | | | | | | | Remove duplicate __cpuinit in smp.c. Already defined in init.h which is already included. Signed-off-by: Ashok Raj <ashok.raj@intel.com> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86_64: Use the DMA32 zone for dma_alloc_coherent()/pci_alloc_consistentAndi Kleen2005-11-141-1/+7
| | | | | Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86_64: Remove obsolete ARCH_HAS_ATOMIC_UNSIGNED and page_flags_tAndi Kleen2005-11-144-11/+5
| | | | | | | | | Has been introduced for x86-64 at some point to save memory in struct page, but has been obsolete for some time. Just remove it. Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86_64: Fix up outdated pfn_to_page commentAndi Kleen2005-11-141-3/+1
| | | | | | | | pfn_to_page really requires pfn_valid to be true now, no question. Some people stumbled over it, but it was misleading and wrong. Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] i386/x86-64: Share interrupt vectors when there is a large number of ↵James Cleverdon2005-11-145-17/+86
| | | | | | | | | | | | | | | | | | | | | interrupt sources Here's a patch that builds on Natalie Protasevich's IRQ compression patch and tries to work for MPS boots as well as ACPI. It is meant for a 4-node IBM x460 NUMA box, which was dying because it had interrupt pins with GSI numbers > NR_IRQS and thus overflowed irq_desc. The problem is that this system has 270 GSIs (which are 1:1 mapped with I/O APIC RTEs) and an 8-node box would have 540. This is much bigger than NR_IRQS (224 for both i386 and x86_64). Also, there aren't enough vectors to go around. There are about 190 usable vectors, not counting the reserved ones and the unused vectors at 0x20 to 0x2F. So, my patch attempts to compress the GSI range and share vectors by sharing IRQs. Cc: "Protasevich, Natalie" <Natalie.Protasevich@unisys.com> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86_64: Support for AMD specific MCE Threshold.Jacob Shin2005-11-1411-1/+582
| | | | | | | | | | | | | | | | | | | | | | MC4_MISC - DRAM Errors Threshold Register realized under AMD K8 Rev F. This register is used to count correctable and uncorrectable ECC errors that occur during DRAM read operations. The user may interface through sysfs files in order to change the threshold configuration. bank%d/error_count - reads current error count, write to clear. bank%d/interrupt_enable - set/clear interrupt enable. bank%d/threshold_limit - read/write the threshold limit. APIC vector 0xF9 in hw_irq.h. 5 software defined bank ids in mce.h. new apic.c function to setup threshold apic lvt. defaults to interrupt off, count enabled, and threshold limit max. sysfs interface created on /sys/devices/system/threshold. AK: added some ifdefs to make it compile on UP Signed-off-by: Jacob Shin <jacob.shin@amd.com> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86_64: Adjust, correct, and complete the HPET definitions for x86-64.Jan Beulich2005-11-141-14/+21
| | | | | | Signed-off-by: Jan Beulich <jbeulich@novell.com> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86_64: Account mem_map in VM holes accountingAndi Kleen2005-11-141-0/+19
| | | | | | | | | | | The VM needs to know about lost memory in zones to accurately balance dirty pages. This patch accounts mem_map in there too, which fixes a constant errror of a few percent. Also some other misc mappings and the kernel text itself are accounted too. Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86_64: When cpu_up fails clean up page allocator properlyAndi Kleen2005-11-141-2/+1
| | | | | Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86_64: Make i386 compile again with fourth DMA32 zoneAndi Kleen2005-11-141-2/+2
| | | | | | | | The code should deal with an additional empty zone, so fix up the #error. Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86_64: Set compatibility flag for 4GB zone on IA64Andi Kleen2005-11-141-0/+4
| | | | | | | | | | | IA64 traditionally had a 4GB DMA32 zone. Set the compatibility flag to keep old drivers working. For new drivers it would be better to use ZONE_DMA32 now. Cc: tony.luck@intel.com Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86_64: Add 4GB DMA32 zoneAndi Kleen2005-11-147-55/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a new 4GB GFP_DMA32 zone between the GFP_DMA and GFP_NORMAL zones. As a bit of historical background: when the x86-64 port was originally designed we had some discussion if we should use a 16MB DMA zone like i386 or a 4GB DMA zone like IA64 or both. Both was ruled out at this point because it was in early 2.4 when VM is still quite shakey and had bad troubles even dealing with one DMA zone. We settled on the 16MB DMA zone mainly because we worried about older soundcards and the floppy. But this has always caused problems since then because device drivers had trouble getting enough DMA able memory. These days the VM works much better and the wide use of NUMA has proven it can deal with many zones successfully. So this patch adds both zones. This helps drivers who need a lot of memory below 4GB because their hardware is not accessing more (graphic drivers - proprietary and free ones, video frame buffer drivers, sound drivers etc.). Previously they could only use IOMMU+16MB GFP_DMA, which was not enough memory. Another common problem is that hardware who has full memory addressing for >4GB misses it for some control structures in memory (like transmit rings or other metadata). They tended to allocate memory in the 16MB GFP_DMA or the IOMMU/swiotlb then using pci_alloc_consistent, but that can tie up a lot of precious 16MB GFPDMA/IOMMU/swiotlb memory (even on AMD systems the IOMMU tends to be quite small) especially if you have many devices. With the new zone pci_alloc_consistent can just put this stuff into memory below 4GB which works better. One argument was still if the zone should be 4GB or 2GB. The main motivation for 2GB would be an unnamed not so unpopular hardware raid controller (mostly found in older machines from a particular four letter company) who has a strange 2GB restriction in firmware. But that one works ok with swiotlb/IOMMU anyways, so it doesn't really need GFP_DMA32. I chose 4GB to be compatible with IA64 and because it seems to be the most common restriction. The new zone is so far added only for x86-64. For other architectures who don't set up this new zone nothing changes. Architectures can set a compatibility define in Kconfig CONFIG_DMA_IS_DMA32 that will define GFP_DMA32 as GFP_DMA. Otherwise it's a nop because on 32bit architectures it's normally not needed because GFP_NORMAL (=0) is DMA able enough. One problem is still that GFP_DMA means different things on different architectures. e.g. some drivers used to have #ifdef ia64 use GFP_DMA (trusting it to be 4GB) #elif __x86_64__ (use other hacks like the swiotlb because 16MB is not enough) ... . This was quite ugly and is now obsolete. These should be now converted to use GFP_DMA32 unconditionally. I haven't done this yet. Or best only use pci_alloc_consistent/dma_alloc_coherent which will use GFP_DMA32 transparently. Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] x86_64: Update defconfigAndi Kleen2005-11-141-15/+83
| | | | | | | Rerun and enable autofs 4, relayfs and softdog Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [libata] ATAPI pad allocation fixes/cleanupJeff Garzik2005-11-045-26/+71
| | | | | | | Use ata_pad_{alloc,free} in two drivers, to factor out common code. Add ata_pad_{alloc,free} to two other drivers, which needed the padding but had not been updated.
* Merge branch 'master'Jeff Garzik2005-11-041852-64762/+103730
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| * [PATCH] nvidiafb: Geforce 7800 series support addedCalin A. Culianu2005-11-042-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for the Nvidia Geforce 7800 series of cards to the nvidiafb framebuffer driver. All it does is add the PCI device id for the 7800, 7800 GTX, 7800 GO, and 7800 GTX GO cards to the module device table for the nvidiafb.ko driver, so that nvidiafb.ko will actually work on these cards. I also added the relevant PCI device ids to linux/pci_ids.h I tested it on my 7800 GTX here and it works like a charm. I now can get framebuffer support on this card! Woo hoo!! Nothing like 200x75 text mode to make your eyes BLEED. ;) Signed-off-by: Linus Torvalds <torvalds@osdl.org>
| * Merge branch 'srp' of ↵Linus Torvalds2005-11-047-0/+2091
| |\ | | | | | | | | | master.kernel.org:/pub/scm/linux/kernel/git/roland/infiniband
| | * IB: Add SCSI RDMA Protocol (SRP) initiatorRoland Dreier2005-11-027-0/+2091
| | | | | | | | | | | | | | | | | | | | | Add an InfiniBand SCSI RDMA Protocol (SRP) initiator. This driver is used to talk talk to InfiniBand SRP targets (storage devices). Signed-off-by: Roland Dreier <rolandd@cisco.com>
| * | Merge branch 'for-linus' of ↵Linus Torvalds2005-11-0425-124/+178
| |\ \ | | | | | | | | | | | | master.kernel.org:/pub/scm/linux/kernel/git/roland/infiniband
| | * | [IB] mthca: check P_Key index in modify QPJack Morgenstein2005-11-031-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make sure that the P_Key index passed into mthca_modify_qp() is within the device's P_Key table. Signed-off-by: Jack Morgenstein <jackm@mellanox.co.il> Signed-off-by: Roland Dreier <rolandd@cisco.com>
| | * | [IB] umad: fix hot remove of IB devicesRoland Dreier2005-11-031-16/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix hotplug of devices for ib_umad module: when a device goes away, kill off all MAD agents for open files associated with that device, and make sure that the device is not touched again after ib_umad returns from its remove_one function. Signed-off-by: Roland Dreier <rolandd@cisco.com>
| | * | [IB] mthca: fix format of FW versionRoland Dreier2005-11-022-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Mellanox has decided that the components of the firmware version are really meant to be displayed in decimal, e.g. 0x000400070190 is version 4.7.400. Change the format we use from "%x.%x.%x" to "%d.%d.%d" to match this convention. Signed-off-by: Roland Dreier <rolandd@cisco.com>
| | * | [IPoIB] don't compile debug code if debugging isn't enabledRoland Dreier2005-11-023-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Don't build ipoib_mcast_iter_ functions if CONFIG_INFINIBAND_IPOIB_DEBUG is not enabled -- their only callers will not be built either. Also move the prototype for ipoib_open() to ipoib.h to fix a sparse warning. Signed-off-by: Roland Dreier <rolandd@cisco.com>
| | * | [IPoIB] remove unneeded initializations to 0Roland Dreier2005-11-021-9/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Shrink our source and .text a little by removing a few assignments of NULL and 0 to memory that is already cleared as part of the allocation. Signed-off-by: Roland Dreier <rolandd@cisco.com>
| | * | [IB] kzalloc() conversionsRoland Dreier2005-11-0211-62/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace kmalloc()+memset(,0,) with kzalloc(), for a net savings of 35 source lines and about 500 bytes of text. Signed-off-by: Roland Dreier <rolandd@cisco.com>
| | * | [IB] ucm: 32/64 compatibility fixesSean Hefty2005-11-011-6/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix structure layouts to ensure same size on 32-bit and 64-bit architectures. This permits 32-bit userspace apps on a 64-bit kernel. Signed-off-by: Sean Hefty <sean.hefty@intel.com> Signed-off-by: Roland Dreier <rolandd@cisco.com>
| | * | [IPoIB] cleanups: fix comment, remove useless variablesRoland Dreier2005-10-312-9/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Minor cleanups: fix a misleading comment, and get rid of attr_mask variables that are only used to hold constants (just use the constants directly). Signed-off-by: Roland Dreier <rolandd@cisco.com>
| | * | [IB] mthca: Avoid SRQ free WQE list corruptionRoland Dreier2005-10-311-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix wqe_to_link() to use a structure field that we know is definitely always unused for receive work requests, so that it really avoids the free list corruption bug that the comment claims it does. Signed-off-by: Roland Dreier <rolandd@cisco.com>
| | * | [IB] uverbs: Avoid NULL pointer deref on CQ async eventRoland Dreier2005-10-313-6/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Userspace CQs that have no completion event channel attached end up with their cq_context set to NULL. However, asynchronous events like "CQ overrun" can still occur on such CQs, so add a uverbs_file member to struct ib_ucq_object that we can follow to deliver these events. Signed-off-by: Roland Dreier <rolandd@cisco.com>
| | * | [IPoIB] use spin_trylock_irqsave()Roland Dreier2005-10-291-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use spin_trylock_irqsave() in ipoib_start_xmit() instead of reinventing it out of local_irq_save(), spin_trylock() and local_irq_restore(). Signed-off-by: Roland Dreier <rolandd@cisco.com>
| | * | [IB] mthca: report asynchronous CQ eventsMichael S. Tsirkin2005-10-293-3/+36
| | |/ | | | | | | | | | | | | | | | | | | Implement reporting asynchronous CQ events in Mellanox HCA driver. Signed-off-by: Michael S. Tsirkin <mst@mellanox.co.il> Signed-off-by: Roland Dreier <rolandd@cisco.com>
| * | Merge master.kernel.org:/pub/scm/linux/kernel/git/paulus/powerpc-mergeLinus Torvalds2005-11-04177-3992/+8618
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