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* ARM: tegra: move serial clock-frequency attr into the Tegra20 dtsiLucas Stach2013-01-288-8/+5
| | | | | | | | | No Tegra20 Platform is running PLL_P at another rate than 216MHz, nor is any using any other PLL as UART source clock. Move attribute into SoC level dtsi file to slim down board DT files. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: harmony: enable keyboard in DTLaxman Dewangan2013-01-281-0/+117
| | | | | | | | Enable Tegra based keyboard interfacing for keys and provide all key mapping through DTS file. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: whistler: enable keyboard in DTLaxman Dewangan2013-01-281-0/+12
| | | | | | | | | | | | Enable Tegra based keyboard controller and populate the key mapping for Whistler. With this patch, HOME, BACK, POWER and MENU keys will work. Still other keys which are in ROW3 and ROW4 will not work as it conflicts with KBC pins on SDIO2 pinmux. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: cardhu: register UARTCLaxman Dewangan2013-01-281-0/+15
| | | | | | | | | UARTC is used for the interfacing with bluetooth device. Register this UART channel as high speed serial channel so that it can use the APB DMA for data transfer. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: seaboard: enable keyboard in DTLaxman Dewangan2013-01-281-0/+139
| | | | | | | | | Enable Tegra based keyboard controller and populate the key matrix for seaboard. The key matrix was originally on driver code which is removed to have clean driver. The key mapping is now passed through dts file. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: add DT entry for KBC controllerLaxman Dewangan2013-01-282-0/+16
| | | | | | | | | | | | NVIDIA's Tegra SoCs have the matrix keyboard controller which supports 16x8 type of matrix. The number of rows and columns are configurable. Add DT entry for KBC controller. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> [swarren: added clocks property] Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: swap cache-/interrupt-ctrlr nodes in DTStephen Warren2013-01-282-18/+18
| | | | | | | | | | | | This ensures nodes are sorted in order of reg address. This makes it easier to compare against e.g. the U-Boot device trees, and is simply consistent and clean. While we're at it, remove the unit address from the cache-controller node name, since it's unique without it. Reported-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ASoC: tegra: add ac97 host controller to device treeLucas Stach2013-01-281-0/+9
| | | | | | | Add default entry for the AC97 host controller. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: DT: tegra: Add Tegra30 Beaver board supportBryan Wu2013-01-283-0/+376
| | | | | | | | | | | | | | | | | | | | This patch adds support for Tegra30 Beaver board in upstream kernel. Beaver board is a Tegra30 SoC based development board, it has following features: - T30 or T33 SoC (Qual core ARM Cortex A9) - 2 GB DDR3L - 16 GB EMMC - 1 SD slot - 1 USB Standart A port and 1 USB micro AB port - PCI-E Gig Ethernet - Audio input/output - SATA port - HDMI output - UART and JTAG Signed-off-by: Bryan Wu <pengw@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: DT: tegra: Add board level compatible propertiesBryan Wu2013-01-281-6/+23
| | | | | | | | | The compatible properties of Tegra SoC based boards or machines need to be documented. This patch adds these board levle compatible properties into device tree binding document. Signed-off-by: Bryan Wu <pengw@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: paz00: enable HDMI portStephen Warren2013-01-281-4/+16
| | | | Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: ventana: enable HDMI portStephen Warren2013-01-281-4/+16
| | | | Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: seaboard: enable HDMI portStephen Warren2013-01-281-3/+15
| | | | Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: trimslice: add gpio-poweroff node to DTStephen Warren2013-01-281-0/+10
| | | | | | | ... and disable tri-state from the pingroup that contains the poweroff GPIO. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: DT: tegra: Unify the description of Tegra20 boardsBryan Wu2013-01-283-3/+3
| | | | | | | Use engineering name 'Tegra20' instead of 'Tegra2' Signed-off-by: Bryan Wu <pengw@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: dts: add aliases and DMA requestor for serial controllerLaxman Dewangan2013-01-282-10/+51
| | | | | | | | | | | | | Add APB DMA requestor and serial aliases for serial controller. There will be two serial driver i.e. 8250 based simple serial driver and APB DMA based serial driver for higher baudrate and performace. The simple serial driver get enabled with compatible nvidia,tegra20-uart and APB DMA based driver will get enabled with compatible nvidia,tegra20-hsuart. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra30: tegra30 gpio is not compatible with tegra20 gpioLaxman Dewangan2013-01-281-1/+1
| | | | | | | | | | tegra30 gpio controller is not compatible with the tegra20 due to their bank stride i.e. Tegra20 bank stride is 0x80 where Tegra30 bank stride is 0x100. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> [swarren: fixed typo syntax error] Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: Add initial support for Tegra114 SoC.Hiroshi Doyu2013-01-284-0/+60
| | | | | | | Add new Tegra 114 SoC support. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: dt: tegra114: Add new board, PlutoHiroshi Doyu2013-01-282-1/+23
| | | | | | | Add a new evaluation board, Pluto for Tegra 114 family. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: dt: tegra114: Add new board, DalmoreHiroshi Doyu2013-01-282-1/+23
| | | | | | | Add a new evaluation board, Dalmore for Tegra 114 family. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: dt: tegra114: Add new SoC base, Tegra114 SoCHiroshi Doyu2013-01-281-0/+114
| | | | | | | | Initial support for Tegra 114 SoC. This is expected to be included in the board DTS files, Tegra 114 SoC based evaluation board family. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: fuse: Add chip ID Tegra114 0x35Hiroshi Doyu2013-01-281-0/+1
| | | | | | | Add tegra_chip_id TEGRA114 0x35 Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Merge branch 'for-3.9/scu-base-rework' into for-3.9/soc-t114Stephen Warren2013-01-2812-68/+141
|\ | | | | | | | | Conflicts: arch/arm/mach-tegra/platsmp.c
| * ARM: OMAP: Make use of available scu_a9_get_base() interfaceSantosh Shilimkar2013-01-282-2/+1
| | | | | | | | | | | | | | | | Drop the define and make use of scu_a9_get_base() which reads the physical address of SCU from CP15 register. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: Skip scu_enable(scu_base) if not Cortex A9Hiroshi Doyu2013-01-281-3/+2
| | | | | | | | | | | | | | | | Skip scu_enable(scu_base) if CPU is not Cortex A9 with SCU. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: Add API to detect SCU base address from CP15Hiroshi Doyu2013-01-281-0/+17
| | | | | | | | | | | | | | | | Add API to detect SCU base address from CP15. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: Use DT /cpu node to detect number of CPU coreHiroshi Doyu2013-01-281-15/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | SCU based detection only works with Cortex-A9 MP and it doesn't support ones with multiple clusters. The only way to detect number of CPU core correctly is with DT /cpu node. Tegra SoCs decided to use DT detection as the only way and to not use SCU based detection at all. Even if DT /cpu node based detection fails, it continues with a single core Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: Add CPU nodes to Tegra30 device treeHiroshi Doyu2013-01-281-0/+29
| | | | | | | | | | | | | | | | Add CPU node for Tegra30. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Reviewed-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: Add CPU nodes to Tegra20 device treeHiroshi Doyu2013-01-281-0/+17
| | | | | | | | | | | | | | | | Add CPU node for Tegra20. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Reviewed-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * Merge remote-tracking branch 'korg_arm-soc/depends/rmk-perf' into ↵Stephen Warren2013-01-286-49/+75
| |\ | | | | | | | | | for-3.9/scu-base-rework
| | * ARM: perf: simplify __hw_perf_event_init err handlingMark Rutland2013-01-181-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently __hw_perf_event_init has an err variable that's ignored right until the end, where it's initialised, conditionally set, and then used as a boolean flag deciding whether to return another error code. This patch removes the err variable and simplifies the associated error handling logic. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| | * ARM: perf: remove unnecessary checks for idx < 0Mark Rutland2013-01-181-8/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We currently check for hwx->idx < 0 in armpmu_read and armpmu_del unnecessarily. The only case where hwc->idx < 0 is when armpmu_add fails, in which case the event's state is set to PERF_EVENT_STATE_INACTIVE. The perf core will not attempt to read from an event in PERF_EVENT_STATE_INACTIVE, and so the check in armpmu_read is unnecessary. Similarly, if perf core cannot add an event it will not attempt to delete it, so the WARN_ON in armpmu_del is unnecessary. This patch removes these two redundant checks. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| | * ARM: perf: handle armpmu_register failingMark Rutland2013-01-181-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently perf_pmu_register may fail for several reasons (e.g. being unable to allocate memory for the struct device it associates with each PMU), and while any error is propagated by armpmu_register, it is ignored by cpu_pmu_device_probe and not propagated to the caller. This also results in a leak of a struct arm_pmu. This patch adds cleanup if armpmu_register fails, and updates the info messages to better differentiate this type of failure from a failure to probe the PMU type from the hardware or dt. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| | * ARM: perf: don't pretend to support counting of L1I writesWill Deacon2013-01-163-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARM has a harvard cache architecture and cannot write directly to the I-side. This patch removes the L1I write events from the cache map (which previously returned *read* events in many cases). Reported-by: Mike Williams <michael.williams@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| | * ARM: perf: remove redundant NULL check on cpu_pmuWill Deacon2013-01-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | cpu_pmu has already been dereferenced before we consider invoking the ->reset function, so remove the redundant NULL check. Reported-by: Cong Ding <dinggnu@gmail.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| | * ARM: Use implementor and part defines from cputype.hChristoffer Dall2013-01-111-18/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of decoding implementor numbers, part numbers and Xscale architecture masks inline in the pmu probing function, use defines and accessor functions from cputype.h, which can also be shared by other subsystems, such as KVM. Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| | * ARM: Define CPU part numbers and implementorsChristoffer Dall2013-01-111-0/+33
| |/ | | | | | | | | | | | | | | | | Define implementor IDs, part numbers and Xscale architecture versions in cputype.h. Also create accessor functions for reading the implementor, part number, and Xscale architecture versions from the CPUID regiser. Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
* | ARM: tegra20: cpuidle: apply coupled cpuidle for powered-down modeJoseph Lo2013-01-285-9/+192
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "powered-down" cpuidle mode of Tegra20 needs the CPU0 be the last one core to go into this mode before other core. The coupled cpuidle framework can help to sync the MPCore to coupled state then go into "powered-down" idle mode together. The driver can just assume the MPCore come into "powered-down" mode at the same time. No need to take care if the CPU_0 goes into this mode along and only can put it into safe idle mode (WFI). The powered-down state of Tegra20 requires power gating both CPU cores. When the secondary CPU requests to enter powered-down state, it saves its own contexts and then enters WFI for waiting CPU0 in the same state. When the CPU0 requests powered-down state, it attempts to put the secondary CPU into reset to prevent it from waking up. Then power down both CPUs together and power off the cpu rail. Be aware of that, you may see the legacy power state "LP2" in the code which is exactly the same meaning of "CPU power down". Based on the work by: Colin Cross <ccross@android.com> Gary King <gking@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Colin Cross <ccross@android.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra20: flowctrl: add support for cpu_suspend_enter/exitJoseph Lo2013-01-282-5/+37
| | | | | | | | | | | | | | | | | | | | The flow controller can help CPU to go into suspend mode (powered-down state). When CPU go into powered-down state, it needs some careful settings before getting into and after leaving. The enter and exit functions do that by configuring appropriate mode for flow controller. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | clk: tegra20: Implementing CPU low-power function for tegra_cpu_car_opsJoseph Lo2013-01-281-0/+93
| | | | | | | | | | | | | | | | Implementing suspend, resume and rail_off_ready API for tegra_cpu_car_ops. These functions were used for CPU powered-down state maintenance. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra20: cpuidle: add powered-down state for secondary CPUJoseph Lo2013-01-284-4/+259
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The powered-down state of Tegra20 requires power gating both CPU cores. When the secondary CPU requests to enter powered-down state, it saves its own contexts and then enters WFI. The Tegra20 had a limition to power down both CPU cores. The secondary CPU must waits for CPU0 in powered-down state too. If the secondary CPU be woken up before CPU0 entering powered-down state, then it needs to restore its CPU states and waits for next chance. Be aware of that, you may see the legacy power state "LP2" in the code which is exactly the same meaning of "CPU power down". Based on the work by: Colin Cross <ccross@android.com> Gary King <gking@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra: add pending SGI checking APIJoseph Lo2013-01-282-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "powered-down" CPU idle mode of Tegra cut off the vdd_cpu rail, it include the power of GIC. That caused the SGI (Software Generated Interrupt) been lost. Because the SGI can't wake up the CPU that in the "powered-down" CPU idle mode. We need to check if there is any pending SGI when go into "powered-down" CPU idle mode. This is important especially when applying the coupled cpuidle framework into "power-down" cpuidle dirver. Because the coupled cpuidle framework may have the chance that misses IPI_SINGLE_FUNC handling sometimes. For the PPI or SPI, something like the legacy peripheral interrupt. It still can be maintained by Tegra legacy interrupt controller. If there is any pending PPI or SPI when CPU in "powered-down" CPU idle mode. The CPU can be woken up immediately. So we don't need to take care the same situation for PPI or SPI. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | usb: host: tegra: don't touch EMC clockStephen Warren2013-01-281-17/+0
| | | | | | | | | | | | | | | | | | Clock "emc" is for the External Memory Controller. The USB driver has no business touching this clock directly. Remove the code that does so. Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Acked-by: Alan Stern <stern@rowland.harvard.edu> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | usb: add APIs to access host registers from Tegra PHYVenu Byravarasu2013-01-283-43/+59
| | | | | | | | | | | | | | | | | | | | As Tegra PHY driver needs to access one of the host registers, added few APIs. Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> Acked-by: Alan Stern <stern@rowland.harvard.edu> [swarren: moved assignment of phy->is_ulpi_phy to previous patch.] Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | USB: PHY: tegra: Get rid of instance number to differentiate PHY typeVenu Byravarasu2013-01-282-14/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra20 USB has 3 PHY instances: Instance 1 and 3 are UTMI. Instance 2 is ULPI. As instance number was used to differentiate ULPI from UTMI, used DT param to get this info and processed accordingly. Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> Acked-by: Felipe Balbi <balbi@ti.com> [swarren: moved assignment of phy->is_ulpi_phy into this patch out of next patch.] Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | USB: PHY: tegra: get rid of instance number to differentiate legacy controllerVenu Byravarasu2013-01-282-17/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | Tegra20 USB has 3 PHY instances. Instance 0 is based on legacy PHY interface and other two are standard interfaces. As instance number was used to differentiate legacy from standard interfaces, used DT param to get this info and processed accordingly. Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> Acked-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra: add clocks properties to USB PHY nodesStephen Warren2013-01-281-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | The patch to add USB PHY nodes to device tree was written before Tegra supported the clocks property in device tree. Now that it does, add the required clocks properties to these nodes. This will allow all clk_get_sys() calls in tegra_usb_phy.c to be replaced by clk_get(phy->dev, clock_name), as part of converting the PHY driver to a platform driver. Acked-by: Venu Byravarasu <vbyravarasu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra: add DT nodes for Tegra USB PHYVenu Byravarasu2013-01-283-0/+37
| | | | | | | | | | | | | | | | | | Add DT nodes for Tegra USB PHY along with related documentation. Also added a phandle property to controller DT node, for referring to connected PHY instance. Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | usb: phy: remove unused APIs from Tegra PHY.Venu Byravarasu2013-01-282-17/+0
| | | | | | | | | | | | | | | | As tegra_usb_phy_clk_disable/enable() are not being used, removing them. Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | usb: host: tegra: Resetting PORT0 based on information received via DT.Venu Byravarasu2013-01-281-1/+5
| | | | | | | | | | | | | | | | | | | | | | Tegra USB host driver is using port instance number, to handle some of the hardware issues on SOC e.g. reset PORT0 twice etc. As instance number based handling looks ugly, making use of information passed through DT for achieving this. Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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