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* ARM: memblock: setup lowmem mappings using memblockRussell King2010-10-281-20/+29
| | | | | | | | | | | | | | | | | | | | | | Use memblock information to setup lowmem mappings rather than the membank array. This allows platforms to manipulate the memblock information during initialization to reserve (and remove) memory from the kernel's view of memory - and thus allowing platforms to setup their own private mappings for this memory without causing problems with multiple aliasing mappings: size = min(size, SZ_2M); base = memblock_alloc(size, min(align, SZ_2M)); memblock_free(base, size); memblock_remove(base, size); This is needed because multiple mappings of regions with differing attributes (sharability, type, cache) are not permitted with ARMv6 and above. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: memblock: move meminfo into find_limits directlyRussell King2010-10-281-4/+4
| | | | | | | | bootmem_init() no longer makes several uses of the membank information, so move this into the one remaining called function which does use it. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: memblock: convert free_highpages() to use memblockRussell King2010-10-281-5/+39
| | | | | | | | Free the high pages using the memblock memory lists - and more importantly, exclude any memblock allocations in highmem from the free'd memory. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: move freeing of highmem pages out of mem_init()Russell King2010-10-281-10/+17
| | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: memblock: convert memory detail printing to use memblockRussell King2010-10-281-3/+6
| | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: memblock: use memblock to free memory into arm_bootmem_init()Russell King2010-10-281-17/+25
| | | | | | | Switch arm_bootmem_init() to use memblock instead of membank to free memory into bootmem. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: memblock: use memblock when initializing memory allocatorsRussell King2010-10-281-9/+16
| | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: ensure membank array is always sortedRussell King2010-10-282-10/+10
| | | | | | | | This was missing from the noMMU code, so there was the possibility of things not working as expected if out of order memory information was passed. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 6466/1: implement flush_icache_all for the rest of the CPUsMika Westerberg2010-10-2818-0/+225
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 81d11955bf0 ("ARM: 6405/1: Handle __flush_icache_all for CONFIG_SMP_ON_UP") added a new function to struct cpu_cache_fns: flush_icache_all(). It also implemented this for v6 and v7 but not for v5 and backwards. Without the function pointer in place, we will be calling wrong cache functions. For example with ep93xx we get following: Unable to handle kernel paging request at virtual address ee070f38 pgd = c0004000 [ee070f38] *pgd=00000000 Internal error: Oops: 80000005 [#1] PREEMPT last sysfs file: Modules linked in: CPU: 0 Not tainted (2.6.36+ #1) PC is at 0xee070f38 LR is at __dma_alloc+0x11c/0x2d0 pc : [<ee070f38>] lr : [<c0032c8c>] psr: 60000013 sp : c581bde0 ip : 00000000 fp : c0472000 r10: c0472000 r9 : 000000d0 r8 : 00020000 r7 : 0001ffff r6 : 00000000 r5 : c0472400 r4 : c5980000 r3 : c03ab7e0 r2 : 00000000 r1 : c59a0000 r0 : c5980000 Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel Control: c000717f Table: c0004000 DAC: 00000017 Process swapper (pid: 1, stack limit = 0xc581a270) [<c0032c8c>] (__dma_alloc+0x11c/0x2d0) [<c0032e5c>] (dma_alloc_writecombine+0x1c/0x24) [<c0204148>] (ep93xx_pcm_preallocate_dma_buffer+0x44/0x60) [<c02041c0>] (ep93xx_pcm_new+0x5c/0x88) [<c01ff188>] (snd_soc_instantiate_cards+0x8a8/0xbc0) [<c01ff59c>] (soc_probe+0xfc/0x134) [<c01adafc>] (platform_drv_probe+0x18/0x1c) [<c01acca4>] (driver_probe_device+0xb0/0x16c) [<c01ac284>] (bus_for_each_drv+0x48/0x84) [<c01ace90>] (device_attach+0x50/0x68) [<c01ac0f8>] (bus_probe_device+0x24/0x44) [<c01aad7c>] (device_add+0x2fc/0x44c) [<c01adfa8>] (platform_device_add+0x104/0x15c) [<c0015eb8>] (simone_init+0x60/0x94) [<c0021410>] (do_one_initcall+0xd0/0x1a4) __dma_alloc() calls (inlined) __dma_alloc_buffer() which ends up calling dmac_flush_range(). Now since the entries in the arm920_cache_fns are shifted by one, we jump into address 0xee070f38 which is actually next instruction after the arm920_cache_fns structure. So implement flush_icache_all() for the rest of the supported CPUs using a generic 'invalidate I cache' instruction. Signed-off-by: Mika Westerberg <mika.westerberg@iki.fi> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 6464/2: fix spinlock recursion in adjust_pte()Mika Westerberg2010-10-281-2/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When running following code in a machine which has VIVT caches and USE_SPLIT_PTLOCKS is not defined: fd = open("/etc/passwd", O_RDONLY); addr = mmap(NULL, 4096, PROT_READ, MAP_SHARED, fd, 0); addr2 = mmap(NULL, 4096, PROT_READ, MAP_SHARED, fd, 0); v = *((int *)addr); we will hang in spinlock recursion in the page fault handler: BUG: spinlock recursion on CPU#0, mmap_test/717 lock: c5e295d8, .magic: dead4ead, .owner: mmap_test/717, .owner_cpu: 0 [<c0026604>] (unwind_backtrace+0x0/0xec) [<c014ee48>] (do_raw_spin_lock+0x40/0x140) [<c0027f68>] (update_mmu_cache+0x208/0x250) [<c0079db4>] (__do_fault+0x320/0x3ec) [<c007af7c>] (handle_mm_fault+0x2f0/0x6d8) [<c0027834>] (do_page_fault+0xdc/0x1cc) [<c00202d0>] (do_DataAbort+0x34/0x94) This comes from the fact that when USE_SPLIT_PTLOCKS is not defined, the only lock protecting the page tables is mm->page_table_lock which is already locked before update_mmu_cache() is called. Signed-off-by: Mika Westerberg <mika.westerberg@iki.fi> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: fix memblock breakageRussell King2010-10-272-10/+1
| | | | | | | | | | | | | Will says: | Commit e63075a3 removed the explicit MEMBLOCK_REAL_LIMIT #define | and introduced the requirement that arch code calls | memblock_set_current_limit to ensure that the __va macro can | be used on physical addresses returned from memblock_alloc. Unfortunately, ARM was missed out of this change. Fix this. Reported-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 6465/1: Fix data abort accessing proc_info from __lookup_processor_typeTony Lindgren2010-10-271-0/+1
| | | | | | | | | | | | | | | | Commit 5085f3ff458521045f7e43da62b8c30ea7df2e82 added better support for CONFIG_HOTPLUG_CPU by keeping proc_info around. However, depending on the Kconfig options selected, this can make the booting fail mysteriously early on. Turns out a data abort can happen in __lookup_processor in ldmia r5 {r3, r4}. When it happens the address loaded to r5 is not aligned. Fix the problem by aligning proc_info. Reported-by: Anand Gadiyar <gadiyar@ti.com> Tested-by: Anand Gadiyar <gadiyar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 6460/1: ixp2000: fix type of ixp2000_timer_interruptUwe Kleine-König2010-10-271-1/+1
| | | | | | | | | This fixes a build warning existing since at least 2.6.30: arch/arm/mach-ixp2000/core.c:217: warning: initialization from incompatible pointer type Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 6449/1: Fix for compiler warning of uninitialized variable.Marcelo Roberto Jimenez2010-10-271-3/+2
| | | | | | | | | | ARM: mach-sa1100: Fix for compiler warning of uninitialized variable. This is a fix for the compiler warning: 'new_ppcr' may be used uninitialized in this function. Signed-off-by: Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 6445/1: fixup TCM memory typesLinus Walleij2010-10-271-7/+7
| | | | | | | | | | | | | After Santosh's fixup of the generic MT_MEMORY and MT_MEMORY_NONCACHED I add this fix to the TCM memory types. The main change is that the ITCM memory is L_PTE_WRITE and DOMAIN_KERNEL which works just fine. The changed to the DTCM is just cosmetic to fit with surrounding code. Cc: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: Rickard Andersson <rickard.andersson@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* fix braino in fs: do not assign default i_ino in new_inodeAl Viro2010-10-261-1/+1
| | | | | | | | | | | usbfs_get_inode() is something completely different... Bogosity introduced by commit 85fe4025c616 ("fs: do not assign default i_ino in new_inode"). Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Cc: Christoph Hellwig <hch@lst.de> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Merge branch 'drm-core-next' of ↵Linus Torvalds2010-10-26212-11671/+18747
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6 * 'drm-core-next' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (476 commits) vmwgfx: Implement a proper GMR eviction mechanism drm/radeon/kms: fix r6xx/7xx 1D tiling CS checker v2 drm/radeon/kms: properly compute group_size on 6xx/7xx drm/radeon/kms: fix 2D tile height alignment in the r600 CS checker drm/radeon/kms/evergreen: set the clear state to the blit state drm/radeon/kms: don't poll dac load detect. gpu: Add Intel GMA500(Poulsbo) Stub Driver drm/radeon/kms: MC vram map needs to be >= pci aperture size drm/radeon/kms: implement display watermark support for evergreen drm/radeon/kms/evergreen: add some additional safe regs v2 drm/radeon/r600: fix tiling issues in CS checker. drm/i915: Move gpu_write_list to per-ring drm/i915: Invalidate the to-ring, flush the old-ring when updating domains drm/i915/ringbuffer: Write the value passed in to the tail register agp/intel: Restore valid PTE bit for Sandybridge after bdd3072 drm/i915: Fix flushing regression from 9af90d19f drm/i915/sdvo: Remove unused encoding member i915: enable AVI infoframe for intel_hdmi.c [v4] drm/i915: Fix current fb blocking for page flip drm/i915: IS_IRONLAKE is synonymous with gen == 5 ... Fix up conflicts in - drivers/gpu/drm/i915/{i915_gem.c, i915/intel_overlay.c}: due to the new simplified stack-based kmap_atomic() interface - drivers/gpu/drm/vmwgfx/vmwgfx_drv.c: added .llseek entry due to BKL removal cleanups.
| * vmwgfx: Implement a proper GMR eviction mechanismThomas Hellstrom2010-10-279-160/+252
| | | | | | | | | | | | | | | | | | | | Use Ben's new range manager hooks to implement a manager for GMRs that manages ids rather than ranges. This means we can use the standard TTM code for binding, unbinding and eviction. Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
| * drm/radeon/kms: fix r6xx/7xx 1D tiling CS checker v2Alex Deucher2010-10-271-0/+3
| | | | | | | | | | | | | | | | | | | | broken by: drm/radeon/r600: fix tiling issues in CS checker. v2: only apply it to 1D tiling case. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
| * drm/radeon/kms: properly compute group_size on 6xx/7xxAlex Deucher2010-10-262-6/+10
| | | | | | | | | | | | | | | | Needed for tiled surfaces. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Cc: stable@kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
| * drm/radeon/kms: fix 2D tile height alignment in the r600 CS checkerAlex Deucher2010-10-261-2/+2
| | | | | | | | | | | | | | | | | | | | macro tile heights are aligned to num channels, not num banks. Noticed by Dave Airlie. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Cc: stable@kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
| * drm/radeon/kms/evergreen: set the clear state to the blit stateAlex Deucher2010-10-264-54/+65
| | | | | | | | | | | | | | | | | | | | | | The hw stores a default clear state for registers in the context range that can be initialized when the CP is set up. Set the blit state as the default clear state and use the CLEAR_STATE packet to load the blit state rather than loading it from an IB. This reduces overhead when doing bo moves using the 3D engine. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
| * drm/radeon/kms: don't poll dac load detect.Dave Airlie2010-10-261-0/+10
| | | | | | | | | | | | This is slightly destructive, cpu intensive and can cause lockups. Signed-off-by: Dave Airlie <airlied@redhat.com>
| * gpu: Add Intel GMA500(Poulsbo) Stub DriverLee, Chun-Yi2010-10-265-1/+81
| | | | | | | | | | | | | | | | | | | | | | Currently, there have no GMA500(Poulsbo) native video driver to support intel opregion. So, use this stub driver to enable the acpi backlight control sysfs entry files by requrest acpi_video_register. [airlied: fix warnings] Signed-off-by: Lee, Chun-Yi <jlee@novell.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
| * drm/radeon/kms: MC vram map needs to be >= pci aperture sizeAlex Deucher2010-10-261-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The vram map in the radeon memory controller needs to be >= the pci aperture size. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=28402 The problematic cards in the above bug have 64 MB of vram, but the pci aperture is 128 MB and the MC vram map was only 64 MB. This can lead to hangs. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Cc: stable@kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
| * drm/radeon/kms: implement display watermark support for evergreenAlex Deucher2010-10-262-1/+449
| | | | | | | | | | | | | | | | | | | | Improper display watermarks can result in underflow to the display controllers which can cause flickering or other artifacts. This patch implements display watermark support and line buffer allocation for evergreen asics. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
| * drm/radeon/kms/evergreen: add some additional safe regs v2Alex Deucher2010-10-262-1/+9
| | | | | | | | | | | | | | | | | | | | These are needed for enabling dynamic GPR allocation in the shaders in the userspace acceleration drivers. v2: fix typo in reg name Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
| * drm/radeon/r600: fix tiling issues in CS checker.Dave Airlie2010-10-262-10/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The CS checker had some incorrect alignment requirements for 2D surfaces, this made rendering to mipmap levels that were 2D broken. Also the CB height was being worked out from the BO size, this doesn't work at all when rendering mipmap levels, instead we work out what height userspace wanted from slice max and use that to check it fits inside the BO, however the DDX send the wrong slice max for an unaligned buffer so we have to workaround for that even though its a userspace bug. Reviewed-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
| * Merge remote branch 'intel/drm-intel-next' of ../drm-next into drm-core-nextDave Airlie2010-10-2629-1366/+1979
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'intel/drm-intel-next' of ../drm-next: (63 commits) drm/i915: Move gpu_write_list to per-ring drm/i915: Invalidate the to-ring, flush the old-ring when updating domains drm/i915/ringbuffer: Write the value passed in to the tail register agp/intel: Restore valid PTE bit for Sandybridge after bdd3072 drm/i915: Fix flushing regression from 9af90d19f drm/i915/sdvo: Remove unused encoding member i915: enable AVI infoframe for intel_hdmi.c [v4] drm/i915: Fix current fb blocking for page flip drm/i915: IS_IRONLAKE is synonymous with gen == 5 drm/i915: Enable SandyBridge blitter ring drm/i915/ringbuffer: Remove broken intel_fill_struct() drm/i915/ringbuffer: Fix emit batch buffer regression from 8187a2b drm/i915: Copy the updated reloc->presumed_offset back to the user drm/i915: Track objects in global active list (as well as per-ring) drm/i915: Simplify most HAS_BSD() checks drm/i915: cache the last object lookup during pin_and_relocate() drm/i915: Do interrupible mutex lock first to avoid locking for unreference drivers: gpu: drm: i915: Fix a typo. agp/intel: Also add B43.1 to list of supported devices drm/i915: rearrange mutex acquisition for pread ...
| | * drm/i915: Move gpu_write_list to per-ringChris Wilson2010-10-244-26/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ... to prevent flush processing of an idle (or even absent) ring. This fixes a regression during suspend from 87acb0a5. Reported-and-tested-by: Alexey Fisher <bug-track@fisher-privat.net> Tested-by: Peter Clifton <pcjc2@cam.ac.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915: Invalidate the to-ring, flush the old-ring when updating domainsChris Wilson2010-10-231-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the object has been written to by the gpu it remains on the ring until its flush has been retired. However, when the object is moving to the ring and the associated cache needs to be invalidated, we need to perform the flush on the target ring, not the one it came from (which is NULL in the reported case and so the flush was entirely absent). Reported-by: Peter Clifton <pcjc2@cam.ac.uk> Reported-and-tested-by: Alexey Fisher <bug-track@fisher-privat.net> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915/ringbuffer: Write the value passed in to the tail registerChris Wilson2010-10-222-16/+16
| | | | | | | | | | | | | | | | | | | | | | | | This should fix the error along the reset path were we tried to clear the tail register by setting it to 0, but were in fact setting it to the current value and complaining when it did not reset to 0. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * agp/intel: Restore valid PTE bit for Sandybridge after bdd3072Chris Wilson2010-10-221-3/+3
| | | | | | | | | | | | | | | | | | | | | In cleaning up the mask functions in bdd3072, the setting of the PTE valid bit was dropped for Sandybridge. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915: Fix flushing regression from 9af90d19fChris Wilson2010-10-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Whilst moving the code around in 9af90d19f, I dropped the or'ing in of new write domains which would zero out the write domain for a render target if later reused as a source later in the batch. This meant that we might drop a required flush before reading from the render target. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=31043 Reported-by: xunx.fang@intel.com Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915/sdvo: Remove unused encoding memberChris Wilson2010-10-221-23/+22
| | | | | | | | | | | | | | | | | | | | | This block is only used when detecting whether the connector is HDMI and never again, so scope the variable to the detection routine. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * i915: enable AVI infoframe for intel_hdmi.c [v4]David Härdeman2010-10-224-105/+130
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables the sending of AVI infoframes in drivers/gpu/drm/i915/intel_hdmi.c. My receiver currently loses sync when the HDMI output on my computer (DG45FC motherboard) is switched from 800x600 (the BIOS resolution) to 1920x1080 as part of the boot. Fixable by switching inputs on the receiver a couple of times. With this patch, my receiver has not lost sync yet (> 40 tries). Fourth version, now based on drm-intel-next from: git://git.kernel.org/pub/scm/linux/kernel/git/ickle/drm-intel.git Two questions still remain: I'm assuming that the sdvo hardware also stores a header ECC byte in the MSB of the first dword - is this correct? Does the SDVOB and SDVOC handling in intel_hdmi_set_avi_infoframe() look correct? Signed-off-by: David Härdeman <david@hardeman.nu> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915: Fix current fb blocking for page flipChia-I Wu2010-10-211-5/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Block execbuffer for the fb to be flipped away, not the one that is to be flipped in. [ickle: rewritten for -next] Signed-off-by: Chia-I Wu <olvaffe@gmail.com> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org> Acked-by: Kristian Høgsberg <krh@bitplanet.net> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915: IS_IRONLAKE is synonymous with gen == 5Chris Wilson2010-10-218-22/+18
| | | | | | | | | | | | | | | | | | | | | So remove the redundant bit in the capabilities block and s/IS_IRONLAKE/IS_GEN5/. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915: Enable SandyBridge blitter ringChris Wilson2010-10-2111-63/+175
| | | | | | | | | | | | | | | | | | | | | | | | Based on an original patch by Zhenyu Wang, this initializes the BLT ring for SandyBridge and enables support for user execbuffers. Cc: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915/ringbuffer: Remove broken intel_fill_struct()Chris Wilson2010-10-212-19/+0
| | | | | | | | | | | | | | | | | | | | | | | | ... before someone tries to use it. The code both calls intel_ring_begin/advance() and open-codes the bookkeeping performed by those two functions. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915/ringbuffer: Fix emit batch buffer regression from 8187a2bChris Wilson2010-10-211-1/+1
| | | | | | | | | | | | | | | | | | | | | In commit 8187a2b, the number of dwords used in the ringbuffer for executing the batch buffer was erroneously changed from 2 to 4. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915: Copy the updated reloc->presumed_offset back to the userChris Wilson2010-10-201-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the userspace driver is using a constant relocation array with a static buffer, they will pass the same relocation array back to the kernel. So we *do* need to update the presumed offset value in those relocations to reflect the current object so that they remain correct with future batchbuffers and we avoid the necessity of having to suspend execution and perform redundant relocations. Fixes the regression introduced by 12f889c for applications using absolute addressing on trees of buffer (i.e. the current consumers of libdrm_intel.so). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=30996 Reported-by: Wang, Jinjin <jinjin.wang@intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915: Track objects in global active list (as well as per-ring)Chris Wilson2010-10-205-96/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To handle retirements, we need per-ring tracking of active objects. To handle evictions, we need global tracking of active objects. As we enable more rings, rebuilding the global list from the individual per-ring lists quickly grows tiresome and overly complicated. Tracking the active objects in two lists is the lesser of two evils. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915: Simplify most HAS_BSD() checksChris Wilson2010-10-203-37/+22
| | | | | | | | | | | | | | | | | | | | | ... by always initialising the empty ringbuffer it is always then safe to check whether it is active. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915: cache the last object lookup during pin_and_relocate()Chris Wilson2010-10-201-171/+144
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The most frequent relocation within a batchbuffer is a contiguous sequence of vertex buffer relocations, for which we can virtually eliminate the drm_gem_object_lookup() overhead by caching the last handle to object translation. In doing so we refactor the pin and relocate retry loop out of do_execbuffer into its own helper function and so improve the error paths. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915: Do interrupible mutex lock first to avoid locking for unreferenceChris Wilson2010-10-191-113/+93
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | One of the primarily consumers of the i915 driver is X, a large signal driven application. Frequently when writing into the buffers, there is a pending signal which causes us not to take the interruptible lock but then we need to take that same lock around the object unreference. By rearranging the code to do the interruptible lock as the first check, we can avoid the frequent additional locking around the unreference. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drivers: gpu: drm: i915: Fix a typo.Andrea Gelmini2010-10-191-1/+1
| | | | | | | | | | | | | | | | | | | | | "userpace" -> "userspace" Signed-off-by: Andrea Gelmini <andrea.gelmini@gelma.net> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * agp/intel: Also add B43.1 to list of supported devicesChris Wilson2010-10-191-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | This was a missing piece from 41a5142 that dropped recognition of the AGP module for the second B43 variant. Reported-by: Stefan Bader <stefan.bader@canonical.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org
| | * drm/i915: rearrange mutex acquisition for preadChris Wilson2010-10-191-56/+43
| | | | | | | | | | | | | | | | | | ... to avoid the double acquisition along fast[er] paths. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915: Rearrange acquisition of mutex during pwriteChris Wilson2010-10-191-105/+65
| | | | | | | | | | | | | | | | | | | | | | | | ... to avoid reacquiring it to drop the object reference count on exit. Note we have to make sure we now drop (and reacquire) the lock around acquiring the mm semaphore on the slow paths. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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