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* [ARM] Feroceon: L2 cache supportLennert Buytenhek2008-06-226-1/+395
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the unified Feroceon L2 cache controller as found in e.g. the Marvell Kirkwood and Marvell Discovery Duo families of ARM SoCs. Note that: - Page table walks are outer uncacheable on Kirkwood and Discovery Duo, since the ARMv5 spec provides no way to indicate outer cacheability of page table walks (specifying it in TTBR[4:3] is an ARMv6+ feature). This requires adding L2 cache clean instructions to proc-feroceon.S (dcache_clean_area(), set_pte()) as well as to tlbflush.h ({flush,clean}_pmd_entry()). The latter case is handled by defining a new TLB type (TLB_FEROCEON) which is almost identical to the v4wbi one but provides a TLB_L2CLEAN_FR flag. - The Feroceon L2 cache controller supports L2 range (i.e. 'clean L2 range by MVA' and 'invalidate L2 range by MVA') operations, and this patch uses those range operations for all Linux outer cache operations, as they are faster than the regular per-line operations. L2 range operations are not interruptible on this hardware, which avoids potential livelock issues, but can be bad for interrupt latency, so there is a compile-time tunable (MAX_RANGE_SIZE) which allows you to select the maximum range size to operate on at once. (Valid range is between one cache line and one 4KiB page, and must be a multiple of the line size.) Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
* [ARM] Feroceon: L1 cache range operation supportStanislav Samsonov2008-06-222-6/+69
| | | | | | | | | | | This patch adds support for the L1 D cache range operations that are supported by the Marvell Discovery Duo and Marvell Kirkwood ARM SoCs. Signed-off-by: Stanislav Samsonov <samsonov@marvell.com> Acked-by: Saeed Bishara <saeed@marvell.com> Reviewed-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
* [ARM] Loki: add defconfigLennert Buytenhek2008-06-221-0/+1147
| | | | Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
* [ARM] add Marvell Loki (88RC8480) SoC supportLennert Buytenhek2008-06-2223-1/+975
| | | | | | | | | | | | | | The Marvell Loki (88RC8480) is an ARM SoC based on a Feroceon CPU core running at between 400 MHz and 1.0 GHz, and features a 64 bit DDR controller, 512K of internal SRAM, two x4 PCI-Express ports, two Gigabit Ethernet ports, two 4x SAS/SATA controllers, two UARTs, two TWSI controllers, and IDMA/XOR engines. This patch adds support for the Marvell LB88RC8480 Development Board, enabling the use of the PCIe interfaces, the ethernet interfaces, the TWSI interfaces and the UARTs. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
* [ARM] Orion: add a separate BRIDGE_INT_TIMER1_CLR defineKe Wei2008-06-222-3/+4
| | | | | | | | | | | | Some Feroceon-based SoCs have an MBUS bridge interrupt controller that requires writing a one instead of a zero to clear edge interrupt sources such as timer expiry. This patch adds a new BRIDGE_INT_TIMER1_CLR define, which platform code can set to either ~BRIDGE_INT_TIMER1 (write-zero-to-clear) or BRIDGE_INT_TIMER1 (write-one-to-clear) depending on the platform. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
* [ARM] Feroceon: allow more old Feroceon IDsKe Wei2008-06-221-2/+2
| | | | | | | | | | There are a couple more Feroceon-based SoCs out in the field that use different Variant and Architecture fields in their Main ID registers -- this patch tweaks the processor match/mask in proc-feroceon.S to catch those SoCs as well. Signed-off-by: Ke Wei <kewei@marvell.com> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
* [ARM] Feroceon: catch other Feroceon CPU IDs in head.SNicolas Pitre2008-06-221-2/+2
| | | | | | | | | Tweak the Feroceon match/mask in arch/arm/boot/compressed/head.S to match a couple of newer Feroceon cores (such as the 88fr571vd with CPU ID 0x56155710, and the 88fr131 with CPU ID 0x56251310) as well. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
* [ARM] Feroceon: speed up flushing of the entire cacheNicolas Pitre2008-06-221-11/+48
| | | | | | | | | | | | | | Flushing the L1 D cache with a test/clean/invalidate loop is very easy in software, but it is not the quickest way of doing it, as there is a lot of overhead involved in re-scanning the cache from the beginning every time we hit a dirty line. This patch makes proc-feroceon.S use "clean+invalidate by set/way" loops according to possible cache configuration of Feroceon CPUs (either direct-mapped or 4-way set associative). Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
* [ARM] Orion: nuke orion5x_{read,write}Lennert Buytenhek2008-06-227-62/+59
| | | | | | Nuke the Orion-specific orion5x_{read,write} wrappers. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
* [ARM] Orion: use linux/serial_reg.h for Orion uncompress.hLennert Buytenhek2008-06-221-7/+22
| | | | Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
* [ARM] Orion: add Maxtor Shared Storage II supportSylver Bruneau2008-06-223-0/+277
| | | | | | | This patch adds support for the Maxtor Shared Storage II hardware. Signed-off-by: Sylver Bruneau <sylver.bruneau@googlemail.com> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
* [ARM] Orion: add Technologic Systems TS-78xx supportAlexander Clouter2008-06-223-0/+284
| | | | | Signed-off-by: Alexander Clouter <alex@digriz.org.uk> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
* [ARM] Orion: remove code duplication in TS209 and TS409 setup filesSylver Bruneau2008-06-225-239/+168
| | | | | Signed-off-by: Sylver Bruneau <sylver.bruneau@googlemail.com> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
* [ARM] Orion: add HP Media Vault mv2120 supportMartin Michlmayr2008-06-223-0/+201
| | | | Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
* [ARM] Orion: add Linksys WRT350N v2 supportLennert Buytenhek2008-06-223-0/+180
| | | | | | Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Tested-by: Dirk Teurlings <dirk@upexia.nl> Tested-by: Peter van Valderen <p.v.valderen@gmail.com>
* [ARM] Orion: add 88F5181L (Orion-VoIP) supportLennert Buytenhek2008-06-223-4/+9
| | | | | Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Acked-by: Russell King <linux@arm.linux.org.uk>
* [ARM] Orion: add QNAP TS-409 supportSylver Bruneau2008-06-223-0/+392
| | | | Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
* [ARM] Orion: implement power-off method for Kurobox ProSylver Bruneau2008-06-221-4/+143
| | | | | | | | | | This patch implements the communication with the microcontroller on the Kurobox Pro and Linkstation Pro/Live boards. This is allowing to send the commands needed to power-off the board correctly. Signed-off-by: Sylver Bruneau <sylver.bruneau@googlemail.com> Acked-by: Russell King <linux@arm.linux.org.uk> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
* [ARM] Orion: avoid setting ->force_phy_addrLennert Buytenhek2008-06-225-5/+0
| | | | | | | | | | | | | | | | The mv643xx_eth platform data field ->force_phy_addr only needs to be set if the passed-in ->phy_addr field is zero (to distinguish the case of not having specified a phy address (force_phy_addr = 0) from the case where a phy address of zero needs to be used (force_phy_addr = 1.)) Also, the ->force_phy_addr field will hopefully disappear in a future mv643xx_eth reorganisation. Therefore, this patch deletes the ->force_phy_addr field initialiser from all Orion board code. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
* [ARM] Orion: remove error printks in ->map_irq() implementationsLennert Buytenhek2008-06-222-4/+0
| | | | | | | | | | | | | | | If all PCI devices are working as expected, the error printks in the various implementations of ->map_irq() doesn't really provide any useful info. And if something is not working as expected, turning on pci=debug gives you more useful information than the printk calls in ->map_irq(), since the former also tells you which devices _did_ get IRQs successfully assigned. Therefore, delete these printks entirely. Spotted by Russell King. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Acked-by: Russell King <linux@arm.linux.org.uk>
* [ARM] Orion: rework MPP handlingLennert Buytenhek2008-06-2210-114/+376
| | | | | | | | | | | | Instead of having board code poke directly into the MPP configuration registers, and separately calling orion5x_gpio_set_valid_pins() to indicate which MPP pins can be used as GPIO pins, introduce a helper function for configuring the roles of each of the MPP pins, and have that helper function handle gpio validity internally. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Acked-by: Sylver Bruneau <sylver.bruneau@googlemail.com> Acked-by: Russell King <linux@arm.linux.org.uk>
* [ARM] Orion: move setting up PCIe WA window into PCIe setup pathLennert Buytenhek2008-06-225-25/+2
| | | | | | | | | | | | | | It makes no sense to do PCIe WA window setup in the individual board support files while the decision whether or not to use the PCIe WA access method is made in a different place, in the PCIe support code. This patch moves the configuration of a PCIe WA window from the individual Orion board support files to the central Orion PCIe support code. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Acked-by: Russell King <linux@arm.linux.org.uk>
* [ARM] Orion: move EHCI/I2C/UART peripheral init into board codeLennert Buytenhek2008-06-227-195/+240
| | | | | | | | | | | | | | | | | This patch moves initialisation of EHCI/I2C/UART platform devices from the common orion5x_init() into the board support code. The rationale behind this is that only the board support code knows whether certain peripherals have been brought out on the board, and not initialising peripherals that haven't been brought out is desirable for example: - to reduce user confusion (e.g. seeing both 'eth0' and 'eth1' appear while there is only one ethernet port on the board); and - to allow for future power savings (peripherals that have not been brought out can be clock gated off entirely). Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Acked-by: Russell King <linux@arm.linux.org.uk>
* [ARM] Orion: delete unused IO_SPACE_REMAP defineLennert Buytenhek2008-06-221-1/+0
| | | | | | | This define isn't used anywhere in the kernel tree -- nuke it. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Acked-by: Russell King <linux@arm.linux.org.uk>
* [ARM] Orion: top-level IRQs are level-triggeredLennert Buytenhek2008-06-221-1/+2
| | | | | | | | | | | | | | | Make it clear that Orion top-level IRQs are level-triggered. This means that we don't need an ->ack() handler, or at least, we don't need the ->ack() handler (or the acking part of the ->mask_ack() handler) to actually do anything. Given that, we might as well point our ->mask_ack() handler at the ->mask() handler instead of providing a dummy ->ack() handler, since providing a ->mask_ack() handler on level IRQ sources will prevent ->ack() from ever being called. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Acked-by: Russell King <linux@arm.linux.org.uk>
* [ARM] Feroceon: annotate 88fr531-vd CPU entriesLennert Buytenhek2008-06-221-4/+9
| | | | | | | | | Annotate the entries for the 88fr531-vd CPU core in arch/arm/boot/compressed/head.S and arch/arm/mm/proc-feroceon.S with the full name of the core. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Acked-by: Russell King <linux@arm.linux.org.uk>
* [ARM] Orion: DRAM mapping granularity is 64KiB, not 16MiBLennert Buytenhek2008-06-221-2/+2
| | | | | | | | | | | | | The DRAM base address and size fields in the CPU's MBUS bridge have 64KiB granularity, instead of the currently used 16MiB. Since all of the currently supported MBUS peripherals support 64KiB granularity as well, this patch changes the Orion address map code to stop rounding base addresses down and sizes up to multiples of 16MiB. Found by Ke Wei <kewei@marvell.com>. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Acked-by: Russell King <linux@arm.linux.org.uk>
* [ARM] Orion: make window setup a little more safeLennert Buytenhek2008-06-221-5/+18
| | | | | | | | | | | | | | Currently, Orion window setup uses hardcoded window indexes for each of the boot/cs0/cs1/cs2/PCIe WA windows. The static window allocation used can clash if board support code will ever attempt to configure both a dev2 and a PCIe WA window, as both of those use CPU mbus window #7 at present. This patch keeps track of the last used window, and opens subsequently requested windows sequentially, starting from 4. (Windows 0-3 are used as MEM/IO windows for the PCI/PCIe buses.) Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
* [ARM] Orion: fix various whitespace and coding style issuesLennert Buytenhek2008-06-228-141/+132
| | | | | | | | | | More cosmetic cleanup: - Replace 8-space indents by proper tab indents. - In structure initialisers, use a trailing comma for every member. - Collapse "},\n{" in structure initialiers to "}, {". Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Acked-by: Russell King <linux@arm.linux.org.uk>
* [ARM] cache align memset and memzeroNicolas Pitre2008-06-222-0/+90
| | | | | | | | This is a natural extension following the previous patch. Non Feroceon based targets are unchanged. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
* [ARM] cache align destination pointer when copying memory for some processorsNicolas Pitre2008-06-223-20/+19
| | | | | | | | | | | | | | | The implementation for memory copy functions on ARM had a (disabled) provision for aligning the source pointer before loading registers with data. Turns out that aligning the _destination_ pointer is much more useful, as the read side is already sufficiently helped with the use of preload. So this changes the definition of the CALGN() macro to target the destination pointer instead, and turns it on for Feroceon processors where the gain is very noticeable. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
* [ARM] fix cache alignment code in memset.SNicolas Pitre2008-06-221-1/+1
| | | | | | | This code is currently disabled, which explains why no one was affected. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
* [ARM] latencytop supportNicolas Pitre2008-06-222-4/+35
| | | | | | | | | | | | | | Available for !SMP only at the moment. From Russell: |Basically, if a thread is running on a CPU, thread_saved_fp() is invalid. |So, the question is: what guarantees do we have here that 'tsk' is not |running on another CPU? Signed-off-by: Nicolas Pitre <nico@marvell.com> Tested-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
* [ARM] Orion: update defconfig to 2.6.26-rc4Nicolas Pitre2008-06-221-122/+187
| | | | | Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
* Linux 2.6.26-rc7v2.6.26-rc7Linus Torvalds2008-06-201-1/+1
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* Merge git://git.kernel.org/pub/scm/linux/kernel/git/bart/ide-2.6Linus Torvalds2008-06-207-110/+21
|\ | | | | | | | | | | | | | | | | | | * git://git.kernel.org/pub/scm/linux/kernel/git/bart/ide-2.6: BAST: Remove old IDE driver pcmcia ide kingston compactflash's have a new manufacturer id pcmcia: add another pata/ide ID pcmcia: add an pata/ide ID ide: increase timeout in wait_drive_not_busy() palm_bk3710: fix resource management
| * BAST: Remove old IDE driverBen Dooks2008-06-203-98/+0
| | | | | | | | | | | | | | | | | | Remove the old BAST IDE driver, as we are now using the platform-pata support. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Cc: Jeff Garzik <jgarzik@pobox.com> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
| * pcmcia ide kingston compactflash's have a new manufacturer idChristophe Niclaes2008-06-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Up to now, Kingston compactflash cards (ab)used the Toshiba Manufacturer's ID, In their new CF cards, they use a new one. Let's the ide subsystem recognize CF cards with the new id. Signed-off-by: Christophe Niclaes <cniclaes@develtech.com> Acked-by: Philippe De Muyter <phdm@macqel.be> Cc: Alan Cox <alan@lxorguk.ukuu.org.uk> Cc: Dominik Brodowski <linux@dominikbrodowski.net> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
| * pcmcia: add another pata/ide IDKristoffer Ericson2008-06-202-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Addition of Transcend 1GB 45x id so that it is properly detected. [bart: fix typo in ide-cs's ID spotted by Alan Cox] Signed-off-by: William Peters <w1ll14@gmail.com> Signed-off-by: Kristoffer Ericson <Kristoffer_e1@hotmail.com> CC: Alan Cox <alan@lxorguk.ukuu.org.uk> CC: linux-ide@vger.kernel.org Signed-off-by: Dominik Brodowski <linux@dominikbrodowski.net> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
| * pcmcia: add an pata/ide IDMatt Reimer2008-06-202-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add an id for: product info: "M-Systems", "CF300", "" manfid: 0x000a, 0x0000 function: 4 (fixed disk) Signed-off-by: Matt Reimer <mreimer@vpop.net> CC: Alan Cox <alan@lxorguk.ukuu.org.uk> CC: linux-ide@vger.kernel.org Signed-off-by: Dominik Brodowski <linux@dominikbrodowski.net> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
| * ide: increase timeout in wait_drive_not_busy()Bartlomiej Zolnierkiewicz2008-06-201-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Some ATAPI devices take longer than the current max timeout value to become ready (i.e. TEAC DV-W28ECW takes 6 ms) so increase the timeout value to 10 ms. This fixes kernel.org bugzilla bug #10887: http://bugzilla.kernel.org/show_bug.cgi?id=10887 Reported-by: Masanari Iida <standby24x7@gmail.com> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
| * palm_bk3710: fix resource managementSergei Shtylyov2008-06-201-9/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | The driver expected a *virtual* address in the IDE platform device's memory resource and didn't request the memory region for the register block. Fix this taking into account the fact that DaVinci SoC devices are fixed-mapped to the virtual memory early and we can get their virtual addresses using IO_ADDRESS() macro, not having to call ioremap()... While at it, also do some cosmetic changes... Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
* | Merge branch 'for-linus' of ↵Linus Torvalds2008-06-205-141/+180
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/ieee1394/linux1394-2.6 * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/ieee1394/linux1394-2.6: ieee1394: Kconfig menu touch-up firewire: Kconfig menu touch-up firewire: deadline for PHY config transmission firewire: fw-ohci: unify printk prefixes firewire: fill_bus_reset_event needs lock protection firewire: fw-ohci: write selfIDBufferPtr before LinkControl.rcvSelfID firewire: fw-ohci: disable PHY packet reception into AR context firewire: fw-ohci: use of uninitialized data in AR handler firewire: don't panic on invalid AR request buffer
| * | ieee1394: Kconfig menu touch-upStefan Richter2008-06-191-52/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename and reorder some prompts and modify some help texts. The result: -------------------- IEEE 1394 (FireWire) support -------------------- *** Enable only one of the two stacks, unless you know what you are doing *** New FireWire stack, EXPERIMENTAL OHCI-1394 controllers Storage devices (SBP-2 protocol) Stable FireWire stack OHCI-1394 controllers PCILynx controller Storage devices (SBP-2 protocol) Enable replacement for physical DMA in SBP2 IP over 1394 raw1394 userspace interface video1394 userspace interface dv1394 userspace interface (deprecated) Excessive debugging output The old prompts for reference: -------------------- IEEE 1394 (FireWire) support -------------------- IEEE 1394 (FireWire) support - alternative stack, EXPERIMENTAL Support for OHCI FireWire host controllers Support for storage devices (SBP-2 protocol driver) IEEE 1394 (FireWire) support *** Subsystem Options *** Excessive debugging output *** Controllers *** Texas Instruments PCILynx support OHCI-1394 support *** Protocols *** OHCI-1394 Video support SBP-2 support (Harddisks etc.) Enable replacement for physical DMA in SBP2 IP over 1394 OHCI-DV I/O support (deprecated) Raw IEEE1394 I/O support Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
| * | firewire: Kconfig menu touch-upStefan Richter2008-06-191-17/+15
| | | | | | | | | | | | | | | | | | | | | Emphasize the recommendation to build only one stack. Trim the prompts to better fit into short attention spans. Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
| * | firewire: deadline for PHY config transmissionStefan Richter2008-06-191-15/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the low-level driver failed to initialize a card properly without noticing it, fw-core was blocked indefinitely when trying to send a PHY config packet. This hung up the events kernel thread, e.g. locked up keyboard input. https://bugzilla.redhat.com/show_bug.cgi?id=444694 https://bugzilla.redhat.com/show_bug.cgi?id=446763 This problem was introduced between 2.6.25 and 2.6.26-rc1 by commit 2a0a2590498be7b92e3e76409c9b8ee722e23c8f "firewire: wait until PHY configuration packet was transmitted (fix bus reset loop)". The solution is to wait with timeout. I tested it with 7 different working controllers and 1 non-working controller. On the working ones, the packet callback complete()s usually --- but not always --- before a timeout of 10ms. Hence I chose a safer timeout of 100ms. On the few tests with the non-working controller ALi M5271, PHY config packet transmission always timed out so far. (Fw-ohci needs to be fixed for this controller independently of this deadline fix. Often the core doesn't even attempt to send a phy config because not even self ID reception works.) Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
| * | firewire: fw-ohci: unify printk prefixesStefan Richter2008-06-191-53/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | The messages which can be enabled by fw-ohci's debug module parameter are changed from KERN_DEBUG to KERN_NOTICE level and uniformly prefixed with "firewire_ohci: ". This further simplifies communication with users when we ask them to capture debug messages. Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
| * | firewire: fill_bus_reset_event needs lock protectionStefan Richter2008-06-191-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Callers of fill_bus_reset_event() have to take card->lock. Otherwise access to node data may oops if node removal is in progress. A lockless alternative would be - event->local_node_id = card->local_node->node_id; + tmp = fw_node_get(card->local_node); + event->local_node_id = tmp->node_id; + fw_node_put(tmp); and ditto with the other node pointers which fill_bus_reset_event() accesses. But I went the locked route because one of the two callers already holds the lock. As a bonus, we don't need the memory barrier anymore because device->generation and device->node_id are written in a card->lock protected section. Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de> Signed-off-by: Kristian Høgsberg <krh@redhat.com>
| * | firewire: fw-ohci: write selfIDBufferPtr before LinkControl.rcvSelfIDStefan Richter2008-06-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OHCI 1.1 clause 5.10 requires that selfIDBufferPtr is valid when a 1 is written into LinkControl.rcvSelfID. This driver bug has so far not been known to cause harm because most chips obviously accept a later selfIDBufferPtr write, at least before HCControl.linkEnable is written. Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de> Signed-off-by: Jarod Wilson <jwilson@redhat.com> Signed-off-by: Kristian Høgsberg <krh@redhat.com>
| * | firewire: fw-ohci: disable PHY packet reception into AR contextStefan Richter2008-06-191-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We want the rcvPhyPkt bit in LinkControl off before we start using the chip. However, the spec says that the reset value of it is undefined. Hence switch it explicitly off. https://bugzilla.redhat.com/show_bug.cgi?id=244576#c48 shows that for example the nForce2 integrated FireWire controller seems to have it on by default. Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de> Signed-off-by: Jarod Wilson <jwilson@redhat.com>
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