summaryrefslogtreecommitdiffstats
path: root/include
diff options
context:
space:
mode:
Diffstat (limited to 'include')
-rw-r--r--include/asm-mips/mach-au1x00/au1000.h624
-rw-r--r--include/asm-mips/mach-db1x00/db1200.h49
-rw-r--r--include/asm-mips/mach-pb1x00/pb1200.h52
-rw-r--r--include/asm-x86/paravirt.h487
-rw-r--r--include/asm-x86/pgtable-3level-defs.h2
-rw-r--r--include/xen/interface/vcpu.h5
6 files changed, 660 insertions, 559 deletions
diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h
index b37baf8cf624..3bdce9126f16 100644
--- a/include/asm-mips/mach-au1x00/au1000.h
+++ b/include/asm-mips/mach-au1x00/au1000.h
@@ -40,7 +40,9 @@
#include <linux/delay.h>
#include <linux/types.h>
+
#include <asm/io.h>
+#include <asm/irq.h>
/* cpu pipeline flush */
void static inline au_sync(void)
@@ -523,63 +525,67 @@ extern struct au1xxx_irqmap au1xxx_irq_map[];
/* Interrupt Numbers */
/* Au1000 */
#ifdef CONFIG_SOC_AU1000
-#define AU1000_UART0_INT 0
-#define AU1000_UART1_INT 1 /* au1000 */
-#define AU1000_UART2_INT 2 /* au1000 */
-#define AU1000_UART3_INT 3
-#define AU1000_SSI0_INT 4 /* au1000 */
-#define AU1000_SSI1_INT 5 /* au1000 */
-#define AU1000_DMA_INT_BASE 6
-#define AU1000_TOY_INT 14
-#define AU1000_TOY_MATCH0_INT 15
-#define AU1000_TOY_MATCH1_INT 16
-#define AU1000_TOY_MATCH2_INT 17
-#define AU1000_RTC_INT 18
-#define AU1000_RTC_MATCH0_INT 19
-#define AU1000_RTC_MATCH1_INT 20
-#define AU1000_RTC_MATCH2_INT 21
-#define AU1000_IRDA_TX_INT 22 /* au1000 */
-#define AU1000_IRDA_RX_INT 23 /* au1000 */
-#define AU1000_USB_DEV_REQ_INT 24
-#define AU1000_USB_DEV_SUS_INT 25
-#define AU1000_USB_HOST_INT 26
-#define AU1000_ACSYNC_INT 27
-#define AU1000_MAC0_DMA_INT 28
-#define AU1000_MAC1_DMA_INT 29
-#define AU1000_I2S_UO_INT 30 /* au1000 */
-#define AU1000_AC97C_INT 31
-#define AU1000_GPIO_0 32
-#define AU1000_GPIO_1 33
-#define AU1000_GPIO_2 34
-#define AU1000_GPIO_3 35
-#define AU1000_GPIO_4 36
-#define AU1000_GPIO_5 37
-#define AU1000_GPIO_6 38
-#define AU1000_GPIO_7 39
-#define AU1000_GPIO_8 40
-#define AU1000_GPIO_9 41
-#define AU1000_GPIO_10 42
-#define AU1000_GPIO_11 43
-#define AU1000_GPIO_12 44
-#define AU1000_GPIO_13 45
-#define AU1000_GPIO_14 46
-#define AU1000_GPIO_15 47
-#define AU1000_GPIO_16 48
-#define AU1000_GPIO_17 49
-#define AU1000_GPIO_18 50
-#define AU1000_GPIO_19 51
-#define AU1000_GPIO_20 52
-#define AU1000_GPIO_21 53
-#define AU1000_GPIO_22 54
-#define AU1000_GPIO_23 55
-#define AU1000_GPIO_24 56
-#define AU1000_GPIO_25 57
-#define AU1000_GPIO_26 58
-#define AU1000_GPIO_27 59
-#define AU1000_GPIO_28 60
-#define AU1000_GPIO_29 61
-#define AU1000_GPIO_30 62
-#define AU1000_GPIO_31 63
+enum soc_au1000_ints {
+ AU1000_FIRST_INT = MIPS_CPU_IRQ_BASE,
+ AU1000_UART0_INT = AU1000_FIRST_INT,
+ AU1000_UART1_INT, /* au1000 */
+ AU1000_UART2_INT, /* au1000 */
+ AU1000_UART3_INT,
+ AU1000_SSI0_INT, /* au1000 */
+ AU1000_SSI1_INT, /* au1000 */
+ AU1000_DMA_INT_BASE,
+
+ AU1000_TOY_INT = AU1000_FIRST_INT + 14,
+ AU1000_TOY_MATCH0_INT,
+ AU1000_TOY_MATCH1_INT,
+ AU1000_TOY_MATCH2_INT,
+ AU1000_RTC_INT,
+ AU1000_RTC_MATCH0_INT,
+ AU1000_RTC_MATCH1_INT,
+ AU1000_RTC_MATCH2_INT,
+ AU1000_IRDA_TX_INT, /* au1000 */
+ AU1000_IRDA_RX_INT, /* au1000 */
+ AU1000_USB_DEV_REQ_INT,
+ AU1000_USB_DEV_SUS_INT,
+ AU1000_USB_HOST_INT,
+ AU1000_ACSYNC_INT,
+ AU1000_MAC0_DMA_INT,
+ AU1000_MAC1_DMA_INT,
+ AU1000_I2S_UO_INT, /* au1000 */
+ AU1000_AC97C_INT,
+ AU1000_GPIO_0,
+ AU1000_GPIO_1,
+ AU1000_GPIO_2,
+ AU1000_GPIO_3,
+ AU1000_GPIO_4,
+ AU1000_GPIO_5,
+ AU1000_GPIO_6,
+ AU1000_GPIO_7,
+ AU1000_GPIO_8,
+ AU1000_GPIO_9,
+ AU1000_GPIO_10,
+ AU1000_GPIO_11,
+ AU1000_GPIO_12,
+ AU1000_GPIO_13,
+ AU1000_GPIO_14,
+ AU1000_GPIO_15,
+ AU1000_GPIO_16,
+ AU1000_GPIO_17,
+ AU1000_GPIO_18,
+ AU1000_GPIO_19,
+ AU1000_GPIO_20,
+ AU1000_GPIO_21,
+ AU1000_GPIO_22,
+ AU1000_GPIO_23,
+ AU1000_GPIO_24,
+ AU1000_GPIO_25,
+ AU1000_GPIO_26,
+ AU1000_GPIO_27,
+ AU1000_GPIO_28,
+ AU1000_GPIO_29,
+ AU1000_GPIO_30,
+ AU1000_GPIO_31,
+};
#define UART0_ADDR 0xB1100000
#define UART1_ADDR 0xB1200000
@@ -598,61 +604,65 @@ extern struct au1xxx_irqmap au1xxx_irq_map[];
/* Au1500 */
#ifdef CONFIG_SOC_AU1500
-#define AU1500_UART0_INT 0
-#define AU1000_PCI_INTA 1 /* au1500 */
-#define AU1000_PCI_INTB 2 /* au1500 */
-#define AU1500_UART3_INT 3
-#define AU1000_PCI_INTC 4 /* au1500 */
-#define AU1000_PCI_INTD 5 /* au1500 */
-#define AU1000_DMA_INT_BASE 6
-#define AU1000_TOY_INT 14
-#define AU1000_TOY_MATCH0_INT 15
-#define AU1000_TOY_MATCH1_INT 16
-#define AU1000_TOY_MATCH2_INT 17
-#define AU1000_RTC_INT 18
-#define AU1000_RTC_MATCH0_INT 19
-#define AU1000_RTC_MATCH1_INT 20
-#define AU1000_RTC_MATCH2_INT 21
-#define AU1500_PCI_ERR_INT 22
-#define AU1000_USB_DEV_REQ_INT 24
-#define AU1000_USB_DEV_SUS_INT 25
-#define AU1000_USB_HOST_INT 26
-#define AU1000_ACSYNC_INT 27
-#define AU1500_MAC0_DMA_INT 28
-#define AU1500_MAC1_DMA_INT 29
-#define AU1000_AC97C_INT 31
-#define AU1000_GPIO_0 32
-#define AU1000_GPIO_1 33
-#define AU1000_GPIO_2 34
-#define AU1000_GPIO_3 35
-#define AU1000_GPIO_4 36
-#define AU1000_GPIO_5 37
-#define AU1000_GPIO_6 38
-#define AU1000_GPIO_7 39
-#define AU1000_GPIO_8 40
-#define AU1000_GPIO_9 41
-#define AU1000_GPIO_10 42
-#define AU1000_GPIO_11 43
-#define AU1000_GPIO_12 44
-#define AU1000_GPIO_13 45
-#define AU1000_GPIO_14 46
-#define AU1000_GPIO_15 47
-#define AU1500_GPIO_200 48
-#define AU1500_GPIO_201 49
-#define AU1500_GPIO_202 50
-#define AU1500_GPIO_203 51
-#define AU1500_GPIO_20 52
-#define AU1500_GPIO_204 53
-#define AU1500_GPIO_205 54
-#define AU1500_GPIO_23 55
-#define AU1500_GPIO_24 56
-#define AU1500_GPIO_25 57
-#define AU1500_GPIO_26 58
-#define AU1500_GPIO_27 59
-#define AU1500_GPIO_28 60
-#define AU1500_GPIO_206 61
-#define AU1500_GPIO_207 62
-#define AU1500_GPIO_208_215 63
+enum soc_au1500_ints {
+ AU1500_FIRST_INT = MIPS_CPU_IRQ_BASE,
+ AU1500_UART0_INT = AU1500_FIRST_INT,
+ AU1000_PCI_INTA, /* au1500 */
+ AU1000_PCI_INTB, /* au1500 */
+ AU1500_UART3_INT,
+ AU1000_PCI_INTC, /* au1500 */
+ AU1000_PCI_INTD, /* au1500 */
+ AU1000_DMA_INT_BASE,
+
+ AU1000_TOY_INT = AU1500_FIRST_INT + 14,
+ AU1000_TOY_MATCH0_INT,
+ AU1000_TOY_MATCH1_INT,
+ AU1000_TOY_MATCH2_INT,
+ AU1000_RTC_INT,
+ AU1000_RTC_MATCH0_INT,
+ AU1000_RTC_MATCH1_INT,
+ AU1000_RTC_MATCH2_INT,
+ AU1500_PCI_ERR_INT,
+ AU1000_USB_DEV_REQ_INT,
+ AU1000_USB_DEV_SUS_INT,
+ AU1000_USB_HOST_INT,
+ AU1000_ACSYNC_INT,
+ AU1500_MAC0_DMA_INT,
+ AU1500_MAC1_DMA_INT,
+ AU1000_AC97C_INT = AU1500_FIRST_INT + 31,
+ AU1000_GPIO_0,
+ AU1000_GPIO_1,
+ AU1000_GPIO_2,
+ AU1000_GPIO_3,
+ AU1000_GPIO_4,
+ AU1000_GPIO_5,
+ AU1000_GPIO_6,
+ AU1000_GPIO_7,
+ AU1000_GPIO_8,
+ AU1000_GPIO_9,
+ AU1000_GPIO_10,
+ AU1000_GPIO_11,
+ AU1000_GPIO_12,
+ AU1000_GPIO_13,
+ AU1000_GPIO_14,
+ AU1000_GPIO_15,
+ AU1500_GPIO_200,
+ AU1500_GPIO_201,
+ AU1500_GPIO_202,
+ AU1500_GPIO_203,
+ AU1500_GPIO_20,
+ AU1500_GPIO_204,
+ AU1500_GPIO_205,
+ AU1500_GPIO_23,
+ AU1500_GPIO_24,
+ AU1500_GPIO_25,
+ AU1500_GPIO_26,
+ AU1500_GPIO_27,
+ AU1500_GPIO_28,
+ AU1500_GPIO_206,
+ AU1500_GPIO_207,
+ AU1500_GPIO_208_215,
+};
/* shortcuts */
#define INTA AU1000_PCI_INTA
@@ -675,63 +685,67 @@ extern struct au1xxx_irqmap au1xxx_irq_map[];
/* Au1100 */
#ifdef CONFIG_SOC_AU1100
-#define AU1100_UART0_INT 0
-#define AU1100_UART1_INT 1
-#define AU1100_SD_INT 2
-#define AU1100_UART3_INT 3
-#define AU1000_SSI0_INT 4
-#define AU1000_SSI1_INT 5
-#define AU1000_DMA_INT_BASE 6
-#define AU1000_TOY_INT 14
-#define AU1000_TOY_MATCH0_INT 15
-#define AU1000_TOY_MATCH1_INT 16
-#define AU1000_TOY_MATCH2_INT 17
-#define AU1000_RTC_INT 18
-#define AU1000_RTC_MATCH0_INT 19
-#define AU1000_RTC_MATCH1_INT 20
-#define AU1000_RTC_MATCH2_INT 21
-#define AU1000_IRDA_TX_INT 22
-#define AU1000_IRDA_RX_INT 23
-#define AU1000_USB_DEV_REQ_INT 24
-#define AU1000_USB_DEV_SUS_INT 25
-#define AU1000_USB_HOST_INT 26
-#define AU1000_ACSYNC_INT 27
-#define AU1100_MAC0_DMA_INT 28
-#define AU1100_GPIO_208_215 29
-#define AU1100_LCD_INT 30
-#define AU1000_AC97C_INT 31
-#define AU1000_GPIO_0 32
-#define AU1000_GPIO_1 33
-#define AU1000_GPIO_2 34
-#define AU1000_GPIO_3 35
-#define AU1000_GPIO_4 36
-#define AU1000_GPIO_5 37
-#define AU1000_GPIO_6 38
-#define AU1000_GPIO_7 39
-#define AU1000_GPIO_8 40
-#define AU1000_GPIO_9 41
-#define AU1000_GPIO_10 42
-#define AU1000_GPIO_11 43
-#define AU1000_GPIO_12 44
-#define AU1000_GPIO_13 45
-#define AU1000_GPIO_14 46
-#define AU1000_GPIO_15 47
-#define AU1000_GPIO_16 48
-#define AU1000_GPIO_17 49
-#define AU1000_GPIO_18 50
-#define AU1000_GPIO_19 51
-#define AU1000_GPIO_20 52
-#define AU1000_GPIO_21 53
-#define AU1000_GPIO_22 54
-#define AU1000_GPIO_23 55
-#define AU1000_GPIO_24 56
-#define AU1000_GPIO_25 57
-#define AU1000_GPIO_26 58
-#define AU1000_GPIO_27 59
-#define AU1000_GPIO_28 60
-#define AU1000_GPIO_29 61
-#define AU1000_GPIO_30 62
-#define AU1000_GPIO_31 63
+enum soc_au1100_ints {
+ AU1100_FIRST_INT = MIPS_CPU_IRQ_BASE,
+ AU1100_UART0_INT,
+ AU1100_UART1_INT,
+ AU1100_SD_INT,
+ AU1100_UART3_INT,
+ AU1000_SSI0_INT,
+ AU1000_SSI1_INT,
+ AU1000_DMA_INT_BASE,
+
+ AU1000_TOY_INT = AU1100_FIRST_INT + 14,
+ AU1000_TOY_MATCH0_INT,
+ AU1000_TOY_MATCH1_INT,
+ AU1000_TOY_MATCH2_INT,
+ AU1000_RTC_INT,
+ AU1000_RTC_MATCH0_INT,
+ AU1000_RTC_MATCH1_INT,
+ AU1000_RTC_MATCH2_INT,
+ AU1000_IRDA_TX_INT,
+ AU1000_IRDA_RX_INT,
+ AU1000_USB_DEV_REQ_INT,
+ AU1000_USB_DEV_SUS_INT,
+ AU1000_USB_HOST_INT,
+ AU1000_ACSYNC_INT,
+ AU1100_MAC0_DMA_INT,
+ AU1100_GPIO_208_215,
+ AU1100_LCD_INT,
+ AU1000_AC97C_INT,
+ AU1000_GPIO_0,
+ AU1000_GPIO_1,
+ AU1000_GPIO_2,
+ AU1000_GPIO_3,
+ AU1000_GPIO_4,
+ AU1000_GPIO_5,
+ AU1000_GPIO_6,
+ AU1000_GPIO_7,
+ AU1000_GPIO_8,
+ AU1000_GPIO_9,
+ AU1000_GPIO_10,
+ AU1000_GPIO_11,
+ AU1000_GPIO_12,
+ AU1000_GPIO_13,
+ AU1000_GPIO_14,
+ AU1000_GPIO_15,
+ AU1000_GPIO_16,
+ AU1000_GPIO_17,
+ AU1000_GPIO_18,
+ AU1000_GPIO_19,
+ AU1000_GPIO_20,
+ AU1000_GPIO_21,
+ AU1000_GPIO_22,
+ AU1000_GPIO_23,
+ AU1000_GPIO_24,
+ AU1000_GPIO_25,
+ AU1000_GPIO_26,
+ AU1000_GPIO_27,
+ AU1000_GPIO_28,
+ AU1000_GPIO_29,
+ AU1000_GPIO_30,
+ AU1000_GPIO_31,
+};
#define UART0_ADDR 0xB1100000
#define UART1_ADDR 0xB1200000
@@ -746,69 +760,73 @@ extern struct au1xxx_irqmap au1xxx_irq_map[];
#endif /* CONFIG_SOC_AU1100 */
#ifdef CONFIG_SOC_AU1550
-#define AU1550_UART0_INT 0
-#define AU1550_PCI_INTA 1
-#define AU1550_PCI_INTB 2
-#define AU1550_DDMA_INT 3
-#define AU1550_CRYPTO_INT 4
-#define AU1550_PCI_INTC 5
-#define AU1550_PCI_INTD 6
-#define AU1550_PCI_RST_INT 7
-#define AU1550_UART1_INT 8
-#define AU1550_UART3_INT 9
-#define AU1550_PSC0_INT 10
-#define AU1550_PSC1_INT 11
-#define AU1550_PSC2_INT 12
-#define AU1550_PSC3_INT 13
-#define AU1000_TOY_INT 14
-#define AU1000_TOY_MATCH0_INT 15
-#define AU1000_TOY_MATCH1_INT 16
-#define AU1000_TOY_MATCH2_INT 17
-#define AU1000_RTC_INT 18
-#define AU1000_RTC_MATCH0_INT 19
-#define AU1000_RTC_MATCH1_INT 20
-#define AU1000_RTC_MATCH2_INT 21
-#define AU1550_NAND_INT 23
-#define AU1550_USB_DEV_REQ_INT 24
-#define AU1550_USB_DEV_SUS_INT 25
-#define AU1550_USB_HOST_INT 26
-#define AU1000_USB_DEV_REQ_INT AU1550_USB_DEV_REQ_INT
-#define AU1000_USB_DEV_SUS_INT AU1550_USB_DEV_SUS_INT
-#define AU1000_USB_HOST_INT AU1550_USB_HOST_INT
-#define AU1550_MAC0_DMA_INT 27
-#define AU1550_MAC1_DMA_INT 28
-#define AU1000_GPIO_0 32
-#define AU1000_GPIO_1 33
-#define AU1000_GPIO_2 34
-#define AU1000_GPIO_3 35
-#define AU1000_GPIO_4 36
-#define AU1000_GPIO_5 37
-#define AU1000_GPIO_6 38
-#define AU1000_GPIO_7 39
-#define AU1000_GPIO_8 40
-#define AU1000_GPIO_9 41
-#define AU1000_GPIO_10 42
-#define AU1000_GPIO_11 43
-#define AU1000_GPIO_12 44
-#define AU1000_GPIO_13 45
-#define AU1000_GPIO_14 46
-#define AU1000_GPIO_15 47
-#define AU1550_GPIO_200 48
-#define AU1500_GPIO_201_205 49 // Logical or of GPIO201:205
-#define AU1500_GPIO_16 50
-#define AU1500_GPIO_17 51
-#define AU1500_GPIO_20 52
-#define AU1500_GPIO_21 53
-#define AU1500_GPIO_22 54
-#define AU1500_GPIO_23 55
-#define AU1500_GPIO_24 56
-#define AU1500_GPIO_25 57
-#define AU1500_GPIO_26 58
-#define AU1500_GPIO_27 59
-#define AU1500_GPIO_28 60
-#define AU1500_GPIO_206 61
-#define AU1500_GPIO_207 62
-#define AU1500_GPIO_208_218 63 // Logical or of GPIO208:218
+enum soc_au1550_ints {
+ AU1550_FIRST_INT = MIPS_CPU_IRQ_BASE,
+ AU1550_UART0_INT = AU1550_FIRST_INT,
+ AU1550_PCI_INTA,
+ AU1550_PCI_INTB,
+ AU1550_DDMA_INT,
+ AU1550_CRYPTO_INT,
+ AU1550_PCI_INTC,
+ AU1550_PCI_INTD,
+ AU1550_PCI_RST_INT,
+ AU1550_UART1_INT,
+ AU1550_UART3_INT,
+ AU1550_PSC0_INT,
+ AU1550_PSC1_INT,
+ AU1550_PSC2_INT,
+ AU1550_PSC3_INT,
+ AU1000_TOY_INT,
+ AU1000_TOY_MATCH0_INT,
+ AU1000_TOY_MATCH1_INT,
+ AU1000_TOY_MATCH2_INT,
+ AU1000_RTC_INT,
+ AU1000_RTC_MATCH0_INT,
+ AU1000_RTC_MATCH1_INT,
+ AU1000_RTC_MATCH2_INT,
+
+ AU1550_NAND_INT = AU1550_FIRST_INT + 23,
+ AU1550_USB_DEV_REQ_INT,
+ AU1000_USB_DEV_REQ_INT = AU1550_USB_DEV_REQ_INT,
+ AU1550_USB_DEV_SUS_INT,
+ AU1000_USB_DEV_SUS_INT = AU1550_USB_DEV_SUS_INT,
+ AU1550_USB_HOST_INT,
+ AU1000_USB_HOST_INT = AU1550_USB_HOST_INT,
+ AU1550_MAC0_DMA_INT,
+ AU1550_MAC1_DMA_INT,
+ AU1000_GPIO_0 = AU1550_FIRST_INT + 32,
+ AU1000_GPIO_1,
+ AU1000_GPIO_2,
+ AU1000_GPIO_3,
+ AU1000_GPIO_4,
+ AU1000_GPIO_5,
+ AU1000_GPIO_6,
+ AU1000_GPIO_7,
+ AU1000_GPIO_8,
+ AU1000_GPIO_9,
+ AU1000_GPIO_10,
+ AU1000_GPIO_11,
+ AU1000_GPIO_12,
+ AU1000_GPIO_13,
+ AU1000_GPIO_14,
+ AU1000_GPIO_15,
+ AU1550_GPIO_200,
+ AU1500_GPIO_201_205, /* Logical or of GPIO201:205 */
+ AU1500_GPIO_16,
+ AU1500_GPIO_17,
+ AU1500_GPIO_20,
+ AU1500_GPIO_21,
+ AU1500_GPIO_22,
+ AU1500_GPIO_23,
+ AU1500_GPIO_24,
+ AU1500_GPIO_25,
+ AU1500_GPIO_26,
+ AU1500_GPIO_27,
+ AU1500_GPIO_28,
+ AU1500_GPIO_206,
+ AU1500_GPIO_207,
+ AU1500_GPIO_208_218, /* Logical or of GPIO208:218 */
+};
/* shortcuts */
#define INTA AU1550_PCI_INTA
@@ -832,70 +850,74 @@ extern struct au1xxx_irqmap au1xxx_irq_map[];
#endif /* CONFIG_SOC_AU1550 */
#ifdef CONFIG_SOC_AU1200
-#define AU1200_UART0_INT 0
-#define AU1200_SWT_INT 1
-#define AU1200_SD_INT 2
-#define AU1200_DDMA_INT 3
-#define AU1200_MAE_BE_INT 4
-#define AU1200_GPIO_200 5
-#define AU1200_GPIO_201 6
-#define AU1200_GPIO_202 7
-#define AU1200_UART1_INT 8
-#define AU1200_MAE_FE_INT 9
-#define AU1200_PSC0_INT 10
-#define AU1200_PSC1_INT 11
-#define AU1200_AES_INT 12
-#define AU1200_CAMERA_INT 13
-#define AU1000_TOY_INT 14
-#define AU1000_TOY_MATCH0_INT 15
-#define AU1000_TOY_MATCH1_INT 16
-#define AU1000_TOY_MATCH2_INT 17
-#define AU1000_RTC_INT 18
-#define AU1000_RTC_MATCH0_INT 19
-#define AU1000_RTC_MATCH1_INT 20
-#define AU1000_RTC_MATCH2_INT 21
-#define AU1200_NAND_INT 23
-#define AU1200_GPIO_204 24
-#define AU1200_GPIO_205 25
-#define AU1200_GPIO_206 26
-#define AU1200_GPIO_207 27
-#define AU1200_GPIO_208_215 28 // Logical OR of 208:215
-#define AU1200_USB_INT 29
-#define AU1000_USB_HOST_INT AU1200_USB_INT
-#define AU1200_LCD_INT 30
-#define AU1200_MAE_BOTH_INT 31
-#define AU1000_GPIO_0 32
-#define AU1000_GPIO_1 33
-#define AU1000_GPIO_2 34
-#define AU1000_GPIO_3 35
-#define AU1000_GPIO_4 36
-#define AU1000_GPIO_5 37
-#define AU1000_GPIO_6 38
-#define AU1000_GPIO_7 39
-#define AU1000_GPIO_8 40
-#define AU1000_GPIO_9 41
-#define AU1000_GPIO_10 42
-#define AU1000_GPIO_11 43
-#define AU1000_GPIO_12 44
-#define AU1000_GPIO_13 45
-#define AU1000_GPIO_14 46
-#define AU1000_GPIO_15 47
-#define AU1000_GPIO_16 48
-#define AU1000_GPIO_17 49
-#define AU1000_GPIO_18 50
-#define AU1000_GPIO_19 51
-#define AU1000_GPIO_20 52
-#define AU1000_GPIO_21 53
-#define AU1000_GPIO_22 54
-#define AU1000_GPIO_23 55
-#define AU1000_GPIO_24 56
-#define AU1000_GPIO_25 57
-#define AU1000_GPIO_26 58
-#define AU1000_GPIO_27 59
-#define AU1000_GPIO_28 60
-#define AU1000_GPIO_29 61
-#define AU1000_GPIO_30 62
-#define AU1000_GPIO_31 63
+enum soc_au1200_ints {
+ AU1200_FIRST_INT = MIPS_CPU_IRQ_BASE,
+ AU1200_UART0_INT = AU1200_FIRST_INT,
+ AU1200_SWT_INT,
+ AU1200_SD_INT,
+ AU1200_DDMA_INT,
+ AU1200_MAE_BE_INT,
+ AU1200_GPIO_200,
+ AU1200_GPIO_201,
+ AU1200_GPIO_202,
+ AU1200_UART1_INT,
+ AU1200_MAE_FE_INT,
+ AU1200_PSC0_INT,
+ AU1200_PSC1_INT,
+ AU1200_AES_INT,
+ AU1200_CAMERA_INT,
+ AU1000_TOY_INT,
+ AU1000_TOY_MATCH0_INT,
+ AU1000_TOY_MATCH1_INT,
+ AU1000_TOY_MATCH2_INT,
+ AU1000_RTC_INT,
+ AU1000_RTC_MATCH0_INT,
+ AU1000_RTC_MATCH1_INT,
+ AU1000_RTC_MATCH2_INT,
+
+ AU1200_NAND_INT = AU1200_FIRST_INT + 23,
+ AU1200_GPIO_204,
+ AU1200_GPIO_205,
+ AU1200_GPIO_206,
+ AU1200_GPIO_207,
+ AU1200_GPIO_208_215, /* Logical OR of 208:215 */
+ AU1200_USB_INT,
+ AU1000_USB_HOST_INT = AU1200_USB_INT,
+ AU1200_LCD_INT,
+ AU1200_MAE_BOTH_INT,
+ AU1000_GPIO_0,
+ AU1000_GPIO_1,
+ AU1000_GPIO_2,
+ AU1000_GPIO_3,
+ AU1000_GPIO_4,
+ AU1000_GPIO_5,
+ AU1000_GPIO_6,
+ AU1000_GPIO_7,
+ AU1000_GPIO_8,
+ AU1000_GPIO_9,
+ AU1000_GPIO_10,
+ AU1000_GPIO_11,
+ AU1000_GPIO_12,
+ AU1000_GPIO_13,
+ AU1000_GPIO_14,
+ AU1000_GPIO_15,
+ AU1000_GPIO_16,
+ AU1000_GPIO_17,
+ AU1000_GPIO_18,
+ AU1000_GPIO_19,
+ AU1000_GPIO_20,
+ AU1000_GPIO_21,
+ AU1000_GPIO_22,
+ AU1000_GPIO_23,
+ AU1000_GPIO_24,
+ AU1000_GPIO_25,
+ AU1000_GPIO_26,
+ AU1000_GPIO_27,
+ AU1000_GPIO_28,
+ AU1000_GPIO_29,
+ AU1000_GPIO_30,
+ AU1000_GPIO_31,
+};
#define UART0_ADDR 0xB1100000
#define UART1_ADDR 0xB1200000
@@ -926,10 +948,12 @@ extern struct au1xxx_irqmap au1xxx_irq_map[];
#endif /* CONFIG_SOC_AU1200 */
-#define AU1000_LAST_INTC0_INT 31
-#define AU1000_LAST_INTC1_INT 63
-#define AU1000_MAX_INTR 63
-#define INTX 0xFF /* not valid */
+#define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 0)
+#define AU1000_INTC0_INT_LAST (MIPS_CPU_IRQ_BASE + 31)
+#define AU1000_INTC1_INT_BASE (MIPS_CPU_IRQ_BASE + 32)
+#define AU1000_INTC1_INT_LAST (MIPS_CPU_IRQ_BASE + 63)
+#define AU1000_MAX_INTR (MIPS_CPU_IRQ_BASE + 63)
+#define INTX 0xFF /* not valid */
/* Programmable Counters 0 and 1 */
#define SYS_BASE 0xB1900000
diff --git a/include/asm-mips/mach-db1x00/db1200.h b/include/asm-mips/mach-db1x00/db1200.h
index 647fdb54cc1d..050eae87ff01 100644
--- a/include/asm-mips/mach-db1x00/db1200.h
+++ b/include/asm-mips/mach-db1x00/db1200.h
@@ -181,29 +181,34 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
#define NAND_PHYS_ADDR 0x20000000
/*
- * External Interrupts for Pb1200 as of 8/6/2004.
- * Bit positions in the CPLD registers can be calculated by taking
- * the interrupt define and subtracting the DB1200_INT_BEGIN value.
- * *example: IDE bis pos is = 64 - 64
- ETH bit pos is = 65 - 64
+ * External Interrupts for Pb1200 as of 8/6/2004.
+ * Bit positions in the CPLD registers can be calculated by taking
+ * the interrupt define and subtracting the DB1200_INT_BEGIN value.
+ *
+ * Example: IDE bis pos is = 64 - 64
+ * ETH bit pos is = 65 - 64
*/
-#define DB1200_INT_BEGIN (AU1000_LAST_INTC1_INT + 1)
-#define DB1200_IDE_INT (DB1200_INT_BEGIN + 0)
-#define DB1200_ETH_INT (DB1200_INT_BEGIN + 1)
-#define DB1200_PC0_INT (DB1200_INT_BEGIN + 2)
-#define DB1200_PC0_STSCHG_INT (DB1200_INT_BEGIN + 3)
-#define DB1200_PC1_INT (DB1200_INT_BEGIN + 4)
-#define DB1200_PC1_STSCHG_INT (DB1200_INT_BEGIN + 5)
-#define DB1200_DC_INT (DB1200_INT_BEGIN + 6)
-#define DB1200_FLASHBUSY_INT (DB1200_INT_BEGIN + 7)
-#define DB1200_PC0_INSERT_INT (DB1200_INT_BEGIN + 8)
-#define DB1200_PC0_EJECT_INT (DB1200_INT_BEGIN + 9)
-#define DB1200_PC1_INSERT_INT (DB1200_INT_BEGIN + 10)
-#define DB1200_PC1_EJECT_INT (DB1200_INT_BEGIN + 11)
-#define DB1200_SD0_INSERT_INT (DB1200_INT_BEGIN + 12)
-#define DB1200_SD0_EJECT_INT (DB1200_INT_BEGIN + 13)
-
-#define DB1200_INT_END (DB1200_INT_BEGIN + 15)
+enum external_pb1200_ints {
+ DB1200_INT_BEGIN = AU1000_MAX_INTR + 1,
+
+ DB1200_IDE_INT = DB1200_INT_BEGIN,
+ DB1200_ETH_INT,
+ DB1200_PC0_INT,
+ DB1200_PC0_STSCHG_INT,
+ DB1200_PC1_INT,
+ DB1200_PC1_STSCHG_INT,
+ DB1200_DC_INT,
+ DB1200_FLASHBUSY_INT,
+ DB1200_PC0_INSERT_INT,
+ DB1200_PC0_EJECT_INT,
+ DB1200_PC1_INSERT_INT,
+ DB1200_PC1_EJECT_INT,
+ DB1200_SD0_INSERT_INT,
+ DB1200_SD0_EJECT_INT,
+
+ DB1200_INT_END = DB1200_INT_BEGIN + 15,
+};
+
/* For drivers/pcmcia/au1000_db1x00.c */
diff --git a/include/asm-mips/mach-pb1x00/pb1200.h b/include/asm-mips/mach-pb1x00/pb1200.h
index 409d443322c1..d9f384acfea9 100644
--- a/include/asm-mips/mach-pb1x00/pb1200.h
+++ b/include/asm-mips/mach-pb1x00/pb1200.h
@@ -217,31 +217,35 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
/*
- * External Interrupts for Pb1200 as of 8/6/2004.
- * Bit positions in the CPLD registers can be calculated by taking
- * the interrupt define and subtracting the PB1200_INT_BEGIN value.
- * *example: IDE bis pos is = 64 - 64
- ETH bit pos is = 65 - 64
+ * External Interrupts for Pb1200 as of 8/6/2004.
+ * Bit positions in the CPLD registers can be calculated by taking
+ * the interrupt define and subtracting the PB1200_INT_BEGIN value.
+ *
+ * Example: IDE bis pos is = 64 - 64
+ * ETH bit pos is = 65 - 64
*/
-#define PB1200_INT_BEGIN (AU1000_LAST_INTC1_INT + 1)
-#define PB1200_IDE_INT (PB1200_INT_BEGIN + 0)
-#define PB1200_ETH_INT (PB1200_INT_BEGIN + 1)
-#define PB1200_PC0_INT (PB1200_INT_BEGIN + 2)
-#define PB1200_PC0_STSCHG_INT (PB1200_INT_BEGIN + 3)
-#define PB1200_PC1_INT (PB1200_INT_BEGIN + 4)
-#define PB1200_PC1_STSCHG_INT (PB1200_INT_BEGIN + 5)
-#define PB1200_DC_INT (PB1200_INT_BEGIN + 6)
-#define PB1200_FLASHBUSY_INT (PB1200_INT_BEGIN + 7)
-#define PB1200_PC0_INSERT_INT (PB1200_INT_BEGIN + 8)
-#define PB1200_PC0_EJECT_INT (PB1200_INT_BEGIN + 9)
-#define PB1200_PC1_INSERT_INT (PB1200_INT_BEGIN + 10)
-#define PB1200_PC1_EJECT_INT (PB1200_INT_BEGIN + 11)
-#define PB1200_SD0_INSERT_INT (PB1200_INT_BEGIN + 12)
-#define PB1200_SD0_EJECT_INT (PB1200_INT_BEGIN + 13)
-#define PB1200_SD1_INSERT_INT (PB1200_INT_BEGIN + 14)
-#define PB1200_SD1_EJECT_INT (PB1200_INT_BEGIN + 15)
-
-#define PB1200_INT_END (PB1200_INT_BEGIN + 15)
+enum external_pb1200_ints {
+ PB1200_INT_BEGIN = AU1000_MAX_INTR + 1,
+
+ PB1200_IDE_INT = PB1200_INT_BEGIN,
+ PB1200_ETH_INT,
+ PB1200_PC0_INT,
+ PB1200_PC0_STSCHG_INT,
+ PB1200_PC1_INT,
+ PB1200_PC1_STSCHG_INT,
+ PB1200_DC_INT,
+ PB1200_FLASHBUSY_INT,
+ PB1200_PC0_INSERT_INT,
+ PB1200_PC0_EJECT_INT,
+ PB1200_PC1_INSERT_INT,
+ PB1200_PC1_EJECT_INT,
+ PB1200_SD0_INSERT_INT,
+ PB1200_SD0_EJECT_INT,
+ PB1200_SD1_INSERT_INT,
+ PB1200_SD1_EJECT_INT,
+
+ PB1200_INT_END (PB1200_INT_BEGIN + 15)
+};
/* For drivers/pcmcia/au1000_db1x00.c */
#define BOARD_PC0_INT PB1200_PC0_INT
diff --git a/include/asm-x86/paravirt.h b/include/asm-x86/paravirt.h
index 9fa3fa9e62d1..f59d370c5df4 100644
--- a/include/asm-x86/paravirt.h
+++ b/include/asm-x86/paravirt.h
@@ -25,27 +25,22 @@ struct tss_struct;
struct mm_struct;
struct desc_struct;
-/* Lazy mode for batching updates / context switch */
-enum paravirt_lazy_mode {
- PARAVIRT_LAZY_NONE = 0,
- PARAVIRT_LAZY_MMU = 1,
- PARAVIRT_LAZY_CPU = 2,
- PARAVIRT_LAZY_FLUSH = 3,
-};
-
-struct paravirt_ops
-{
+/* general info */
+struct pv_info {
unsigned int kernel_rpl;
int shared_kernel_pmd;
- int paravirt_enabled;
+ int paravirt_enabled;
const char *name;
+};
+struct pv_init_ops {
/*
- * Patch may replace one of the defined code sequences with arbitrary
- * code, subject to the same register constraints. This generally
- * means the code is not free to clobber any registers other than EAX.
- * The patch function should return the number of bytes of code
- * generated, as we nop pad the rest in generic code.
+ * Patch may replace one of the defined code sequences with
+ * arbitrary code, subject to the same register constraints.
+ * This generally means the code is not free to clobber any
+ * registers other than EAX. The patch function should return
+ * the number of bytes of code generated, as we nop pad the
+ * rest in generic code.
*/
unsigned (*patch)(u8 type, u16 clobber, void *insnbuf,
unsigned long addr, unsigned len);
@@ -55,29 +50,29 @@ struct paravirt_ops
char *(*memory_setup)(void);
void (*post_allocator_init)(void);
- void (*init_IRQ)(void);
- void (*time_init)(void);
-
- /*
- * Called before/after init_mm pagetable setup. setup_start
- * may reset %cr3, and may pre-install parts of the pagetable;
- * pagetable setup is expected to preserve any existing
- * mapping.
- */
- void (*pagetable_setup_start)(pgd_t *pgd_base);
- void (*pagetable_setup_done)(pgd_t *pgd_base);
-
/* Print a banner to identify the environment */
void (*banner)(void);
+};
+
+
+struct pv_lazy_ops {
+ /* Set deferred update mode, used for batching operations. */
+ void (*enter)(void);
+ void (*leave)(void);
+};
+
+struct pv_time_ops {
+ void (*time_init)(void);
/* Set and set time of day */
unsigned long (*get_wallclock)(void);
int (*set_wallclock)(unsigned long);
- /* cpuid emulation, mostly so that caps bits can be disabled */
- void (*cpuid)(unsigned int *eax, unsigned int *ebx,
- unsigned int *ecx, unsigned int *edx);
+ unsigned long long (*sched_clock)(void);
+ unsigned long (*get_cpu_khz)(void);
+};
+struct pv_cpu_ops {
/* hooks for various privileged instructions */
unsigned long (*get_debugreg)(int regno);
void (*set_debugreg)(int regno, unsigned long value);
@@ -87,41 +82,10 @@ struct paravirt_ops
unsigned long (*read_cr0)(void);
void (*write_cr0)(unsigned long);
- unsigned long (*read_cr2)(void);
- void (*write_cr2)(unsigned long);
-
- unsigned long (*read_cr3)(void);
- void (*write_cr3)(unsigned long);
-
unsigned long (*read_cr4_safe)(void);
unsigned long (*read_cr4)(void);
void (*write_cr4)(unsigned long);
- /*
- * Get/set interrupt state. save_fl and restore_fl are only
- * expected to use X86_EFLAGS_IF; all other bits
- * returned from save_fl are undefined, and may be ignored by
- * restore_fl.
- */
- unsigned long (*save_fl)(void);
- void (*restore_fl)(unsigned long);
- void (*irq_disable)(void);
- void (*irq_enable)(void);
- void (*safe_halt)(void);
- void (*halt)(void);
-
- void (*wbinvd)(void);
-
- /* MSR, PMC and TSR operations.
- err = 0/-EFAULT. wrmsr returns 0/-EFAULT. */
- u64 (*read_msr)(unsigned int msr, int *err);
- int (*write_msr)(unsigned int msr, u64 val);
-
- u64 (*read_tsc)(void);
- u64 (*read_pmc)(void);
- unsigned long long (*sched_clock)(void);
- unsigned long (*get_cpu_khz)(void);
-
/* Segment descriptor handling */
void (*load_tr_desc)(void);
void (*load_gdt)(const struct Xgt_desc_struct *);
@@ -140,18 +104,47 @@ struct paravirt_ops
void (*load_esp0)(struct tss_struct *tss, struct thread_struct *t);
void (*set_iopl_mask)(unsigned mask);
+
+ void (*wbinvd)(void);
void (*io_delay)(void);
+ /* cpuid emulation, mostly so that caps bits can be disabled */
+ void (*cpuid)(unsigned int *eax, unsigned int *ebx,
+ unsigned int *ecx, unsigned int *edx);
+
+ /* MSR, PMC and TSR operations.
+ err = 0/-EFAULT. wrmsr returns 0/-EFAULT. */
+ u64 (*read_msr)(unsigned int msr, int *err);
+ int (*write_msr)(unsigned int msr, u64 val);
+
+ u64 (*read_tsc)(void);
+ u64 (*read_pmc)(void);
+
+ /* These two are jmp to, not actually called. */
+ void (*irq_enable_sysexit)(void);
+ void (*iret)(void);
+
+ struct pv_lazy_ops lazy_mode;
+};
+
+struct pv_irq_ops {
+ void (*init_IRQ)(void);
+
/*
- * Hooks for intercepting the creation/use/destruction of an
- * mm_struct.
+ * Get/set interrupt state. save_fl and restore_fl are only
+ * expected to use X86_EFLAGS_IF; all other bits
+ * returned from save_fl are undefined, and may be ignored by
+ * restore_fl.
*/
- void (*activate_mm)(struct mm_struct *prev,
- struct mm_struct *next);
- void (*dup_mmap)(struct mm_struct *oldmm,
- struct mm_struct *mm);
- void (*exit_mmap)(struct mm_struct *mm);
+ unsigned long (*save_fl)(void);
+ void (*restore_fl)(unsigned long);
+ void (*irq_disable)(void);
+ void (*irq_enable)(void);
+ void (*safe_halt)(void);
+ void (*halt)(void);
+};
+struct pv_apic_ops {
#ifdef CONFIG_X86_LOCAL_APIC
/*
* Direct APIC operations, principally for VMI. Ideally
@@ -167,6 +160,34 @@ struct paravirt_ops
unsigned long start_eip,
unsigned long start_esp);
#endif
+};
+
+struct pv_mmu_ops {
+ /*
+ * Called before/after init_mm pagetable setup. setup_start
+ * may reset %cr3, and may pre-install parts of the pagetable;
+ * pagetable setup is expected to preserve any existing
+ * mapping.
+ */
+ void (*pagetable_setup_start)(pgd_t *pgd_base);
+ void (*pagetable_setup_done)(pgd_t *pgd_base);
+
+ unsigned long (*read_cr2)(void);
+ void (*write_cr2)(unsigned long);
+
+ unsigned long (*read_cr3)(void);
+ void (*write_cr3)(unsigned long);
+
+ /*
+ * Hooks for intercepting the creation/use/destruction of an
+ * mm_struct.
+ */
+ void (*activate_mm)(struct mm_struct *prev,
+ struct mm_struct *next);
+ void (*dup_mmap)(struct mm_struct *oldmm,
+ struct mm_struct *mm);
+ void (*exit_mmap)(struct mm_struct *mm);
+
/* TLB operations */
void (*flush_tlb_user)(void);
@@ -191,15 +212,12 @@ struct paravirt_ops
void (*pte_update_defer)(struct mm_struct *mm,
unsigned long addr, pte_t *ptep);
-#ifdef CONFIG_HIGHPTE
- void *(*kmap_atomic_pte)(struct page *page, enum km_type type);
-#endif
-
#ifdef CONFIG_X86_PAE
void (*set_pte_atomic)(pte_t *ptep, pte_t pteval);
- void (*set_pte_present)(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pte);
+ void (*set_pte_present)(struct mm_struct *mm, unsigned long addr,
+ pte_t *ptep, pte_t pte);
void (*set_pud)(pud_t *pudp, pud_t pudval);
- void (*pte_clear)(struct mm_struct *mm, unsigned long addr, pte_t *ptep);
+ void (*pte_clear)(struct mm_struct *mm, unsigned long addr, pte_t *ptep);
void (*pmd_clear)(pmd_t *pmdp);
unsigned long long (*pte_val)(pte_t);
@@ -217,21 +235,40 @@ struct paravirt_ops
pgd_t (*make_pgd)(unsigned long pgd);
#endif
- /* Set deferred update mode, used for batching operations. */
- void (*set_lazy_mode)(enum paravirt_lazy_mode mode);
+#ifdef CONFIG_HIGHPTE
+ void *(*kmap_atomic_pte)(struct page *page, enum km_type type);
+#endif
- /* These two are jmp to, not actually called. */
- void (*irq_enable_sysexit)(void);
- void (*iret)(void);
+ struct pv_lazy_ops lazy_mode;
};
-extern struct paravirt_ops paravirt_ops;
+/* This contains all the paravirt structures: we get a convenient
+ * number for each function using the offset which we use to indicate
+ * what to patch. */
+struct paravirt_patch_template
+{
+ struct pv_init_ops pv_init_ops;
+ struct pv_time_ops pv_time_ops;
+ struct pv_cpu_ops pv_cpu_ops;
+ struct pv_irq_ops pv_irq_ops;
+ struct pv_apic_ops pv_apic_ops;
+ struct pv_mmu_ops pv_mmu_ops;
+};
+
+extern struct pv_info pv_info;
+extern struct pv_init_ops pv_init_ops;
+extern struct pv_time_ops pv_time_ops;
+extern struct pv_cpu_ops pv_cpu_ops;
+extern struct pv_irq_ops pv_irq_ops;
+extern struct pv_apic_ops pv_apic_ops;
+extern struct pv_mmu_ops pv_mmu_ops;
#define PARAVIRT_PATCH(x) \
- (offsetof(struct paravirt_ops, x) / sizeof(void *))
+ (offsetof(struct paravirt_patch_template, x) / sizeof(void *))
-#define paravirt_type(type) \
- [paravirt_typenum] "i" (PARAVIRT_PATCH(type))
+#define paravirt_type(op) \
+ [paravirt_typenum] "i" (PARAVIRT_PATCH(op)), \
+ [paravirt_opptr] "m" (op)
#define paravirt_clobber(clobber) \
[paravirt_clobber] "i" (clobber)
@@ -258,7 +295,7 @@ unsigned paravirt_patch_call(void *insnbuf,
const void *target, u16 tgt_clobbers,
unsigned long addr, u16 site_clobbers,
unsigned len);
-unsigned paravirt_patch_jmp(const void *target, void *insnbuf,
+unsigned paravirt_patch_jmp(void *insnbuf, const void *target,
unsigned long addr, unsigned len);
unsigned paravirt_patch_default(u8 type, u16 clobbers, void *insnbuf,
unsigned long addr, unsigned len);
@@ -271,14 +308,14 @@ int paravirt_disable_iospace(void);
/*
* This generates an indirect call based on the operation type number.
* The type number, computed in PARAVIRT_PATCH, is derived from the
- * offset into the paravirt_ops structure, and can therefore be freely
- * converted back into a structure offset.
+ * offset into the paravirt_patch_template structure, and can therefore be
+ * freely converted back into a structure offset.
*/
-#define PARAVIRT_CALL "call *(paravirt_ops+%c[paravirt_typenum]*4);"
+#define PARAVIRT_CALL "call *%[paravirt_opptr];"
/*
- * These macros are intended to wrap calls into a paravirt_ops
- * operation, so that they can be later identified and patched at
+ * These macros are intended to wrap calls through one of the paravirt
+ * ops structs, so that they can be later identified and patched at
* runtime.
*
* Normally, a call to a pv_op function is a simple indirect call:
@@ -301,7 +338,7 @@ int paravirt_disable_iospace(void);
* The call instruction itself is marked by placing its start address
* and size into the .parainstructions section, so that
* apply_paravirt() in arch/i386/kernel/alternative.c can do the
- * appropriate patching under the control of the backend paravirt_ops
+ * appropriate patching under the control of the backend pv_init_ops
* implementation.
*
* Unfortunately there's no way to get gcc to generate the args setup
@@ -409,36 +446,36 @@ int paravirt_disable_iospace(void);
static inline int paravirt_enabled(void)
{
- return paravirt_ops.paravirt_enabled;
+ return pv_info.paravirt_enabled;
}
static inline void load_esp0(struct tss_struct *tss,
struct thread_struct *thread)
{
- PVOP_VCALL2(load_esp0, tss, thread);
+ PVOP_VCALL2(pv_cpu_ops.load_esp0, tss, thread);
}
-#define ARCH_SETUP paravirt_ops.arch_setup();
+#define ARCH_SETUP pv_init_ops.arch_setup();
static inline unsigned long get_wallclock(void)
{
- return PVOP_CALL0(unsigned long, get_wallclock);
+ return PVOP_CALL0(unsigned long, pv_time_ops.get_wallclock);
}
static inline int set_wallclock(unsigned long nowtime)
{
- return PVOP_CALL1(int, set_wallclock, nowtime);
+ return PVOP_CALL1(int, pv_time_ops.set_wallclock, nowtime);
}
static inline void (*choose_time_init(void))(void)
{
- return paravirt_ops.time_init;
+ return pv_time_ops.time_init;
}
/* The paravirtualized CPUID instruction. */
static inline void __cpuid(unsigned int *eax, unsigned int *ebx,
unsigned int *ecx, unsigned int *edx)
{
- PVOP_VCALL4(cpuid, eax, ebx, ecx, edx);
+ PVOP_VCALL4(pv_cpu_ops.cpuid, eax, ebx, ecx, edx);
}
/*
@@ -446,87 +483,87 @@ static inline void __cpuid(unsigned int *eax, unsigned int *ebx,
*/
static inline unsigned long paravirt_get_debugreg(int reg)
{
- return PVOP_CALL1(unsigned long, get_debugreg, reg);
+ return PVOP_CALL1(unsigned long, pv_cpu_ops.get_debugreg, reg);
}
#define get_debugreg(var, reg) var = paravirt_get_debugreg(reg)
static inline void set_debugreg(unsigned long val, int reg)
{
- PVOP_VCALL2(set_debugreg, reg, val);
+ PVOP_VCALL2(pv_cpu_ops.set_debugreg, reg, val);
}
static inline void clts(void)
{
- PVOP_VCALL0(clts);
+ PVOP_VCALL0(pv_cpu_ops.clts);
}
static inline unsigned long read_cr0(void)
{
- return PVOP_CALL0(unsigned long, read_cr0);
+ return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr0);
}
static inline void write_cr0(unsigned long x)
{
- PVOP_VCALL1(write_cr0, x);
+ PVOP_VCALL1(pv_cpu_ops.write_cr0, x);
}
static inline unsigned long read_cr2(void)
{
- return PVOP_CALL0(unsigned long, read_cr2);
+ return PVOP_CALL0(unsigned long, pv_mmu_ops.read_cr2);
}
static inline void write_cr2(unsigned long x)
{
- PVOP_VCALL1(write_cr2, x);
+ PVOP_VCALL1(pv_mmu_ops.write_cr2, x);
}
static inline unsigned long read_cr3(void)
{
- return PVOP_CALL0(unsigned long, read_cr3);
+ return PVOP_CALL0(unsigned long, pv_mmu_ops.read_cr3);
}
static inline void write_cr3(unsigned long x)
{
- PVOP_VCALL1(write_cr3, x);
+ PVOP_VCALL1(pv_mmu_ops.write_cr3, x);
}
static inline unsigned long read_cr4(void)
{
- return PVOP_CALL0(unsigned long, read_cr4);
+ return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr4);
}
static inline unsigned long read_cr4_safe(void)
{
- return PVOP_CALL0(unsigned long, read_cr4_safe);
+ return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr4_safe);
}
static inline void write_cr4(unsigned long x)
{
- PVOP_VCALL1(write_cr4, x);
+ PVOP_VCALL1(pv_cpu_ops.write_cr4, x);
}
static inline void raw_safe_halt(void)
{
- PVOP_VCALL0(safe_halt);
+ PVOP_VCALL0(pv_irq_ops.safe_halt);
}
static inline void halt(void)
{
- PVOP_VCALL0(safe_halt);
+ PVOP_VCALL0(pv_irq_ops.safe_halt);
}
static inline void wbinvd(void)
{
- PVOP_VCALL0(wbinvd);
+ PVOP_VCALL0(pv_cpu_ops.wbinvd);
}
-#define get_kernel_rpl() (paravirt_ops.kernel_rpl)
+#define get_kernel_rpl() (pv_info.kernel_rpl)
static inline u64 paravirt_read_msr(unsigned msr, int *err)
{
- return PVOP_CALL2(u64, read_msr, msr, err);
+ return PVOP_CALL2(u64, pv_cpu_ops.read_msr, msr, err);
}
static inline int paravirt_write_msr(unsigned msr, unsigned low, unsigned high)
{
- return PVOP_CALL3(int, write_msr, msr, low, high);
+ return PVOP_CALL3(int, pv_cpu_ops.write_msr, msr, low, high);
}
/* These should all do BUG_ON(_err), but our headers are too tangled. */
@@ -560,7 +597,7 @@ static inline int paravirt_write_msr(unsigned msr, unsigned low, unsigned high)
static inline u64 paravirt_read_tsc(void)
{
- return PVOP_CALL0(u64, read_tsc);
+ return PVOP_CALL0(u64, pv_cpu_ops.read_tsc);
}
#define rdtscl(low) do { \
@@ -572,15 +609,15 @@ static inline u64 paravirt_read_tsc(void)
static inline unsigned long long paravirt_sched_clock(void)
{
- return PVOP_CALL0(unsigned long long, sched_clock);
+ return PVOP_CALL0(unsigned long long, pv_time_ops.sched_clock);
}
-#define calculate_cpu_khz() (paravirt_ops.get_cpu_khz())
+#define calculate_cpu_khz() (pv_time_ops.get_cpu_khz())
#define write_tsc(val1,val2) wrmsr(0x10, val1, val2)
static inline unsigned long long paravirt_read_pmc(int counter)
{
- return PVOP_CALL1(u64, read_pmc, counter);
+ return PVOP_CALL1(u64, pv_cpu_ops.read_pmc, counter);
}
#define rdpmc(counter,low,high) do { \
@@ -591,61 +628,61 @@ static inline unsigned long long paravirt_read_pmc(int counter)
static inline void load_TR_desc(void)
{
- PVOP_VCALL0(load_tr_desc);
+ PVOP_VCALL0(pv_cpu_ops.load_tr_desc);
}
static inline void load_gdt(const struct Xgt_desc_struct *dtr)
{
- PVOP_VCALL1(load_gdt, dtr);
+ PVOP_VCALL1(pv_cpu_ops.load_gdt, dtr);
}
static inline void load_idt(const struct Xgt_desc_struct *dtr)
{
- PVOP_VCALL1(load_idt, dtr);
+ PVOP_VCALL1(pv_cpu_ops.load_idt, dtr);
}
static inline void set_ldt(const void *addr, unsigned entries)
{
- PVOP_VCALL2(set_ldt, addr, entries);
+ PVOP_VCALL2(pv_cpu_ops.set_ldt, addr, entries);
}
static inline void store_gdt(struct Xgt_desc_struct *dtr)
{
- PVOP_VCALL1(store_gdt, dtr);
+ PVOP_VCALL1(pv_cpu_ops.store_gdt, dtr);
}
static inline void store_idt(struct Xgt_desc_struct *dtr)
{
- PVOP_VCALL1(store_idt, dtr);
+ PVOP_VCALL1(pv_cpu_ops.store_idt, dtr);
}
static inline unsigned long paravirt_store_tr(void)
{
- return PVOP_CALL0(unsigned long, store_tr);
+ return PVOP_CALL0(unsigned long, pv_cpu_ops.store_tr);
}
#define store_tr(tr) ((tr) = paravirt_store_tr())
static inline void load_TLS(struct thread_struct *t, unsigned cpu)
{
- PVOP_VCALL2(load_tls, t, cpu);
+ PVOP_VCALL2(pv_cpu_ops.load_tls, t, cpu);
}
static inline void write_ldt_entry(void *dt, int entry, u32 low, u32 high)
{
- PVOP_VCALL4(write_ldt_entry, dt, entry, low, high);
+ PVOP_VCALL4(pv_cpu_ops.write_ldt_entry, dt, entry, low, high);
}
static inline void write_gdt_entry(void *dt, int entry, u32 low, u32 high)
{
- PVOP_VCALL4(write_gdt_entry, dt, entry, low, high);
+ PVOP_VCALL4(pv_cpu_ops.write_gdt_entry, dt, entry, low, high);
}
static inline void write_idt_entry(void *dt, int entry, u32 low, u32 high)
{
- PVOP_VCALL4(write_idt_entry, dt, entry, low, high);
+ PVOP_VCALL4(pv_cpu_ops.write_idt_entry, dt, entry, low, high);
}
static inline void set_iopl_mask(unsigned mask)
{
- PVOP_VCALL1(set_iopl_mask, mask);
+ PVOP_VCALL1(pv_cpu_ops.set_iopl_mask, mask);
}
/* The paravirtualized I/O functions */
static inline void slow_down_io(void) {
- paravirt_ops.io_delay();
+ pv_cpu_ops.io_delay();
#ifdef REALLY_SLOW_IO
- paravirt_ops.io_delay();
- paravirt_ops.io_delay();
- paravirt_ops.io_delay();
+ pv_cpu_ops.io_delay();
+ pv_cpu_ops.io_delay();
+ pv_cpu_ops.io_delay();
#endif
}
@@ -655,121 +692,120 @@ static inline void slow_down_io(void) {
*/
static inline void apic_write(unsigned long reg, unsigned long v)
{
- PVOP_VCALL2(apic_write, reg, v);
+ PVOP_VCALL2(pv_apic_ops.apic_write, reg, v);
}
static inline void apic_write_atomic(unsigned long reg, unsigned long v)
{
- PVOP_VCALL2(apic_write_atomic, reg, v);
+ PVOP_VCALL2(pv_apic_ops.apic_write_atomic, reg, v);
}
static inline unsigned long apic_read(unsigned long reg)
{
- return PVOP_CALL1(unsigned long, apic_read, reg);
+ return PVOP_CALL1(unsigned long, pv_apic_ops.apic_read, reg);
}
static inline void setup_boot_clock(void)
{
- PVOP_VCALL0(setup_boot_clock);
+ PVOP_VCALL0(pv_apic_ops.setup_boot_clock);
}
static inline void setup_secondary_clock(void)
{
- PVOP_VCALL0(setup_secondary_clock);
+ PVOP_VCALL0(pv_apic_ops.setup_secondary_clock);
}
#endif
static inline void paravirt_post_allocator_init(void)
{
- if (paravirt_ops.post_allocator_init)
- (*paravirt_ops.post_allocator_init)();
+ if (pv_init_ops.post_allocator_init)
+ (*pv_init_ops.post_allocator_init)();
}
static inline void paravirt_pagetable_setup_start(pgd_t *base)
{
- if (paravirt_ops.pagetable_setup_start)
- (*paravirt_ops.pagetable_setup_start)(base);
+ (*pv_mmu_ops.pagetable_setup_start)(base);
}
static inline void paravirt_pagetable_setup_done(pgd_t *base)
{
- if (paravirt_ops.pagetable_setup_done)
- (*paravirt_ops.pagetable_setup_done)(base);
+ (*pv_mmu_ops.pagetable_setup_done)(base);
}
#ifdef CONFIG_SMP
static inline void startup_ipi_hook(int phys_apicid, unsigned long start_eip,
unsigned long start_esp)
{
- PVOP_VCALL3(startup_ipi_hook, phys_apicid, start_eip, start_esp);
+ PVOP_VCALL3(pv_apic_ops.startup_ipi_hook,
+ phys_apicid, start_eip, start_esp);
}
#endif
static inline void paravirt_activate_mm(struct mm_struct *prev,
struct mm_struct *next)
{
- PVOP_VCALL2(activate_mm, prev, next);
+ PVOP_VCALL2(pv_mmu_ops.activate_mm, prev, next);
}
static inline void arch_dup_mmap(struct mm_struct *oldmm,
struct mm_struct *mm)
{
- PVOP_VCALL2(dup_mmap, oldmm, mm);
+ PVOP_VCALL2(pv_mmu_ops.dup_mmap, oldmm, mm);
}
static inline void arch_exit_mmap(struct mm_struct *mm)
{
- PVOP_VCALL1(exit_mmap, mm);
+ PVOP_VCALL1(pv_mmu_ops.exit_mmap, mm);
}
static inline void __flush_tlb(void)
{
- PVOP_VCALL0(flush_tlb_user);
+ PVOP_VCALL0(pv_mmu_ops.flush_tlb_user);
}
static inline void __flush_tlb_global(void)
{
- PVOP_VCALL0(flush_tlb_kernel);
+ PVOP_VCALL0(pv_mmu_ops.flush_tlb_kernel);
}
static inline void __flush_tlb_single(unsigned long addr)
{
- PVOP_VCALL1(flush_tlb_single, addr);
+ PVOP_VCALL1(pv_mmu_ops.flush_tlb_single, addr);
}
static inline void flush_tlb_others(cpumask_t cpumask, struct mm_struct *mm,
unsigned long va)
{
- PVOP_VCALL3(flush_tlb_others, &cpumask, mm, va);
+ PVOP_VCALL3(pv_mmu_ops.flush_tlb_others, &cpumask, mm, va);
}
static inline void paravirt_alloc_pt(struct mm_struct *mm, unsigned pfn)
{
- PVOP_VCALL2(alloc_pt, mm, pfn);
+ PVOP_VCALL2(pv_mmu_ops.alloc_pt, mm, pfn);
}
static inline void paravirt_release_pt(unsigned pfn)
{
- PVOP_VCALL1(release_pt, pfn);
+ PVOP_VCALL1(pv_mmu_ops.release_pt, pfn);
}
static inline void paravirt_alloc_pd(unsigned pfn)
{
- PVOP_VCALL1(alloc_pd, pfn);
+ PVOP_VCALL1(pv_mmu_ops.alloc_pd, pfn);
}
static inline void paravirt_alloc_pd_clone(unsigned pfn, unsigned clonepfn,
unsigned start, unsigned count)
{
- PVOP_VCALL4(alloc_pd_clone, pfn, clonepfn, start, count);
+ PVOP_VCALL4(pv_mmu_ops.alloc_pd_clone, pfn, clonepfn, start, count);
}
static inline void paravirt_release_pd(unsigned pfn)
{
- PVOP_VCALL1(release_pd, pfn);
+ PVOP_VCALL1(pv_mmu_ops.release_pd, pfn);
}
#ifdef CONFIG_HIGHPTE
static inline void *kmap_atomic_pte(struct page *page, enum km_type type)
{
unsigned long ret;
- ret = PVOP_CALL2(unsigned long, kmap_atomic_pte, page, type);
+ ret = PVOP_CALL2(unsigned long, pv_mmu_ops.kmap_atomic_pte, page, type);
return (void *)ret;
}
#endif
@@ -777,162 +813,191 @@ static inline void *kmap_atomic_pte(struct page *page, enum km_type type)
static inline void pte_update(struct mm_struct *mm, unsigned long addr,
pte_t *ptep)
{
- PVOP_VCALL3(pte_update, mm, addr, ptep);
+ PVOP_VCALL3(pv_mmu_ops.pte_update, mm, addr, ptep);
}
static inline void pte_update_defer(struct mm_struct *mm, unsigned long addr,
pte_t *ptep)
{
- PVOP_VCALL3(pte_update_defer, mm, addr, ptep);
+ PVOP_VCALL3(pv_mmu_ops.pte_update_defer, mm, addr, ptep);
}
#ifdef CONFIG_X86_PAE
static inline pte_t __pte(unsigned long long val)
{
- unsigned long long ret = PVOP_CALL2(unsigned long long, make_pte,
+ unsigned long long ret = PVOP_CALL2(unsigned long long,
+ pv_mmu_ops.make_pte,
val, val >> 32);
return (pte_t) { ret, ret >> 32 };
}
static inline pmd_t __pmd(unsigned long long val)
{
- return (pmd_t) { PVOP_CALL2(unsigned long long, make_pmd, val, val >> 32) };
+ return (pmd_t) { PVOP_CALL2(unsigned long long, pv_mmu_ops.make_pmd,
+ val, val >> 32) };
}
static inline pgd_t __pgd(unsigned long long val)
{
- return (pgd_t) { PVOP_CALL2(unsigned long long, make_pgd, val, val >> 32) };
+ return (pgd_t) { PVOP_CALL2(unsigned long long, pv_mmu_ops.make_pgd,
+ val, val >> 32) };
}
static inline unsigned long long pte_val(pte_t x)
{
- return PVOP_CALL2(unsigned long long, pte_val, x.pte_low, x.pte_high);
+ return PVOP_CALL2(unsigned long long, pv_mmu_ops.pte_val,
+ x.pte_low, x.pte_high);
}
static inline unsigned long long pmd_val(pmd_t x)
{
- return PVOP_CALL2(unsigned long long, pmd_val, x.pmd, x.pmd >> 32);
+ return PVOP_CALL2(unsigned long long, pv_mmu_ops.pmd_val,
+ x.pmd, x.pmd >> 32);
}
static inline unsigned long long pgd_val(pgd_t x)
{
- return PVOP_CALL2(unsigned long long, pgd_val, x.pgd, x.pgd >> 32);
+ return PVOP_CALL2(unsigned long long, pv_mmu_ops.pgd_val,
+ x.pgd, x.pgd >> 32);
}
static inline void set_pte(pte_t *ptep, pte_t pteval)
{
- PVOP_VCALL3(set_pte, ptep, pteval.pte_low, pteval.pte_high);
+ PVOP_VCALL3(pv_mmu_ops.set_pte, ptep, pteval.pte_low, pteval.pte_high);
}
static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
pte_t *ptep, pte_t pteval)
{
/* 5 arg words */
- paravirt_ops.set_pte_at(mm, addr, ptep, pteval);
+ pv_mmu_ops.set_pte_at(mm, addr, ptep, pteval);
}
static inline void set_pte_atomic(pte_t *ptep, pte_t pteval)
{
- PVOP_VCALL3(set_pte_atomic, ptep, pteval.pte_low, pteval.pte_high);
+ PVOP_VCALL3(pv_mmu_ops.set_pte_atomic, ptep,
+ pteval.pte_low, pteval.pte_high);
}
static inline void set_pte_present(struct mm_struct *mm, unsigned long addr,
pte_t *ptep, pte_t pte)
{
/* 5 arg words */
- paravirt_ops.set_pte_present(mm, addr, ptep, pte);
+ pv_mmu_ops.set_pte_present(mm, addr, ptep, pte);
}
static inline void set_pmd(pmd_t *pmdp, pmd_t pmdval)
{
- PVOP_VCALL3(set_pmd, pmdp, pmdval.pmd, pmdval.pmd >> 32);
+ PVOP_VCALL3(pv_mmu_ops.set_pmd, pmdp,
+ pmdval.pmd, pmdval.pmd >> 32);
}
static inline void set_pud(pud_t *pudp, pud_t pudval)
{
- PVOP_VCALL3(set_pud, pudp, pudval.pgd.pgd, pudval.pgd.pgd >> 32);
+ PVOP_VCALL3(pv_mmu_ops.set_pud, pudp,
+ pudval.pgd.pgd, pudval.pgd.pgd >> 32);
}
static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
{
- PVOP_VCALL3(pte_clear, mm, addr, ptep);
+ PVOP_VCALL3(pv_mmu_ops.pte_clear, mm, addr, ptep);
}
static inline void pmd_clear(pmd_t *pmdp)
{
- PVOP_VCALL1(pmd_clear, pmdp);
+ PVOP_VCALL1(pv_mmu_ops.pmd_clear, pmdp);
}
#else /* !CONFIG_X86_PAE */
static inline pte_t __pte(unsigned long val)
{
- return (pte_t) { PVOP_CALL1(unsigned long, make_pte, val) };
+ return (pte_t) { PVOP_CALL1(unsigned long, pv_mmu_ops.make_pte, val) };
}
static inline pgd_t __pgd(unsigned long val)
{
- return (pgd_t) { PVOP_CALL1(unsigned long, make_pgd, val) };
+ return (pgd_t) { PVOP_CALL1(unsigned long, pv_mmu_ops.make_pgd, val) };
}
static inline unsigned long pte_val(pte_t x)
{
- return PVOP_CALL1(unsigned long, pte_val, x.pte_low);
+ return PVOP_CALL1(unsigned long, pv_mmu_ops.pte_val, x.pte_low);
}
static inline unsigned long pgd_val(pgd_t x)
{
- return PVOP_CALL1(unsigned long, pgd_val, x.pgd);
+ return PVOP_CALL1(unsigned long, pv_mmu_ops.pgd_val, x.pgd);
}
static inline void set_pte(pte_t *ptep, pte_t pteval)
{
- PVOP_VCALL2(set_pte, ptep, pteval.pte_low);
+ PVOP_VCALL2(pv_mmu_ops.set_pte, ptep, pteval.pte_low);
}
static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
pte_t *ptep, pte_t pteval)
{
- PVOP_VCALL4(set_pte_at, mm, addr, ptep, pteval.pte_low);
+ PVOP_VCALL4(pv_mmu_ops.set_pte_at, mm, addr, ptep, pteval.pte_low);
}
static inline void set_pmd(pmd_t *pmdp, pmd_t pmdval)
{
- PVOP_VCALL2(set_pmd, pmdp, pmdval.pud.pgd.pgd);
+ PVOP_VCALL2(pv_mmu_ops.set_pmd, pmdp, pmdval.pud.pgd.pgd);
}
#endif /* CONFIG_X86_PAE */
+/* Lazy mode for batching updates / context switch */
+enum paravirt_lazy_mode {
+ PARAVIRT_LAZY_NONE,
+ PARAVIRT_LAZY_MMU,
+ PARAVIRT_LAZY_CPU,
+};
+
+enum paravirt_lazy_mode paravirt_get_lazy_mode(void);
+void paravirt_enter_lazy_cpu(void);
+void paravirt_leave_lazy_cpu(void);
+void paravirt_enter_lazy_mmu(void);
+void paravirt_leave_lazy_mmu(void);
+void paravirt_leave_lazy(enum paravirt_lazy_mode mode);
+
#define __HAVE_ARCH_ENTER_LAZY_CPU_MODE
static inline void arch_enter_lazy_cpu_mode(void)
{
- PVOP_VCALL1(set_lazy_mode, PARAVIRT_LAZY_CPU);
+ PVOP_VCALL0(pv_cpu_ops.lazy_mode.enter);
}
static inline void arch_leave_lazy_cpu_mode(void)
{
- PVOP_VCALL1(set_lazy_mode, PARAVIRT_LAZY_NONE);
+ PVOP_VCALL0(pv_cpu_ops.lazy_mode.leave);
}
static inline void arch_flush_lazy_cpu_mode(void)
{
- PVOP_VCALL1(set_lazy_mode, PARAVIRT_LAZY_FLUSH);
+ if (unlikely(paravirt_get_lazy_mode() == PARAVIRT_LAZY_CPU)) {
+ arch_leave_lazy_cpu_mode();
+ arch_enter_lazy_cpu_mode();
+ }
}
#define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
static inline void arch_enter_lazy_mmu_mode(void)
{
- PVOP_VCALL1(set_lazy_mode, PARAVIRT_LAZY_MMU);
+ PVOP_VCALL0(pv_mmu_ops.lazy_mode.enter);
}
static inline void arch_leave_lazy_mmu_mode(void)
{
- PVOP_VCALL1(set_lazy_mode, PARAVIRT_LAZY_NONE);
+ PVOP_VCALL0(pv_mmu_ops.lazy_mode.leave);
}
static inline void arch_flush_lazy_mmu_mode(void)
{
- PVOP_VCALL1(set_lazy_mode, PARAVIRT_LAZY_FLUSH);
+ if (unlikely(paravirt_get_lazy_mode() == PARAVIRT_LAZY_MMU)) {
+ arch_leave_lazy_mmu_mode();
+ arch_enter_lazy_mmu_mode();
+ }
}
void _paravirt_nop(void);
@@ -957,7 +1022,7 @@ static inline unsigned long __raw_local_save_flags(void)
PARAVIRT_CALL
"popl %%edx; popl %%ecx")
: "=a"(f)
- : paravirt_type(save_fl),
+ : paravirt_type(pv_irq_ops.save_fl),
paravirt_clobber(CLBR_EAX)
: "memory", "cc");
return f;
@@ -970,7 +1035,7 @@ static inline void raw_local_irq_restore(unsigned long f)
"popl %%edx; popl %%ecx")
: "=a"(f)
: "0"(f),
- paravirt_type(restore_fl),
+ paravirt_type(pv_irq_ops.restore_fl),
paravirt_clobber(CLBR_EAX)
: "memory", "cc");
}
@@ -981,7 +1046,7 @@ static inline void raw_local_irq_disable(void)
PARAVIRT_CALL
"popl %%edx; popl %%ecx")
:
- : paravirt_type(irq_disable),
+ : paravirt_type(pv_irq_ops.irq_disable),
paravirt_clobber(CLBR_EAX)
: "memory", "eax", "cc");
}
@@ -992,7 +1057,7 @@ static inline void raw_local_irq_enable(void)
PARAVIRT_CALL
"popl %%edx; popl %%ecx")
:
- : paravirt_type(irq_enable),
+ : paravirt_type(pv_irq_ops.irq_enable),
paravirt_clobber(CLBR_EAX)
: "memory", "eax", "cc");
}
@@ -1008,21 +1073,23 @@ static inline unsigned long __raw_local_irq_save(void)
#define CLI_STRING \
_paravirt_alt("pushl %%ecx; pushl %%edx;" \
- "call *paravirt_ops+%c[paravirt_cli_type]*4;" \
+ "call *%[paravirt_cli_opptr];" \
"popl %%edx; popl %%ecx", \
"%c[paravirt_cli_type]", "%c[paravirt_clobber]")
#define STI_STRING \
_paravirt_alt("pushl %%ecx; pushl %%edx;" \
- "call *paravirt_ops+%c[paravirt_sti_type]*4;" \
+ "call *%[paravirt_sti_opptr];" \
"popl %%edx; popl %%ecx", \
"%c[paravirt_sti_type]", "%c[paravirt_clobber]")
#define CLI_STI_CLOBBERS , "%eax"
#define CLI_STI_INPUT_ARGS \
, \
- [paravirt_cli_type] "i" (PARAVIRT_PATCH(irq_disable)), \
- [paravirt_sti_type] "i" (PARAVIRT_PATCH(irq_enable)), \
+ [paravirt_cli_type] "i" (PARAVIRT_PATCH(pv_irq_ops.irq_disable)), \
+ [paravirt_cli_opptr] "m" (pv_irq_ops.irq_disable), \
+ [paravirt_sti_type] "i" (PARAVIRT_PATCH(pv_irq_ops.irq_enable)), \
+ [paravirt_sti_opptr] "m" (pv_irq_ops.irq_enable), \
paravirt_clobber(CLBR_EAX)
/* Make sure as little as possible of this mess escapes. */
@@ -1042,7 +1109,7 @@ static inline unsigned long __raw_local_irq_save(void)
#else /* __ASSEMBLY__ */
-#define PARA_PATCH(off) ((off) / 4)
+#define PARA_PATCH(struct, off) ((PARAVIRT_PATCH_##struct + (off)) / 4)
#define PARA_SITE(ptype, clobbers, ops) \
771:; \
@@ -1055,29 +1122,29 @@ static inline unsigned long __raw_local_irq_save(void)
.short clobbers; \
.popsection
-#define INTERRUPT_RETURN \
- PARA_SITE(PARA_PATCH(PARAVIRT_iret), CLBR_NONE, \
- jmp *%cs:paravirt_ops+PARAVIRT_iret)
+#define INTERRUPT_RETURN \
+ PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_iret), CLBR_NONE, \
+ jmp *%cs:pv_cpu_ops+PV_CPU_iret)
#define DISABLE_INTERRUPTS(clobbers) \
- PARA_SITE(PARA_PATCH(PARAVIRT_irq_disable), clobbers, \
+ PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_disable), clobbers, \
pushl %eax; pushl %ecx; pushl %edx; \
- call *%cs:paravirt_ops+PARAVIRT_irq_disable; \
+ call *%cs:pv_irq_ops+PV_IRQ_irq_disable; \
popl %edx; popl %ecx; popl %eax) \
#define ENABLE_INTERRUPTS(clobbers) \
- PARA_SITE(PARA_PATCH(PARAVIRT_irq_enable), clobbers, \
+ PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_enable), clobbers, \
pushl %eax; pushl %ecx; pushl %edx; \
- call *%cs:paravirt_ops+PARAVIRT_irq_enable; \
+ call *%cs:pv_irq_ops+PV_IRQ_irq_enable; \
popl %edx; popl %ecx; popl %eax)
-#define ENABLE_INTERRUPTS_SYSEXIT \
- PARA_SITE(PARA_PATCH(PARAVIRT_irq_enable_sysexit), CLBR_NONE, \
- jmp *%cs:paravirt_ops+PARAVIRT_irq_enable_sysexit)
+#define ENABLE_INTERRUPTS_SYSEXIT \
+ PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_irq_enable_sysexit), CLBR_NONE,\
+ jmp *%cs:pv_cpu_ops+PV_CPU_irq_enable_sysexit)
#define GET_CR0_INTO_EAX \
push %ecx; push %edx; \
- call *paravirt_ops+PARAVIRT_read_cr0; \
+ call *pv_cpu_ops+PV_CPU_read_cr0; \
pop %edx; pop %ecx
#endif /* __ASSEMBLY__ */
diff --git a/include/asm-x86/pgtable-3level-defs.h b/include/asm-x86/pgtable-3level-defs.h
index c0df89f66e8b..448ac9516314 100644
--- a/include/asm-x86/pgtable-3level-defs.h
+++ b/include/asm-x86/pgtable-3level-defs.h
@@ -2,7 +2,7 @@
#define _I386_PGTABLE_3LEVEL_DEFS_H
#ifdef CONFIG_PARAVIRT
-#define SHARED_KERNEL_PMD (paravirt_ops.shared_kernel_pmd)
+#define SHARED_KERNEL_PMD (pv_info.shared_kernel_pmd)
#else
#define SHARED_KERNEL_PMD 1
#endif
diff --git a/include/xen/interface/vcpu.h b/include/xen/interface/vcpu.h
index ff61ea365997..b05d8a6d9143 100644
--- a/include/xen/interface/vcpu.h
+++ b/include/xen/interface/vcpu.h
@@ -160,8 +160,9 @@ struct vcpu_set_singleshot_timer {
*/
#define VCPUOP_register_vcpu_info 10 /* arg == struct vcpu_info */
struct vcpu_register_vcpu_info {
- uint32_t mfn; /* mfn of page to place vcpu_info */
- uint32_t offset; /* offset within page */
+ uint64_t mfn; /* mfn of page to place vcpu_info */
+ uint32_t offset; /* offset within page */
+ uint32_t rsvd; /* unused */
};
#endif /* __XEN_PUBLIC_VCPU_H__ */
OpenPOWER on IntegriCloud