diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-mips/cpu-features.h | 11 | ||||
| -rw-r--r-- | include/asm-mips/mach-ja/cpu-feature-overrides.h | 6 | ||||
| -rw-r--r-- | include/asm-mips/mach-ocelot3/cpu-feature-overrides.h | 6 | ||||
| -rw-r--r-- | include/asm-mips/mach-yosemite/cpu-feature-overrides.h | 6 | ||||
| -rw-r--r-- | include/asm-mips/war.h | 14 |
5 files changed, 14 insertions, 29 deletions
diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h index 4930824a43aa..bb2212cf460a 100644 --- a/include/asm-mips/cpu-features.h +++ b/include/asm-mips/cpu-features.h @@ -109,17 +109,6 @@ #define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) #endif -/* - * Certain CPUs may throw bizarre exceptions if not the whole cacheline - * contains valid instructions. For these we ensure proper alignment of - * signal trampolines and pad them to the size of a full cache lines with - * nops. This is also used in structure definitions so can't be a test macro - * like the others. - */ -#ifndef PLAT_TRAMPOLINE_STUFF_LINE -#define PLAT_TRAMPOLINE_STUFF_LINE 0UL -#endif - #ifdef CONFIG_32BIT # ifndef cpu_has_nofpuex # define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX) diff --git a/include/asm-mips/mach-ja/cpu-feature-overrides.h b/include/asm-mips/mach-ja/cpu-feature-overrides.h index 310609c0f4ad..a0fde405d4c4 100644 --- a/include/asm-mips/mach-ja/cpu-feature-overrides.h +++ b/include/asm-mips/mach-ja/cpu-feature-overrides.h @@ -37,10 +37,4 @@ #define cpu_icache_line_size() 32 #define cpu_scache_line_size() 32 -/* - * On the RM9000 we need to ensure that I-cache lines being fetches only - * contain valid instructions are funny things will happen. - */ -#define PLAT_TRAMPOLINE_STUFF_LINE 32UL - #endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */ diff --git a/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h b/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h index 1812fc0408d3..825c5f674dfc 100644 --- a/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h +++ b/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h @@ -40,10 +40,4 @@ #define cpu_icache_line_size() 32 #define cpu_scache_line_size() 32 -/* - * On the RM9000 we need to ensure that I-cache lines being fetches only - * contain valid instructions are funny things will happen. - */ -#define PLAT_TRAMPOLINE_STUFF_LINE 32UL - #endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */ diff --git a/include/asm-mips/mach-yosemite/cpu-feature-overrides.h b/include/asm-mips/mach-yosemite/cpu-feature-overrides.h index 63e94342e087..463d051f4683 100644 --- a/include/asm-mips/mach-yosemite/cpu-feature-overrides.h +++ b/include/asm-mips/mach-yosemite/cpu-feature-overrides.h @@ -37,10 +37,4 @@ #define cpu_icache_line_size() 32 #define cpu_scache_line_size() 32 -/* - * On the RM9000 we need to ensure that I-cache lines being fetches only - * contain valid instructions are funny things will happen. - */ -#define PLAT_TRAMPOLINE_STUFF_LINE 32UL - #endif /* __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H */ diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h index 04ee53b34c2e..ad374bd3f130 100644 --- a/include/asm-mips/war.h +++ b/include/asm-mips/war.h @@ -177,6 +177,17 @@ #endif /* + * The RM9000 has a bug (though PMC-Sierra opposes it being called that) + * where invalid instructions in the same I-cache line worth of instructions + * being fetched may case spurious exceptions. + */ +#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_MOMENCO_OCELOT_3) || \ + defined(CONFIG_PMC_YOSEMITE) +#define ICACHE_REFILLS_WORKAROUND_WAR 1 +#endif + + +/* * ON the R10000 upto version 2.6 (not sure about 2.7) there is a bug that * may cause ll / sc and lld / scd sequences to execute non-atomically. */ @@ -187,6 +198,9 @@ /* * Workarounds default to off */ +#ifndef ICACHE_REFILLS_WORKAROUND_WAR +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#endif #ifndef R4600_V1_INDEX_ICACHEOP_WAR #define R4600_V1_INDEX_ICACHEOP_WAR 0 #endif |
