diff options
Diffstat (limited to 'include')
186 files changed, 4925 insertions, 1496 deletions
diff --git a/include/asm-alpha/smp.h b/include/asm-alpha/smp.h index 06fb6c119671..a1a1eca6be45 100644 --- a/include/asm-alpha/smp.h +++ b/include/asm-alpha/smp.h @@ -44,10 +44,8 @@ extern struct cpuinfo_alpha cpu_data[NR_CPUS]; #define hard_smp_processor_id() __hard_smp_processor_id() #define raw_smp_processor_id() (current_thread_info()->cpu) -extern cpumask_t cpu_present_mask; -extern cpumask_t cpu_online_map; extern int smp_num_cpus; -#define cpu_possible_map cpu_present_mask +#define cpu_possible_map cpu_present_map int smp_call_function_on_cpu(void (*func) (void *info), void *info,int retry, int wait, cpumask_t cpu); diff --git a/include/asm-alpha/termbits.h b/include/asm-alpha/termbits.h index f4837fa29420..5541101b58ae 100644 --- a/include/asm-alpha/termbits.h +++ b/include/asm-alpha/termbits.h @@ -148,6 +148,7 @@ struct termios { #define HUPCL 00040000 #define CLOCAL 00100000 +#define CMSPAR 010000000000 /* mark or space (stick) parity */ #define CRTSCTS 020000000000 /* flow control */ /* c_lflag bits */ diff --git a/include/asm-arm/arch-ixp23xx/memory.h b/include/asm-arm/arch-ixp23xx/memory.h index 6e19f46d54d1..c85fc06a043c 100644 --- a/include/asm-arm/arch-ixp23xx/memory.h +++ b/include/asm-arm/arch-ixp23xx/memory.h @@ -49,7 +49,7 @@ static inline int __ixp23xx_arch_is_coherent(void) { extern unsigned int processor_id; - if (((processor_id & 15) >= 2) || machine_is_roadrunner()) + if (((processor_id & 15) >= 4) || machine_is_roadrunner()) return 1; return 0; diff --git a/include/asm-arm/arch-l7200/serial_l7200.h b/include/asm-arm/arch-l7200/serial_l7200.h index 238c595d97ea..b1008a9d23e5 100644 --- a/include/asm-arm/arch-l7200/serial_l7200.h +++ b/include/asm-arm/arch-l7200/serial_l7200.h @@ -28,7 +28,7 @@ #define UARTDR 0x00 /* Tx/Rx data */ #define RXSTAT 0x04 /* Rx status */ #define H_UBRLCR 0x08 /* mode register high */ -#define M_UBRLCR 0x0C /* mode reg mid (MSB of buad)*/ +#define M_UBRLCR 0x0C /* mode reg mid (MSB of baud)*/ #define L_UBRLCR 0x10 /* mode reg low (LSB of baud)*/ #define UARTCON 0x14 /* control register */ #define UARTFLG 0x18 /* flag register */ diff --git a/include/asm-arm/arch-l7200/uncompress.h b/include/asm-arm/arch-l7200/uncompress.h index 9fcd40aee3e3..04be2a088639 100644 --- a/include/asm-arm/arch-l7200/uncompress.h +++ b/include/asm-arm/arch-l7200/uncompress.h @@ -6,7 +6,7 @@ * Changelog: * 05-01-2000 SJH Created * 05-13-2000 SJH Filled in function bodies - * 07-26-2000 SJH Removed hard coded buad rate + * 07-26-2000 SJH Removed hard coded baud rate */ #include <asm/hardware.h> diff --git a/include/asm-arm/arch-lh7a40x/clocks.h b/include/asm-arm/arch-lh7a40x/clocks.h new file mode 100644 index 000000000000..bee02fd8dab1 --- /dev/null +++ b/include/asm-arm/arch-lh7a40x/clocks.h @@ -0,0 +1,20 @@ +/* include/asm-arm/arch-lh7a40x/clocks.h + * + * Copyright (C) 2004 Marc Singer + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + */ + +#include <linux/config.h> + +#ifndef __ASM_ARCH_CLOCKS_H +#define __ASM_ARCH_CLOCKS_H + +unsigned int fclkfreq_get (void); +unsigned int hclkfreq_get (void); +unsigned int pclkfreq_get (void); + +#endif /* _ASM_ARCH_CLOCKS_H */ diff --git a/include/asm-arm/arch-lh7a40x/constants.h b/include/asm-arm/arch-lh7a40x/constants.h index 267d1145c3f9..51de96e87faf 100644 --- a/include/asm-arm/arch-lh7a40x/constants.h +++ b/include/asm-arm/arch-lh7a40x/constants.h @@ -28,8 +28,7 @@ #if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404) -# define IOBARRIER_PHYS 0xc0000000 /* Start of SDRAM */ -/*# define IOBARRIER_PHYS 0x00000000 */ /* Start of flash */ +# define IOBARRIER_PHYS 0x10000000 /* Second bank, fastest timing */ # define IOBARRIER_VIRT 0xf0000000 # define IOBARRIER_SIZE PAGE_SIZE @@ -52,6 +51,9 @@ # define CPLD08_PHYS CPLDX_PHYS (0x08) # define CPLD08_VIRT CPLDX_VIRT (0x08) # define CPLD08_SIZE PAGE_SIZE +# define CPLD0A_PHYS CPLDX_PHYS (0x0a) +# define CPLD0A_VIRT CPLDX_VIRT (0x0a) +# define CPLD0A_SIZE PAGE_SIZE # define CPLD0C_PHYS CPLDX_PHYS (0x0c) # define CPLD0C_VIRT CPLDX_VIRT (0x0c) # define CPLD0C_SIZE PAGE_SIZE @@ -83,5 +85,7 @@ #define XTAL_IN 14745600 /* 14.7456 MHz crystal */ #define PLL_CLOCK (XTAL_IN * 21) /* 309 MHz PLL clock */ #define MAX_HCLK_KHZ 100000 /* HCLK max limit ~100MHz */ +#define HCLK (99993600) +//#define HCLK (119808000) #endif /* __ASM_ARCH_CONSTANTS_H */ diff --git a/include/asm-arm/arch-lh7a40x/dma.h b/include/asm-arm/arch-lh7a40x/dma.h index 15492e3253f6..a8cbd14bbf9d 100644 --- a/include/asm-arm/arch-lh7a40x/dma.h +++ b/include/asm-arm/arch-lh7a40x/dma.h @@ -1,9 +1,86 @@ /* include/asm-arm/arch-lh7a40x/dma.h * - * Copyright (C) 2003 Coastal Environmental Systems + * Copyright (C) 2005 Marc Singer * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * version 2 as published by the Free Software Foundation. * */ + +typedef enum { + DMA_M2M0 = 0, + DMA_M2M1 = 1, + DMA_M2P0 = 2, /* Tx */ + DMA_M2P1 = 3, /* Rx */ + DMA_M2P2 = 4, /* Tx */ + DMA_M2P3 = 5, /* Rx */ + DMA_M2P4 = 6, /* Tx - AC97 */ + DMA_M2P5 = 7, /* Rx - AC97 */ + DMA_M2P6 = 8, /* Tx */ + DMA_M2P7 = 9, /* Rx */ +} dma_device_t; + +#define DMA_LENGTH_MAX ((64*1024) - 4) /* bytes */ + +#define DMAC_GCA __REG(DMAC_PHYS + 0x2b80) +#define DMAC_GIR __REG(DMAC_PHYS + 0x2bc0) + +#define DMAC_GIR_MMI1 (1<<11) +#define DMAC_GIR_MMI0 (1<<10) +#define DMAC_GIR_MPI8 (1<<9) +#define DMAC_GIR_MPI9 (1<<8) +#define DMAC_GIR_MPI6 (1<<7) +#define DMAC_GIR_MPI7 (1<<6) +#define DMAC_GIR_MPI4 (1<<5) +#define DMAC_GIR_MPI5 (1<<4) +#define DMAC_GIR_MPI2 (1<<3) +#define DMAC_GIR_MPI3 (1<<2) +#define DMAC_GIR_MPI0 (1<<1) +#define DMAC_GIR_MPI1 (1<<0) + +#define DMAC_M2P0 0x0000 +#define DMAC_M2P1 0x0040 +#define DMAC_M2P2 0x0080 +#define DMAC_M2P3 0x00c0 +#define DMAC_M2P4 0x0240 +#define DMAC_M2P5 0x0200 +#define DMAC_M2P6 0x02c0 +#define DMAC_M2P7 0x0280 +#define DMAC_M2P8 0x0340 +#define DMAC_M2P9 0x0300 +#define DMAC_M2M0 0x0100 +#define DMAC_M2M1 0x0140 + +#define DMAC_P_PCONTROL(c) __REG(DMAC_PHYS + (c) + 0x00) +#define DMAC_P_PINTERRUPT(c) __REG(DMAC_PHYS + (c) + 0x04) +#define DMAC_P_PPALLOC(c) __REG(DMAC_PHYS + (c) + 0x08) +#define DMAC_P_PSTATUS(c) __REG(DMAC_PHYS + (c) + 0x0c) +#define DMAC_P_REMAIN(c) __REG(DMAC_PHYS + (c) + 0x14) +#define DMAC_P_MAXCNT0(c) __REG(DMAC_PHYS + (c) + 0x20) +#define DMAC_P_BASE0(c) __REG(DMAC_PHYS + (c) + 0x24) +#define DMAC_P_CURRENT0(c) __REG(DMAC_PHYS + (c) + 0x28) +#define DMAC_P_MAXCNT1(c) __REG(DMAC_PHYS + (c) + 0x30) +#define DMAC_P_BASE1(c) __REG(DMAC_PHYS + (c) + 0x34) +#define DMAC_P_CURRENT1(c) __REG(DMAC_PHYS + (c) + 0x38) + +#define DMAC_PCONTROL_ENABLE (1<<4) + +#define DMAC_PORT_USB 0 +#define DMAC_PORT_SDMMC 1 +#define DMAC_PORT_AC97_1 2 +#define DMAC_PORT_AC97_2 3 +#define DMAC_PORT_AC97_3 4 +#define DMAC_PORT_UART1 6 +#define DMAC_PORT_UART2 7 +#define DMAC_PORT_UART3 8 + +#define DMAC_PSTATUS_CURRSTATE_SHIFT 4 +#define DMAC_PSTATUS_CURRSTATE_MASK 0x3 + +#define DMAC_PSTATUS_NEXTBUF (1<<6) +#define DMAC_PSTATUS_STALLRINT (1<<0) + +#define DMAC_INT_CHE (1<<3) +#define DMAC_INT_NFB (1<<1) +#define DMAC_INT_STALL (1<<0) diff --git a/include/asm-arm/arch-lh7a40x/entry-macro.S b/include/asm-arm/arch-lh7a40x/entry-macro.S index a2f67c06d9c9..9fc7f4988124 100644 --- a/include/asm-arm/arch-lh7a40x/entry-macro.S +++ b/include/asm-arm/arch-lh7a40x/entry-macro.S @@ -10,11 +10,73 @@ #include <asm/hardware.h> #include <asm/arch/irqs.h> -# if defined (CONFIG_ARCH_LH7A400) && defined (CONFIG_ARCH_LH7A404) -# error "LH7A400 and LH7A404 are mutually exclusive" -# endif +/* In order to allow there to be support for both of the processor + classes at the same time, we make a hack here that isn't very + pretty. At startup, the link pointed to with the + branch_irq_lh7a400 symbol is replaced with a NOP when the CPU is + detected as a lh7a404. -# if defined (CONFIG_ARCH_LH7A400) + *** FIXME: we should clean this up so that there is only one + implementation for each CPU's design. + +*/ + +#if defined (CONFIG_ARCH_LH7A400) && defined (CONFIG_ARCH_LH7A404) + + .macro disable_fiq + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + +branch_irq_lh7a400: b 1000f + +@ Implementation of the LH7A404 get_irqnr_and_base. + + mov \irqnr, #0 @ VIC1 irq base + mov \base, #io_p2v(0x80000000) @ APB registers + add \base, \base, #0x8000 + ldr \tmp, [\base, #0x0030] @ VIC1_VECTADDR + tst \tmp, #VA_VECTORED @ Direct vectored + bne 1002f + tst \tmp, #VA_VIC1DEFAULT @ Default vectored VIC1 + ldrne \irqstat, [\base, #0] @ VIC1_IRQSTATUS + bne 1001f + add \base, \base, #(0xa000 - 0x8000) + ldr \tmp, [\base, #0x0030] @ VIC2_VECTADDR + tst \tmp, #VA_VECTORED @ Direct vectored + bne 1002f + ldr \irqstat, [\base, #0] @ VIC2_IRQSTATUS + mov \irqnr, #32 @ VIC2 irq base + +1001: movs \irqstat, \irqstat, lsr #1 @ Shift into carry + bcs 1008f @ Bit set; irq found + add \irqnr, \irqnr, #1 + bne 1001b @ Until no bits + b 1009f @ Nothing? Hmm. +1002: and \irqnr, \tmp, #0x3f @ Mask for valid bits +1008: movs \irqstat, #1 @ Force !Z + str \tmp, [\base, #0x0030] @ Clear vector + b 1009f + +@ Implementation of the LH7A400 get_irqnr_and_base. + +1000: mov \irqnr, #0 + mov \base, #io_p2v(0x80000000) @ APB registers + ldr \irqstat, [\base, #0x500] @ PIC INTSR + +1001: movs \irqstat, \irqstat, lsr #1 @ Shift into carry + bcs 1008f @ Bit set; irq found + add \irqnr, \irqnr, #1 + bne 1001b @ Until no bits + b 1009f @ Nothing? Hmm. +1008: movs \irqstat, #1 @ Force !Z + +1009: + .endm + + + +#elif defined (CONFIG_ARCH_LH7A400) .macro disable_fiq .endm diff --git a/include/asm-arm/arch-lh7a40x/hardware.h b/include/asm-arm/arch-lh7a40x/hardware.h index aeb07c162e25..e9ff74fd7939 100644 --- a/include/asm-arm/arch-lh7a40x/hardware.h +++ b/include/asm-arm/arch-lh7a40x/hardware.h @@ -13,6 +13,8 @@ #ifndef __ASM_ARCH_HARDWARE_H #define __ASM_ARCH_HARDWARE_H +#include <asm/sizes.h> /* Added for the sake of amba-clcd driver */ + #define io_p2v(x) (0xf0000000 | (((x) & 0xfff00000) >> 4) | ((x) & 0x0000ffff)) #define io_v2p(x) ( (((x) & 0x0fff0000) << 4) | ((x) & 0x0000ffff)) @@ -53,6 +55,8 @@ typedef struct { volatile u8 offset[4096]; } __regbase8; #endif +#define MASK_AND_SET(v,m,s) (v) = ((v)&~(m))|(s) + #include "registers.h" #endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/include/asm-arm/arch-lh7a40x/irqs.h b/include/asm-arm/arch-lh7a40x/irqs.h index 189908b2b79a..afe8c7cbad6a 100644 --- a/include/asm-arm/arch-lh7a40x/irqs.h +++ b/include/asm-arm/arch-lh7a40x/irqs.h @@ -153,9 +153,10 @@ #if !defined (IRQ_GPIO0INTR) # define IRQ_GPIO0INTR IRQ_GPIO0FIQ #endif -#define IRQ_TICK IRQ_TINTR +#define IRQ_TICK IRQ_TINTR #define IRQ_PCC1_RDY IRQ_GPIO6INTR /* PCCard 1 ready */ #define IRQ_PCC2_RDY IRQ_GPIO7INTR /* PCCard 2 ready */ +#define IRQ_USB IRQ_USBINTR /* USB device */ #ifdef CONFIG_MACH_KEV7A400 # define IRQ_TS IRQ_GPIOFIQ /* Touchscreen */ @@ -190,6 +191,10 @@ # define IRQ_LPD7A400_TS IRQ_LPD7A40X_CPLD + 1 /* Touch screen */ #endif +#if defined (CONFIG_MACH_LPD7A400) +# define IRQ_TOUCH IRQ_LPD7A400_TS +#endif + #define NR_IRQS (NR_IRQ_CPU + NR_IRQ_BOARD) #endif diff --git a/include/asm-arm/arch-lh7a40x/registers.h b/include/asm-arm/arch-lh7a40x/registers.h index 3b0d4fcd36f7..b4f09b3e2d03 100644 --- a/include/asm-arm/arch-lh7a40x/registers.h +++ b/include/asm-arm/arch-lh7a40x/registers.h @@ -17,7 +17,7 @@ /* Physical register base addresses */ -#define AC97_PHYS (0x80000000) /* AC97 Controller */ +#define AC97C_PHYS (0x80000000) /* AC97 Controller */ #define MMC_PHYS (0x80000100) /* Multimedia Card Controller */ #define USB_PHYS (0x80000200) /* USB Client */ #define SCI_PHYS (0x80000300) /* Secure Card Interface */ @@ -34,6 +34,8 @@ #define RTC_PHYS (0x80000d00) /* Real-time Clock */ #define GPIO_PHYS (0x80000e00) /* General Purpose IO */ #define BMI_PHYS (0x80000f00) /* Battery Monitor Interface */ +#define HRTFTC_PHYS (0x80001000) /* High-res TFT Controller (LH7A400) */ +#define ALI_PHYS (0x80001000) /* Advanced LCD Interface (LH7A404) */ #define WDT_PHYS (0x80001400) /* Watchdog Timer */ #define SMC_PHYS (0x80002000) /* Static Memory Controller */ #define SDRC_PHYS (0x80002400) /* SDRAM Controller */ @@ -42,6 +44,7 @@ /* Physical registers of the LH7A404 */ +#define ADC_PHYS (0x80001300) /* A/D & Touchscreen Controller */ #define VIC1_PHYS (0x80008000) /* Vectored Interrupt Controller 1 */ #define USBH_PHYS (0x80009000) /* USB OHCI host controller */ #define VIC2_PHYS (0x8000a000) /* Vectored Interrupt Controller 2 */ @@ -52,10 +55,32 @@ /* Clock/State Controller register */ +#define CSC_PWRSR __REG(CSC_PHYS + 0x00) /* Reset register & ID */ #define CSC_PWRCNT __REG(CSC_PHYS + 0x04) /* Power control */ +#define CSC_CLKSET __REG(CSC_PHYS + 0x20) /* Clock speed control */ +#define CSC_USBDRESET __REG(CSC_PHYS + 0x4c) /* USB Device resets */ #define CSC_PWRCNT_USBH_EN (1<<28) /* USB Host power enable */ - +#define CSC_PWRCNT_DMAC_M2M1_EN (1<<27) +#define CSC_PWRCNT_DMAC_M2M0_EN (1<<26) +#define CSC_PWRCNT_DMAC_M2P8_EN (1<<25) +#define CSC_PWRCNT_DMAC_M2P9_EN (1<<24) +#define CSC_PWRCNT_DMAC_M2P6_EN (1<<23) +#define CSC_PWRCNT_DMAC_M2P7_EN (1<<22) +#define CSC_PWRCNT_DMAC_M2P4_EN (1<<21) +#define CSC_PWRCNT_DMAC_M2P5_EN (1<<20) +#define CSC_PWRCNT_DMAC_M2P2_EN (1<<19) +#define CSC_PWRCNT_DMAC_M2P3_EN (1<<18) +#define CSC_PWRCNT_DMAC_M2P0_EN (1<<17) +#define CSC_PWRCNT_DMAC_M2P1_EN (1<<16) + +#define CSC_PWRSR_CHIPMAN_SHIFT (24) +#define CSC_PWRSR_CHIPMAN_MASK (0xff) +#define CSC_PWRSR_CHIPID_SHIFT (16) +#define CSC_PWRSR_CHIPID_MASK (0xff) + +#define CSC_USBDRESET_APBRESETREG (1<<1) +#define CSC_USBDRESET_IORESETREG (1<<0) /* Interrupt Controller registers */ @@ -108,6 +133,13 @@ #define GPIO_GPIOFEOI __REG(GPIO_PHYS + 0x54) /* GPIO End-of-Interrupt */ #define GPIO_GPIOINTEN __REG(GPIO_PHYS + 0x58) /* GPIO Interrupt Enable */ #define GPIO_INTSTATUS __REG(GPIO_PHYS + 0x5c) /* GPIO Interrupt Status */ +#define GPIO_PINMUX __REG(GPIO_PHYS + 0x2c) +#define GPIO_PADD __REG(GPIO_PHYS + 0x10) +#define GPIO_PAD __REG(GPIO_PHYS + 0x00) +#define GPIO_PCD __REG(GPIO_PHYS + 0x08) +#define GPIO_PCDD __REG(GPIO_PHYS + 0x18) +#define GPIO_PEDD __REG(GPIO_PHYS + 0x24) +#define GPIO_PED __REG(GPIO_PHYS + 0x20) /* Static Memory Controller registers */ @@ -137,20 +169,21 @@ #endif #if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404) -# define CPLD_CONTROL __REG8(CPLD02_PHYS) -# define CPLD_SPI_DATA __REG8(CPLD06_PHYS) -# define CPLD_SPI_CONTROL __REG8(CPLD08_PHYS) -# define CPLD_SPI_EEPROM __REG8(CPLD0A_PHYS) -# define CPLD_INTERRUPTS __REG8(CPLD0C_PHYS) /* IRQ mask/status */ -# define CPLD_BOOT_MODE __REG8(CPLD0E_PHYS) -# define CPLD_FLASH __REG8(CPLD10_PHYS) -# define CPLD_POWER_MGMT __REG8(CPLD12_PHYS) -# define CPLD_REVISION __REG8(CPLD14_PHYS) -# define CPLD_GPIO_EXT __REG8(CPLD16_PHYS) -# define CPLD_GPIO_DATA __REG8(CPLD18_PHYS) -# define CPLD_GPIO_DIR __REG8(CPLD1A_PHYS) -#endif +# define CPLD_CONTROL __REG16(CPLD02_PHYS) +# define CPLD_SPI_DATA __REG16(CPLD06_PHYS) +# define CPLD_SPI_CONTROL __REG16(CPLD08_PHYS) +# define CPLD_SPI_EEPROM __REG16(CPLD0A_PHYS) +# define CPLD_INTERRUPTS __REG16(CPLD0C_PHYS) /* IRQ mask/status */ +# define CPLD_BOOT_MODE __REG16(CPLD0E_PHYS) +# define CPLD_FLASH __REG16(CPLD10_PHYS) +# define CPLD_POWER_MGMT __REG16(CPLD12_PHYS) +# define CPLD_REVISION __REG16(CPLD14_PHYS) +# define CPLD_GPIO_EXT __REG16(CPLD16_PHYS) +# define CPLD_GPIO_DATA __REG16(CPLD18_PHYS) +# define CPLD_GPIO_DIR __REG16(CPLD1A_PHYS) + +#endif /* Timer registers */ @@ -189,4 +222,3 @@ #endif /* _ASM_ARCH_REGISTERS_H */ - diff --git a/include/asm-arm/arch-lh7a40x/ssp.h b/include/asm-arm/arch-lh7a40x/ssp.h new file mode 100644 index 000000000000..132b1c4d5ce6 --- /dev/null +++ b/include/asm-arm/arch-lh7a40x/ssp.h @@ -0,0 +1,71 @@ +/* ssp.h + $Id$ + + written by Marc Singer + 6 Dec 2004 + + Copyright (C) 2004 Marc Singer + + ----------- + DESCRIPTION + ----------- + + This SSP header is available throughout the kernel, for this + machine/architecture, because drivers that use it may be dispersed. + + This file was cloned from the 7952x implementation. It would be + better to share them, but we're taking an easier approach for the + time being. + +*/ + +#if !defined (__SSP_H__) +# define __SSP_H__ + +/* ----- Includes */ + +/* ----- Types */ + +struct ssp_driver { + int (*init) (void); + void (*exit) (void); + void (*acquire) (void); + void (*release) (void); + int (*configure) (int device, int mode, int speed, + int frame_size_write, int frame_size_read); + void (*chip_select) (int enable); + void (*set_callbacks) (void* handle, + irqreturn_t (*callback_tx)(void*), + irqreturn_t (*callback_rx)(void*)); + void (*enable) (void); + void (*disable) (void); +// int (*save_state) (void*); +// void (*restore_state) (void*); + int (*read) (void); + int (*write) (u16 data); + int (*write_read) (u16 data); + void (*flush) (void); + void (*write_async) (void* pv, size_t cb); + size_t (*write_pos) (void); +}; + + /* These modes are only available on the LH79524 */ +#define SSP_MODE_SPI (1) +#define SSP_MODE_SSI (2) +#define SSP_MODE_MICROWIRE (3) +#define SSP_MODE_I2S (4) + + /* CPLD SPI devices */ +#define DEVICE_EEPROM 0 /* Configuration eeprom */ +#define DEVICE_MAC 1 /* MAC eeprom (LPD79524) */ +#define DEVICE_CODEC 2 /* Audio codec */ +#define DEVICE_TOUCH 3 /* Touch screen (LPD79520) */ + +/* ----- Globals */ + +/* ----- Prototypes */ + +//extern struct ssp_driver lh79520_i2s_driver; +extern struct ssp_driver lh7a400_cpld_ssp_driver; + +#endif /* __SSP_H__ */ diff --git a/include/asm-arm/arch-lh7a40x/uncompress.h b/include/asm-arm/arch-lh7a40x/uncompress.h index f8053346f608..3d1ce0426a33 100644 --- a/include/asm-arm/arch-lh7a40x/uncompress.h +++ b/include/asm-arm/arch-lh7a40x/uncompress.h @@ -16,7 +16,7 @@ #ifndef UART_R_STATUS # define UART_R_STATUS (0x10) #endif -#define nTxRdy (0x20) /* Not TxReady (literally Tx FIFO full) */ +#define nTxRdy (0x20) /* Not TxReady (literally Tx FIFO full) */ /* Access UART with physical addresses before MMU is setup */ #define UART_STATUS (*(volatile unsigned long*) (UART2_PHYS + UART_R_STATUS)) diff --git a/include/asm-arm/arch-pnx4008/clock.h b/include/asm-arm/arch-pnx4008/clock.h new file mode 100644 index 000000000000..91ae0030fdf2 --- /dev/null +++ b/include/asm-arm/arch-pnx4008/clock.h @@ -0,0 +1,61 @@ +/* + * include/asm-arm/arch-pnx4008/clock.h + * + * Clock control driver for PNX4008 - header file + * + * Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com> + * + * 2005 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __PNX4008_CLOCK_H__ +#define __PNX4008_CLOCK_H__ + +struct module; +struct clk; + +#define PWRMAN_VA_BASE IO_ADDRESS(PNX4008_PWRMAN_BASE) +#define HCLKDIVCTRL_REG (PWRMAN_VA_BASE + 0x40) +#define PWRCTRL_REG (PWRMAN_VA_BASE + 0x44) +#define PLLCTRL_REG (PWRMAN_VA_BASE + 0x48) +#define OSC13CTRL_REG (PWRMAN_VA_BASE + 0x4c) +#define SYSCLKCTRL_REG (PWRMAN_VA_BASE + 0x50) +#define HCLKPLLCTRL_REG (PWRMAN_VA_BASE + 0x58) +#define USBCTRL_REG (PWRMAN_VA_BASE + 0x64) +#define SDRAMCLKCTRL_REG (PWRMAN_VA_BASE + 0x68) +#define MSCTRL_REG (PWRMAN_VA_BASE + 0x80) +#define BTCLKCTRL (PWRMAN_VA_BASE + 0x84) +#define DUMCLKCTRL_REG (PWRMAN_VA_BASE + 0x90) +#define I2CCLKCTRL_REG (PWRMAN_VA_BASE + 0xac) +#define KEYCLKCTRL_REG (PWRMAN_VA_BASE + 0xb0) +#define TSCLKCTRL_REG (PWRMAN_VA_BASE + 0xb4) +#define PWMCLKCTRL_REG (PWRMAN_VA_BASE + 0xb8) +#define SPICTRL_REG (PWRMAN_VA_BASE + 0xc4) +#define FLASHCLKCTRL_REG (PWRMAN_VA_BASE + 0xc8) +#define UART3CLK_REG (PWRMAN_VA_BASE + 0xd0) +#define UARTCLKCTRL_REG (PWRMAN_VA_BASE + 0xe4) +#define DMACLKCTRL_REG (PWRMAN_VA_BASE + 0xe8) +#define AUTOCLK_CTRL (PWRMAN_VA_BASE + 0xec) +#define JPEGCLKCTRL_REG (PWRMAN_VA_BASE + 0xfc) + +#define AUDIOCONFIG_VA_BASE IO_ADDRESS(PNX4008_AUDIOCONFIG_BASE) +#define DSPPLLCTRL_REG (AUDIOCONFIG_VA_BASE + 0x60) +#define DSPCLKCTRL_REG (AUDIOCONFIG_VA_BASE + 0x64) +#define AUDIOCLKCTRL_REG (AUDIOCONFIG_VA_BASE + 0x68) +#define AUDIOPLLCTRL_REG (AUDIOCONFIG_VA_BASE + 0x6C) + +#define USB_OTG_CLKCTRL_REG IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0xff4) + +#define VFP9CLKCTRL_REG IO_ADDRESS(PNX4008_DEBUG_BASE) + +#define CLK_RATE_13MHZ 13000 +#define CLK_RATE_1MHZ 1000 +#define CLK_RATE_208MHZ 208000 +#define CLK_RATE_48MHZ 48000 +#define CLK_RATE_32KHZ 32 + +#define PNX4008_UART_CLK CLK_RATE_13MHZ * 1000 /* in MHz */ + +#endif diff --git a/include/asm-arm/arch-pnx4008/debug-macro.S b/include/asm-arm/arch-pnx4008/debug-macro.S new file mode 100644 index 000000000000..eb3839de389a --- /dev/null +++ b/include/asm-arm/arch-pnx4008/debug-macro.S @@ -0,0 +1,27 @@ +/* linux/include/asm-arm/arch-pnx4008/debug-macro.S + * + * Debugging macro include header + * + * Copyright (C) 1994-1999 Russell King + * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * +*/ + + .macro addruart,rx + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ MMU enabled? + mov \rx, #0x00090000 + addeq \rx, \rx, #0x40000000 + addne \rx, \rx, #0xf4000000 + .endm + + .macro senduart,rd,rx + strb \rd, [\rx, #0x0] + .endm + +#define UART_SHIFT 2 +#include <asm/hardware/debug-8250.S> diff --git a/include/asm-arm/arch-pnx4008/dma.h b/include/asm-arm/arch-pnx4008/dma.h new file mode 100644 index 000000000000..3aee1204795b --- /dev/null +++ b/include/asm-arm/arch-pnx4008/dma.h @@ -0,0 +1,162 @@ +/* + * linux/include/asm-arm/arch-pnx4008/dma.h + * + * PNX4008 DMA header file + * + * Author: Vitaly Wool + * Copyright: MontaVista Software Inc. (c) 2005 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_DMA_H +#define __ASM_ARCH_DMA_H + +#include "platform.h" + +#define MAX_DMA_ADDRESS 0xffffffff + +#define MAX_DMA_CHANNELS 8 + +#define DMAC_BASE IO_ADDRESS(PNX4008_DMA_CONFIG_BASE) +#define DMAC_INT_STAT (DMAC_BASE + 0x0000) +#define DMAC_INT_TC_STAT (DMAC_BASE + 0x0004) +#define DMAC_INT_TC_CLEAR (DMAC_BASE + 0x0008) +#define DMAC_INT_ERR_STAT (DMAC_BASE + 0x000c) +#define DMAC_INT_ERR_CLEAR (DMAC_BASE + 0x0010) +#define DMAC_SOFT_SREQ (DMAC_BASE + 0x0024) +#define DMAC_CONFIG (DMAC_BASE + 0x0030) +#define DMAC_Cx_SRC_ADDR(c) (DMAC_BASE + 0x0100 + (c) * 0x20) +#define DMAC_Cx_DEST_ADDR(c) (DMAC_BASE + 0x0104 + (c) * 0x20) +#define DMAC_Cx_LLI(c) (DMAC_BASE + 0x0108 + (c) * 0x20) +#define DMAC_Cx_CONTROL(c) (DMAC_BASE + 0x010c + (c) * 0x20) +#define DMAC_Cx_CONFIG(c) (DMAC_BASE + 0x0110 + (c) * 0x20) + +enum { + WIDTH_BYTE = 0, + WIDTH_HWORD, + WIDTH_WORD +}; + +enum { + FC_MEM2MEM_DMA, + FC_MEM2PER_DMA, + FC_PER2MEM_DMA, + FC_PER2PER_DMA, + FC_PER2PER_DPER, + FC_MEM2PER_PER, + FC_PER2MEM_PER, + FC_PER2PER_SPER +}; + +enum { + DMA_INT_UNKNOWN = 0, + DMA_ERR_INT = 1, + DMA_TC_INT = 2, +}; + +enum { + DMA_BUFFER_ALLOCATED = 1, + DMA_HAS_LL = 2, +}; + +enum { + PER_CAM_DMA_1 = 0, + PER_NDF_FLASH = 1, + PER_MBX_SLAVE_FIFO = 2, + PER_SPI2_REC_XMIT = 3, + PER_MS_SD_RX_XMIT = 4, + PER_HS_UART_1_XMIT = 5, + PER_HS_UART_1_RX = 6, + PER_HS_UART_2_XMIT = 7, + PER_HS_UART_2_RX = 8, + PER_HS_UART_7_XMIT = 9, + PER_HS_UART_7_RX = 10, + PER_SPI1_REC_XMIT = 11, + PER_MLC_NDF_SREC = 12, + PER_CAM_DMA_2 = 13, + PER_PRNG_INFIFO = 14, + PER_PRNG_OUTFIFO = 15, +}; + +struct pnx4008_dma_ch_ctrl { + int tc_mask; + int cacheable; + int bufferable; + int priv_mode; + int di; + int si; + int dest_ahb1; + int src_ahb1; + int dwidth; + int swidth; + int dbsize; + int sbsize; + int tr_size; +}; + +struct pnx4008_dma_ch_config { + int halt; + int active; + int lock; + int itc; + int ie; + int flow_cntrl; + int dest_per; + int src_per; +}; + +struct pnx4008_dma_ll { + unsigned long src_addr; + unsigned long dest_addr; + u32 next_dma; + unsigned long ch_ctrl; + struct pnx4008_dma_ll *next; + int flags; + void *alloc_data; + int (*free) (void *); +}; + +struct pnx4008_dma_config { + int is_ll; + unsigned long src_addr; + unsigned long dest_addr; + unsigned long ch_ctrl; + unsigned long ch_cfg; + struct pnx4008_dma_ll *ll; + u32 ll_dma; + int flags; + void *alloc_data; + int (*free) (void *); +}; + +extern struct pnx4008_dma_ll *pnx4008_alloc_ll_entry(dma_addr_t *); +extern void pnx4008_free_ll_entry(struct pnx4008_dma_ll *, dma_addr_t); +extern void pnx4008_free_ll(u32 ll_dma, struct pnx4008_dma_ll *); + +extern int pnx4008_request_channel(char *, int, + void (*)(int, int, void *, struct pt_regs *), + void *); +extern void pnx4008_free_channel(int); +extern int pnx4008_config_dma(int, int, int); +extern int pnx4008_dma_pack_control(const struct pnx4008_dma_ch_ctrl *, + unsigned long *); +extern int pnx4008_dma_parse_control(unsigned long, + struct pnx4008_dma_ch_ctrl *); +extern int pnx4008_dma_pack_config(const struct pnx4008_dma_ch_config *, + unsigned long *); +extern int pnx4008_dma_parse_config(unsigned long, + struct pnx4008_dma_ch_config *); +extern int pnx4008_config_channel(int, struct pnx4008_dma_config *); +extern int pnx4008_channel_get_config(int, struct pnx4008_dma_config *); +extern int pnx4008_dma_ch_enable(int); +extern int pnx4008_dma_ch_disable(int); +extern int pnx4008_dma_ch_enabled(int); +extern void pnx4008_dma_split_head_entry(struct pnx4008_dma_config *, + struct pnx4008_dma_ch_ctrl *); +extern void pnx4008_dma_split_ll_entry(struct pnx4008_dma_ll *, + struct pnx4008_dma_ch_ctrl *); + +#endif /* _ASM_ARCH_DMA_H */ diff --git a/include/asm-arm/arch-pnx4008/entry-macro.S b/include/asm-arm/arch-pnx4008/entry-macro.S new file mode 100644 index 000000000000..c1c198e3680b --- /dev/null +++ b/include/asm-arm/arch-pnx4008/entry-macro.S @@ -0,0 +1,121 @@ +/* + * include/asm-arm/arch-pnx4008/entry-macro.S + * + * Low-level IRQ helper macros for PNX4008-based platforms + * + * 2005-2006 (c) MontaVista Software, Inc. + * Author: Vitaly Wool <vwool@ru.mvista.com> + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include "platform.h" + +#define IO_BASE 0xF0000000 +#define IO_ADDRESS(x) (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) | IO_BASE) + +#define INTRC_MASK 0x00 +#define INTRC_RAW_STAT 0x04 +#define INTRC_STAT 0x08 +#define INTRC_POLAR 0x0C +#define INTRC_ACT_TYPE 0x10 +#define INTRC_TYPE 0x14 + +#define SIC1_BASE_INT 32 +#define SIC2_BASE_INT 64 + + .macro disable_fiq + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp +/* decode the MIC interrupt numbers */ + ldr \base, =IO_ADDRESS(PNX4008_INTCTRLMIC_BASE) + ldr \irqstat, [\base, #INTRC_STAT] + + cmp \irqstat,#1<<16 + movhs \irqnr,#16 + movlo \irqnr,#0 + movhs \irqstat,\irqstat,lsr#16 + cmp \irqstat,#1<<8 + addhs \irqnr,\irqnr,#8 + movhs \irqstat,\irqstat,lsr#8 + cmp \irqstat,#1<<4 + addhs \irqnr,\irqnr,#4 + movhs \irqstat,\irqstat,lsr#4 + cmp \irqstat,#1<<2 + addhs \irqnr,\irqnr,#2 + movhs \irqstat,\irqstat,lsr#2 + cmp \irqstat,#1<<1 + addhs \irqnr,\irqnr,#1 + +/* was there an interrupt ? if not then drop out with EQ status */ + teq \irqstat,#0 + beq 1003f + +/* and now check for extended IRQ reasons */ + cmp \irqnr,#1 + bls 1003f + cmp \irqnr,#30 + blo 1002f + +/* IRQ 31,30 : High priority cascade IRQ handle */ +/* read the correct SIC */ +/* decoding status after compare : eq is 30 (SIC1) , ne is 31 (SIC2) */ +/* set the base IRQ number */ + ldreq \base, =IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE) + moveq \irqnr,#SIC1_BASE_INT + ldrne \base, =IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE) + movne \irqnr,#SIC2_BASE_INT + ldr \irqstat, [\base, #INTRC_STAT] + ldr \tmp, [\base, #INTRC_TYPE] +/* and with inverted mask : low priority interrupts */ + and \irqstat,\irqstat,\tmp + b 1004f + +1003: +/* IRQ 1,0 : Low priority cascade IRQ handle */ +/* read the correct SIC */ +/* decoding status after compare : eq is 1 (SIC2) , ne is 0 (SIC1)*/ +/* read the correct SIC */ +/* set the base IRQ number */ + ldrne \base, =IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE) + movne \irqnr,#SIC1_BASE_INT + ldreq \base, =IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE) + moveq \irqnr,#SIC2_BASE_INT + ldr \irqstat, [\base, #INTRC_STAT] + ldr \tmp, [\base, #INTRC_TYPE] +/* and with inverted mask : low priority interrupts */ + bic \irqstat,\irqstat,\tmp + +1004: + + cmp \irqstat,#1<<16 + addhs \irqnr,\irqnr,#16 + movhs \irqstat,\irqstat,lsr#16 + cmp \irqstat,#1<<8 + addhs \irqnr,\irqnr,#8 + movhs \irqstat,\irqstat,lsr#8 + cmp \irqstat,#1<<4 + addhs \irqnr,\irqnr,#4 + movhs \irqstat,\irqstat,lsr#4 + cmp \irqstat,#1<<2 + addhs \irqnr,\irqnr,#2 + movhs \irqstat,\irqstat,lsr#2 + cmp \irqstat,#1<<1 + addhs \irqnr,\irqnr,#1 + + +/* is irqstat not zero */ + +1002: +/* we assert that irqstat is not equal to zero and return ne status if true*/ + teq \irqstat,#0 +1003: + .endm + + + .macro irq_prio_table + .endm + + diff --git a/include/asm-arm/arch-pnx4008/gpio.h b/include/asm-arm/arch-pnx4008/gpio.h new file mode 100644 index 000000000000..1fa5a77c3010 --- /dev/null +++ b/include/asm-arm/arch-pnx4008/gpio.h @@ -0,0 +1,139 @@ +/* + * include/asm-arm/arch-pnx4008/gpio.h + * + * PNX4008 GPIO driver - header file + * + * Author: Dmitry Chigirev <source@mvista.com> + * + * Based on reference code by Iwo Mergler and Z.Tabaaloute from Philips: + * Copyright (c) 2005 Koninklijke Philips Electronics N.V. + * + * 2005 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ + +#ifndef _PNX4008_GPIO_H_ +#define _PNX4008_GPIO_H_ + + +/* Block numbers */ +#define GPIO_IN (0) +#define GPIO_OUT (0x100) +#define GPIO_BID (0x200) +#define GPIO_RAM (0x300) +#define GPIO_MUX (0x400) + +#define GPIO_TYPE_MASK(K) ((K) & 0x700) + +/* INPUT GPIOs */ +/* GPI */ +#define GPI_00 (GPIO_IN | 0) +#define GPI_01 (GPIO_IN | 1) +#define GPI_02 (GPIO_IN | 2) +#define GPI_03 (GPIO_IN | 3) +#define GPI_04 (GPIO_IN | 4) +#define GPI_05 (GPIO_IN | 5) +#define GPI_06 (GPIO_IN | 6) +#define GPI_07 (GPIO_IN | 7) +#define GPI_08 (GPIO_IN | 8) +#define GPI_09 (GPIO_IN | 9) +#define U1_RX (GPIO_IN | 15) +#define U2_HTCS (GPIO_IN | 16) +#define U2_RX (GPIO_IN | 17) +#define U3_RX (GPIO_IN | 18) +#define U4_RX (GPIO_IN | 19) +#define U5_RX (GPIO_IN | 20) +#define U6_IRRX (GPIO_IN | 21) +#define U7_HCTS (GPIO_IN | 22) +#define U7_RX (GPIO_IN | 23) +/* MISC IN */ +#define SPI1_DATIN (GPIO_IN | 25) +#define DISP_SYNC (GPIO_IN | 26) +#define SPI2_DATIN (GPIO_IN | 27) +#define GPI_11 (GPIO_IN | 28) + +#define GPIO_IN_MASK 0x1eff83ff + +/* OUTPUT GPIOs */ +/* GPO */ +#define GPO_00 (GPIO_OUT | 0) +#define GPO_01 (GPIO_OUT | 1) +#define GPO_02 (GPIO_OUT | 2) +#define GPO_03 (GPIO_OUT | 3) +#define GPO_04 (GPIO_OUT | 4) +#define GPO_05 (GPIO_OUT | 5) +#define GPO_06 (GPIO_OUT | 6) +#define GPO_07 (GPIO_OUT | 7) +#define GPO_08 (GPIO_OUT | 8) +#define GPO_09 (GPIO_OUT | 9) +#define GPO_10 (GPIO_OUT | 10) +#define GPO_11 (GPIO_OUT | 11) +#define GPO_12 (GPIO_OUT | 12) +#define GPO_13 (GPIO_OUT | 13) +#define GPO_14 (GPIO_OUT | 14) +#define GPO_15 (GPIO_OUT | 15) +#define GPO_16 (GPIO_OUT | 16) +#define GPO_17 (GPIO_OUT | 17) +#define GPO_18 (GPIO_OUT | 18) +#define GPO_19 (GPIO_OUT | 19) +#define GPO_20 (GPIO_OUT | 20) +#define GPO_21 (GPIO_OUT | 21) +#define GPO_22 (GPIO_OUT | 22) +#define GPO_23 (GPIO_OUT | 23) + +#define GPIO_OUT_MASK 0xffffff + +/* BIDIRECTIONAL GPIOs */ +/* RAM pins */ +#define RAM_D19 (GPIO_RAM | 0) +#define RAM_D20 (GPIO_RAM | 1) +#define RAM_D21 (GPIO_RAM | 2) +#define RAM_D22 (GPIO_RAM | 3) +#define RAM_D23 (GPIO_RAM | 4) +#define RAM_D24 (GPIO_RAM | 5) +#define RAM_D25 (GPIO_RAM | 6) +#define RAM_D26 (GPIO_RAM | 7) +#define RAM_D27 (GPIO_RAM | 8) +#define RAM_D28 (GPIO_RAM | 9) +#define RAM_D29 (GPIO_RAM | 10) +#define RAM_D30 (GPIO_RAM | 11) +#define RAM_D31 (GPIO_RAM | 12) + +#define GPIO_RAM_MASK 0x1fff + +/* I/O pins */ +#define GPIO_00 (GPIO_BID | 25) +#define GPIO_01 (GPIO_BID | 26) +#define GPIO_02 (GPIO_BID | 27) +#define GPIO_03 (GPIO_BID | 28) +#define GPIO_04 (GPIO_BID | 29) +#define GPIO_05 (GPIO_BID | 30) + +#define GPIO_BID_MASK 0x7e000000 + +/* Non-GPIO multiplexed PIOs. For multiplexing with GPIO, please use GPIO macros */ +#define GPIO_SDRAM_SEL (GPIO_MUX | 3) + +#define GPIO_MUX_MASK 0x8 + +/* Extraction/assembly macros */ +#define GPIO_BIT_MASK(K) ((K) & 0x1F) +#define GPIO_BIT(K) (1 << GPIO_BIT_MASK(K)) +#define GPIO_ISMUX(K) ((GPIO_TYPE_MASK(K) == GPIO_MUX) && (GPIO_BIT(K) & GPIO_MUX_MASK)) +#define GPIO_ISRAM(K) ((GPIO_TYPE_MASK(K) == GPIO_RAM) && (GPIO_BIT(K) & GPIO_RAM_MASK)) +#define GPIO_ISBID(K) ((GPIO_TYPE_MASK(K) == GPIO_BID) && (GPIO_BIT(K) & GPIO_BID_MASK)) +#define GPIO_ISOUT(K) ((GPIO_TYPE_MASK(K) == GPIO_OUT) && (GPIO_BIT(K) & GPIO_OUT_MASK)) +#define GPIO_ISIN(K) ((GPIO_TYPE_MASK(K) == GPIO_IN) && (GPIO_BIT(K) & GPIO_IN_MASK)) + +extern int pnx4008_gpio_register_pin(unsigned short pin); +extern int pnx4008_gpio_unregister_pin(unsigned short pin); +extern unsigned long pnx4008_gpio_read_pin(unsigned short pin); +extern int pnx4008_gpio_write_pin(unsigned short pin, int output); +extern int pnx4008_gpio_set_pin_direction(unsigned short pin, int output); +extern int pnx4008_gpio_read_pin_direction(unsigned short pin); +extern int pnx4008_gpio_set_pin_mux(unsigned short pin, int output); +extern int pnx4008_gpio_read_pin_mux(unsigned short pin); + +#endif /* _PNX4008_GPIO_H_ */ diff --git a/include/asm-arm/arch-pnx4008/hardware.h b/include/asm-arm/arch-pnx4008/hardware.h new file mode 100644 index 000000000000..a4410397a921 --- /dev/null +++ b/include/asm-arm/arch-pnx4008/hardware.h @@ -0,0 +1,32 @@ +/* + * linux/include/asm-arm/arch-pnx4008/hardware.h + * + * Copyright (c) 2005 MontaVista Software, Inc. <source@mvista.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include <asm/sizes.h> +#include <asm/arch/platform.h> + +/* Start of virtual addresses for IO devices */ +#define IO_BASE 0xF0000000 + +/* This macro relies on fact that for all HW i/o addresses bits 20-23 are 0 */ +#define IO_ADDRESS(x) (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) | IO_BASE) + +#endif diff --git a/include/asm-arm/arch-pnx4008/io.h b/include/asm-arm/arch-pnx4008/io.h new file mode 100644 index 000000000000..29ee43955c52 --- /dev/null +++ b/include/asm-arm/arch-pnx4008/io.h @@ -0,0 +1,21 @@ + +/* + * include/asm-arm/arch-pnx4008/io.h + * + * Author: Dmitry Chigirev <chigirev@ru.mvista.com> + * + * 2005 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ + +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H + +#define IO_SPACE_LIMIT 0xffffffff + +#define __io(a) ((void __iomem *)(a)) +#define __mem_pci(a) (a) + +#endif diff --git a/include/asm-arm/arch-pnx4008/irq.h b/include/asm-arm/arch-pnx4008/irq.h new file mode 100644 index 000000000000..fabff5dc337f --- /dev/null +++ b/include/asm-arm/arch-pnx4008/irq.h @@ -0,0 +1,42 @@ +/* + * include/asm-arm/arch-pnx4008/irq.h + * + * PNX4008 IRQ controller driver - header file + * this one is used in entry-arnv.S as well so it cannot contain C code + * + * Copyright (c) 2005 Philips Semiconductors + * Copyright (c) 2005 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#ifndef __PNX4008_IRQ_H__ +#define __PNX4008_IRQ_H__ + +#define MIC_VA_BASE IO_ADDRESS(PNX4008_INTCTRLMIC_BASE) +#define SIC1_VA_BASE IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE) +#define SIC2_VA_BASE IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE) + +/* Manual: Chapter 20, page 195 */ + +#define INTC_BIT(irq) (1<< ((irq) & 0x1F)) + +#define INTC_ER(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x0 + (((irq)&(0x3<<5))<<9))) +#define INTC_RSR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x4 + (((irq)&(0x3<<5))<<9))) +#define INTC_SR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x8 + (((irq)&(0x3<<5))<<9))) +#define INTC_APR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0xC + (((irq)&(0x3<<5))<<9))) +#define INTC_ATR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x10 + (((irq)&(0x3<<5))<<9))) +#define INTC_ITR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x14 + (((irq)&(0x3<<5))<<9))) + +#define START_INT_REG_BIT(irq) (1<<((irq)&0x1F)) + +#define START_INT_ER_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x20 + (((irq)&(0x1<<5))>>1))) +#define START_INT_RSR_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x24 + (((irq)&(0x1<<5))>>1))) +#define START_INT_SR_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x28 + (((irq)&(0x1<<5))>>1))) +#define START_INT_APR_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x2C + (((irq)&(0x1<<5))>>1))) + +extern void __init pnx4008_init_irq(void); + +#endif /* __PNX4008_IRQ_H__ */ diff --git a/include/asm-arm/arch-pnx4008/irqs.h b/include/asm-arm/arch-pnx4008/irqs.h new file mode 100644 index 000000000000..13ec7ed0f501 --- /dev/null +++ b/include/asm-arm/arch-pnx4008/irqs.h @@ -0,0 +1,215 @@ +/* + * include/asm-arm/arch-pnx4008/irqs.h + * + * PNX4008 IRQ controller driver - header file + * + * Author: Dmitry Chigirev <source@mvista.com> + * + * 2005 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __PNX4008_IRQS_h__ +#define __PNX4008_IRQS_h__ + +#define NR_IRQS 96 + +/*Manual: table 259, page 199*/ + +/*SUB2 Interrupt Routing (SIC2)*/ + +#define SIC2_BASE_INT 64 + +#define CLK_SWITCH_ARM_INT 95 /*manual: Clkswitch ARM */ +#define CLK_SWITCH_DSP_INT 94 /*manual: ClkSwitch DSP */ +#define CLK_SWITCH_AUD_INT 93 /*manual: Clkswitch AUD */ +#define GPI_06_INT 92 +#define GPI_05_INT 91 +#define GPI_04_INT 90 +#define GPI_03_INT 89 +#define GPI_02_INT 88 +#define GPI_01_INT 87 +#define GPI_00_INT 86 +#define BT_CLKREQ_INT 85 +#define SPI1_DATIN_INT 84 +#define U5_RX_INT 83 +#define SDIO_INT_N 82 +#define CAM_HS_INT 81 +#define CAM_VS_INT 80 +#define GPI_07_INT 79 +#define DISP_SYNC_INT 78 +#define DSP_INT8 77 +#define U7_HCTS_INT 76 +#define GPI_10_INT 75 +#define GPI_09_INT 74 +#define GPI_08_INT 73 +#define DSP_INT7 72 +#define U2_HCTS_INT 71 +#define SPI2_DATIN_INT 70 +#define GPIO_05_INT 69 +#define GPIO_04_INT 68 +#define GPIO_03_INT 67 +#define GPIO_02_INT 66 +#define GPIO_01_INT 65 +#define GPIO_00_INT 64 + +/*Manual: table 258, page 198*/ + +/*SUB1 Interrupt Routing (SIC1)*/ + +#define SIC1_BASE_INT 32 + +#define USB_I2C_INT 63 +#define USB_DEV_HP_INT 62 +#define USB_DEV_LP_INT 61 +#define USB_DEV_DMA_INT 60 +#define USB_HOST_INT 59 +#define USB_OTG_ATX_INT_N 58 +#define USB_OTG_TIMER_INT 57 +#define SW_INT 56 +#define SPI1_INT 55 +#define KEY_IRQ 54 +#define DSP_M_INT 53 +#define RTC_INT 52 +#define I2C_1_INT 51 +#define I2C_2_INT 50 +#define PLL1_LOCK_INT 49 +#define PLL2_LOCK_INT 48 +#define PLL3_LOCK_INT 47 +#define PLL4_LOCK_INT 46 +#define PLL5_LOCK_INT 45 +#define SPI2_INT 44 +#define DSP_INT1 43 +#define DSP_INT2 42 +#define DSP_TDM_INT2 41 +#define TS_AUX_INT 40 +#define TS_IRQ 39 +#define TS_P_INT 38 +#define UOUT1_TO_PAD_INT 37 +#define GPI_11_INT 36 +#define DSP_INT4 35 +#define JTAG_COMM_RX_INT 34 +#define JTAG_COMM_TX_INT 33 +#define DSP_INT3 32 + +/*Manual: table 257, page 197*/ + +/*MAIN Interrupt Routing*/ + +#define MAIN_BASE_INT 0 + +#define SUB2_FIQ_N 31 /*active low */ +#define SUB1_FIQ_N 30 /*active low */ +#define JPEG_INT 29 +#define DMA_INT 28 +#define MSTIMER_INT 27 +#define IIR1_INT 26 +#define IIR2_INT 25 +#define IIR7_INT 24 +#define DSP_TDM_INT0 23 +#define DSP_TDM_INT1 22 +#define DSP_P_INT 21 +#define DSP_INT0 20 +#define DUM_INT 19 +#define UOUT0_TO_PAD_INT 18 +#define MP4_ENC_INT 17 +#define MP4_DEC_INT 16 +#define SD0_INT 15 +#define MBX_INT 14 +#define SD1_INT 13 +#define MS_INT_N 12 +#define FLASH_INT 11 /*NAND*/ +#define IIR6_INT 10 +#define IIR5_INT 9 +#define IIR4_INT 8 +#define IIR3_INT 7 +#define WATCH_INT 6 +#define HSTIMER_INT 5 +#define ARCH_TIMER_IRQ HSTIMER_INT +#define CAM_INT 4 +#define PRNG_INT 3 +#define CRYPTO_INT 2 +#define SUB2_IRQ_N 1 /*active low */ +#define SUB1_IRQ_N 0 /*active low */ + +#define PNX4008_IRQ_TYPES \ +{ /*IRQ #'s: */ \ +IRQT_LOW, IRQT_LOW, IRQT_LOW, IRQT_HIGH, /* 0, 1, 2, 3 */ \ +IRQT_LOW, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 4, 5, 6, 7 */ \ +IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 8, 9,10,11 */ \ +IRQT_LOW, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 12,13,14,15 */ \ +IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 16,17,18,19 */ \ +IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 20,21,22,23 */ \ +IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 24,25,26,27 */ \ +IRQT_HIGH, IRQT_HIGH, IRQT_LOW, IRQT_LOW, /* 28,29,30,31 */ \ +IRQT_HIGH, IRQT_LOW, IRQT_HIGH, IRQT_HIGH, /* 32,33,34,35 */ \ +IRQT_HIGH, IRQT_HIGH, IRQT_FALLING, IRQT_HIGH, /* 36,37,38,39 */ \ +IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 40,41,42,43 */ \ +IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 44,45,46,47 */ \ +IRQT_HIGH, IRQT_HIGH, IRQT_LOW, IRQT_LOW, /* 48,49,50,51 */ \ +IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 52,53,54,55 */ \ +IRQT_HIGH, IRQT_HIGH, IRQT_LOW, IRQT_HIGH, /* 56,57,58,59 */ \ +IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 60,61,62,63 */ \ +IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 64,65,66,67 */ \ +IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 68,69,70,71 */ \ +IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 72,73,74,75 */ \ +IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 76,77,78,79 */ \ +IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 80,81,82,83 */ \ +IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 84,85,86,87 */ \ +IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 88,89,90,91 */ \ +IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 92,93,94,95 */ \ +} + +/* Start Enable Pin Interrupts - table 58 page 66 */ + +#define SE_PIN_BASE_INT 32 + +#define SE_U7_RX_INT 63 +#define SE_U7_HCTS_INT 62 +#define SE_BT_CLKREQ_INT 61 +#define SE_U6_IRRX_INT 60 +/*59 unused*/ +#define SE_U5_RX_INT 58 +#define SE_GPI_11_INT 57 +#define SE_U3_RX_INT 56 +#define SE_U2_HCTS_INT 55 +#define SE_U2_RX_INT 54 +#define SE_U1_RX_INT 53 +#define SE_DISP_SYNC_INT 52 +/*51 unused*/ +#define SE_SDIO_INT_N 50 +#define SE_MSDIO_START_INT 49 +#define SE_GPI_06_INT 48 +#define SE_GPI_05_INT 47 +#define SE_GPI_04_INT 46 +#define SE_GPI_03_INT 45 +#define SE_GPI_02_INT 44 +#define SE_GPI_01_INT 43 +#define SE_GPI_00_INT 42 +#define SE_SYSCLKEN_PIN_INT 41 +#define SE_SPI1_DATAIN_INT 40 +#define SE_GPI_07_INT 39 +#define SE_SPI2_DATAIN_INT 38 +#define SE_GPI_10_INT 37 +#define SE_GPI_09_INT 36 +#define SE_GPI_08_INT 35 +/*34-32 unused*/ + +/* Start Enable Internal Interrupts - table 57 page 65 */ + +#define SE_INT_BASE_INT 0 + +#define SE_TS_IRQ 31 +#define SE_TS_P_INT 30 +#define SE_TS_AUX_INT 29 +/*27-28 unused*/ +#define SE_USB_AHB_NEED_CLK_INT 26 +#define SE_MSTIMER_INT 25 +#define SE_RTC_INT 24 +#define SE_USB_NEED_CLK_INT 23 +#define SE_USB_INT 22 +#define SE_USB_I2C_INT 21 +#define SE_USB_OTG_TIMER_INT 20 + +#endif /* __PNX4008_IRQS_h__ */ diff --git a/include/asm-arm/arch-pnx4008/memory.h b/include/asm-arm/arch-pnx4008/memory.h new file mode 100644 index 000000000000..0d8268a95261 --- /dev/null +++ b/include/asm-arm/arch-pnx4008/memory.h @@ -0,0 +1,24 @@ +/* + * linux/include/asm-arm/arch-pnx4008/memory.h + * + * Copyright (c) 2005 Philips Semiconductors + * Copyright (c) 2005 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +/* + * Physical DRAM offset. + */ +#define PHYS_OFFSET (0x80000000) + +#define __virt_to_bus(x) ((x) - PAGE_OFFSET + PHYS_OFFSET) +#define __bus_to_virt(x) ((x) + PAGE_OFFSET - PHYS_OFFSET) + +#endif diff --git a/include/asm-arm/arch-pnx4008/param.h b/include/asm-arm/arch-pnx4008/param.h new file mode 100644 index 000000000000..95d5f547b416 --- /dev/null +++ b/include/asm-arm/arch-pnx4008/param.h @@ -0,0 +1,21 @@ +/* + * linux/include/asm-arm/arch-pnx4008/param.h + * + * Copyright (C) 1999 ARM Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#define HZ 100 diff --git a/include/asm-arm/arch-pnx4008/platform.h b/include/asm-arm/arch-pnx4008/platform.h new file mode 100644 index 000000000000..485a3651b4d7 --- /dev/null +++ b/include/asm-arm/arch-pnx4008/platform.h @@ -0,0 +1,69 @@ +/* + * include/asm-arm/arch-pnx4008/platfrom.h + * + * PNX4008 Base addresses - header file + * + * Author: Dmitry Chigirev <source@mvista.com> + * + * Based on reference code received from Philips: + * Copyright (C) 2003 Philips Semiconductors + * + * 2005 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ + + +#ifndef __ASM_ARCH_PLATFORM_H__ +#define __ASM_ARCH_PLATFORM_H__ + +#define PNX4008_IRAM_BASE 0x08000000 +#define PNX4008_IRAM_SIZE 0x00010000 +#define PNX4008_YUV_SLAVE_BASE 0x10000000 +#define PNX4008_DUM_SLAVE_BASE 0x18000000 +#define PNX4008_NDF_FLASH_BASE 0x20020000 +#define PNX4008_SPI1_BASE 0x20088000 +#define PNX4008_SPI2_BASE 0x20090000 +#define PNX4008_SD_CONFIG_BASE 0x20098000 +#define PNX4008_FLASH_DATA 0x200B0000 +#define PNX4008_MLC_FLASH_BASE 0x200B8000 +#define PNX4008_JPEG_CONFIG_BASE 0x300A0000 +#define PNX4008_DMA_CONFIG_BASE 0x31000000 +#define PNX4008_USB_CONFIG_BASE 0x31020000 +#define PNX4008_SDRAM_CFG_BASE 0x31080000 +#define PNX4008_AHB2FAB_BASE 0x40000000 +#define PNX4008_PWRMAN_BASE 0x40004000 +#define PNX4008_INTCTRLMIC_BASE 0x40008000 +#define PNX4008_INTCTRLSIC1_BASE 0x4000C000 +#define PNX4008_INTCTRLSIC2_BASE 0x40010000 +#define PNX4008_HSUART1_BASE 0x40014000 +#define PNX4008_HSUART2_BASE 0x40018000 +#define PNX4008_HSUART7_BASE 0x4001C000 +#define PNX4008_RTC_BASE 0x40024000 +#define PNX4008_PIO_BASE 0x40028000 +#define PNX4008_MSTIMER_BASE 0x40034000 +#define PNX4008_HSTIMER_BASE 0x40038000 +#define PNX4008_WDOG_BASE 0x4003C000 +#define PNX4008_DEBUG_BASE 0x40040000 +#define PNX4008_TOUCH1_BASE 0x40048000 +#define PNX4008_KEYSCAN_BASE 0x40050000 +#define PNX4008_UARTCTRL_BASE 0x40054000 +#define PNX4008_PWM_BASE 0x4005C000 +#define PNX4008_UART3_BASE 0x40080000 +#define PNX4008_UART4_BASE 0x40088000 +#define PNX4008_UART5_BASE 0x40090000 +#define PNX4008_UART6_BASE 0x40098000 +#define PNX4008_I2C1_BASE 0x400A0000 +#define PNX4008_I2C2_BASE 0x400A8000 +#define PNX4008_MAGICGATE_BASE 0x400B0000 +#define PNX4008_DUMCONF_BASE 0x400B8000 +#define PNX4008_DUM_MAINCFG_BASE 0x400BC000 +#define PNX4008_DSP_BASE 0x400C0000 +#define PNX4008_PROFCOUNTER_BASE 0x400C8000 +#define PNX4008_CRYPTO_BASE 0x400D0000 +#define PNX4008_CAMIFCONF_BASE 0x400D8000 +#define PNX4008_YUV2RGB_BASE 0x400E0000 +#define PNX4008_AUDIOCONFIG_BASE 0x400E8000 + +#endif diff --git a/include/asm-arm/arch-pnx4008/pm.h b/include/asm-arm/arch-pnx4008/pm.h new file mode 100644 index 000000000000..c660486670fb --- /dev/null +++ b/include/asm-arm/arch-pnx4008/pm.h @@ -0,0 +1,62 @@ +/* + * include/asm-arm/arch-pnx4008/pm.h + * + * PNX4008 Power Management Routiness - header file + * + * Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com> + * + * 2005 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ + +#ifndef __ASM_ARCH_PNX4008_PM_H +#define __ASM_ARCH_PNX4008_PM_H + +#ifndef __ASSEMBLER__ +#include "irq.h" +#include "irqs.h" +#include "clock.h" + +extern void pnx4008_pm_idle(void); +extern void pnx4008_pm_suspend(void); +extern unsigned int pnx4008_cpu_suspend_sz; +extern void pnx4008_cpu_suspend(void); +extern unsigned int pnx4008_cpu_standby_sz; +extern void pnx4008_cpu_standby(void); + +extern int pnx4008_startup_pll(struct clk *); +extern int pnx4008_shutdown_pll(struct clk *); + +static inline void start_int_umask(u8 irq) +{ + __raw_writel(__raw_readl(START_INT_ER_REG(irq)) | + START_INT_REG_BIT(irq), START_INT_ER_REG(irq)); +} + +static inline void start_int_mask(u8 irq) +{ + __raw_writel(__raw_readl(START_INT_ER_REG(irq)) & + ~START_INT_REG_BIT(irq), START_INT_ER_REG(irq)); +} + +static inline void start_int_ack(u8 irq) +{ + __raw_writel(START_INT_REG_BIT(irq), START_INT_RSR_REG(irq)); +} + +static inline void start_int_set_falling_edge(u8 irq) +{ + __raw_writel(__raw_readl(START_INT_APR_REG(irq)) & + ~START_INT_REG_BIT(irq), START_INT_APR_REG(irq)); +} + +static inline void start_int_set_rising_edge(u8 irq) +{ + __raw_writel(__raw_readl(START_INT_APR_REG(irq)) | + START_INT_REG_BIT(irq), START_INT_APR_REG(irq)); +} + +#endif /* ASSEMBLER */ +#endif /* __ASM_ARCH_PNX4008_PM_H */ diff --git a/include/asm-arm/arch-pnx4008/system.h b/include/asm-arm/arch-pnx4008/system.h new file mode 100644 index 000000000000..6e3da70ab107 --- /dev/null +++ b/include/asm-arm/arch-pnx4008/system.h @@ -0,0 +1,38 @@ +/* + * linux/include/asm-arm/arch-pnx4008/system.h + * + * Copyright (C) 2003 Philips Semiconductors + * Copyright (C) 2005 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_SYSTEM_H +#define __ASM_ARCH_SYSTEM_H + +#include <asm/hardware.h> +#include <asm/io.h> +#include <asm/arch/platform.h> + +static void arch_idle(void) +{ + cpu_do_idle(); +} + +static inline void arch_reset(char mode) +{ + cpu_reset(0); +} + +#endif diff --git a/include/asm-arm/arch-pnx4008/timex.h b/include/asm-arm/arch-pnx4008/timex.h new file mode 100644 index 000000000000..ee470a39089a --- /dev/null +++ b/include/asm-arm/arch-pnx4008/timex.h @@ -0,0 +1,73 @@ +/* + * include/asm-arm/arch-pnx4008/timex.h + * + * PNX4008 timers header file + * + * Author: Dmitry Chigirev <source@mvista.com> + * + * 2005 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ + +#ifndef __PNX4008_TIMEX_H +#define __PNX4008_TIMEX_H + +#include <asm/hardware.h> +#include <asm/io.h> + +#define CLOCK_TICK_RATE 1000000 + +#define TICKS2USECS(x) (x) + +/* MilliSecond Timer - Chapter 21 Page 202 */ + +#define MSTIM_INT IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x0)) +#define MSTIM_CTRL IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x4)) +#define MSTIM_COUNTER IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x8)) +#define MSTIM_MCTRL IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x14)) +#define MSTIM_MATCH0 IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x18)) +#define MSTIM_MATCH1 IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x1c)) + +/* High Speed Timer - Chpater 22, Page 205 */ + +#define HSTIM_INT IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x0)) +#define HSTIM_CTRL IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x4)) +#define HSTIM_COUNTER IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x8)) +#define HSTIM_PMATCH IO_ADDRESS((PNX4008_HSTIMER_BASE + 0xC)) +#define HSTIM_PCOUNT IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x10)) +#define HSTIM_MCTRL IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x14)) +#define HSTIM_MATCH0 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x18)) +#define HSTIM_MATCH1 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x1c)) +#define HSTIM_MATCH2 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x20)) +#define HSTIM_CCR IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x28)) +#define HSTIM_CR0 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x2C)) +#define HSTIM_CR1 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x30)) + +/* IMPORTANT: both timers are UPCOUNTING */ + +/* xSTIM_MCTRL bit definitions */ +#define MR0_INT 1 +#define RESET_COUNT0 (1<<1) +#define STOP_COUNT0 (1<<2) +#define MR1_INT (1<<3) +#define RESET_COUNT1 (1<<4) +#define STOP_COUNT1 (1<<5) +#define MR2_INT (1<<6) +#define RESET_COUNT2 (1<<7) +#define STOP_COUNT2 (1<<8) + +/* xSTIM_CTRL bit definitions */ +#define COUNT_ENAB 1 +#define RESET_COUNT (1<<1) +#define DEBUG_EN (1<<2) + +/* xSTIM_INT bit definitions */ +#define MATCH0_INT 1 +#define MATCH1_INT (1<<1) +#define MATCH2_INT (1<<2) +#define RTC_TICK0 (1<<4) +#define RTC_TICK1 (1<<5) + +#endif diff --git a/include/asm-arm/arch-pnx4008/uncompress.h b/include/asm-arm/arch-pnx4008/uncompress.h new file mode 100644 index 000000000000..8fa4d24b72b4 --- /dev/null +++ b/include/asm-arm/arch-pnx4008/uncompress.h @@ -0,0 +1,46 @@ +/* + * linux/include/asm-arm/arch-pnx4008/uncompress.h + * + * Copyright (C) 1999 ARM Limited + * Copyright (C) 2006 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#define UART5_BASE 0x40090000 + +#define UART5_DR (*(volatile unsigned char *) (UART5_BASE)) +#define UART5_FR (*(volatile unsigned char *) (UART5_BASE + 18)) + +static __inline__ void putc(char c) +{ + while (UART5_FR & (1 << 5)) + barrier(); + + UART5_DR = c; +} + +/* + * This does not append a newline + */ +static inline void flush(void) +{ +} + +/* + * nothing to do + */ +#define arch_decomp_setup() +#define arch_decomp_wdog() diff --git a/include/asm-arm/arch-pnx4008/vmalloc.h b/include/asm-arm/arch-pnx4008/vmalloc.h new file mode 100644 index 000000000000..140d925f6f37 --- /dev/null +++ b/include/asm-arm/arch-pnx4008/vmalloc.h @@ -0,0 +1,20 @@ +/* + * include/asm-arm/arch-pnx4008/vmalloc.h + * + * Author: Vitaly Wool <source@mvista.com> + * + * 2006 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ + +/* + * Just any arbitrary offset to the start of the vmalloc VM area: the + * current 8MB value just means that there will be a 8MB "hole" after the + * physical memory until the kernel virtual memory starts. That means that + * any out-of-bounds memory accesses will hopefully be caught. + * The vmalloc() routines leaves a hole of 4kB between each vmalloced + * area for the same reason. ;) + */ +#define VMALLOC_END (PAGE_OFFSET + 0x10000000) diff --git a/include/asm-arm/arch-pxa/ohci.h b/include/asm-arm/arch-pxa/ohci.h index 7da89569061e..e848a47128cd 100644 --- a/include/asm-arm/arch-pxa/ohci.h +++ b/include/asm-arm/arch-pxa/ohci.h @@ -11,6 +11,8 @@ struct pxaohci_platform_data { #define PMM_NPS_MODE 1 #define PMM_GLOBAL_MODE 2 #define PMM_PERPORT_MODE 3 + + int power_budget; }; extern void pxa_set_ohci_info(struct pxaohci_platform_data *info); diff --git a/include/asm-arm/arch-s3c2410/map.h b/include/asm-arm/arch-s3c2410/map.h index c380d264a847..5e4c8c37bc66 100644 --- a/include/asm-arm/arch-s3c2410/map.h +++ b/include/asm-arm/arch-s3c2410/map.h @@ -126,9 +126,18 @@ #define S3C24XX_SZ_IIS SZ_1M /* GPIO ports */ -#define S3C24XX_VA_GPIO S3C2410_ADDR(0x00E00000) + +/* the calculation for the VA of this must ensure that + * it is the same distance apart from the UART in the + * phsyical address space, as the initial mapping for the IO + * is done as a 1:1 maping. This puts it (currently) at + * 0xF6800000, which is not in the way of any current mapping + * by the base system. +*/ + #define S3C2400_PA_GPIO (0x15600000) #define S3C2410_PA_GPIO (0x56000000) +#define S3C24XX_VA_GPIO ((S3C2410_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART) #define S3C24XX_SZ_GPIO SZ_1M /* RTC */ diff --git a/include/asm-arm/arch-s3c2410/regs-clock.h b/include/asm-arm/arch-s3c2410/regs-clock.h index 34360706e016..6c92faffe985 100644 --- a/include/asm-arm/arch-s3c2410/regs-clock.h +++ b/include/asm-arm/arch-s3c2410/regs-clock.h @@ -114,7 +114,7 @@ s3c2410_get_pll(unsigned int pllval, unsigned int baseclk) #endif /* __ASSEMBLY__ */ -#ifdef CONFIG_CPU_S3C2440 +#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442) /* extra registers */ #define S3C2440_CAMDIVN S3C2410_CLKREG(0x18) @@ -136,7 +136,9 @@ s3c2410_get_pll(unsigned int pllval, unsigned int baseclk) #define S3C2440_CAMDIVN_HCLK4_HALF (1<<9) #define S3C2440_CAMDIVN_DVSEN (1<<12) -#endif /* CONFIG_CPU_S3C2440 */ +#define S3C2442_CAMDIVN_CAMCLK_DIV3 (1<<5) + +#endif /* CONFIG_CPU_S3C2440 or CONFIG_CPU_S3C2442 */ #endif /* __ASM_ARM_REGS_CLOCK */ diff --git a/include/asm-arm/arch-s3c2410/regs-gpio.h b/include/asm-arm/arch-s3c2410/regs-gpio.h index d2574084697f..5f10334f06bf 100644 --- a/include/asm-arm/arch-s3c2410/regs-gpio.h +++ b/include/asm-arm/arch-s3c2410/regs-gpio.h @@ -450,12 +450,14 @@ #define S3C2410_GPD0_OUTP (0x01 << 0) #define S3C2410_GPD0_VD8 (0x02 << 0) #define S3C2400_GPD0_VFRAME (0x02 << 0) +#define S3C2442_GPD0_nSPICS1 (0x03 << 0) #define S3C2410_GPD1 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 1) #define S3C2410_GPD1_INP (0x00 << 2) #define S3C2410_GPD1_OUTP (0x01 << 2) #define S3C2410_GPD1_VD9 (0x02 << 2) #define S3C2400_GPD1_VM (0x02 << 2) +#define S3C2442_GPD1_SPICLK1 (0x03 << 2) #define S3C2410_GPD2 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 2) #define S3C2410_GPD2_INP (0x00 << 4) @@ -858,6 +860,7 @@ #define S3C2410_GPG12_OUTP (0x01 << 24) #define S3C2410_GPG12_EINT20 (0x02 << 24) #define S3C2410_GPG12_XMON (0x03 << 24) +#define S3C2442_GPG12_nSPICS0 (0x03 << 24) #define S3C2410_GPG13 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 13) #define S3C2410_GPG13_INP (0x00 << 26) @@ -943,6 +946,7 @@ #define S3C2410_GPH9_INP (0x00 << 18) #define S3C2410_GPH9_OUTP (0x01 << 18) #define S3C2410_GPH9_CLKOUT0 (0x02 << 18) +#define S3C2442_GPH9_nSPICS0 (0x03 << 18) #define S3C2410_GPH10 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 10) #define S3C2410_GPH10_INP (0x00 << 20) @@ -1051,6 +1055,7 @@ #define S3C2410_GSTATUS1_IDMASK (0xffff0000) #define S3C2410_GSTATUS1_2410 (0x32410000) #define S3C2410_GSTATUS1_2440 (0x32440000) +#define S3C2410_GSTATUS1_2442 (0x32440aaa) #define S3C2410_GSTATUS2_WTRESET (1<<2) #define S3C2410_GSTATUS2_OFFRESET (1<<1) diff --git a/include/asm-arm/arch-s3c2410/uncompress.h b/include/asm-arm/arch-s3c2410/uncompress.h index 0ecb8103fa70..8e152a05e533 100644 --- a/include/asm-arm/arch-s3c2410/uncompress.h +++ b/include/asm-arm/arch-s3c2410/uncompress.h @@ -81,7 +81,8 @@ static void putc(int ch) while (1) { level = uart_rd(S3C2410_UFSTAT); - if (cpuid == S3C2410_GSTATUS1_2440) { + if (cpuid == S3C2410_GSTATUS1_2440 || + cpuid == S3C2410_GSTATUS1_2442) { level &= S3C2440_UFSTAT_TXMASK; level >>= S3C2440_UFSTAT_TXSHIFT; } else { @@ -129,7 +130,7 @@ static void arch_decomp_wdog_start(void) { __raw_writel(WDOG_COUNT, S3C2410_WTDAT); __raw_writel(WDOG_COUNT, S3C2410_WTCNT); - __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON); + __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON); } #else diff --git a/include/asm-arm/mach/time.h b/include/asm-arm/mach/time.h index 96c6db7dd0e1..9f28073559e8 100644 --- a/include/asm-arm/mach/time.h +++ b/include/asm-arm/mach/time.h @@ -50,6 +50,7 @@ struct sys_timer { #define DYN_TICK_ENABLED (1 << 1) struct dyn_tick_timer { + spinlock_t lock; unsigned int state; /* Current state */ int (*enable)(void); /* Enables dynamic tick */ int (*disable)(void); /* Disables dynamic tick */ diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h index f5eafd7ed8fa..9c744ae6c6e3 100644 --- a/include/asm-arm/system.h +++ b/include/asm-arm/system.h @@ -126,6 +126,12 @@ static inline int cpu_is_xsc3(void) } #endif +#if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3) +#define cpu_is_xscale() 0 +#else +#define cpu_is_xscale() 1 +#endif + #define set_cr(x) \ __asm__ __volatile__( \ "mcr p15, 0, %0, c1, c0, 0 @ set CR" \ diff --git a/include/asm-generic/pgtable.h b/include/asm-generic/pgtable.h index 358e4d309ceb..c2059a3a0621 100644 --- a/include/asm-generic/pgtable.h +++ b/include/asm-generic/pgtable.h @@ -159,17 +159,8 @@ static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addres #define lazy_mmu_prot_update(pte) do { } while (0) #endif -#ifndef __HAVE_ARCH_MULTIPLE_ZERO_PAGE +#ifndef __HAVE_ARCH_MOVE_PTE #define move_pte(pte, prot, old_addr, new_addr) (pte) -#else -#define move_pte(pte, prot, old_addr, new_addr) \ -({ \ - pte_t newpte = (pte); \ - if (pte_present(pte) && pfn_valid(pte_pfn(pte)) && \ - pte_page(pte) == ZERO_PAGE(old_addr)) \ - newpte = mk_pte(ZERO_PAGE(new_addr), (prot)); \ - newpte; \ -}) #endif /* diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h index a7d0d26e93c9..45c706e34df1 100644 --- a/include/asm-mips/addrspace.h +++ b/include/asm-mips/addrspace.h @@ -128,60 +128,26 @@ #if defined (CONFIG_CPU_R4300) \ || defined (CONFIG_CPU_R4X00) \ || defined (CONFIG_CPU_R5000) \ + || defined (CONFIG_CPU_RM7000) \ || defined (CONFIG_CPU_NEVADA) \ || defined (CONFIG_CPU_TX49XX) \ || defined (CONFIG_CPU_MIPS64) -#define KUSIZE _LLCONST_(0x0000010000000000) /* 2^^40 */ -#define KUSIZE_64 _LLCONST_(0x0000010000000000) /* 2^^40 */ -#define K0SIZE _LLCONST_(0x0000001000000000) /* 2^^36 */ -#define K1SIZE _LLCONST_(0x0000001000000000) /* 2^^36 */ -#define K2SIZE _LLCONST_(0x000000ff80000000) -#define KSEGSIZE _LLCONST_(0x000000ff80000000) /* max syssegsz */ #define TO_PHYS_MASK _LLCONST_(0x0000000fffffffff) /* 2^^36 - 1 */ #endif #if defined (CONFIG_CPU_R8000) /* We keep KUSIZE consistent with R4000 for now (2^^40) instead of (2^^48) */ -#define KUSIZE _LLCONST_(0x0000010000000000) /* 2^^40 */ -#define KUSIZE_64 _LLCONST_(0x0000010000000000) /* 2^^40 */ -#define K0SIZE _LLCONST_(0x0000010000000000) /* 2^^40 */ -#define K1SIZE _LLCONST_(0x0000010000000000) /* 2^^40 */ -#define K2SIZE _LLCONST_(0x0001000000000000) -#define KSEGSIZE _LLCONST_(0x0000010000000000) /* max syssegsz */ #define TO_PHYS_MASK _LLCONST_(0x000000ffffffffff) /* 2^^40 - 1 */ #endif #if defined (CONFIG_CPU_R10000) -#define KUSIZE _LLCONST_(0x0000010000000000) /* 2^^40 */ -#define KUSIZE_64 _LLCONST_(0x0000010000000000) /* 2^^40 */ -#define K0SIZE _LLCONST_(0x0000010000000000) /* 2^^40 */ -#define K1SIZE _LLCONST_(0x0000010000000000) /* 2^^40 */ -#define K2SIZE _LLCONST_(0x00000fff80000000) -#define KSEGSIZE _LLCONST_(0x00000fff80000000) /* max syssegsz */ #define TO_PHYS_MASK _LLCONST_(0x000000ffffffffff) /* 2^^40 - 1 */ #endif #if defined(CONFIG_CPU_SB1) || defined(CONFIG_CPU_SB1A) -#define KUSIZE _LLCONST_(0x0000100000000000) /* 2^^44 */ -#define KUSIZE_64 _LLCONST_(0x0000100000000000) /* 2^^44 */ -#define K0SIZE _LLCONST_(0x0000100000000000) /* 2^^44 */ -#define K1SIZE _LLCONST_(0x0000100000000000) /* 2^^44 */ -#define K2SIZE _LLCONST_(0x0000ffff80000000) -#define KSEGSIZE _LLCONST_(0x0000ffff80000000) /* max syssegsz */ #define TO_PHYS_MASK _LLCONST_(0x00000fffffffffff) /* 2^^44 - 1 */ #endif -/* - * Further names for SGI source compatibility. These are stolen from - * IRIX's <sys/mips_addrspace.h>. - */ -#define KUBASE _LLCONST_(0) -#define KUSIZE_32 _LLCONST_(0x0000000080000000) /* KUSIZE - for a 32 bit proc */ -#define K0BASE_EXL_WR _LLCONST_(0xa800000000000000) /* exclusive on write */ -#define K0BASE_NONCOH _LLCONST_(0x9800000000000000) /* noncoherent */ -#define K0BASE_EXL _LLCONST_(0xa000000000000000) /* exclusive */ - #ifndef CONFIG_CPU_R8000 /* diff --git a/include/asm-mips/apm.h b/include/asm-mips/apm.h new file mode 100644 index 000000000000..e8c69208f63a --- /dev/null +++ b/include/asm-mips/apm.h @@ -0,0 +1,65 @@ +/* -*- linux-c -*- + * + * (C) 2003 zecke@handhelds.org + * + * GPL version 2 + * + * based on arch/arm/kernel/apm.c + * factor out the information needed by architectures to provide + * apm status + * + * + */ +#ifndef MIPS_ASM_SA1100_APM_H +#define MIPS_ASM_SA1100_APM_H + +#include <linux/config.h> +#include <linux/apm_bios.h> + +/* + * This structure gets filled in by the machine specific 'get_power_status' + * implementation. Any fields which are not set default to a safe value. + */ +struct apm_power_info { + unsigned char ac_line_status; +#define APM_AC_OFFLINE 0 +#define APM_AC_ONLINE 1 +#define APM_AC_BACKUP 2 +#define APM_AC_UNKNOWN 0xff + + unsigned char battery_status; +#define APM_BATTERY_STATUS_HIGH 0 +#define APM_BATTERY_STATUS_LOW 1 +#define APM_BATTERY_STATUS_CRITICAL 2 +#define APM_BATTERY_STATUS_CHARGING 3 +#define APM_BATTERY_STATUS_NOT_PRESENT 4 +#define APM_BATTERY_STATUS_UNKNOWN 0xff + + unsigned char battery_flag; +#define APM_BATTERY_FLAG_HIGH (1 << 0) +#define APM_BATTERY_FLAG_LOW (1 << 1) +#define APM_BATTERY_FLAG_CRITICAL (1 << 2) +#define APM_BATTERY_FLAG_CHARGING (1 << 3) +#define APM_BATTERY_FLAG_NOT_PRESENT (1 << 7) +#define APM_BATTERY_FLAG_UNKNOWN 0xff + + int battery_life; + int time; + int units; +#define APM_UNITS_MINS 0 +#define APM_UNITS_SECS 1 +#define APM_UNITS_UNKNOWN -1 + +}; + +/* + * This allows machines to provide their own "apm get power status" function. + */ +extern void (*apm_get_power_status)(struct apm_power_info *); + +/* + * Queue an event (APM_SYS_SUSPEND or APM_CRITICAL_SUSPEND) + */ +void apm_queue_event(apm_event_t event); + +#endif diff --git a/include/asm-mips/asmmacro-32.h b/include/asm-mips/asmmacro-32.h index 11daf5ceb7b4..5de3963f511e 100644 --- a/include/asm-mips/asmmacro-32.h +++ b/include/asm-mips/asmmacro-32.h @@ -12,7 +12,7 @@ #include <asm/fpregdef.h> #include <asm/mipsregs.h> - .macro fpu_save_double thread status tmp1=t0 tmp2 + .macro fpu_save_double thread status tmp1=t0 cfc1 \tmp1, fcr31 sdc1 $f0, THREAD_FPR0(\thread) sdc1 $f2, THREAD_FPR2(\thread) @@ -70,7 +70,7 @@ sw \tmp, THREAD_FCR31(\thread) .endm - .macro fpu_restore_double thread tmp=t0 + .macro fpu_restore_double thread status tmp=t0 lw \tmp, THREAD_FCR31(\thread) ldc1 $f0, THREAD_FPR0(\thread) ldc1 $f2, THREAD_FPR2(\thread) diff --git a/include/asm-mips/asmmacro-64.h b/include/asm-mips/asmmacro-64.h index 559c355b9b86..225feefcb25d 100644 --- a/include/asm-mips/asmmacro-64.h +++ b/include/asm-mips/asmmacro-64.h @@ -53,12 +53,12 @@ sdc1 $f31, THREAD_FPR31(\thread) .endm - .macro fpu_save_double thread status tmp1 tmp2 - sll \tmp2, \tmp1, 5 - bgez \tmp2, 2f + .macro fpu_save_double thread status tmp + sll \tmp, \status, 5 + bgez \tmp, 2f fpu_save_16odd \thread 2: - fpu_save_16even \thread \tmp1 # clobbers t1 + fpu_save_16even \thread \tmp .endm .macro fpu_restore_16even thread tmp=t0 @@ -101,13 +101,12 @@ ldc1 $f31, THREAD_FPR31(\thread) .endm - .macro fpu_restore_double thread tmp - mfc0 t0, CP0_STATUS - sll t1, t0, 5 - bgez t1, 1f # 16 register mode? + .macro fpu_restore_double thread status tmp + sll \tmp, \status, 5 + bgez \tmp, 1f # 16 register mode? - fpu_restore_16odd a0 -1: fpu_restore_16even a0, t0 # clobbers t0 + fpu_restore_16odd \thread +1: fpu_restore_16even \thread \tmp .endm .macro cpu_save_nonscratch thread diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h index 14fc88f27226..3b745e76f429 100644 --- a/include/asm-mips/bootinfo.h +++ b/include/asm-mips/bootinfo.h @@ -217,6 +217,13 @@ */ #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */ #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */ +#define MACH_TITAN_EXCITE 2 /* Basler eXcite */ + +/* + * Valid machtype for group NEC EMMA2RH + */ +#define MACH_GROUP_NEC_EMMA2RH 25 /* NEC EMMA2RH (was 23) */ +#define MACH_NEC_MARKEINS 0 /* NEC EMMA2RH Mark-eins */ #define CL_SIZE COMMAND_LINE_SIZE @@ -258,4 +265,10 @@ extern char arcs_cmdline[CL_SIZE]; * Registers a0, a1, a3 and a4 as passed to the kenrel entry by firmware */ extern unsigned long fw_arg0, fw_arg1, fw_arg2, fw_arg3; + +/* + * Platform memory detection hook called by setup_arch + */ +extern void plat_mem_setup(void); + #endif /* _ASM_BOOTINFO_H */ diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h index 818b9a97e214..dff2a0a52f8f 100644 --- a/include/asm-mips/cpu.h +++ b/include/asm-mips/cpu.h @@ -51,6 +51,7 @@ #define PRID_IMP_R4300 0x0b00 #define PRID_IMP_VR41XX 0x0c00 #define PRID_IMP_R12000 0x0e00 +#define PRID_IMP_R14000 0x0f00 #define PRID_IMP_R8000 0x1000 #define PRID_IMP_PR4450 0x1200 #define PRID_IMP_R4600 0x2000 @@ -87,6 +88,7 @@ #define PRID_IMP_24K 0x9300 #define PRID_IMP_34K 0x9500 #define PRID_IMP_24KE 0x9600 +#define PRID_IMP_74K 0x9700 /* * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE @@ -196,7 +198,9 @@ #define CPU_34K 60 #define CPU_PR4450 61 #define CPU_SB1A 62 -#define CPU_LAST 62 +#define CPU_74K 63 +#define CPU_R14000 64 +#define CPU_LAST 64 /* * ISA Level encodings diff --git a/include/asm-mips/ddb5074.h b/include/asm-mips/ddb5074.h deleted file mode 100644 index 0d09ac27f9a5..000000000000 --- a/include/asm-mips/ddb5074.h +++ /dev/null @@ -1,11 +0,0 @@ -/* - * include/asm-mips/ddb5074.h -- NEC DDB Vrc-5074 definitions - * - * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com> - * Sony Software Development Center Europe (SDCE), Brussels - */ - -extern void ddb5074_led_hex(int hex); -extern void ddb5074_led_d2(int on); -extern void ddb5074_led_d3(int on); - diff --git a/include/asm-mips/ddb5xxx/ddb5074.h b/include/asm-mips/ddb5xxx/ddb5074.h deleted file mode 100644 index 58d88306af65..000000000000 --- a/include/asm-mips/ddb5xxx/ddb5074.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * include/asm-mips/ddb5074.h -- NEC DDB Vrc-5074 definitions - * - * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com> - * Sony Software Development Center Europe (SDCE), Brussels - */ - -#ifndef _ASM_DDB5XXX_DDB5074_H -#define _ASM_DDB5XXX_DDB5074_H - -#include <asm/nile4.h> - -#define DDB_SDRAM_SIZE 0x04000000 /* 64MB */ - -#define DDB_PCI_IO_BASE 0x06000000 -#define DDB_PCI_IO_SIZE 0x02000000 /* 32 MB */ - -#define DDB_PCI_MEM_BASE 0x08000000 -#define DDB_PCI_MEM_SIZE 0x08000000 /* 128 MB */ - -#define DDB_PCI_CONFIG_BASE DDB_PCI_MEM_BASE -#define DDB_PCI_CONFIG_SIZE DDB_PCI_MEM_SIZE - -#define NILE4_PCI_IO_BASE 0xa6000000 -#define NILE4_PCI_MEM_BASE 0xa8000000 -#define NILE4_PCI_CFG_BASE NILE4_PCI_MEM_BASE -#define DDB_PCI_IACK_BASE NILE4_PCI_IO_BASE - -#define NILE4_IRQ_BASE NUM_I8259_INTERRUPTS -#define CPU_IRQ_BASE (NUM_NILE4_INTERRUPTS + NILE4_IRQ_BASE) -#define CPU_NILE4_CASCADE 2 - -extern void ddb5074_led_hex(int hex); -extern void ddb5074_led_d2(int on); -extern void ddb5074_led_d3(int on); - -extern void nile4_irq_setup(u32 base); -#endif diff --git a/include/asm-mips/ddb5xxx/ddb5476.h b/include/asm-mips/ddb5xxx/ddb5476.h deleted file mode 100644 index 4c23390d9354..000000000000 --- a/include/asm-mips/ddb5xxx/ddb5476.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - * header file specific for ddb5476 - * - * Copyright (C) 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -/* - * Memory map (physical address) - * - * Note most of the following address must be properly aligned by the - * corresponding size. For example, if PCI_IO_SIZE is 16MB, then - * PCI_IO_BASE must be aligned along 16MB boundary. - */ -#define DDB_SDRAM_BASE 0x00000000 -#define DDB_SDRAM_SIZE 0x04000000 /* 64MB */ - -#define DDB_DCS3_BASE 0x04000000 /* flash 1 */ -#define DDB_DCS3_SIZE 0x01000000 /* 16MB */ - -#define DDB_DCS2_BASE 0x05000000 /* flash 2 */ -#define DDB_DCS2_SIZE 0x01000000 /* 16MB */ - -#define DDB_PCI_IO_BASE 0x06000000 -#define DDB_PCI_IO_SIZE 0x02000000 /* 32 MB */ - -#define DDB_PCI_MEM_BASE 0x08000000 -#define DDB_PCI_MEM_SIZE 0x08000000 /* 128 MB */ - -#define DDB_DCS5_BASE 0x13000000 /* DDB status regs */ -#define DDB_DCS5_SIZE 0x00200000 /* 2MB, 8-bit */ - -#define DDB_DCS4_BASE 0x14000000 /* DDB control regs */ -#define DDB_DCS4_SIZE 0x00200000 /* 2MB, 8-bit */ - -#define DDB_INTCS_BASE 0x1fa00000 /* VRC5476 control regs */ -#define DDB_INTCS_SIZE 0x00200000 /* 2MB */ - -#define DDB_BOOTCS_BASE 0x1fc00000 /* Boot ROM / EPROM /Flash */ -#define DDB_BOOTCS_SIZE 0x00200000 /* 2 MB - doc says 4MB */ - - -/* aliases */ -#define DDB_PCI_CONFIG_BASE DDB_PCI_MEM_BASE -#define DDB_PCI_CONFIG_SIZE DDB_PCI_MEM_SIZE - -/* PCI intr ack share PCIW0 with PCI IO */ -#define DDB_PCI_IACK_BASE DDB_PCI_IO_BASE - -/* - * Interrupt mapping - * - * We have three interrupt controllers: - * - * . CPU itself - 8 sources - * . i8259 - 16 sources - * . vrc5476 - 16 sources - * - * They connected as follows: - * all vrc5476 interrupts are routed to cpu IP2 (by software setting) - * all i2869 are routed to INTC in vrc5476 (by hardware connection) - * - * All VRC5476 PCI interrupts are level-triggered (no ack needed). - * All PCI irq but INTC are active low. - */ - -/* - * irq number block assignment - */ - -#define NUM_CPU_IRQ 8 -#define NUM_I8259_IRQ 16 -#define NUM_VRC5476_IRQ 16 - -#define DDB_IRQ_BASE 0 - -#define I8259_IRQ_BASE DDB_IRQ_BASE -#define VRC5476_IRQ_BASE (I8259_IRQ_BASE + NUM_I8259_IRQ) -#define CPU_IRQ_BASE (VRC5476_IRQ_BASE + NUM_VRC5476_IRQ) - -/* - * vrc5476 irq defs, see page 52-64 of Vrc5074 system controller manual - */ - -#define VRC5476_IRQ_CPCE 0 /* cpu parity error */ -#define VRC5476_IRQ_CNTD 1 /* cpu no target */ -#define VRC5476_IRQ_MCE 2 /* memory check error */ -#define VRC5476_IRQ_DMA 3 /* DMA */ -#define VRC5476_IRQ_UART 4 /* vrc5476 builtin UART, not used */ -#define VRC5476_IRQ_WDOG 5 /* watchdog timer */ -#define VRC5476_IRQ_GPT 6 /* general purpose timer */ -#define VRC5476_IRQ_LBRT 7 /* local bus read timeout */ -#define VRC5476_IRQ_INTA 8 /* PCI INT #A */ -#define VRC5476_IRQ_INTB 9 /* PCI INT #B */ -#define VRC5476_IRQ_INTC 10 /* PCI INT #C */ -#define VRC5476_IRQ_INTD 11 /* PCI INT #D */ -#define VRC5476_IRQ_INTE 12 /* PCI INT #E */ -#define VRC5476_IRQ_RESERVED_13 13 /* reserved */ -#define VRC5476_IRQ_PCIS 14 /* PCI SERR # */ -#define VRC5476_IRQ_PCI 15 /* PCI internal error */ - -/* - * i2859 irq assignment - */ -#define I8259_IRQ_RESERVED_0 0 -#define I8259_IRQ_KEYBOARD 1 /* M1543 default */ -#define I8259_IRQ_CASCADE 2 -#define I8259_IRQ_UART_B 3 /* M1543 default, may conflict with RTC according to schematic diagram */ -#define I8259_IRQ_UART_A 4 /* M1543 default */ -#define I8259_IRQ_PARALLEL 5 /* M1543 default */ -#define I8259_IRQ_RESERVED_6 6 -#define I8259_IRQ_RESERVED_7 7 -#define I8259_IRQ_RTC 8 /* who set this? */ -#define I8259_IRQ_USB 9 /* ddb_setup */ -#define I8259_IRQ_PMU 10 /* ddb_setup */ -#define I8259_IRQ_RESERVED_11 11 -#define I8259_IRQ_RESERVED_12 12 /* m1543_irq_setup */ -#define I8259_IRQ_RESERVED_13 13 -#define I8259_IRQ_HDC1 14 /* default and ddb_setup */ -#define I8259_IRQ_HDC2 15 /* default */ - - -/* - * misc - */ -#define VRC5476_I8259_CASCADE VRC5476_IRQ_INTC -#define CPU_VRC5476_CASCADE 2 - -#define is_i8259_irq(irq) ((irq) < NUM_I8259_IRQ) -#define nile4_to_irq(n) ((n)+NUM_I8259_IRQ) -#define irq_to_nile4(n) ((n)-NUM_I8259_IRQ) - -/* - * low-level irq functions - */ -#ifndef __ASSEMBLY__ -extern void nile4_map_irq(int nile4_irq, int cpu_irq); -extern void nile4_map_irq_all(int cpu_irq); -extern void nile4_enable_irq(int nile4_irq); -extern void nile4_disable_irq(int nile4_irq); -extern void nile4_disable_irq_all(void); -extern u16 nile4_get_irq_stat(int cpu_irq); -extern void nile4_enable_irq_output(int cpu_irq); -extern void nile4_disable_irq_output(int cpu_irq); -extern void nile4_set_pci_irq_polarity(int pci_irq, int high); -extern void nile4_set_pci_irq_level_or_edge(int pci_irq, int level); -extern void nile4_clear_irq(int nile4_irq); -extern void nile4_clear_irq_mask(u32 mask); -extern u8 nile4_i8259_iack(void); -extern void nile4_dump_irq_status(void); /* Debug */ -#endif /* !__ASSEMBLY__ */ diff --git a/include/asm-mips/ddb5xxx/ddb5xxx.h b/include/asm-mips/ddb5xxx/ddb5xxx.h index 42c274871625..e97fcc8d548b 100644 --- a/include/asm-mips/ddb5xxx/ddb5xxx.h +++ b/include/asm-mips/ddb5xxx/ddb5xxx.h @@ -173,13 +173,8 @@ static inline void ddb_sync(void) { -/* The DDB5074 doesn't seem to like these accesses. They kill the board on - * interrupt load - */ -#ifndef CONFIG_DDB5074 volatile u32 *p = (volatile u32 *)0xbfc00000; (void)(*p); -#endif } static inline void ddb_out32(u32 offset, u32 val) @@ -259,11 +254,7 @@ extern void ddb_pci_reset_bus(void); /* * include the board dependent part */ -#if defined(CONFIG_DDB5074) -#include <asm/ddb5xxx/ddb5074.h> -#elif defined(CONFIG_DDB5476) -#include <asm/ddb5xxx/ddb5476.h> -#elif defined(CONFIG_DDB5477) +#if defined(CONFIG_DDB5477) #include <asm/ddb5xxx/ddb5477.h> #else #error "Unknown DDB board!" diff --git a/include/asm-mips/delay.h b/include/asm-mips/delay.h index b2c9ed47508d..ea77050f8e3a 100644 --- a/include/asm-mips/delay.h +++ b/include/asm-mips/delay.h @@ -18,20 +18,22 @@ static inline void __delay(unsigned long loops) { if (sizeof(long) == 4) __asm__ __volatile__ ( - ".set\tnoreorder\n" - "1:\tbnez\t%0,1b\n\t" - "subu\t%0,1\n\t" - ".set\treorder" + " .set noreorder \n" + " .align 3 \n" + "1: bnez %0, 1b \n" + " subu %0, 1 \n" + " .set reorder \n" : "=r" (loops) : "0" (loops)); else if (sizeof(long) == 8) __asm__ __volatile__ ( - ".set\tnoreorder\n" - "1:\tbnez\t%0,1b\n\t" - "dsubu\t%0,1\n\t" - ".set\treorder" - :"=r" (loops) - :"0" (loops)); + " .set noreorder \n" + " .align 3 \n" + "1: bnez %0, 1b \n" + " dsubu %0, 1 \n" + " .set reorder \n" + : "=r" (loops) + : "0" (loops)); } diff --git a/include/asm-mips/emma2rh/emma2rh.h b/include/asm-mips/emma2rh/emma2rh.h new file mode 100644 index 000000000000..4fb8df71caa9 --- /dev/null +++ b/include/asm-mips/emma2rh/emma2rh.h @@ -0,0 +1,330 @@ +/* + * include/asm-mips/emma2rh/emma2rh.h + * This file is EMMA2RH common header. + * + * Copyright (C) NEC Electronics Corporation 2005-2006 + * + * This file based on include/asm-mips/ddb5xxx/ddb5xxx.h + * Copyright 2001 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_EMMA2RH_EMMA2RH_H +#define __ASM_EMMA2RH_EMMA2RH_H + +/* + * EMMA2RH registers + */ +#define REGBASE 0x10000000 + +#define EMMA2RH_BHIF_STRAP_0 (0x000010+REGBASE) +#define EMMA2RH_BHIF_INT_ST_0 (0x000030+REGBASE) +#define EMMA2RH_BHIF_INT_ST_1 (0x000034+REGBASE) +#define EMMA2RH_BHIF_INT_ST_2 (0x000038+REGBASE) +#define EMMA2RH_BHIF_INT_EN_0 (0x000040+REGBASE) +#define EMMA2RH_BHIF_INT_EN_1 (0x000044+REGBASE) +#define EMMA2RH_BHIF_INT_EN_2 (0x000048+REGBASE) +#define EMMA2RH_BHIF_INT1_EN_0 (0x000050+REGBASE) +#define EMMA2RH_BHIF_INT1_EN_1 (0x000054+REGBASE) +#define EMMA2RH_BHIF_INT1_EN_2 (0x000058+REGBASE) +#define EMMA2RH_BHIF_SW_INT (0x000070+REGBASE) +#define EMMA2RH_BHIF_SW_INT_EN (0x000080+REGBASE) +#define EMMA2RH_BHIF_SW_INT_CLR (0x000090+REGBASE) +#define EMMA2RH_BHIF_MAIN_CTRL (0x0000b4+REGBASE) +#define EMMA2RH_BHIF_EXCEPT_VECT_BASE_ADDRESS (0x0000c0+REGBASE) +#define EMMA2RH_GPIO_DIR (0x110d20+REGBASE) +#define EMMA2RH_GPIO_INT_ST (0x110d30+REGBASE) +#define EMMA2RH_GPIO_INT_MASK (0x110d3c+REGBASE) +#define EMMA2RH_GPIO_INT_MODE (0x110d48+REGBASE) +#define EMMA2RH_GPIO_INT_CND_A (0x110d54+REGBASE) +#define EMMA2RH_GPIO_INT_CND_B (0x110d60+REGBASE) +#define EMMA2RH_PBRD_INT_EN (0x100010+REGBASE) +#define EMMA2RH_PBRD_CLKSEL (0x100028+REGBASE) +#define EMMA2RH_PFUR0_BASE (0x101000+REGBASE) +#define EMMA2RH_PFUR1_BASE (0x102000+REGBASE) +#define EMMA2RH_PFUR2_BASE (0x103000+REGBASE) +#define EMMA2RH_PIIC0_BASE (0x107000+REGBASE) +#define EMMA2RH_PIIC1_BASE (0x108000+REGBASE) +#define EMMA2RH_PIIC2_BASE (0x109000+REGBASE) +#define EMMA2RH_PCI_CONTROL (0x200000+REGBASE) +#define EMMA2RH_PCI_ARBIT_CTR (0x200004+REGBASE) +#define EMMA2RH_PCI_IWIN0_CTR (0x200010+REGBASE) +#define EMMA2RH_PCI_IWIN1_CTR (0x200014+REGBASE) +#define EMMA2RH_PCI_INIT_ESWP (0x200018+REGBASE) +#define EMMA2RH_PCI_INT (0x200020+REGBASE) +#define EMMA2RH_PCI_INT_EN (0x200024+REGBASE) +#define EMMA2RH_PCI_TWIN_CTR (0x200030+REGBASE) +#define EMMA2RH_PCI_TWIN_BADR (0x200034+REGBASE) +#define EMMA2RH_PCI_TWIN0_DADR (0x200038+REGBASE) +#define EMMA2RH_PCI_TWIN1_DADR (0x20003c+REGBASE) + +/* + * Memory map (physical address) + * + * Note most of the following address must be properly aligned by the + * corresponding size. For example, if PCI_IO_SIZE is 16MB, then + * PCI_IO_BASE must be aligned along 16MB boundary. + */ + +/* the actual ram size is detected at run-time */ +#define EMMA2RH_RAM_BASE 0x00000000 +#define EMMA2RH_RAM_SIZE 0x10000000 /* less than 256MB */ + +#define EMMA2RH_IO_BASE 0x10000000 +#define EMMA2RH_IO_SIZE 0x01000000 /* 16 MB */ + +#define EMMA2RH_GENERALIO_BASE 0x11000000 +#define EMMA2RH_GENERALIO_SIZE 0x01000000 /* 16 MB */ + +#define EMMA2RH_PCI_IO_BASE 0x12000000 +#define EMMA2RH_PCI_IO_SIZE 0x02000000 /* 32 MB */ + +#define EMMA2RH_PCI_MEM_BASE 0x14000000 +#define EMMA2RH_PCI_MEM_SIZE 0x08000000 /* 128 MB */ + +#define EMMA2RH_ROM_BASE 0x1c000000 +#define EMMA2RH_ROM_SIZE 0x04000000 /* 64 MB */ + +#define EMMA2RH_PCI_CONFIG_BASE EMMA2RH_PCI_IO_BASE +#define EMMA2RH_PCI_CONFIG_SIZE EMMA2RH_PCI_IO_SIZE + +#define NUM_CPU_IRQ 8 +#define NUM_EMMA2RH_IRQ 96 + +#define CPU_EMMA2RH_CASCADE 2 +#define EMMA2RH_IRQ_BASE 0 + +/* + * emma2rh irq defs + */ + +#define EMMA2RH_IRQ_INT0 (0 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT1 (1 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT2 (2 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT3 (3 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT4 (4 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT5 (5 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT6 (6 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT7 (7 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT8 (8 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT9 (9 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT10 (10 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT11 (11 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT12 (12 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT13 (13 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT14 (14 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT15 (15 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT16 (16 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT17 (17 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT18 (18 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT19 (19 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT20 (20 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT21 (21 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT22 (22 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT23 (23 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT24 (24 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT25 (25 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT26 (26 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT27 (27 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT28 (28 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT29 (29 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT30 (30 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT31 (31 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT32 (32 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT33 (33 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT34 (34 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT35 (35 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT36 (36 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT37 (37 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT38 (38 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT39 (39 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT40 (40 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT41 (41 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT42 (42 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT43 (43 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT44 (44 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT45 (45 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT46 (46 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT47 (47 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT48 (48 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT49 (49 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT50 (50 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT51 (51 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT52 (52 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT53 (53 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT54 (54 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT55 (55 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT56 (56 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT57 (57 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT58 (58 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT59 (59 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT60 (60 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT61 (61 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT62 (62 + EMMA2RH_IRQ_BASE) +#define EMMA2RH_IRQ_INT63 (63 + EMMA2RH_IRQ_BASE) + +#define EMMA2RH_IRQ_PFUR0 EMMA2RH_IRQ_INT49 +#define EMMA2RH_IRQ_PFUR1 EMMA2RH_IRQ_INT50 +#define EMMA2RH_IRQ_PFUR2 EMMA2RH_IRQ_INT51 +#define EMMA2RH_IRQ_PIIC0 EMMA2RH_IRQ_INT56 +#define EMMA2RH_IRQ_PIIC1 EMMA2RH_IRQ_INT57 +#define EMMA2RH_IRQ_PIIC2 EMMA2RH_IRQ_INT58 + +/* + * EMMA2RH Register Access + */ + +#define EMMA2RH_BASE (0xa0000000) + +static inline void emma2rh_sync(void) +{ + volatile u32 *p = (volatile u32 *)0xbfc00000; + (void)(*p); +} + +static inline void emma2rh_out32(u32 offset, u32 val) +{ + *(volatile u32 *)(EMMA2RH_BASE | offset) = val; + emma2rh_sync(); +} + +static inline u32 emma2rh_in32(u32 offset) +{ + u32 val = *(volatile u32 *)(EMMA2RH_BASE | offset); + emma2rh_sync(); + return val; +} + +static inline void emma2rh_out16(u32 offset, u16 val) +{ + *(volatile u16 *)(EMMA2RH_BASE | offset) = val; + emma2rh_sync(); +} + +static inline u16 emma2rh_in16(u32 offset) +{ + u16 val = *(volatile u16 *)(EMMA2RH_BASE | offset); + emma2rh_sync(); + return val; +} + +static inline void emma2rh_out8(u32 offset, u8 val) +{ + *(volatile u8 *)(EMMA2RH_BASE | offset) = val; + emma2rh_sync(); +} + +static inline u8 emma2rh_in8(u32 offset) +{ + u8 val = *(volatile u8 *)(EMMA2RH_BASE | offset); + emma2rh_sync(); + return val; +} + +/** + * IIC registers map + **/ + +/*---------------------------------------------------------------------------*/ +/* CNT - Control register (00H R/W) */ +/*---------------------------------------------------------------------------*/ +#define SPT 0x00000001 +#define STT 0x00000002 +#define ACKE 0x00000004 +#define WTIM 0x00000008 +#define SPIE 0x00000010 +#define WREL 0x00000020 +#define LREL 0x00000040 +#define IICE 0x00000080 +#define CNT_RESERVED 0x000000ff /* reserved bit 0 */ + +#define I2C_EMMA_START (IICE | STT) +#define I2C_EMMA_STOP (IICE | SPT) +#define I2C_EMMA_REPSTART I2C_EMMA_START + +/*---------------------------------------------------------------------------*/ +/* STA - Status register (10H Read) */ +/*---------------------------------------------------------------------------*/ +#define MSTS 0x00000080 +#define ALD 0x00000040 +#define EXC 0x00000020 +#define COI 0x00000010 +#define TRC 0x00000008 +#define ACKD 0x00000004 +#define STD 0x00000002 +#define SPD 0x00000001 + +/*---------------------------------------------------------------------------*/ +/* CSEL - Clock select register (20H R/W) */ +/*---------------------------------------------------------------------------*/ +#define FCL 0x00000080 +#define ND50 0x00000040 +#define CLD 0x00000020 +#define DAD 0x00000010 +#define SMC 0x00000008 +#define DFC 0x00000004 +#define CL 0x00000003 +#define CSEL_RESERVED 0x000000ff /* reserved bit 0 */ + +#define FAST397 0x0000008b +#define FAST297 0x0000008a +#define FAST347 0x0000000b +#define FAST260 0x0000000a +#define FAST130 0x00000008 +#define STANDARD108 0x00000083 +#define STANDARD83 0x00000082 +#define STANDARD95 0x00000003 +#define STANDARD73 0x00000002 +#define STANDARD36 0x00000001 +#define STANDARD71 0x00000000 + +/*---------------------------------------------------------------------------*/ +/* SVA - Slave address register (30H R/W) */ +/*---------------------------------------------------------------------------*/ +#define SVA 0x000000fe + +/*---------------------------------------------------------------------------*/ +/* SHR - Shift register (40H R/W) */ +/*---------------------------------------------------------------------------*/ +#define SR 0x000000ff + +/*---------------------------------------------------------------------------*/ +/* INT - Interrupt register (50H R/W) */ +/* INTM - Interrupt mask register (60H R/W) */ +/*---------------------------------------------------------------------------*/ +#define INTE0 0x00000001 + +/*********************************************************************** + * I2C registers + *********************************************************************** + */ +#define I2C_EMMA_CNT 0x00 +#define I2C_EMMA_STA 0x10 +#define I2C_EMMA_CSEL 0x20 +#define I2C_EMMA_SVA 0x30 +#define I2C_EMMA_SHR 0x40 +#define I2C_EMMA_INT 0x50 +#define I2C_EMMA_INTM 0x60 + +/* + * include the board dependent part + */ +#if defined(CONFIG_MARKEINS) +#include <asm/emma2rh/markeins.h> +#else +#error "Unknown EMMA2RH board!" +#endif + +#endif /* __ASM_EMMA2RH_EMMA2RH_H */ diff --git a/include/asm-mips/emma2rh/markeins.h b/include/asm-mips/emma2rh/markeins.h new file mode 100644 index 000000000000..8fa766795078 --- /dev/null +++ b/include/asm-mips/emma2rh/markeins.h @@ -0,0 +1,76 @@ +/* + * include/asm-mips/emma2rh/markeins.h + * This file is EMMA2RH board depended header. + * + * Copyright (C) NEC Electronics Corporation 2005-2006 + * + * This file based on include/asm-mips/ddb5xxx/ddb5xxx.h + * Copyright 2001 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef MARKEINS_H +#define MARKEINS_H + +#define NUM_EMMA2RH_IRQ_SW 32 +#define NUM_EMMA2RH_IRQ_GPIO 32 + +#define EMMA2RH_SW_CASCADE (EMMA2RH_IRQ_INT7 - EMMA2RH_IRQ_INT0) +#define EMMA2RH_GPIO_CASCADE (EMMA2RH_IRQ_INT46 - EMMA2RH_IRQ_INT0) + +#define EMMA2RH_SW_IRQ_BASE (EMMA2RH_IRQ_BASE + NUM_EMMA2RH_IRQ) +#define EMMA2RH_GPIO_IRQ_BASE (EMMA2RH_SW_IRQ_BASE + NUM_EMMA2RH_IRQ_SW) +#define CPU_IRQ_BASE (EMMA2RH_GPIO_IRQ_BASE + NUM_EMMA2RH_IRQ_GPIO) + +#define EMMA2RH_SW_IRQ_INT0 (0+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT1 (1+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT2 (2+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT3 (3+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT4 (4+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT5 (5+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT6 (6+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT7 (7+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT8 (8+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT9 (9+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT10 (10+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT11 (11+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT12 (12+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT13 (13+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT14 (14+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT15 (15+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT16 (16+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT17 (17+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT18 (18+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT19 (19+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT20 (20+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT21 (21+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT22 (22+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT23 (23+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT24 (24+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT25 (25+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT26 (26+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT27 (27+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT28 (28+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT29 (29+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT30 (30+EMMA2RH_SW_IRQ_BASE) +#define EMMA2RH_SW_IRQ_INT31 (31+EMMA2RH_SW_IRQ_BASE) + +#define MARKEINS_PCI_IRQ_INTA EMMA2RH_GPIO_IRQ_BASE+15 +#define MARKEINS_PCI_IRQ_INTB EMMA2RH_GPIO_IRQ_BASE+16 +#define MARKEINS_PCI_IRQ_INTC EMMA2RH_GPIO_IRQ_BASE+17 +#define MARKEINS_PCI_IRQ_INTD EMMA2RH_GPIO_IRQ_BASE+18 + +#endif /* CONFIG_MARKEINS */ diff --git a/include/asm-mips/fpu.h b/include/asm-mips/fpu.h index 199e768ff73a..58c561a9ec6b 100644 --- a/include/asm-mips/fpu.h +++ b/include/asm-mips/fpu.h @@ -137,10 +137,9 @@ static inline fpureg_t *get_fpu_regs(struct task_struct *tsk) if (cpu_has_fpu) { if ((tsk == current) && __is_fpu_owner()) _save_fp(current); - return tsk->thread.fpu.hard.fpr; } - return tsk->thread.fpu.soft.fpr; + return tsk->thread.fpu.fpr; } #endif /* _ASM_FPU_H */ diff --git a/include/asm-mips/fpu_emulator.h b/include/asm-mips/fpu_emulator.h index 16cb4d11dd0b..2731c38bd7ae 100644 --- a/include/asm-mips/fpu_emulator.h +++ b/include/asm-mips/fpu_emulator.h @@ -12,8 +12,8 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. * - * Further private data for which no space exists in mips_fpu_soft_struct. - * This should be subsumed into the mips_fpu_soft_struct structure as + * Further private data for which no space exists in mips_fpu_struct. + * This should be subsumed into the mips_fpu_struct structure as * defined in processor.h as soon as the absurd wired absolute assembler * offsets become dynamic at compile time. * diff --git a/include/asm-mips/futex.h b/include/asm-mips/futex.h index d71d878990df..ed023eae0674 100644 --- a/include/asm-mips/futex.h +++ b/include/asm-mips/futex.h @@ -6,6 +6,7 @@ #include <linux/futex.h> #include <asm/errno.h> #include <asm/uaccess.h> +#include <asm/war.h> #ifdef CONFIG_SMP #define __FUTEX_SMP_SYNC " sync \n" @@ -15,30 +16,60 @@ #define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \ { \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " .set mips3 \n" \ - "1: ll %1, (%3) # __futex_atomic_op1 \n" \ - " .set mips0 \n" \ - " " insn " \n" \ - " .set mips3 \n" \ - "2: sc $1, (%3) \n" \ - " beqzl $1, 1b \n" \ - __FUTEX_SMP_SYNC \ - "3: \n" \ - " .set pop \n" \ - " .set mips0 \n" \ - " .section .fixup,\"ax\" \n" \ - "4: li %0, %5 \n" \ - " j 2b \n" \ - " .previous \n" \ - " .section __ex_table,\"a\" \n" \ - " "__UA_ADDR "\t1b, 4b \n" \ - " "__UA_ADDR "\t2b, 4b \n" \ - " .previous \n" \ - : "=r" (ret), "=r" (oldval) \ - : "0" (0), "r" (uaddr), "Jr" (oparg), "i" (-EFAULT)); \ + if (cpu_has_llsc && R10000_LLSC_WAR) { \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " .set mips3 \n" \ + "1: ll %1, %4 # __futex_atomic_op \n" \ + " .set mips0 \n" \ + " " insn " \n" \ + " .set mips3 \n" \ + "2: sc $1, %2 \n" \ + " beqzl $1, 1b \n" \ + __FUTEX_SMP_SYNC \ + "3: \n" \ + " .set pop \n" \ + " .set mips0 \n" \ + " .section .fixup,\"ax\" \n" \ + "4: li %0, %6 \n" \ + " j 2b \n" \ + " .previous \n" \ + " .section __ex_table,\"a\" \n" \ + " "__UA_ADDR "\t1b, 4b \n" \ + " "__UA_ADDR "\t2b, 4b \n" \ + " .previous \n" \ + : "=r" (ret), "=&r" (oldval), "=R" (*uaddr) \ + : "0" (0), "R" (*uaddr), "Jr" (oparg), "i" (-EFAULT) \ + : "memory"); \ + } else if (cpu_has_llsc) { \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noat \n" \ + " .set mips3 \n" \ + "1: ll %1, %4 # __futex_atomic_op \n" \ + " .set mips0 \n" \ + " " insn " \n" \ + " .set mips3 \n" \ + "2: sc $1, %2 \n" \ + " beqz $1, 1b \n" \ + __FUTEX_SMP_SYNC \ + "3: \n" \ + " .set pop \n" \ + " .set mips0 \n" \ + " .section .fixup,\"ax\" \n" \ + "4: li %0, %6 \n" \ + " j 2b \n" \ + " .previous \n" \ + " .section __ex_table,\"a\" \n" \ + " "__UA_ADDR "\t1b, 4b \n" \ + " "__UA_ADDR "\t2b, 4b \n" \ + " .previous \n" \ + : "=r" (ret), "=&r" (oldval), "=R" (*uaddr) \ + : "0" (0), "R" (*uaddr), "Jr" (oparg), "i" (-EFAULT) \ + : "memory"); \ + } else \ + ret = -ENOSYS; \ } static inline int @@ -59,23 +90,23 @@ futex_atomic_op_inuser (int encoded_op, int __user *uaddr) switch (op) { case FUTEX_OP_SET: - __futex_atomic_op("move $1, %z4", ret, oldval, uaddr, oparg); + __futex_atomic_op("move $1, %z5", ret, oldval, uaddr, oparg); break; case FUTEX_OP_ADD: - __futex_atomic_op("addu $1, %1, %z4", + __futex_atomic_op("addu $1, %1, %z5", ret, oldval, uaddr, oparg); break; case FUTEX_OP_OR: - __futex_atomic_op("or $1, %1, %z4", + __futex_atomic_op("or $1, %1, %z5", ret, oldval, uaddr, oparg); break; case FUTEX_OP_ANDN: - __futex_atomic_op("and $1, %1, %z4", + __futex_atomic_op("and $1, %1, %z5", ret, oldval, uaddr, ~oparg); break; case FUTEX_OP_XOR: - __futex_atomic_op("xor $1, %1, %z4", + __futex_atomic_op("xor $1, %1, %z5", ret, oldval, uaddr, oparg); break; default: @@ -101,7 +132,69 @@ futex_atomic_op_inuser (int encoded_op, int __user *uaddr) static inline int futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval) { - return -ENOSYS; + int retval; + + if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int))) + return -EFAULT; + + if (cpu_has_llsc && R10000_LLSC_WAR) { + __asm__ __volatile__( + "# futex_atomic_cmpxchg_inatomic \n" + " .set push \n" + " .set noat \n" + " .set mips3 \n" + "1: ll %0, %2 \n" + " bne %0, %z3, 3f \n" + " .set mips0 \n" + " move $1, %z4 \n" + " .set mips3 \n" + "2: sc $1, %1 \n" + " beqzl $1, 1b \n" + __FUTEX_SMP_SYNC + "3: \n" + " .set pop \n" + " .section .fixup,\"ax\" \n" + "4: li %0, %5 \n" + " j 3b \n" + " .previous \n" + " .section __ex_table,\"a\" \n" + " "__UA_ADDR "\t1b, 4b \n" + " "__UA_ADDR "\t2b, 4b \n" + " .previous \n" + : "=&r" (retval), "=R" (*uaddr) + : "R" (*uaddr), "Jr" (oldval), "Jr" (newval), "i" (-EFAULT) + : "memory"); + } else if (cpu_has_llsc) { + __asm__ __volatile__( + "# futex_atomic_cmpxchg_inatomic \n" + " .set push \n" + " .set noat \n" + " .set mips3 \n" + "1: ll %0, %2 \n" + " bne %0, %z3, 3f \n" + " .set mips0 \n" + " move $1, %z4 \n" + " .set mips3 \n" + "2: sc $1, %1 \n" + " beqz $1, 1b \n" + __FUTEX_SMP_SYNC + "3: \n" + " .set pop \n" + " .section .fixup,\"ax\" \n" + "4: li %0, %5 \n" + " j 3b \n" + " .previous \n" + " .section __ex_table,\"a\" \n" + " "__UA_ADDR "\t1b, 4b \n" + " "__UA_ADDR "\t2b, 4b \n" + " .previous \n" + : "=&r" (retval), "=R" (*uaddr) + : "R" (*uaddr), "Jr" (oldval), "Jr" (newval), "i" (-EFAULT) + : "memory"); + } else + return -ENOSYS; + + return retval; } #endif diff --git a/include/asm-mips/inst.h b/include/asm-mips/inst.h index e0745f4ff624..1ed8d0f62577 100644 --- a/include/asm-mips/inst.h +++ b/include/asm-mips/inst.h @@ -6,6 +6,7 @@ * for more details. * * Copyright (C) 1996, 2000 by Ralf Baechle + * Copyright (C) 2006 by Thiemo Seufer */ #ifndef _ASM_INST_H #define _ASM_INST_H @@ -21,14 +22,14 @@ enum major_op { cop0_op, cop1_op, cop2_op, cop1x_op, beql_op, bnel_op, blezl_op, bgtzl_op, daddi_op, daddiu_op, ldl_op, ldr_op, - major_1c_op, jalx_op, major_1e_op, major_1f_op, + spec2_op, jalx_op, mdmx_op, spec3_op, lb_op, lh_op, lwl_op, lw_op, lbu_op, lhu_op, lwr_op, lwu_op, sb_op, sh_op, swl_op, sw_op, sdl_op, sdr_op, swr_op, cache_op, ll_op, lwc1_op, lwc2_op, pref_op, lld_op, ldc1_op, ldc2_op, ld_op, - sc_op, swc1_op, swc2_op, rdhwr_op, + sc_op, swc1_op, swc2_op, major_3b_op, scd_op, sdc1_op, sdc2_op, sd_op }; @@ -37,7 +38,7 @@ enum major_op { */ enum spec_op { sll_op, movc_op, srl_op, sra_op, - sllv_op, srlv_op, srav_op, spec1_unused_op, /* Opcode 0x07 is unused */ + sllv_op, pmon_op, srlv_op, srav_op, jr_op, jalr_op, movz_op, movn_op, syscall_op, break_op, spim_op, sync_op, mfhi_op, mthi_op, mflo_op, mtlo_op, @@ -55,6 +56,28 @@ enum spec_op { }; /* + * func field of spec2 opcode. + */ +enum spec2_op { + madd_op, maddu_op, mul_op, spec2_3_unused_op, + msub_op, msubu_op, /* more unused ops */ + clz_op = 0x20, clo_op, + dclz_op = 0x24, dclo_op, + sdbpp_op = 0x3f +}; + +/* + * func field of spec3 opcode. + */ +enum spec3_op { + ext_op, dextm_op, dextu_op, dext_op, + ins_op, dinsm_op, dinsu_op, dins_op, + bshfl_op = 0x20, + dbshfl_op = 0x24, + rdhwr_op = 0x3f +}; + +/* * rt field of bcond opcodes. */ enum rt_op { @@ -151,8 +174,8 @@ enum cop1x_func { * func field for mad opcodes (MIPS IV). */ enum mad_func { - madd_op = 0x08, msub_op = 0x0a, - nmadd_op = 0x0c, nmsub_op = 0x0e + madd_fp_op = 0x08, msub_fp_op = 0x0a, + nmadd_fp_op = 0x0c, nmsub_fp_op = 0x0e }; /* diff --git a/include/asm-mips/mach-ddb5074/mc146818rtc.h b/include/asm-mips/mach-ddb5074/mc146818rtc.h deleted file mode 100644 index 2eb9acb10a5a..000000000000 --- a/include/asm-mips/mach-ddb5074/mc146818rtc.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1998, 2001, 03 by Ralf Baechle - * - * RTC routines for PC style attached Dallas chip. - */ -#ifndef __ASM_MACH_DDB5074_MC146818RTC_H -#define __ASM_MACH_DDB5074_MC146818RTC_H - -#include <asm/ddb5xxx/ddb5074.h> -#include <asm/ddb5xxx/ddb5xxx.h> - -#define RTC_PORT(x) (0x70 + (x)) -#define RTC_IRQ 8 - -static inline unsigned char CMOS_READ(unsigned long addr) -{ - return *(volatile unsigned char *)(KSEG1ADDR(DDB_PCI_MEM_BASE)+addr); -} - -static inline void CMOS_WRITE(unsigned char data, unsigned long addr) -{ - *(volatile unsigned char *)(KSEG1ADDR(DDB_PCI_MEM_BASE)+addr) = data; -} - -#define RTC_ALWAYS_BCD 1 - -#endif /* __ASM_MACH_DDB5074_MC146818RTC_H */ diff --git a/include/asm-mips/mach-dec/param.h b/include/asm-mips/mach-dec/param.h deleted file mode 100644 index 3e4f0e390847..000000000000 --- a/include/asm-mips/mach-dec/param.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2003 by Ralf Baechle - */ -#ifndef __ASM_MACH_DEC_PARAM_H -#define __ASM_MACH_DEC_PARAM_H - -/* - * log2(HZ), change this here if you want another HZ value. This is also - * used in dec_time_init. Minimum is 1, Maximum is 15. - */ -#define LOG_2_HZ 7 -#define HZ (1 << LOG_2_HZ) - -#endif /* __ASM_MACH_DEC_PARAM_H */ diff --git a/include/asm-mips/mach-mips/param.h b/include/asm-mips/mach-emma2rh/irq.h index 805ef6d27d3c..bce64244b800 100644 --- a/include/asm-mips/mach-mips/param.h +++ b/include/asm-mips/mach-emma2rh/irq.h @@ -5,9 +5,9 @@ * * Copyright (C) 2003 by Ralf Baechle */ -#ifndef __ASM_MACH_MIPS_PARAM_H -#define __ASM_MACH_MIPS_PARAM_H +#ifndef __ASM_MACH_EMMA2RH_IRQ_H +#define __ASM_MACH_EMMA2RH_IRQ_H -#define HZ 100 /* Internal kernel timer frequency */ +#define NR_IRQS 256 -#endif /* __ASM_MACH_MIPS_PARAM_H */ +#endif /* __ASM_MACH_EMMA2RH_IRQ_H */ diff --git a/include/asm-mips/mach-excite/cpu-feature-overrides.h b/include/asm-mips/mach-excite/cpu-feature-overrides.h new file mode 100644 index 000000000000..abb76b2fd865 --- /dev/null +++ b/include/asm-mips/mach-excite/cpu-feature-overrides.h @@ -0,0 +1,40 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2004 Thomas Koeller <thomas.koeller@baslerweb.com> + */ +#ifndef __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H + +/* + * Basler eXcite has an RM9122 processor. + */ +#define cpu_has_watch 1 +#define cpu_has_mips16 0 +#define cpu_has_divec 0 +#define cpu_has_vce 0 +#define cpu_has_cache_cdex_p 0 +#define cpu_has_cache_cdex_s 0 +#define cpu_has_prefetch 1 +#define cpu_has_mcheck 0 +#define cpu_has_ejtag 0 + +#define cpu_has_llsc 1 +#define cpu_has_vtag_icache 0 +#define cpu_has_dc_aliases 0 +#define cpu_has_ic_fills_f_dc 0 +#define cpu_has_dsp 0 +#define cpu_icache_snoops_remote_store 0 + +#define cpu_has_nofpuex 0 +#define cpu_has_64bits 1 + +#define cpu_has_subset_pcaches 0 + +#define cpu_dcache_line_size() 32 +#define cpu_icache_line_size() 32 +#define cpu_scache_line_size() 32 + +#endif /* __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H */ diff --git a/include/asm-mips/mach-excite/excite.h b/include/asm-mips/mach-excite/excite.h new file mode 100644 index 000000000000..c52610de2b3a --- /dev/null +++ b/include/asm-mips/mach-excite/excite.h @@ -0,0 +1,155 @@ +#ifndef __EXCITE_H__ +#define __EXCITE_H__ + +#include <linux/config.h> +#include <linux/init.h> +#include <asm/addrspace.h> +#include <asm/types.h> + +#define EXCITE_CPU_EXT_CLOCK 100000000 + +#if !defined(__ASSEMBLER__) +void __init excite_kgdb_init(void); +void excite_procfs_init(void); +extern unsigned long memsize; +extern char modetty[]; +extern u32 unit_id; +#endif + +/* Base name for XICAP devices */ +#define XICAP_NAME "xicap_gpi" + +/* OCD register offsets */ +#define LKB0 0x0038 +#define LKB5 0x0128 +#define LKM5 0x012C +#define LKB7 0x0138 +#define LKM7 0x013c +#define LKB8 0x0140 +#define LKM8 0x0144 +#define LKB9 0x0148 +#define LKM9 0x014c +#define LKB10 0x0150 +#define LKM10 0x0154 +#define LKB11 0x0158 +#define LKM11 0x015c +#define LKB12 0x0160 +#define LKM12 0x0164 +#define LKB13 0x0168 +#define LKM13 0x016c +#define LDP0 0x0200 +#define LDP1 0x0210 +#define LDP2 0x0220 +#define LDP3 0x0230 +#define INTPIN0 0x0A40 +#define INTPIN1 0x0A44 +#define INTPIN2 0x0A48 +#define INTPIN3 0x0A4C +#define INTPIN4 0x0A50 +#define INTPIN5 0x0A54 +#define INTPIN6 0x0A58 +#define INTPIN7 0x0A5C + + + + +/* TITAN register offsets */ +#define CPRR 0x0004 +#define CPDSR 0x0008 +#define CPTC0R 0x000c +#define CPTC1R 0x0010 +#define CPCFG0 0x0020 +#define CPCFG1 0x0024 +#define CPDST0A 0x0028 +#define CPDST0B 0x002c +#define CPDST1A 0x0030 +#define CPDST1B 0x0034 +#define CPXDSTA 0x0038 +#define CPXDSTB 0x003c +#define CPXCISRA 0x0048 +#define CPXCISRB 0x004c +#define CPGIG0ER 0x0050 +#define CPGIG1ER 0x0054 +#define CPGRWL 0x0068 +#define CPURSLMT 0x00f8 +#define UACFG 0x0200 +#define UAINTS 0x0204 +#define SDRXFCIE 0x4828 +#define SDTXFCIE 0x4928 +#define INTP0Status0 0x1B00 +#define INTP0Mask0 0x1B04 +#define INTP0Set0 0x1B08 +#define INTP0Clear0 0x1B0C +#define GXCFG 0x5000 +#define GXDMADRPFX 0x5018 +#define GXDMA_DESCADR 0x501c +#define GXCH0TDESSTRT 0x5054 + +/* IRQ definitions */ +#define NMICONFIG 0xac0 +#define TITAN_MSGINT 0xc4 +#define TITAN_IRQ ((TITAN_MSGINT / 0x20) + 2) +#define FPGA0_MSGINT 0x5a +#define FPGA0_IRQ ((FPGA0_MSGINT / 0x20) + 2) +#define FPGA1_MSGINT 0x7b +#define FPGA1_IRQ ((FPGA1_MSGINT / 0x20) + 2) +#define PHY_MSGINT 0x9c +#define PHY_IRQ ((PHY_MSGINT / 0x20) + 2) + +#if defined(CONFIG_BASLER_EXCITE_PROTOTYPE) +/* Pre-release units used interrupt pin #9 */ +#define USB_IRQ 11 +#else +/* Re-designed units use interrupt pin #1 */ +#define USB_MSGINT 0x39 +#define USB_IRQ ((USB_MSGINT / 0x20) + 2) +#endif +#define TIMER_IRQ 12 + + +/* Device address ranges */ +#define EXCITE_OFFS_OCD 0x1fffc000 +#define EXCITE_SIZE_OCD (16 * 1024) +#define EXCITE_PHYS_OCD CPHYSADDR(EXCITE_OFFS_OCD) +#define EXCITE_ADDR_OCD CKSEG1ADDR(EXCITE_OFFS_OCD) + +#define EXCITE_OFFS_SCRAM 0x1fffa000 +#define EXCITE_SIZE_SCRAM (8 << 10) +#define EXCITE_PHYS_SCRAM CPHYSADDR(EXCITE_OFFS_SCRAM) +#define EXCITE_ADDR_SCRAM CKSEG1ADDR(EXCITE_OFFS_SCRAM) + +#define EXCITE_OFFS_PCI_IO 0x1fff8000 +#define EXCITE_SIZE_PCI_IO (8 << 10) +#define EXCITE_PHYS_PCI_IO CPHYSADDR(EXCITE_OFFS_PCI_IO) +#define EXCITE_ADDR_PCI_IO CKSEG1ADDR(EXCITE_OFFS_PCI_IO) + +#define EXCITE_OFFS_TITAN 0x1fff0000 +#define EXCITE_SIZE_TITAN (32 << 10) +#define EXCITE_PHYS_TITAN CPHYSADDR(EXCITE_OFFS_TITAN) +#define EXCITE_ADDR_TITAN CKSEG1ADDR(EXCITE_OFFS_TITAN) + +#define EXCITE_OFFS_PCI_MEM 0x1ffe0000 +#define EXCITE_SIZE_PCI_MEM (64 << 10) +#define EXCITE_PHYS_PCI_MEM CPHYSADDR(EXCITE_OFFS_PCI_MEM) +#define EXCITE_ADDR_PCI_MEM CKSEG1ADDR(EXCITE_OFFS_PCI_MEM) + +#define EXCITE_OFFS_FPGA 0x1ffdc000 +#define EXCITE_SIZE_FPGA (16 << 10) +#define EXCITE_PHYS_FPGA CPHYSADDR(EXCITE_OFFS_FPGA) +#define EXCITE_ADDR_FPGA CKSEG1ADDR(EXCITE_OFFS_FPGA) + +#define EXCITE_OFFS_NAND 0x1ffd8000 +#define EXCITE_SIZE_NAND (16 << 10) +#define EXCITE_PHYS_NAND CPHYSADDR(EXCITE_OFFS_NAND) +#define EXCITE_ADDR_NAND CKSEG1ADDR(EXCITE_OFFS_NAND) + +#define EXCITE_OFFS_BOOTROM 0x1f000000 +#define EXCITE_SIZE_BOOTROM (8 << 20) +#define EXCITE_PHYS_BOOTROM CPHYSADDR(EXCITE_OFFS_BOOTROM) +#define EXCITE_ADDR_BOOTROM CKSEG1ADDR(EXCITE_OFFS_BOOTROM) + +/* FPGA address offsets */ +#define EXCITE_FPGA_DPR 0x0104 /* dual-ported ram */ +#define EXCITE_FPGA_SYSCTL 0x0200 /* system control register block */ + +#endif /* __EXCITE_H__ */ diff --git a/include/asm-mips/mach-excite/excite_nandflash.h b/include/asm-mips/mach-excite/excite_nandflash.h new file mode 100644 index 000000000000..c4cf6140622e --- /dev/null +++ b/include/asm-mips/mach-excite/excite_nandflash.h @@ -0,0 +1,7 @@ +#ifndef __EXCITE_NANDFLASH_H__ +#define __EXCITE_NANDFLASH_H__ + +/* Resource names */ +#define EXCITE_NANDFLASH_RESOURCE_REGS "excite_nandflash_regs" + +#endif /* __EXCITE_NANDFLASH_H__ */ diff --git a/include/asm-mips/mach-excite/rm9k_eth.h b/include/asm-mips/mach-excite/rm9k_eth.h new file mode 100644 index 000000000000..94705a46f72e --- /dev/null +++ b/include/asm-mips/mach-excite/rm9k_eth.h @@ -0,0 +1,23 @@ +#if !defined(__RM9K_ETH_H__) +#define __RM9K_ETH_H__ + +#define RM9K_GE_NAME "rm9k_ge" + +/* Resource names */ +#define RM9K_GE_RESOURCE_MAC "rm9k_ge_mac" +#define RM9K_GE_RESOURCE_MSTAT "rm9k_ge_mstat" +#define RM9K_GE_RESOURCE_PKTPROC "rm9k_ge_pktproc" +#define RM9K_GE_RESOURCE_XDMA "rm9k_ge_xdma" +#define RM9K_GE_RESOURCE_FIFO_RX "rm9k_ge_fifo_rx" +#define RM9K_GE_RESOURCE_FIFO_TX "rm9k_ge_fifo_tx" +#define RM9K_GE_RESOURCE_FIFOMEM_RX "rm9k_ge_fifo_memory_rx" +#define RM9K_GE_RESOURCE_FIFOMEM_TX "rm9k_ge_fifo_memory_tx" +#define RM9K_GE_RESOURCE_PHY "rm9k_ge_phy" +#define RM9K_GE_RESOURCE_DMADESC_RX "rm9k_ge_dmadesc_rx" +#define RM9K_GE_RESOURCE_DMADESC_TX "rm9k_ge_dmadesc_tx" +#define RM9K_GE_RESOURCE_IRQ_MAIN "rm9k_ge_irq_main" +#define RM9K_GE_RESOURCE_IRQ_PHY "rm9k_ge_irq_phy" +#define RM9K_GE_RESOURCE_GPI_SLICE "rm9k_ge_gpi_slice" +#define RM9K_GE_RESOURCE_MDIO_CHANNEL "rm9k_ge_mdio_channel" + +#endif /* !defined(__RM9K_ETH_H__) */ diff --git a/include/asm-mips/mach-excite/rm9k_wdt.h b/include/asm-mips/mach-excite/rm9k_wdt.h new file mode 100644 index 000000000000..3fa3c08d2da7 --- /dev/null +++ b/include/asm-mips/mach-excite/rm9k_wdt.h @@ -0,0 +1,12 @@ +#ifndef __RM9K_WDT_H__ +#define __RM9K_WDT_H__ + +/* Device name */ +#define WDT_NAME "wdt_gpi" + +/* Resource names */ +#define WDT_RESOURCE_REGS "excite_watchdog_regs" +#define WDT_RESOURCE_IRQ "excite_watchdog_irq" +#define WDT_RESOURCE_COUNTER "excite_watchdog_counter" + +#endif /* __RM9K_WDT_H__ */ diff --git a/include/asm-mips/mach-excite/rm9k_xicap.h b/include/asm-mips/mach-excite/rm9k_xicap.h new file mode 100644 index 000000000000..009577734a8d --- /dev/null +++ b/include/asm-mips/mach-excite/rm9k_xicap.h @@ -0,0 +1,16 @@ +#ifndef __EXCITE_XICAP_H__ +#define __EXCITE_XICAP_H__ + + +/* Resource names */ +#define XICAP_RESOURCE_FIFO_RX "xicap_fifo_rx" +#define XICAP_RESOURCE_FIFO_TX "xicap_fifo_tx" +#define XICAP_RESOURCE_XDMA "xicap_xdma" +#define XICAP_RESOURCE_DMADESC "xicap_dmadesc" +#define XICAP_RESOURCE_PKTPROC "xicap_pktproc" +#define XICAP_RESOURCE_IRQ "xicap_irq" +#define XICAP_RESOURCE_GPI_SLICE "xicap_gpi_slice" +#define XICAP_RESOURCE_FIFO_BLK "xicap_fifo_blocks" +#define XICAP_RESOURCE_PKT_STREAM "xicap_pkt_stream" + +#endif /* __EXCITE_XICAP_H__ */ diff --git a/include/asm-mips/mach-generic/param.h b/include/asm-mips/mach-generic/param.h deleted file mode 100644 index a0d12f964e4f..000000000000 --- a/include/asm-mips/mach-generic/param.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2003 by Ralf Baechle - */ -#ifndef __ASM_MACH_GENERIC_PARAM_H -#define __ASM_MACH_GENERIC_PARAM_H - -#define HZ 1000 /* Internal kernel timer frequency */ - -#endif /* __ASM_MACH_GENERIC_PARAM_H */ diff --git a/include/asm-mips/mach-ip22/cpu-feature-overrides.h b/include/asm-mips/mach-ip22/cpu-feature-overrides.h index 2a37bedb4053..f7c5dc8a5336 100644 --- a/include/asm-mips/mach-ip22/cpu-feature-overrides.h +++ b/include/asm-mips/mach-ip22/cpu-feature-overrides.h @@ -13,7 +13,7 @@ */ #define cpu_has_tlb 1 #define cpu_has_4kex 1 -#define cpu_has_4kcache 1 +#define cpu_has_4k_cache 1 #define cpu_has_fpu 1 #define cpu_has_32fpr 1 #define cpu_has_counter 1 diff --git a/include/asm-mips/mach-ip27/cpu-feature-overrides.h b/include/asm-mips/mach-ip27/cpu-feature-overrides.h index 2d2f5b91e47f..19c2d135985b 100644 --- a/include/asm-mips/mach-ip27/cpu-feature-overrides.h +++ b/include/asm-mips/mach-ip27/cpu-feature-overrides.h @@ -31,6 +31,9 @@ #define cpu_has_nofpuex 0 #define cpu_has_64bits 1 +#define cpu_has_4kex 1 +#define cpu_has_4k_cache 1 + #define cpu_has_subset_pcaches 1 #define cpu_dcache_line_size() 32 diff --git a/include/asm-mips/mach-ip32/cpu-feature-overrides.h b/include/asm-mips/mach-ip32/cpu-feature-overrides.h index 5312a11098d9..2a3de092bf13 100644 --- a/include/asm-mips/mach-ip32/cpu-feature-overrides.h +++ b/include/asm-mips/mach-ip32/cpu-feature-overrides.h @@ -37,6 +37,8 @@ #define cpu_has_vtag_icache 0 #define cpu_has_ic_fills_f_dc 0 #define cpu_has_dsp 0 +#define cpu_has_4k_cache 1 + #define cpu_has_mips32r1 0 #define cpu_has_mips32r2 0 diff --git a/include/asm-mips/mach-jazz/param.h b/include/asm-mips/mach-jazz/param.h deleted file mode 100644 index 639763a517bc..000000000000 --- a/include/asm-mips/mach-jazz/param.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2003 by Ralf Baechle - */ -#ifndef __ASM_MACH_JAZZ_PARAM_H -#define __ASM_MACH_JAZZ_PARAM_H - -/* - * Jazz is currently using the internal 100Hz timer of the R4030 - */ -#define HZ 100 /* Internal kernel timer frequency */ - -#endif /* __ASM_MACH_JAZZ_PARAM_H */ diff --git a/include/asm-mips/mach-mips/cpu-feature-overrides.h b/include/asm-mips/mach-mips/cpu-feature-overrides.h index 7efbff50fcdd..e960679f54ba 100644 --- a/include/asm-mips/mach-mips/cpu-feature-overrides.h +++ b/include/asm-mips/mach-mips/cpu-feature-overrides.h @@ -16,7 +16,7 @@ #ifdef CONFIG_CPU_MIPS32 #define cpu_has_tlb 1 #define cpu_has_4kex 1 -#define cpu_has_4kcache 1 +#define cpu_has_4k_cache 1 /* #define cpu_has_fpu ? */ /* #define cpu_has_32fpr ? */ #define cpu_has_counter 1 @@ -46,7 +46,7 @@ #ifdef CONFIG_CPU_MIPS64 #define cpu_has_tlb 1 #define cpu_has_4kex 1 -#define cpu_has_4kcache 1 +#define cpu_has_4k_cache 1 /* #define cpu_has_fpu ? */ /* #define cpu_has_32fpr ? */ #define cpu_has_counter 1 diff --git a/include/asm-mips/mach-qemu/param.h b/include/asm-mips/mach-qemu/param.h deleted file mode 100644 index cb30ee490ae6..000000000000 --- a/include/asm-mips/mach-qemu/param.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2005 by Ralf Baechle - */ -#ifndef __ASM_MACH_QEMU_PARAM_H -#define __ASM_MACH_QEMU_PARAM_H - -#define HZ 100 /* Internal kernel timer frequency */ - -#endif /* __ASM_MACH_QEMU_PARAM_H */ diff --git a/include/asm-mips/mach-rm200/cpu-feature-overrides.h b/include/asm-mips/mach-rm200/cpu-feature-overrides.h index 91e7cf5f2bfe..11410ae10d36 100644 --- a/include/asm-mips/mach-rm200/cpu-feature-overrides.h +++ b/include/asm-mips/mach-rm200/cpu-feature-overrides.h @@ -14,7 +14,7 @@ #define cpu_has_tlb 1 #define cpu_has_4kex 1 -#define cpu_has_4kcache 1 +#define cpu_has_4k_cache 1 #define cpu_has_fpu 1 #define cpu_has_32fpr 1 #define cpu_has_counter 1 @@ -35,10 +35,8 @@ #define cpu_has_nofpuex 0 #define cpu_has_64bits 1 -#define cpu_has_subset_pcaches 0 /* No S-cache on R5000 I think ... */ #define cpu_dcache_line_size() 32 #define cpu_icache_line_size() 32 -#define cpu_scache_line_size() 0 /* No S-cache on R5000 I think ... */ #define cpu_has_mips32r1 0 #define cpu_has_mips32r2 0 diff --git a/include/asm-mips/mach-sim/cpu-feature-overrides.h b/include/asm-mips/mach-sim/cpu-feature-overrides.h index f86f2751bc0c..d736bdadb6df 100644 --- a/include/asm-mips/mach-sim/cpu-feature-overrides.h +++ b/include/asm-mips/mach-sim/cpu-feature-overrides.h @@ -15,7 +15,7 @@ #ifdef CONFIG_CPU_MIPS32 #define cpu_has_tlb 1 #define cpu_has_4kex 1 -#define cpu_has_4kcache 1 +#define cpu_has_4k_cache 1 #define cpu_has_fpu 0 /* #define cpu_has_32fpr ? */ #define cpu_has_counter 1 @@ -40,7 +40,7 @@ #ifdef CONFIG_CPU_MIPS64 #define cpu_has_tlb 1 #define cpu_has_4kex 1 -#define cpu_has_4kcache 1 +#define cpu_has_4k_cache 1 /* #define cpu_has_fpu ? */ /* #define cpu_has_32fpr ? */ #define cpu_has_counter 1 diff --git a/include/asm-mips/mach-wrppmc/mach-gt64120.h b/include/asm-mips/mach-wrppmc/mach-gt64120.h new file mode 100644 index 000000000000..ba9205a04582 --- /dev/null +++ b/include/asm-mips/mach-wrppmc/mach-gt64120.h @@ -0,0 +1,84 @@ +/* + * This is a direct copy of the ev96100.h file, with a global + * search and replace. The numbers are the same. + * + * The reason I'm duplicating this is so that the 64120/96100 + * defines won't be confusing in the source code. + */ +#ifndef __ASM_MIPS_GT64120_H +#define __ASM_MIPS_GT64120_H + +/* + * This is the CPU physical memory map of PPMC Board: + * + * 0x00000000-0x03FFFFFF - 64MB SDRAM (SCS[0]#) + * 0x1C000000-0x1C000000 - LED (CS0) + * 0x1C800000-0x1C800007 - UART 16550 port (CS1) + * 0x1F000000-0x1F000000 - MailBox (CS3) + * 0x1FC00000-0x20000000 - 4MB Flash (BOOT CS) + */ + +#define WRPPMC_SDRAM_SCS0_BASE 0x00000000 +#define WRPPMC_SDRAM_SCS0_SIZE 0x04000000 + +#define WRPPMC_UART16550_BASE 0x1C800000 +#define WRPPMC_UART16550_CLOCK 3686400 /* 3.68MHZ */ + +#define WRPPMC_LED_BASE 0x1C000000 +#define WRPPMC_MBOX_BASE 0x1F000000 + +#define WRPPMC_BOOTROM_BASE 0x1FC00000 +#define WRPPMC_BOOTROM_SIZE 0x00400000 /* 4M Flash */ + +#define WRPPMC_MIPS_TIMER_IRQ 7 /* MIPS compare/count timer interrupt */ +#define WRPPMC_UART16550_IRQ 6 +#define WRPPMC_PCI_INTA_IRQ 3 + +/* + * PCI Bus I/O and Memory resources allocation + * + * NOTE: We only have PCI_0 hose interface + */ +#define GT_PCI_MEM_BASE 0x13000000UL +#define GT_PCI_MEM_SIZE 0x02000000UL +#define GT_PCI_IO_BASE 0x11000000UL +#define GT_PCI_IO_SIZE 0x02000000UL +#define GT_ISA_IO_BASE PCI_IO_BASE + +/* + * PCI interrupts will come in on either the INTA or INTD interrups lines, + * which are mapped to the #2 and #5 interrupt pins of the MIPS. On our + * boards, they all either come in on IntD or they all come in on IntA, they + * aren't mixed. There can be numerous PCI interrupts, so we keep a list of the + * "requested" interrupt numbers and go through the list whenever we get an + * IntA/D. + * + * Interrupts < 8 are directly wired to the processor; PCI INTA is 8 and + * INTD is 11. + */ +#define GT_TIMER 4 +#define GT_INTA 2 +#define GT_INTD 5 + +#ifndef __ASSEMBLY__ + +/* + * GT64120 internal register space base address + */ +extern unsigned long gt64120_base; + +#define GT64120_BASE (gt64120_base) + +/* define WRPPMC_EARLY_DEBUG to enable early output something to UART */ +#undef WRPPMC_EARLY_DEBUG + +#ifdef WRPPMC_EARLY_DEBUG +extern void wrppmc_led_on(int mask); +extern void wrppmc_led_off(int mask); +extern void wrppmc_early_printk(const char *fmt, ...); +#else +#define wrppmc_early_printk(fmt, ...) do {} while (0) +#endif /* WRPPMC_EARLY_DEBUG */ + +#endif /* __ASSEMBLY__ */ +#endif /* __ASM_MIPS_GT64120_H */ diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h index 87e95b5e27d4..673977901ed3 100644 --- a/include/asm-mips/mipsregs.h +++ b/include/asm-mips/mipsregs.h @@ -290,7 +290,7 @@ #define ST0_DL (_ULCAST_(1) << 24) /* - * Enable the MIPS DSP ASE + * Enable the MIPS MDMX and DSP ASEs */ #define ST0_MX 0x01000000 @@ -1450,12 +1450,10 @@ static inline void __emt(unsigned int previous) { if ((previous & __EMT_ENABLE)) __asm__ __volatile__( - " .set noreorder \n" " .set mips32r2 \n" " .word 0x41600be1 # emt \n" " ehb \n" - " .set mips0 \n" - " .set reorder \n"); + " .set mips0 \n"); } static inline void __ehb(void) diff --git a/include/asm-mips/mmzone.h b/include/asm-mips/mmzone.h index e132975256b2..dc231c89bef9 100644 --- a/include/asm-mips/mmzone.h +++ b/include/asm-mips/mmzone.h @@ -13,17 +13,6 @@ #define kvaddr_to_nid(kvaddr) pa_to_nid(__pa(kvaddr)) #define pfn_to_nid(pfn) pa_to_nid((pfn) << PAGE_SHIFT) -#define pfn_valid(pfn) \ -({ \ - unsigned long __pfn = (pfn); \ - int __n = pfn_to_nid(__pfn); \ - ((__n >= 0) ? (__pfn < NODE_DATA(__n)->node_start_pfn + \ - NODE_DATA(__n)->node_spanned_pages) : 0);\ -}) - -/* XXX: FIXME -- wli */ -#define kern_addr_valid(addr) (0) - #endif /* CONFIG_DISCONTIGMEM */ #endif /* _ASM_MMZONE_H_ */ diff --git a/include/asm-mips/page.h b/include/asm-mips/page.h index f2b3314fcabc..6b97744f00cd 100644 --- a/include/asm-mips/page.h +++ b/include/asm-mips/page.h @@ -138,9 +138,30 @@ typedef struct { unsigned long pgprot; } pgprot_t; #define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT) +#ifndef CONFIG_SPARSEMEM #ifndef CONFIG_NEED_MULTIPLE_NODES #define pfn_valid(pfn) ((pfn) < max_mapnr) #endif +#endif + +#ifdef CONFIG_FLATMEM + +#define pfn_valid(pfn) ((pfn) < max_mapnr) + +#elif defined(CONFIG_NEED_MULTIPLE_NODES) + +#define pfn_valid(pfn) \ +({ \ + unsigned long __pfn = (pfn); \ + int __n = pfn_to_nid(__pfn); \ + ((__n >= 0) ? (__pfn < NODE_DATA(__n)->node_start_pfn + \ + NODE_DATA(__n)->node_spanned_pages) \ + : 0); \ +}) + +#else +#error Provide a definition of pfn_valid +#endif #define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT) #define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT) diff --git a/include/asm-mips/param.h b/include/asm-mips/param.h index 2bead8273ced..1d9bb8c5ab24 100644 --- a/include/asm-mips/param.h +++ b/include/asm-mips/param.h @@ -11,7 +11,7 @@ #ifdef __KERNEL__ -# include <param.h> /* Internal kernel timer frequency */ +# define HZ CONFIG_HZ /* Internal kernel timer frequency */ # define USER_HZ 100 /* .. some user interfaces are in "ticks" */ # define CLOCKS_PER_SEC (USER_HZ) /* like times() */ #endif diff --git a/include/asm-mips/pci/bridge.h b/include/asm-mips/pci/bridge.h index b4ee995c56e6..0c45e7598f3f 100644 --- a/include/asm-mips/pci/bridge.h +++ b/include/asm-mips/pci/bridge.h @@ -15,6 +15,7 @@ #include <linux/types.h> #include <linux/pci.h> #include <asm/xtalk/xwidget.h> /* generic widget header */ +#include <asm/sn/types.h> /* I/O page size */ @@ -848,4 +849,6 @@ struct bridge_controller { extern void register_bridge_irq(unsigned int irq); extern int request_bridge_irq(struct bridge_controller *bc); +extern struct pci_ops bridge_pci_ops; + #endif /* _ASM_PCI_BRIDGE_H */ diff --git a/include/asm-mips/pgtable-32.h b/include/asm-mips/pgtable-32.h index e1c0e88f03f5..4b26d8528133 100644 --- a/include/asm-mips/pgtable-32.h +++ b/include/asm-mips/pgtable-32.h @@ -176,48 +176,67 @@ pfn_pte(unsigned long pfn, pgprot_t prot) ((swp_entry_t) { ((type) << 10) | ((offset) << 15) }) /* - * Bits 0, 1, 2, 9 and 10 are taken, split up the 27 bits of offset - * into this range: + * Bits 0, 4, 8, and 9 are taken, split up 28 bits of offset into this range: */ -#define PTE_FILE_MAX_BITS 27 +#define PTE_FILE_MAX_BITS 28 -#define pte_to_pgoff(_pte) \ - ((((_pte).pte >> 3) & 0x3f ) + (((_pte).pte >> 11) << 8 )) +#define pte_to_pgoff(_pte) ((((_pte).pte >> 1 ) & 0x07) | \ + (((_pte).pte >> 2 ) & 0x38) | \ + (((_pte).pte >> 10) << 6 )) -#define pgoff_to_pte(off) \ - ((pte_t) { (((off) & 0x3f) << 3) + (((off) >> 8) << 11) + _PAGE_FILE }) +#define pgoff_to_pte(off) ((pte_t) { (((off) & 0x07) << 1 ) | \ + (((off) & 0x38) << 2 ) | \ + (((off) >> 6 ) << 10) | \ + _PAGE_FILE }) #else /* Swap entries must have VALID and GLOBAL bits cleared. */ +#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) +#define __swp_type(x) (((x).val >> 2) & 0x1f) +#define __swp_offset(x) ((x).val >> 7) +#define __swp_entry(type,offset) \ + ((swp_entry_t) { ((type) << 2) | ((offset) << 7) }) +#else #define __swp_type(x) (((x).val >> 8) & 0x1f) -#define __swp_offset(x) ((x).val >> 13) +#define __swp_offset(x) ((x).val >> 13) #define __swp_entry(type,offset) \ - ((swp_entry_t) { ((type) << 8) | ((offset) << 13) }) + ((swp_entry_t) { ((type) << 8) | ((offset) << 13) }) +#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */ +#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) /* - * Bits 0, 1, 2, 7 and 8 are taken, split up the 27 bits of offset - * into this range: + * Bits 0 and 1 of pte_high are taken, use the rest for the page offset... */ -#define PTE_FILE_MAX_BITS 27 +#define PTE_FILE_MAX_BITS 30 -#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) - /* fixme */ -#define pte_to_pgoff(_pte) (((_pte).pte_high >> 6) + ((_pte).pte_high & 0x3f)) -#define pgoff_to_pte(off) \ - ((pte_t){(((off) & 0x3f) + ((off) << 6) + _PAGE_FILE)}) +#define pte_to_pgoff(_pte) ((_pte).pte_high >> 2) +#define pgoff_to_pte(off) ((pte_t) { _PAGE_FILE, (off) << 2 }) #else -#define pte_to_pgoff(_pte) \ - ((((_pte).pte >> 3) & 0x1f ) + (((_pte).pte >> 9) << 6 )) +/* + * Bits 0, 4, 6, and 7 are taken, split up 28 bits of offset into this range: + */ +#define PTE_FILE_MAX_BITS 28 + +#define pte_to_pgoff(_pte) ((((_pte).pte >> 1) & 0x7) | \ + (((_pte).pte >> 2) & 0x8) | \ + (((_pte).pte >> 8) << 4)) -#define pgoff_to_pte(off) \ - ((pte_t) { (((off) & 0x1f) << 3) + (((off) >> 6) << 9) + _PAGE_FILE }) +#define pgoff_to_pte(off) ((pte_t) { (((off) & 0x7) << 1) | \ + (((off) & 0x8) << 2) | \ + (((off) >> 4) << 8) | \ + _PAGE_FILE }) #endif #endif +#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) +#define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_high }) +#define __swp_entry_to_pte(x) ((pte_t) { 0, (x).val }) +#else #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) +#endif #endif /* _ASM_PGTABLE_32_H */ diff --git a/include/asm-mips/pgtable-64.h b/include/asm-mips/pgtable-64.h index 0ae30d56d019..e3db93212eab 100644 --- a/include/asm-mips/pgtable-64.h +++ b/include/asm-mips/pgtable-64.h @@ -223,15 +223,12 @@ static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) /* - * Bits 0, 1, 2, 7 and 8 are taken, split up the 32 bits of offset - * into this range: + * Bits 0, 4, 6, and 7 are taken. Let's leave bits 1, 2, 3, and 5 alone to + * make things easier, and only use the upper 56 bits for the page offset... */ -#define PTE_FILE_MAX_BITS 32 +#define PTE_FILE_MAX_BITS 56 -#define pte_to_pgoff(_pte) \ - ((((_pte).pte >> 3) & 0x1f ) + (((_pte).pte >> 9) << 6 )) - -#define pgoff_to_pte(off) \ - ((pte_t) { (((off) & 0x1f) << 3) + (((off) >> 6) << 9) + _PAGE_FILE }) +#define pte_to_pgoff(_pte) ((_pte).pte >> 8) +#define pgoff_to_pte(off) ((pte_t) { ((off) << 8) | _PAGE_FILE }) #endif /* _ASM_PGTABLE_64_H */ diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h index d02b47933d7f..a36ca1be17f2 100644 --- a/include/asm-mips/pgtable.h +++ b/include/asm-mips/pgtable.h @@ -69,7 +69,15 @@ extern unsigned long zero_page_mask; #define ZERO_PAGE(vaddr) \ (virt_to_page(empty_zero_page + (((unsigned long)(vaddr)) & zero_page_mask))) -#define __HAVE_ARCH_MULTIPLE_ZERO_PAGE +#define __HAVE_ARCH_MOVE_PTE +#define move_pte(pte, prot, old_addr, new_addr) \ +({ \ + pte_t newpte = (pte); \ + if (pte_present(pte) && pfn_valid(pte_pfn(pte)) && \ + pte_page(pte) == ZERO_PAGE(old_addr)) \ + newpte = mk_pte(ZERO_PAGE(new_addr), (prot)); \ + newpte; \ +}) extern void paging_init(void); @@ -81,10 +89,11 @@ extern void paging_init(void); #define pmd_page(pmd) (pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT)) #define pmd_page_kernel(pmd) pmd_val(pmd) -#define pte_none(pte) (!(pte_val(pte) & ~_PAGE_GLOBAL)) -#define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT) - #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) + +#define pte_none(pte) (!(((pte).pte_low | (pte).pte_high) & ~_PAGE_GLOBAL)) +#define pte_present(pte) ((pte).pte_low & _PAGE_PRESENT) + static inline void set_pte(pte_t *ptep, pte_t pte) { ptep->pte_high = pte.pte_high; @@ -92,27 +101,35 @@ static inline void set_pte(pte_t *ptep, pte_t pte) ptep->pte_low = pte.pte_low; //printk("pte_high %x pte_low %x\n", ptep->pte_high, ptep->pte_low); - if (pte_val(pte) & _PAGE_GLOBAL) { + if (pte.pte_low & _PAGE_GLOBAL) { pte_t *buddy = ptep_buddy(ptep); /* * Make sure the buddy is global too (if it's !none, * it better already be global) */ - if (pte_none(*buddy)) - buddy->pte_low |= _PAGE_GLOBAL; + if (pte_none(*buddy)) { + buddy->pte_low |= _PAGE_GLOBAL; + buddy->pte_high |= _PAGE_GLOBAL; + } } } #define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) { + pte_t null = __pte(0); + /* Preserve global status for the pair */ - if (pte_val(*ptep_buddy(ptep)) & _PAGE_GLOBAL) - set_pte_at(mm, addr, ptep, __pte(_PAGE_GLOBAL)); - else - set_pte_at(mm, addr, ptep, __pte(0)); + if (ptep_buddy(ptep)->pte_low & _PAGE_GLOBAL) + null.pte_low = null.pte_high = _PAGE_GLOBAL; + + set_pte_at(mm, addr, ptep, null); } #else + +#define pte_none(pte) (!(pte_val(pte) & ~_PAGE_GLOBAL)) +#define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT) + /* * Certain architectures need to do special things when pte's * within a page table are directly modified. Thus, the following @@ -173,75 +190,76 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; */ static inline int pte_user(pte_t pte) { BUG(); return 0; } #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) -static inline int pte_read(pte_t pte) { return (pte).pte_low & _PAGE_READ; } -static inline int pte_write(pte_t pte) { return (pte).pte_low & _PAGE_WRITE; } -static inline int pte_dirty(pte_t pte) { return (pte).pte_low & _PAGE_MODIFIED; } -static inline int pte_young(pte_t pte) { return (pte).pte_low & _PAGE_ACCESSED; } -static inline int pte_file(pte_t pte) { return (pte).pte_low & _PAGE_FILE; } +static inline int pte_read(pte_t pte) { return pte.pte_low & _PAGE_READ; } +static inline int pte_write(pte_t pte) { return pte.pte_low & _PAGE_WRITE; } +static inline int pte_dirty(pte_t pte) { return pte.pte_low & _PAGE_MODIFIED; } +static inline int pte_young(pte_t pte) { return pte.pte_low & _PAGE_ACCESSED; } +static inline int pte_file(pte_t pte) { return pte.pte_low & _PAGE_FILE; } + static inline pte_t pte_wrprotect(pte_t pte) { - (pte).pte_low &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE); - (pte).pte_high &= ~_PAGE_SILENT_WRITE; + pte.pte_low &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE); + pte.pte_high &= ~_PAGE_SILENT_WRITE; return pte; } static inline pte_t pte_rdprotect(pte_t pte) { - (pte).pte_low &= ~(_PAGE_READ | _PAGE_SILENT_READ); - (pte).pte_high &= ~_PAGE_SILENT_READ; + pte.pte_low &= ~(_PAGE_READ | _PAGE_SILENT_READ); + pte.pte_high &= ~_PAGE_SILENT_READ; return pte; } static inline pte_t pte_mkclean(pte_t pte) { - (pte).pte_low &= ~(_PAGE_MODIFIED|_PAGE_SILENT_WRITE); - (pte).pte_high &= ~_PAGE_SILENT_WRITE; + pte.pte_low &= ~(_PAGE_MODIFIED | _PAGE_SILENT_WRITE); + pte.pte_high &= ~_PAGE_SILENT_WRITE; return pte; } static inline pte_t pte_mkold(pte_t pte) { - (pte).pte_low &= ~(_PAGE_ACCESSED|_PAGE_SILENT_READ); - (pte).pte_high &= ~_PAGE_SILENT_READ; + pte.pte_low &= ~(_PAGE_ACCESSED | _PAGE_SILENT_READ); + pte.pte_high &= ~_PAGE_SILENT_READ; return pte; } static inline pte_t pte_mkwrite(pte_t pte) { - (pte).pte_low |= _PAGE_WRITE; - if ((pte).pte_low & _PAGE_MODIFIED) { - (pte).pte_low |= _PAGE_SILENT_WRITE; - (pte).pte_high |= _PAGE_SILENT_WRITE; + pte.pte_low |= _PAGE_WRITE; + if (pte.pte_low & _PAGE_MODIFIED) { + pte.pte_low |= _PAGE_SILENT_WRITE; + pte.pte_high |= _PAGE_SILENT_WRITE; } return pte; } static inline pte_t pte_mkread(pte_t pte) { - (pte).pte_low |= _PAGE_READ; - if ((pte).pte_low & _PAGE_ACCESSED) { - (pte).pte_low |= _PAGE_SILENT_READ; - (pte).pte_high |= _PAGE_SILENT_READ; + pte.pte_low |= _PAGE_READ; + if (pte.pte_low & _PAGE_ACCESSED) { + pte.pte_low |= _PAGE_SILENT_READ; + pte.pte_high |= _PAGE_SILENT_READ; } return pte; } static inline pte_t pte_mkdirty(pte_t pte) { - (pte).pte_low |= _PAGE_MODIFIED; - if ((pte).pte_low & _PAGE_WRITE) { - (pte).pte_low |= _PAGE_SILENT_WRITE; - (pte).pte_high |= _PAGE_SILENT_WRITE; + pte.pte_low |= _PAGE_MODIFIED; + if (pte.pte_low & _PAGE_WRITE) { + pte.pte_low |= _PAGE_SILENT_WRITE; + pte.pte_high |= _PAGE_SILENT_WRITE; } return pte; } static inline pte_t pte_mkyoung(pte_t pte) { - (pte).pte_low |= _PAGE_ACCESSED; - if ((pte).pte_low & _PAGE_READ) - (pte).pte_low |= _PAGE_SILENT_READ; - (pte).pte_high |= _PAGE_SILENT_READ; + pte.pte_low |= _PAGE_ACCESSED; + if (pte.pte_low & _PAGE_READ) + pte.pte_low |= _PAGE_SILENT_READ; + pte.pte_high |= _PAGE_SILENT_READ; return pte; } #else @@ -334,8 +352,9 @@ static inline pgprot_t pgprot_noncached(pgprot_t _prot) #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) { - pte.pte_low &= _PAGE_CHG_MASK; - pte.pte_low |= pgprot_val(newprot); + pte.pte_low &= _PAGE_CHG_MASK; + pte.pte_high &= ~0x3f; + pte.pte_low |= pgprot_val(newprot); pte.pte_high |= pgprot_val(newprot) & 0x3f; return pte; } @@ -359,9 +378,7 @@ static inline void update_mmu_cache(struct vm_area_struct *vma, __update_cache(vma, address, pte); } -#ifndef CONFIG_NEED_MULTIPLE_NODES #define kern_addr_valid(addr) (1) -#endif #ifdef CONFIG_64BIT_PHYS_ADDR extern int remap_pfn_range(struct vm_area_struct *vma, unsigned long from, unsigned long pfn, unsigned long size, pgprot_t prot); diff --git a/include/asm-mips/processor.h b/include/asm-mips/processor.h index 532df530b4ec..5f80ba71ab92 100644 --- a/include/asm-mips/processor.h +++ b/include/asm-mips/processor.h @@ -70,11 +70,6 @@ extern unsigned int vced_count, vcei_count; typedef __u64 fpureg_t; -struct mips_fpu_hard_struct { - fpureg_t fpr[NUM_FPU_REGS]; - unsigned int fcr31; -}; - /* * It would be nice to add some more fields for emulator statistics, but there * are a number of fixed offsets in offset.h and elsewhere that would have to @@ -82,18 +77,13 @@ struct mips_fpu_hard_struct { * the FPU emulator for now. See asm-mips/fpu_emulator.h. */ -struct mips_fpu_soft_struct { +struct mips_fpu_struct { fpureg_t fpr[NUM_FPU_REGS]; unsigned int fcr31; }; -union mips_fpu_union { - struct mips_fpu_hard_struct hard; - struct mips_fpu_soft_struct soft; -}; - #define INIT_FPU { \ - {{0,},} \ + {0,} \ } #define NUM_DSP_REGS 6 @@ -132,7 +122,7 @@ struct thread_struct { unsigned long cp0_status; /* Saved fpu/fpu emulator stuff. */ - union mips_fpu_union fpu; + struct mips_fpu_struct fpu; #ifdef CONFIG_MIPS_MT_FPAFF /* Emulated instruction count */ unsigned long emulated_fp; diff --git a/include/asm-mips/qemu.h b/include/asm-mips/qemu.h index 905c39585903..531caf44560c 100644 --- a/include/asm-mips/qemu.h +++ b/include/asm-mips/qemu.h @@ -21,4 +21,10 @@ */ #define QEMU_C0_COUNTER_CLOCK 100000000 +/* + * Magic qemu system control location. + */ +#define QEMU_RESTART_REG 0xBFBF0000 +#define QEMU_HALT_REG 0xBFBF0004 + #endif /* __ASM_QEMU_H */ diff --git a/include/asm-mips/rm9k-ocd.h b/include/asm-mips/rm9k-ocd.h new file mode 100644 index 000000000000..b0b80d9ecf96 --- /dev/null +++ b/include/asm-mips/rm9k-ocd.h @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2004 by Basler Vision Technologies AG + * Author: Thomas Koeller <thomas.koeller@baslerweb.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#if !defined(_ASM_RM9K_OCD_H) +#define _ASM_RM9K_OCD_H + +#include <linux/types.h> +#include <linux/spinlock.h> +#include <asm/io.h> + +extern volatile void __iomem * const ocd_base; +extern volatile void __iomem * const titan_base; + +#define ocd_addr(__x__) (ocd_base + (__x__)) +#define titan_addr(__x__) (titan_base + (__x__)) +#define scram_addr(__x__) (scram_base + (__x__)) + +/* OCD register access */ +#define ocd_readl(__offs__) __raw_readl(ocd_addr(__offs__)) +#define ocd_readw(__offs__) __raw_readw(ocd_addr(__offs__)) +#define ocd_readb(__offs__) __raw_readb(ocd_addr(__offs__)) +#define ocd_writel(__val__, __offs__) \ + __raw_writel((__val__), ocd_addr(__offs__)) +#define ocd_writew(__val__, __offs__) \ + __raw_writew((__val__), ocd_addr(__offs__)) +#define ocd_writeb(__val__, __offs__) \ + __raw_writeb((__val__), ocd_addr(__offs__)) + +/* TITAN register access - 32 bit-wide only */ +#define titan_readl(__offs__) __raw_readl(titan_addr(__offs__)) +#define titan_writel(__val__, __offs__) \ + __raw_writel((__val__), titan_addr(__offs__)) + +/* Protect access to shared TITAN registers */ +extern spinlock_t titan_lock; +extern int titan_irqflags; +#define lock_titan_regs() spin_lock_irqsave(&titan_lock, titan_irqflags) +#define unlock_titan_regs() spin_unlock_irqrestore(&titan_lock, titan_irqflags) + +#endif /* !defined(_ASM_RM9K_OCD_H) */ diff --git a/include/asm-mips/sigcontext.h b/include/asm-mips/sigcontext.h index 8edabb0be23f..cefa657dd04a 100644 --- a/include/asm-mips/sigcontext.h +++ b/include/asm-mips/sigcontext.h @@ -55,8 +55,14 @@ struct sigcontext { struct sigcontext { unsigned long sc_regs[32]; unsigned long sc_fpregs[32]; - unsigned long sc_hi[4]; - unsigned long sc_lo[4]; + unsigned long sc_mdhi; + unsigned long sc_hi1; + unsigned long sc_hi2; + unsigned long sc_hi3; + unsigned long sc_mdlo; + unsigned long sc_lo1; + unsigned long sc_lo2; + unsigned long sc_lo3; unsigned long sc_pc; unsigned int sc_fpc_csr; unsigned int sc_used_math; diff --git a/include/asm-mips/smp.h b/include/asm-mips/smp.h index ffcb7a336b17..1608fd71d6f7 100644 --- a/include/asm-mips/smp.h +++ b/include/asm-mips/smp.h @@ -47,7 +47,6 @@ extern struct call_data_struct *call_data; #define SMP_CALL_FUNCTION 0x2 extern cpumask_t phys_cpu_present_map; -extern cpumask_t cpu_online_map; #define cpu_possible_map phys_cpu_present_map extern cpumask_t cpu_callout_map; @@ -85,9 +84,9 @@ extern void prom_init_secondary(void); extern void plat_smp_setup(void); /* - * Called after init_IRQ but before __cpu_up. + * Called in smp_prepare_cpus. */ -extern void prom_prepare_cpus(unsigned int max_cpus); +extern void plat_prepare_cpus(unsigned int max_cpus); /* * Last chance for the board code to finish SMP initialization before diff --git a/include/asm-mips/sn/addrs.h b/include/asm-mips/sn/addrs.h index 3f6891b0c0ea..8fa0af6b68d2 100644 --- a/include/asm-mips/sn/addrs.h +++ b/include/asm-mips/sn/addrs.h @@ -26,13 +26,8 @@ #ifndef __ASSEMBLY__ -#if defined(CONFIG_SGI_IO) /* FIXME */ -#define PS_UINT_CAST (__psunsigned_t) -#define UINT64_CAST (__uint64_t) -#else /* CONFIG_SGI_IO */ #define PS_UINT_CAST (unsigned long) #define UINT64_CAST (unsigned long) -#endif /* CONFIG_SGI_IO */ #define HUBREG_CAST (volatile hubreg_t *) @@ -252,14 +247,6 @@ * for _x. */ -#ifdef _STANDALONE - -/* DO NOT USE THESE DIRECTLY IN THE KERNEL. SEE BELOW. */ -#define LOCAL_HUB(_x) (HUBREG_CAST (IALIAS_BASE + (_x))) -#define REMOTE_HUB(_n, _x) (HUBREG_CAST (NODE_SWIN_BASE(_n, 1) + \ - 0x800000 + (_x))) -#endif /* _STANDALONE */ - /* * WARNING: * When certain Hub chip workaround are defined, it's not sufficient @@ -326,20 +313,6 @@ PHYS_TO_K0(NODE_OFFSET(nasid) | ARCS_SPB_OFFSET) #define ARCS_SPB_SIZE 0x0400 -#ifdef _STANDALONE - -#define ARCS_TVECTOR_OFFSET 0x2800 -#define ARCS_PVECTOR_OFFSET 0x2c00 - -/* - * These addresses are used by the master CPU to install the transfer - * and private vectors. All others use the SPB to find them. - */ -#define TVADDR (NODE_CAC_BASE(get_nasid()) + ARCS_TVECTOR_OFFSET) -#define PVADDR (NODE_CAC_BASE(get_nasid()) + ARCS_PVECTOR_OFFSET) - -#endif /* _STANDALONE */ - #define KLDIR_OFFSET 0x2000 #define KLDIR_ADDR(nasid) \ TO_NODE_UNCAC((nasid), KLDIR_OFFSET) diff --git a/include/asm-mips/sn/sn0/sn0_fru.h b/include/asm-mips/sn/fru.h index 82c6377c275a..b3e3606723b7 100644 --- a/include/asm-mips/sn/sn0/sn0_fru.h +++ b/include/asm-mips/sn/fru.h @@ -6,10 +6,10 @@ * Derived from IRIX <sys/SN/SN0/sn0_fru.h> * * Copyright (C) 1992 - 1997, 1999 Silcon Graphics, Inc. - * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org) + * Copyright (C) 1999, 2006 Ralf Baechle (ralf@linux-mips) */ -#ifndef _ASM_SN_SN0_SN0_FRU_H -#define _ASM_SN_SN0_SN0_FRU_H +#ifndef __ASM_SN_FRU_H +#define __ASM_SN_FRU_H #define MAX_DIMMS 8 /* max # of dimm banks */ #define MAX_PCIDEV 8 /* max # of pci devices on a pci bus */ @@ -41,4 +41,4 @@ typedef struct kf_pci_bus_s { /* confidence level that the pci dev is bad */ } kf_pci_bus_t; -#endif /* _ASM_SN_SN0_SN0_FRU_H */ +#endif /* __ASM_SN_FRU_H */ diff --git a/include/asm-mips/sn/klconfig.h b/include/asm-mips/sn/klconfig.h index 19e0e926be55..52238e65af8e 100644 --- a/include/asm-mips/sn/klconfig.h +++ b/include/asm-mips/sn/klconfig.h @@ -36,7 +36,7 @@ //#include <sys/SN/router.h> // XXX Stolen from <sys/SN/router.h>: #define MAX_ROUTER_PORTS (6) /* Max. number of ports on a router */ -#include <asm/sn/sn0/sn0_fru.h> +#include <asm/sn/fru.h> //#include <sys/graph.h> //#include <sys/xtalk/xbow.h> @@ -53,32 +53,21 @@ #include <asm/sn/agent.h> #include <asm/arc/types.h> #include <asm/arc/hinv.h> -#if defined(CONFIG_SGI_IO) || defined(CONFIG_SGI_IP35) +#if defined(CONFIG_SGI_IP35) // The hack file has to be before vector and after sn0_fru.... #include <asm/hack.h> #include <asm/sn/vector.h> #include <asm/xtalk/xtalk.h> -#endif /* CONFIG_SGI_IO || CONFIG_SGI_IP35 */ +#endif /* CONFIG_SGI_IP35 */ #endif /* CONFIG_SGI_IP27 || CONFIG_SGI_IP35 */ #define KLCFGINFO_MAGIC 0xbeedbabe -#ifdef FRUTEST -typedef u64 klconf_off_t; -#else typedef s32 klconf_off_t; -#endif /* * Some IMPORTANT OFFSETS. These are the offsets on all NODES. */ -#if 0 -#define RAMBASE 0 -#define ARCSSPB_OFF 0x1000 /* shift it to sys/arcs/spb.h */ - -#define OFF_HWGRAPH 0 -#endif - #define MAX_MODULE_ID 255 #define SIZE_PAD 4096 /* 4k padding for structures */ /* @@ -133,15 +122,9 @@ typedef s32 klconf_off_t; typedef struct console_s { -#if defined(CONFIG_SGI_IO) /* FIXME */ - __psunsigned_t uart_base; - __psunsigned_t config_base; - __psunsigned_t memory_base; -#else unsigned long uart_base; unsigned long config_base; unsigned long memory_base; -#endif short baud; short flag; int type; @@ -173,10 +156,6 @@ typedef struct kl_config_hdr { #define KL_CONFIG_HDR(_nasid) ((kl_config_hdr_t *)(KLCONFIG_ADDR(_nasid))) -#if 0 -#define KL_CONFIG_MALLOC_HDR(_nasid) \ - (KL_CONFIG_HDR(_nasid)->ch_malloc_hdr) -#endif #define KL_CONFIG_INFO_OFFSET(_nasid) \ (KL_CONFIG_HDR(_nasid)->ch_board_info) #define KL_CONFIG_INFO_SET_OFFSET(_nasid, _off) \ @@ -196,23 +175,13 @@ typedef struct kl_config_hdr { /* --- New Macros for the changed kl_config_hdr_t structure --- */ -#if defined(CONFIG_SGI_IO) -#define PTR_CH_MALLOC_HDR(_k) ((klc_malloc_hdr_t *)\ - ((__psunsigned_t)_k + (_k->ch_malloc_hdr_off))) -#else #define PTR_CH_MALLOC_HDR(_k) ((klc_malloc_hdr_t *)\ (unsigned long)_k + (_k->ch_malloc_hdr_off))) -#endif #define KL_CONFIG_CH_MALLOC_HDR(_n) PTR_CH_MALLOC_HDR(KL_CONFIG_HDR(_n)) -#if defined(CONFIG_SGI_IO) -#define PTR_CH_CONS_INFO(_k) ((console_t *)\ - ((__psunsigned_t)_k + (_k->ch_cons_off))) -#else #define PTR_CH_CONS_INFO(_k) ((console_t *)\ ((unsigned long)_k + (_k->ch_cons_off))) -#endif #define KL_CONFIG_CH_CONS_INFO(_n) PTR_CH_CONS_INFO(KL_CONFIG_HDR(_n)) @@ -489,14 +458,6 @@ typedef struct lboard_s { #define KLCF_NUM_COMPS(_brd) ((_brd)->brd_numcompts) #define KLCF_MODULE_ID(_brd) ((_brd)->brd_module) -#ifdef FRUTEST - -#define KLCF_NEXT(_brd) ((_brd)->brd_next ? (lboard_t *)((_brd)->brd_next): NULL) -#define KLCF_COMP(_brd, _ndx) (klinfo_t *)((_brd)->brd_compts[(_ndx)]) -#define KLCF_COMP_ERROR(_brd, _comp) (_brd = _brd , (_comp)->errinfo) - -#else - #define KLCF_NEXT(_brd) \ ((_brd)->brd_next ? \ (lboard_t *)(NODE_OFFSET_TO_K1(NASID_GET(_brd), (_brd)->brd_next)):\ @@ -508,8 +469,6 @@ typedef struct lboard_s { #define KLCF_COMP_ERROR(_brd, _comp) \ (NODE_OFFSET_TO_K1(NASID_GET(_brd), (_comp)->errinfo)) -#endif - #define KLCF_COMP_TYPE(_comp) ((_comp)->struct_type) #define KLCF_BRIDGE_W_ID(_comp) ((_comp)->physid) /* Widget ID */ @@ -630,18 +589,6 @@ typedef struct klport_s { klconf_off_t port_offset; } klport_t; -#if 0 -/* - * This is very similar to the klport_s but instead of having a componant - * offset it has a board offset. - */ -typedef struct klxbow_port_s { - nasid_t port_nasid; - unsigned char port_flag; - klconf_off_t board_offset; -} klxbow_port_t; -#endif - typedef struct klcpu_s { /* CPU */ klinfo_t cpu_info; unsigned short cpu_prid; /* Processor PRID value */ @@ -944,36 +891,6 @@ extern klcpu_t *nasid_slice_to_cpuinfo(nasid_t, int); extern lboard_t *find_lboard_class(lboard_t *start, unsigned char brd_class); -#if defined(CONFIG_SGI_IO) -extern xwidgetnum_t nodevertex_widgetnum_get(vertex_hdl_t node_vtx); -extern vertex_hdl_t nodevertex_xbow_peer_get(vertex_hdl_t node_vtx); -extern lboard_t *find_gfxpipe(int pipenum); -extern void setup_gfxpipe_link(vertex_hdl_t vhdl,int pipenum); -extern lboard_t *find_lboard_module_class(lboard_t *start, moduleid_t mod, - unsigned char brd_class); -extern lboard_t *find_nic_lboard(lboard_t *, nic_t); -extern lboard_t *find_nic_type_lboard(nasid_t, unsigned char, nic_t); -extern lboard_t *find_lboard_modslot(lboard_t *start, moduleid_t mod, slotid_t slot); -extern lboard_t *find_lboard_module(lboard_t *start, moduleid_t mod); -extern lboard_t *get_board_name(nasid_t nasid, moduleid_t mod, slotid_t slot, char *name); -extern int config_find_nic_router(nasid_t, nic_t, lboard_t **, klrou_t**); -extern int config_find_nic_hub(nasid_t, nic_t, lboard_t **, klhub_t**); -extern int config_find_xbow(nasid_t, lboard_t **, klxbow_t**); -extern klcpu_t *get_cpuinfo(cpuid_t cpu); -extern int update_klcfg_cpuinfo(nasid_t, int); -extern void board_to_path(lboard_t *brd, char *path); -extern moduleid_t get_module_id(nasid_t nasid); -extern void nic_name_convert(char *old_name, char *new_name); -extern int module_brds(nasid_t nasid, lboard_t **module_brds, int n); -extern lboard_t *brd_from_key(ulong_t key); -extern void device_component_canonical_name_get(lboard_t *,klinfo_t *, - char *); -extern int board_serial_number_get(lboard_t *,char *); -extern int is_master_baseio(nasid_t,moduleid_t,slotid_t); -extern nasid_t get_actual_nasid(lboard_t *brd) ; -extern net_vec_t klcfg_discover_route(lboard_t *, lboard_t *, int); -#else /* CONFIG_SGI_IO */ extern klcpu_t *sn_get_cpuinfo(cpuid_t cpu); -#endif /* CONFIG_SGI_IO */ #endif /* _ASM_SN_KLCONFIG_H */ diff --git a/include/asm-mips/sn/kldir.h b/include/asm-mips/sn/kldir.h index e3e231f0b79d..0573cbffc104 100644 --- a/include/asm-mips/sn/kldir.h +++ b/include/asm-mips/sn/kldir.h @@ -12,10 +12,6 @@ #define _ASM_SN_KLDIR_H -#if defined(CONFIG_SGI_IO) -#include <asm/hack.h> -#endif - /* * The kldir memory area resides at a fixed place in each node's memory and * provides pointers to most other IP27 memory areas. This allows us to @@ -135,8 +131,6 @@ #define KLDIR_OFF_STRIDE 0x28 #endif /* __ASSEMBLY__ */ -#if !defined(CONFIG_SGI_IO) - /* * This is defined here because IP27_SYMMON_STK_SIZE must be at least what * we define here. Since it's set up in the prom. We can't redefine it later @@ -146,7 +140,7 @@ */ #define SYMMON_STACK_SIZE 0x8000 -#if defined (PROM) || defined (SABLE) +#if defined (PROM) /* * These defines are prom version dependent. No code other than the IP27 @@ -183,7 +177,7 @@ #define IP27_FREEMEM_COUNT 1 #define IP27_FREEMEM_STRIDE 0 -#endif /* PROM || SABLE*/ +#endif /* PROM */ /* * There will be only one of these in a partition so the IO6 must set it up. */ @@ -206,17 +200,11 @@ #define KLDIR_ENT_SIZE 0x40 #define KLDIR_MAX_ENTRIES (0x400 / 0x40) -#endif /* !CONFIG_SGI_IO */ - #ifndef __ASSEMBLY__ typedef struct kldir_ent_s { u64 magic; /* Indicates validity of entry */ off_t offset; /* Offset from start of node space */ -#if defined(CONFIG_SGI_IO) /* FIXME */ - __psunsigned_t pointer; /* Pointer to area in some cases */ -#else unsigned long pointer; /* Pointer to area in some cases */ -#endif size_t size; /* Size in bytes */ u64 count; /* Repeat count if array, 1 if not */ size_t stride; /* Stride if array, 0 if not */ @@ -226,22 +214,4 @@ typedef struct kldir_ent_s { } kldir_ent_t; #endif /* !__ASSEMBLY__ */ -#if defined(CONFIG_SGI_IO) - -#define KLDIR_ENT_SIZE 0x40 -#define KLDIR_MAX_ENTRIES (0x400 / 0x40) - -/* - * The actual offsets of each memory area are machine-dependent - */ -#ifdef CONFIG_SGI_IP27 -// Not yet #include <asm/sn/sn0/kldir.h> -#elif defined(CONFIG_SGI_IP35) -#include <asm/sn/sn1/kldir.h> -#else -#error "kldir.h is currently defined for IP27 and IP35 platforms only" -#endif - -#endif /* CONFIG_SGI_IO */ - #endif /* _ASM_SN_KLDIR_H */ diff --git a/include/asm-mips/sn/sn0/addrs.h b/include/asm-mips/sn/sn0/addrs.h index c0905c1ac938..9e8cc52910f6 100644 --- a/include/asm-mips/sn/sn0/addrs.h +++ b/include/asm-mips/sn/sn0/addrs.h @@ -48,7 +48,7 @@ * so for now we just use defines bracketed by an ifdef. */ -#ifdef CONFIG_SGI_SN0_N_MODE +#ifdef CONFIG_SGI_SN_N_MODE #define NODE_SIZE_BITS 31 #define BWIN_SIZE_BITS 28 @@ -62,7 +62,7 @@ #define BDDIR_UPPER_MASK (UINT64_CAST 0x7ffff << 10) #define BDECC_UPPER_MASK (UINT64_CAST 0x3ffffff << 3) -#else /* !defined(CONFIG_SGI_SN0_N_MODE), assume that M-mode is desired */ +#else /* !defined(CONFIG_SGI_SN_N_MODE), assume that M-mode is desired */ #define NODE_SIZE_BITS 32 #define BWIN_SIZE_BITS 29 @@ -76,7 +76,7 @@ #define BDDIR_UPPER_MASK (UINT64_CAST 0xfffff << 10) #define BDECC_UPPER_MASK (UINT64_CAST 0x7ffffff << 3) -#endif /* !defined(CONFIG_SGI_SN0_N_MODE) */ +#endif /* !defined(CONFIG_SGI_SN_N_MODE) */ #define NODE_ADDRSPACE_SIZE (UINT64_CAST 1 << NODE_SIZE_BITS) @@ -84,15 +84,15 @@ #define NASID_GET(_pa) (int) ((UINT64_CAST (_pa) >> \ NASID_SHFT) & NASID_BITMASK) -#if !defined(__ASSEMBLY__) && !defined(_STANDALONE) +#if !defined(__ASSEMBLY__) #define NODE_SWIN_BASE(nasid, widget) \ ((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN) \ : RAW_NODE_SWIN_BASE(nasid, widget)) -#else /* __ASSEMBLY__ || _STANDALONE */ +#else /* __ASSEMBLY__ */ #define NODE_SWIN_BASE(nasid, widget) \ (NODE_IO_BASE(nasid) + (UINT64_CAST (widget) << SWIN_SIZE_BITS)) -#endif /* __ASSEMBLY__ || _STANDALONE */ +#endif /* __ASSEMBLY__ */ /* * The following definitions pertain to the IO special address @@ -142,12 +142,7 @@ #define SN0_WIDGET_BASE(_nasid, _wid) (NODE_SWIN_BASE((_nasid), (_wid))) /* Turn on sable logging for the processors whose bits are set. */ -#ifdef SABLE -#define SABLE_LOG_TRIGGER(_map) \ - *((volatile hubreg_t *)(IO_BASE + 0x17ffff0)) = (_map) -#else #define SABLE_LOG_TRIGGER(_map) -#endif /* SABLE */ #ifndef __ASSEMBLY__ #define KERN_NMI_ADDR(nasid, slice) \ @@ -280,76 +275,6 @@ #define _ARCSPROM -#ifdef _STANDALONE - -/* - * The PROM needs to pass the device base address and the - * device pci cfg space address to the device drivers during - * install. The COMPONENT->Key field is used for this purpose. - * Macros needed by SN0 device drivers to convert the - * COMPONENT->Key field to the respective base address. - * Key field looks as follows: - * - * +----------------------------------------------------+ - * |devnasid | widget |pciid |hubwidid|hstnasid | adap | - * | 2 | 1 | 1 | 1 | 2 | 1 | - * +----------------------------------------------------+ - * | | | | | | | - * 64 48 40 32 24 8 0 - * - * These are used by standalone drivers till the io infrastructure - * is in place. - */ - -#ifndef __ASSEMBLY__ - -#define uchar unsigned char - -#define KEY_DEVNASID_SHFT 48 -#define KEY_WIDID_SHFT 40 -#define KEY_PCIID_SHFT 32 -#define KEY_HUBWID_SHFT 24 -#define KEY_HSTNASID_SHFT 8 - -#define MK_SN0_KEY(nasid, widid, pciid) \ - ((((__psunsigned_t)nasid)<< KEY_DEVNASID_SHFT |\ - ((__psunsigned_t)widid) << KEY_WIDID_SHFT) |\ - ((__psunsigned_t)pciid) << KEY_PCIID_SHFT) - -#define ADD_HUBWID_KEY(key,hubwid)\ - (key|=((__psunsigned_t)hubwid << KEY_HUBWID_SHFT)) - -#define ADD_HSTNASID_KEY(key,hstnasid)\ - (key|=((__psunsigned_t)hstnasid << KEY_HSTNASID_SHFT)) - -#define GET_DEVNASID_FROM_KEY(key) ((short)(key >> KEY_DEVNASID_SHFT)) -#define GET_WIDID_FROM_KEY(key) ((uchar)(key >> KEY_WIDID_SHFT)) -#define GET_PCIID_FROM_KEY(key) ((uchar)(key >> KEY_PCIID_SHFT)) -#define GET_HUBWID_FROM_KEY(key) ((uchar)(key >> KEY_HUBWID_SHFT)) -#define GET_HSTNASID_FROM_KEY(key) ((short)(key >> KEY_HSTNASID_SHFT)) - -#define PCI_64_TARGID_SHFT 60 - -#define GET_PCIBASE_FROM_KEY(key) (NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\ - GET_WIDID_FROM_KEY(key))\ - | BRIDGE_DEVIO(GET_PCIID_FROM_KEY(key))) - -#define GET_PCICFGBASE_FROM_KEY(key) \ - (NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\ - GET_WIDID_FROM_KEY(key))\ - | BRIDGE_TYPE0_CFG_DEV(GET_PCIID_FROM_KEY(key))) - -#define GET_WIDBASE_FROM_KEY(key) \ - (NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\ - GET_WIDID_FROM_KEY(key))) - -#define PUT_INSTALL_STATUS(c,s) c->Revision = s -#define GET_INSTALL_STATUS(c) c->Revision - -#endif /* !__ASSEMBLY__ */ - -#endif /* _STANDALONE */ - #if defined (HUB_ERR_STS_WAR) #define ERR_STS_WAR_REGISTER IIO_IIBUSERR diff --git a/include/asm-mips/sn/sn0/arch.h b/include/asm-mips/sn/sn0/arch.h index 7a221666c58e..f734f2007f24 100644 --- a/include/asm-mips/sn/sn0/arch.h +++ b/include/asm-mips/sn/sn0/arch.h @@ -12,8 +12,6 @@ #define _ASM_SN_SN0_ARCH_H -#ifndef SABLE - #ifndef SN0XXL /* 128 cpu SMP max */ /* * This is the maximum number of nodes that can be part of a kernel. @@ -53,25 +51,16 @@ */ #define MAX_PARTITIONS MAX_REGIONS - -#else - -#define MAX_COMPACT_NODES 4 -#define MAX_NASIDS 4 -#define MAXCPUS 8 - -#endif - #define NASID_MASK_BYTES ((MAX_NASIDS + 7) / 8) /* * Slot constants for SN0 */ -#ifdef CONFIG_SGI_SN0_N_MODE +#ifdef CONFIG_SGI_SN_N_MODE #define MAX_MEM_SLOTS 16 /* max slots per node */ -#else /* !CONFIG_SGI_SN0_N_MODE, assume M_MODE */ +#else /* !CONFIG_SGI_SN_N_MODE, assume CONFIG_SGI_SN_M_MODE */ #define MAX_MEM_SLOTS 32 /* max slots per node */ -#endif /* defined(N_MODE) */ +#endif /* CONFIG_SGI_SN_M_MODE */ #define SLOT_SHIFT (27) #define SLOT_MIN_MEM_SIZE (32*1024*1024) diff --git a/include/asm-mips/sn/sn0/hub.h b/include/asm-mips/sn/sn0/hub.h index f5dbba6f4610..3e228f8e7969 100644 --- a/include/asm-mips/sn/sn0/hub.h +++ b/include/asm-mips/sn/sn0/hub.h @@ -31,10 +31,6 @@ #include <asm/sn/sn0/hubni.h> //#include <asm/sn/sn0/hubcore.h> -#ifdef SABLE -#define IP27_NO_HUBUART_INT 1 -#endif - /* Translation of uncached attributes */ #define UATTR_HSPEC 0 #define UATTR_IO 1 diff --git a/include/asm-mips/sn/sn0/hubio.h b/include/asm-mips/sn/sn0/hubio.h index f314da21b970..ef91b3363554 100644 --- a/include/asm-mips/sn/sn0/hubio.h +++ b/include/asm-mips/sn/sn0/hubio.h @@ -486,22 +486,6 @@ typedef union h1_icrba_u { #define ICRBN_A_CERR_SHFT 54 #define ICRBN_A_ERR_MASK 0x3ff -#if 0 /* Disabled, this causes namespace polution and break allmodconfig */ -/* - * Easy access macros. - */ -#define a_error icrba_fields_s.error -#define a_ecode icrba_fields_s.ecode -#define a_lnetuce icrba_fields_s.lnetuce -#define a_mark icrba_fields_s.mark -#define a_xerr icrba_fields_s.xerr -#define a_sidn icrba_fields_s.sidn -#define a_tnum icrba_fields_s.tnum -#define a_addr icrba_fields_s.addr -#define a_valid icrba_fields_s.valid -#define a_iow icrba_fields_s.iow -#endif - #endif /* !__ASSEMBLY__ */ #define IIO_ICRB_ADDR_SHFT 2 /* Shift to get proper address */ diff --git a/include/asm-mips/sn/sn0/hubmd.h b/include/asm-mips/sn/sn0/hubmd.h index f01000241884..14c225d80664 100644 --- a/include/asm-mips/sn/sn0/hubmd.h +++ b/include/asm-mips/sn/sn0/hubmd.h @@ -91,7 +91,7 @@ #define MD_UREG1_14 0x2200f0 /* uController/UART 1 register */ #define MD_UREG1_15 0x2200f8 /* uController/UART 1 register */ -#ifdef CONFIG_SGI_SN0_N_MODE +#ifdef CONFIG_SGI_SN_N_MODE #define MD_MEM_BANKS 4 /* 4 banks of memory max in N mode */ #else #define MD_MEM_BANKS 8 /* 8 banks of memory max in M mode */ diff --git a/include/asm-mips/sn/sn0/hubpi.h b/include/asm-mips/sn/sn0/hubpi.h index 355bba8552e3..e39f5f9da040 100644 --- a/include/asm-mips/sn/sn0/hubpi.h +++ b/include/asm-mips/sn/sn0/hubpi.h @@ -398,24 +398,6 @@ typedef u64 rtc_time_t; /* PI_RT_FILTER_CTRL mask and shift definitions */ -#if 0 -/* - * XXX - This register's definition has changed, but it's only implemented - * in Hub 2. - */ -#define PRFC_DROP_COUNT_SHFT 27 -#define PRFC_DROP_COUNT_MASK (UINT64_CAST 0x3ff << 27) -#define PRFC_DROP_CTR_SHFT 18 -#define PRFC_DROP_CTR_MASK (UINT64_CAST 0x1ff << 18) -#define PRFC_MASK_ENABLE_SHFT 10 -#define PRFC_MASK_ENABLE_MASK (UINT64_CAST 0x7f << 10) -#define PRFC_MASK_CTR_SHFT 2 -#define PRFC_MASK_CTR_MASK (UINT64_CAST 0xff << 2) -#define PRFC_OFFSET_SHFT 0 -#define PRFC_OFFSET_MASK (UINT64_CAST 3) -#endif /* 0 */ - - /* * Bits for NACK_CNT_A/B and NACK_CMP */ diff --git a/include/asm-mips/sn/sn0/ip27.h b/include/asm-mips/sn/sn0/ip27.h index ade0e974dd78..3c97e0855c8d 100644 --- a/include/asm-mips/sn/sn0/ip27.h +++ b/include/asm-mips/sn/sn0/ip27.h @@ -6,7 +6,7 @@ * Derived from IRIX <sys/SN/SN0/IP27.h>. * * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc. - * Copyright (C) 1999 by Ralf Baechle + * Copyright (C) 1999, 2006 by Ralf Baechle */ #ifndef _ASM_SN_SN0_IP27_H #define _ASM_SN_SN0_IP27_H @@ -82,11 +82,4 @@ #define SEND_NMI(_nasid, _slice) \ REMOTE_HUB_S((_nasid), (PI_NMI_A + ((_slice) * PI_NMI_OFFSET)), 1) -/* Sanity hazzard ... Below all the Origin hacks are following. */ - -#define SN00_BRIDGE 0x9200000008000000 -#define SN00I_BRIDGE0 0x920000000b000000 -#define SN00I_BRIDGE1 0x920000000e000000 -#define SN00I_BRIDGE2 0x920000000f000000 - #endif /* _ASM_SN_SN0_IP27_H */ diff --git a/include/asm-mips/sni.h b/include/asm-mips/sni.h index b3bc698dfdee..b9ba54d0dd35 100644 --- a/include/asm-mips/sni.h +++ b/include/asm-mips/sni.h @@ -15,9 +15,6 @@ /* * ASIC PCI registers for little endian configuration. */ -#ifndef __MIPSEL__ -#error "Fix me for big endian" -#endif #define PCIMT_UCONF 0xbfff0000 #define PCIMT_IOADTIMEOUT2 0xbfff0008 #define PCIMT_IOMEMCONF 0xbfff0010 @@ -51,9 +48,9 @@ #define PCIMT_PCI_CONF 0xbfff0100 /* - * Data port for the PCI bus. + * Data port for the PCI bus in IO space */ -#define PCIMT_CONFIG_DATA 0xb4000cfc +#define PCIMT_CONFIG_DATA 0x0cfc /* * Board specific registers diff --git a/include/asm-mips/sparsemem.h b/include/asm-mips/sparsemem.h new file mode 100644 index 000000000000..795ac6c23203 --- /dev/null +++ b/include/asm-mips/sparsemem.h @@ -0,0 +1,14 @@ +#ifndef _MIPS_SPARSEMEM_H +#define _MIPS_SPARSEMEM_H +#ifdef CONFIG_SPARSEMEM + +/* + * SECTION_SIZE_BITS 2^N: how big each section will be + * MAX_PHYSMEM_BITS 2^N: how much memory we can have in that space + */ +#define SECTION_SIZE_BITS 28 +#define MAX_PHYSMEM_BITS 35 + +#endif /* CONFIG_SPARSEMEM */ +#endif /* _MIPS_SPARSEMEM_H */ + diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h index 9844f0c2dfee..3ac146c019c9 100644 --- a/include/asm-mips/war.h +++ b/include/asm-mips/war.h @@ -171,7 +171,8 @@ * On the RM9000 there is a problem which makes the CreateDirtyExclusive * cache operation unusable on SMP systems. */ -#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_PMC_YOSEMITE) +#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_PMC_YOSEMITE) || \ + defined(CONFIG_BASLER_EXCITE) #define RM9000_CDEX_SMP_WAR 1 #endif @@ -181,7 +182,7 @@ * being fetched may case spurious exceptions. */ #if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_MOMENCO_OCELOT_3) || \ - defined(CONFIG_PMC_YOSEMITE) + defined(CONFIG_PMC_YOSEMITE) || defined(CONFIG_BASLER_EXCITE) #define ICACHE_REFILLS_WORKAROUND_WAR 1 #endif diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h index 9fcf0162d859..f6265c2a0dd2 100644 --- a/include/asm-powerpc/cputable.h +++ b/include/asm-powerpc/cputable.h @@ -329,7 +329,7 @@ extern void do_cpu_ftr_fixups(unsigned long offset); #define CPU_FTRS_CELL (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \ CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ - CPU_FTR_CTRL | CPU_FTR_PAUSE_ZERO) + CPU_FTR_CTRL | CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE) #define CPU_FTRS_COMPATIBLE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2) #endif diff --git a/include/asm-powerpc/termbits.h b/include/asm-powerpc/termbits.h index ebf6055481dc..6d533b07aaf5 100644 --- a/include/asm-powerpc/termbits.h +++ b/include/asm-powerpc/termbits.h @@ -153,6 +153,7 @@ struct termios { #define HUPCL 00040000 #define CLOCAL 00100000 +#define CMSPAR 010000000000 /* mark or space (stick) parity */ #define CRTSCTS 020000000000 /* flow control */ /* c_lflag bits */ diff --git a/include/asm-s390/futex.h b/include/asm-s390/futex.h index 40c25e166a9b..1802775568b9 100644 --- a/include/asm-s390/futex.h +++ b/include/asm-s390/futex.h @@ -11,23 +11,24 @@ #define __futex_atomic_fixup \ ".section __ex_table,\"a\"\n" \ " .align 4\n" \ - " .long 0b,2b,1b,2b\n" \ + " .long 0b,4b,2b,4b,3b,4b\n" \ ".previous" #else /* __s390x__ */ #define __futex_atomic_fixup \ ".section __ex_table,\"a\"\n" \ " .align 8\n" \ - " .quad 0b,2b,1b,2b\n" \ + " .quad 0b,4b,2b,4b,3b,4b\n" \ ".previous" #endif /* __s390x__ */ #define __futex_atomic_op(insn, ret, oldval, newval, uaddr, oparg) \ - asm volatile(" l %1,0(%6)\n" \ - "0: " insn \ - " cs %1,%2,0(%6)\n" \ - "1: jl 0b\n" \ + asm volatile(" sacf 256\n" \ + "0: l %1,0(%6)\n" \ + "1: " insn \ + "2: cs %1,%2,0(%6)\n" \ + "3: jl 1b\n" \ " lhi %0,0\n" \ - "2:\n" \ + "4: sacf 0\n" \ __futex_atomic_fixup \ : "=d" (ret), "=&d" (oldval), "=&d" (newval), \ "=m" (*uaddr) \ diff --git a/include/asm-s390/lowcore.h b/include/asm-s390/lowcore.h index e17d181b98a9..596c8b172104 100644 --- a/include/asm-s390/lowcore.h +++ b/include/asm-s390/lowcore.h @@ -98,8 +98,8 @@ #define __LC_KERNEL_ASCE 0xD58 #define __LC_USER_ASCE 0xD60 #define __LC_PANIC_STACK 0xD68 -#define __LC_CPUID 0xD90 -#define __LC_CPUADDR 0xD98 +#define __LC_CPUID 0xD80 +#define __LC_CPUADDR 0xD88 #define __LC_IPLDEV 0xDB8 #define __LC_JIFFY_TIMER 0xDC0 #define __LC_CURRENT 0xDD8 diff --git a/include/asm-sparc64/pgtable.h b/include/asm-sparc64/pgtable.h index 72f9a524dc67..4e218814bb3c 100644 --- a/include/asm-sparc64/pgtable.h +++ b/include/asm-sparc64/pgtable.h @@ -688,6 +688,23 @@ static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *p #define pte_clear(mm,addr,ptep) \ set_pte_at((mm), (addr), (ptep), __pte(0UL)) +#ifdef DCACHE_ALIASING_POSSIBLE +#define __HAVE_ARCH_MOVE_PTE +#define move_pte(pte, prot, old_addr, new_addr) \ +({ \ + pte_t newpte = (pte); \ + if (tlb_type != hypervisor && pte_present(pte)) { \ + unsigned long this_pfn = pte_pfn(pte); \ + \ + if (pfn_valid(this_pfn) && \ + (((old_addr) ^ (new_addr)) & (1 << 13))) \ + flush_dcache_page_all(current->mm, \ + pfn_to_page(this_pfn)); \ + } \ + newpte; \ +}) +#endif + extern pgd_t swapper_pg_dir[2048]; extern pmd_t swapper_low_pmd_dir[2048]; diff --git a/include/asm-um/irqflags.h b/include/asm-um/irqflags.h new file mode 100644 index 000000000000..659b9abdfdba --- /dev/null +++ b/include/asm-um/irqflags.h @@ -0,0 +1,6 @@ +#ifndef __UM_IRQFLAGS_H +#define __UM_IRQFLAGS_H + +/* Empty for now */ + +#endif diff --git a/include/asm-um/uaccess.h b/include/asm-um/uaccess.h index bea5a015f667..16c734af9193 100644 --- a/include/asm-um/uaccess.h +++ b/include/asm-um/uaccess.h @@ -41,11 +41,11 @@ #define __get_user(x, ptr) \ ({ \ - const __typeof__(ptr) __private_ptr = ptr; \ + const __typeof__(*(ptr)) __user *__private_ptr = (ptr); \ __typeof__(x) __private_val; \ int __private_ret = -EFAULT; \ (x) = (__typeof__(*(__private_ptr)))0; \ - if (__copy_from_user((void *) &__private_val, (__private_ptr), \ + if (__copy_from_user((__force void *)&__private_val, (__private_ptr),\ sizeof(*(__private_ptr))) == 0) { \ (x) = (__typeof__(*(__private_ptr))) __private_val; \ __private_ret = 0; \ @@ -62,7 +62,7 @@ #define __put_user(x, ptr) \ ({ \ - __typeof__(ptr) __private_ptr = ptr; \ + __typeof__(*(ptr)) __user *__private_ptr = ptr; \ __typeof__(*(__private_ptr)) __private_val; \ int __private_ret = -EFAULT; \ __private_val = (__typeof__(*(__private_ptr))) (x); \ diff --git a/include/asm-x86_64/elf.h b/include/asm-x86_64/elf.h index c98633af07d2..b4f8f4a41a6e 100644 --- a/include/asm-x86_64/elf.h +++ b/include/asm-x86_64/elf.h @@ -159,7 +159,7 @@ extern int dump_task_fpu (struct task_struct *, elf_fpregset_t *); #define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) dump_task_fpu(tsk, elf_fpregs) /* 1GB for 64bit, 8MB for 32bit */ -#define STACK_RND_MASK (is_compat_task() ? 0x7ff : 0x3fffff) +#define STACK_RND_MASK (test_thread_flag(TIF_IA32) ? 0x7ff : 0x3fffff) #endif diff --git a/include/linux/console.h b/include/linux/console.h index 721371382ae5..08734e660d41 100644 --- a/include/linux/console.h +++ b/include/linux/console.h @@ -117,6 +117,10 @@ extern void console_stop(struct console *); extern void console_start(struct console *); extern int is_console_locked(void); +/* Suspend and resume console messages over PM events */ +extern void suspend_console(void); +extern void resume_console(void); + /* Some debug stub to catch some of the obvious races in the VT code */ #if 1 #define WARN_CONSOLE_UNLOCKED() WARN_ON(!is_console_locked() && !oops_in_progress) diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h new file mode 100644 index 000000000000..78b236ca04f8 --- /dev/null +++ b/include/linux/dmaengine.h @@ -0,0 +1,359 @@ +/* + * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., 59 + * Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * The full GNU General Public License is included in this distribution in the + * file called COPYING. + */ +#ifndef DMAENGINE_H +#define DMAENGINE_H +#include <linux/config.h> +#ifdef CONFIG_DMA_ENGINE + +#include <linux/device.h> +#include <linux/uio.h> +#include <linux/kref.h> +#include <linux/completion.h> +#include <linux/rcupdate.h> + +/** + * enum dma_event - resource PNP/power managment events + * @DMA_RESOURCE_SUSPEND: DMA device going into low power state + * @DMA_RESOURCE_RESUME: DMA device returning to full power + * @DMA_RESOURCE_ADDED: DMA device added to the system + * @DMA_RESOURCE_REMOVED: DMA device removed from the system + */ +enum dma_event { + DMA_RESOURCE_SUSPEND, + DMA_RESOURCE_RESUME, + DMA_RESOURCE_ADDED, + DMA_RESOURCE_REMOVED, +}; + +/** + * typedef dma_cookie_t + * + * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code + */ +typedef s32 dma_cookie_t; + +#define dma_submit_error(cookie) ((cookie) < 0 ? 1 : 0) + +/** + * enum dma_status - DMA transaction status + * @DMA_SUCCESS: transaction completed successfully + * @DMA_IN_PROGRESS: transaction not yet processed + * @DMA_ERROR: transaction failed + */ +enum dma_status { + DMA_SUCCESS, + DMA_IN_PROGRESS, + DMA_ERROR, +}; + +/** + * struct dma_chan_percpu - the per-CPU part of struct dma_chan + * @refcount: local_t used for open-coded "bigref" counting + * @memcpy_count: transaction counter + * @bytes_transferred: byte counter + */ + +struct dma_chan_percpu { + local_t refcount; + /* stats */ + unsigned long memcpy_count; + unsigned long bytes_transferred; +}; + +/** + * struct dma_chan - devices supply DMA channels, clients use them + * @client: ptr to the client user of this chan, will be NULL when unused + * @device: ptr to the dma device who supplies this channel, always !NULL + * @cookie: last cookie value returned to client + * @chan_id: + * @class_dev: + * @refcount: kref, used in "bigref" slow-mode + * @slow_ref: + * @rcu: + * @client_node: used to add this to the client chan list + * @device_node: used to add this to the device chan list + * @local: per-cpu pointer to a struct dma_chan_percpu + */ +struct dma_chan { + struct dma_client *client; + struct dma_device *device; + dma_cookie_t cookie; + + /* sysfs */ + int chan_id; + struct class_device class_dev; + + struct kref refcount; + int slow_ref; + struct rcu_head rcu; + + struct list_head client_node; + struct list_head device_node; + struct dma_chan_percpu *local; +}; + +void dma_chan_cleanup(struct kref *kref); + +static inline void dma_chan_get(struct dma_chan *chan) +{ + if (unlikely(chan->slow_ref)) + kref_get(&chan->refcount); + else { + local_inc(&(per_cpu_ptr(chan->local, get_cpu())->refcount)); + put_cpu(); + } +} + +static inline void dma_chan_put(struct dma_chan *chan) +{ + if (unlikely(chan->slow_ref)) + kref_put(&chan->refcount, dma_chan_cleanup); + else { + local_dec(&(per_cpu_ptr(chan->local, get_cpu())->refcount)); + put_cpu(); + } +} + +/* + * typedef dma_event_callback - function pointer to a DMA event callback + */ +typedef void (*dma_event_callback) (struct dma_client *client, + struct dma_chan *chan, enum dma_event event); + +/** + * struct dma_client - info on the entity making use of DMA services + * @event_callback: func ptr to call when something happens + * @chan_count: number of chans allocated + * @chans_desired: number of chans requested. Can be +/- chan_count + * @lock: protects access to the channels list + * @channels: the list of DMA channels allocated + * @global_node: list_head for global dma_client_list + */ +struct dma_client { + dma_event_callback event_callback; + unsigned int chan_count; + unsigned int chans_desired; + + spinlock_t lock; + struct list_head channels; + struct list_head global_node; +}; + +/** + * struct dma_device - info on the entity supplying DMA services + * @chancnt: how many DMA channels are supported + * @channels: the list of struct dma_chan + * @global_node: list_head for global dma_device_list + * @refcount: + * @done: + * @dev_id: + * Other func ptrs: used to make use of this device's capabilities + */ +struct dma_device { + + unsigned int chancnt; + struct list_head channels; + struct list_head global_node; + + struct kref refcount; + struct completion done; + + int dev_id; + + int (*device_alloc_chan_resources)(struct dma_chan *chan); + void (*device_free_chan_resources)(struct dma_chan *chan); + dma_cookie_t (*device_memcpy_buf_to_buf)(struct dma_chan *chan, + void *dest, void *src, size_t len); + dma_cookie_t (*device_memcpy_buf_to_pg)(struct dma_chan *chan, + struct page *page, unsigned int offset, void *kdata, + size_t len); + dma_cookie_t (*device_memcpy_pg_to_pg)(struct dma_chan *chan, + struct page *dest_pg, unsigned int dest_off, + struct page *src_pg, unsigned int src_off, size_t len); + enum dma_status (*device_memcpy_complete)(struct dma_chan *chan, + dma_cookie_t cookie, dma_cookie_t *last, + dma_cookie_t *used); + void (*device_memcpy_issue_pending)(struct dma_chan *chan); +}; + +/* --- public DMA engine API --- */ + +struct dma_client *dma_async_client_register(dma_event_callback event_callback); +void dma_async_client_unregister(struct dma_client *client); +void dma_async_client_chan_request(struct dma_client *client, + unsigned int number); + +/** + * dma_async_memcpy_buf_to_buf - offloaded copy between virtual addresses + * @chan: DMA channel to offload copy to + * @dest: destination address (virtual) + * @src: source address (virtual) + * @len: length + * + * Both @dest and @src must be mappable to a bus address according to the + * DMA mapping API rules for streaming mappings. + * Both @dest and @src must stay memory resident (kernel memory or locked + * user space pages) + */ +static inline dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan, + void *dest, void *src, size_t len) +{ + int cpu = get_cpu(); + per_cpu_ptr(chan->local, cpu)->bytes_transferred += len; + per_cpu_ptr(chan->local, cpu)->memcpy_count++; + put_cpu(); + + return chan->device->device_memcpy_buf_to_buf(chan, dest, src, len); +} + +/** + * dma_async_memcpy_buf_to_pg - offloaded copy + * @chan: DMA channel to offload copy to + * @page: destination page + * @offset: offset in page to copy to + * @kdata: source address (virtual) + * @len: length + * + * Both @page/@offset and @kdata must be mappable to a bus address according + * to the DMA mapping API rules for streaming mappings. + * Both @page/@offset and @kdata must stay memory resident (kernel memory or + * locked user space pages) + */ +static inline dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan, + struct page *page, unsigned int offset, void *kdata, size_t len) +{ + int cpu = get_cpu(); + per_cpu_ptr(chan->local, cpu)->bytes_transferred += len; + per_cpu_ptr(chan->local, cpu)->memcpy_count++; + put_cpu(); + + return chan->device->device_memcpy_buf_to_pg(chan, page, offset, + kdata, len); +} + +/** + * dma_async_memcpy_buf_to_pg - offloaded copy + * @chan: DMA channel to offload copy to + * @dest_page: destination page + * @dest_off: offset in page to copy to + * @src_page: source page + * @src_off: offset in page to copy from + * @len: length + * + * Both @dest_page/@dest_off and @src_page/@src_off must be mappable to a bus + * address according to the DMA mapping API rules for streaming mappings. + * Both @dest_page/@dest_off and @src_page/@src_off must stay memory resident + * (kernel memory or locked user space pages) + */ +static inline dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan, + struct page *dest_pg, unsigned int dest_off, struct page *src_pg, + unsigned int src_off, size_t len) +{ + int cpu = get_cpu(); + per_cpu_ptr(chan->local, cpu)->bytes_transferred += len; + per_cpu_ptr(chan->local, cpu)->memcpy_count++; + put_cpu(); + + return chan->device->device_memcpy_pg_to_pg(chan, dest_pg, dest_off, + src_pg, src_off, len); +} + +/** + * dma_async_memcpy_issue_pending - flush pending copies to HW + * @chan: + * + * This allows drivers to push copies to HW in batches, + * reducing MMIO writes where possible. + */ +static inline void dma_async_memcpy_issue_pending(struct dma_chan *chan) +{ + return chan->device->device_memcpy_issue_pending(chan); +} + +/** + * dma_async_memcpy_complete - poll for transaction completion + * @chan: DMA channel + * @cookie: transaction identifier to check status of + * @last: returns last completed cookie, can be NULL + * @used: returns last issued cookie, can be NULL + * + * If @last and @used are passed in, upon return they reflect the driver + * internal state and can be used with dma_async_is_complete() to check + * the status of multiple cookies without re-checking hardware state. + */ +static inline enum dma_status dma_async_memcpy_complete(struct dma_chan *chan, + dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used) +{ + return chan->device->device_memcpy_complete(chan, cookie, last, used); +} + +/** + * dma_async_is_complete - test a cookie against chan state + * @cookie: transaction identifier to test status of + * @last_complete: last know completed transaction + * @last_used: last cookie value handed out + * + * dma_async_is_complete() is used in dma_async_memcpy_complete() + * the test logic is seperated for lightweight testing of multiple cookies + */ +static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie, + dma_cookie_t last_complete, dma_cookie_t last_used) +{ + if (last_complete <= last_used) { + if ((cookie <= last_complete) || (cookie > last_used)) + return DMA_SUCCESS; + } else { + if ((cookie <= last_complete) && (cookie > last_used)) + return DMA_SUCCESS; + } + return DMA_IN_PROGRESS; +} + + +/* --- DMA device --- */ + +int dma_async_device_register(struct dma_device *device); +void dma_async_device_unregister(struct dma_device *device); + +/* --- Helper iov-locking functions --- */ + +struct dma_page_list { + char *base_address; + int nr_pages; + struct page **pages; +}; + +struct dma_pinned_list { + int nr_iovecs; + struct dma_page_list page_list[0]; +}; + +struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len); +void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list); + +dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov, + struct dma_pinned_list *pinned_list, unsigned char *kdata, size_t len); +dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov, + struct dma_pinned_list *pinned_list, struct page *page, + unsigned int offset, size_t len); + +#endif /* CONFIG_DMA_ENGINE */ +#endif /* DMAENGINE_H */ diff --git a/include/linux/elevator.h b/include/linux/elevator.h index ad133fcfb239..1713ace808bf 100644 --- a/include/linux/elevator.h +++ b/include/linux/elevator.h @@ -21,7 +21,7 @@ typedef void (elevator_put_req_fn) (request_queue_t *, struct request *); typedef void (elevator_activate_req_fn) (request_queue_t *, struct request *); typedef void (elevator_deactivate_req_fn) (request_queue_t *, struct request *); -typedef int (elevator_init_fn) (request_queue_t *, elevator_t *); +typedef void *(elevator_init_fn) (request_queue_t *, elevator_t *); typedef void (elevator_exit_fn) (elevator_t *); struct elevator_ops diff --git a/include/linux/hrtimer.h b/include/linux/hrtimer.h index 306acf1dc6d5..7d2a1b974c5e 100644 --- a/include/linux/hrtimer.h +++ b/include/linux/hrtimer.h @@ -127,7 +127,7 @@ extern ktime_t hrtimer_get_next_event(void); static inline int hrtimer_active(const struct hrtimer *timer) { - return timer->node.rb_parent != HRTIMER_INACTIVE; + return rb_parent(&timer->node) != &timer->node; } /* Forward a hrtimer so it expires after now: */ diff --git a/include/linux/i2o.h b/include/linux/i2o.h index dd7d627bf66f..c115e9e840b4 100644 --- a/include/linux/i2o.h +++ b/include/linux/i2o.h @@ -1114,8 +1114,11 @@ static inline struct i2o_message *i2o_msg_get(struct i2o_controller *c) mmsg->mfa = readl(c->in_port); if (unlikely(mmsg->mfa >= c->in_queue.len)) { + u32 mfa = mmsg->mfa; + mempool_free(mmsg, c->in_msg.mempool); - if(mmsg->mfa == I2O_QUEUE_EMPTY) + + if (mfa == I2O_QUEUE_EMPTY) return ERR_PTR(-EBUSY); return ERR_PTR(-EFAULT); } diff --git a/include/linux/igmp.h b/include/linux/igmp.h index 28f4f3b36950..899c3d4776f3 100644 --- a/include/linux/igmp.h +++ b/include/linux/igmp.h @@ -169,7 +169,7 @@ struct ip_sf_list struct ip_mc_list { struct in_device *interface; - unsigned long multiaddr; + __be32 multiaddr; struct ip_sf_list *sources; struct ip_sf_list *tomb; unsigned int sfmode; diff --git a/include/linux/input.h b/include/linux/input.h index b48d9873cbbc..b32c2b6e53f6 100644 --- a/include/linux/input.h +++ b/include/linux/input.h @@ -346,6 +346,8 @@ struct input_absinfo { #define KEY_SAVE 234 #define KEY_DOCUMENTS 235 +#define KEY_BATTERY 236 + #define KEY_UNKNOWN 240 #define BTN_MISC 0x100 @@ -578,14 +580,9 @@ struct input_absinfo { * Switch events */ -#define SW_0 0x00 -#define SW_1 0x01 -#define SW_2 0x02 -#define SW_3 0x03 -#define SW_4 0x04 -#define SW_5 0x05 -#define SW_6 0x06 -#define SW_7 0x07 +#define SW_LID 0x00 /* set = lid shut */ +#define SW_TABLET_MODE 0x01 /* set = tablet mode */ +#define SW_HEADPHONE_INSERT 0x02 /* set = inserted */ #define SW_MAX 0x0f /* diff --git a/include/linux/jffs2.h b/include/linux/jffs2.h index cf792bb3c726..c6f70660b371 100644 --- a/include/linux/jffs2.h +++ b/include/linux/jffs2.h @@ -65,6 +65,18 @@ #define JFFS2_NODETYPE_SUMMARY (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 6) +#define JFFS2_NODETYPE_XATTR (JFFS2_FEATURE_INCOMPAT | JFFS2_NODE_ACCURATE | 8) +#define JFFS2_NODETYPE_XREF (JFFS2_FEATURE_INCOMPAT | JFFS2_NODE_ACCURATE | 9) + +/* XATTR Related */ +#define JFFS2_XPREFIX_USER 1 /* for "user." */ +#define JFFS2_XPREFIX_SECURITY 2 /* for "security." */ +#define JFFS2_XPREFIX_ACL_ACCESS 3 /* for "system.posix_acl_access" */ +#define JFFS2_XPREFIX_ACL_DEFAULT 4 /* for "system.posix_acl_default" */ +#define JFFS2_XPREFIX_TRUSTED 5 /* for "trusted.*" */ + +#define JFFS2_ACL_VERSION 0x0001 + // Maybe later... //#define JFFS2_NODETYPE_CHECKPOINT (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 3) //#define JFFS2_NODETYPE_OPTIONS (JFFS2_FEATURE_RWCOMPAT_COPY | JFFS2_NODE_ACCURATE | 4) @@ -82,11 +94,11 @@ typedef struct { uint32_t v32; -} __attribute__((packed)) jint32_t; +} __attribute__((packed)) jint32_t; typedef struct { uint32_t m; -} __attribute__((packed)) jmode_t; +} __attribute__((packed)) jmode_t; typedef struct { uint16_t v16; @@ -99,7 +111,7 @@ struct jffs2_unknown_node jint16_t nodetype; jint32_t totlen; /* So we can skip over nodes we don't grok */ jint32_t hdr_crc; -} __attribute__((packed)); +}; struct jffs2_raw_dirent { @@ -117,7 +129,7 @@ struct jffs2_raw_dirent jint32_t node_crc; jint32_t name_crc; uint8_t name[0]; -} __attribute__((packed)); +}; /* The JFFS2 raw inode structure: Used for storage on physical media. */ /* The uid, gid, atime, mtime and ctime members could be longer, but @@ -149,6 +161,32 @@ struct jffs2_raw_inode jint32_t data_crc; /* CRC for the (compressed) data. */ jint32_t node_crc; /* CRC for the raw inode (excluding data) */ uint8_t data[0]; +}; + +struct jffs2_raw_xattr { + jint16_t magic; + jint16_t nodetype; /* = JFFS2_NODETYPE_XATTR */ + jint32_t totlen; + jint32_t hdr_crc; + jint32_t xid; /* XATTR identifier number */ + jint32_t version; + uint8_t xprefix; + uint8_t name_len; + jint16_t value_len; + jint32_t data_crc; + jint32_t node_crc; + uint8_t data[0]; +} __attribute__((packed)); + +struct jffs2_raw_xref +{ + jint16_t magic; + jint16_t nodetype; /* = JFFS2_NODETYPE_XREF */ + jint32_t totlen; + jint32_t hdr_crc; + jint32_t ino; /* inode number */ + jint32_t xid; /* XATTR identifier number */ + jint32_t node_crc; } __attribute__((packed)); struct jffs2_raw_summary @@ -163,14 +201,22 @@ struct jffs2_raw_summary jint32_t sum_crc; /* summary information crc */ jint32_t node_crc; /* node crc */ jint32_t sum[0]; /* inode summary info */ -} __attribute__((packed)); +}; union jffs2_node_union { struct jffs2_raw_inode i; struct jffs2_raw_dirent d; + struct jffs2_raw_xattr x; + struct jffs2_raw_xref r; struct jffs2_raw_summary s; struct jffs2_unknown_node u; }; +/* Data payload for device nodes. */ +union jffs2_device_node { + jint16_t old; + jint32_t new; +}; + #endif /* __LINUX_JFFS2_H__ */ diff --git a/include/linux/jffs2_fs_i.h b/include/linux/jffs2_fs_i.h deleted file mode 100644 index ad565bf9dcc1..000000000000 --- a/include/linux/jffs2_fs_i.h +++ /dev/null @@ -1,50 +0,0 @@ -/* $Id: jffs2_fs_i.h,v 1.19 2005/11/07 11:14:52 gleixner Exp $ */ - -#ifndef _JFFS2_FS_I -#define _JFFS2_FS_I - -#include <linux/version.h> -#include <linux/rbtree.h> -#include <asm/semaphore.h> - -struct jffs2_inode_info { - /* We need an internal mutex similar to inode->i_mutex. - Unfortunately, we can't used the existing one, because - either the GC would deadlock, or we'd have to release it - before letting GC proceed. Or we'd have to put ugliness - into the GC code so it didn't attempt to obtain the i_mutex - for the inode(s) which are already locked */ - struct semaphore sem; - - /* The highest (datanode) version number used for this ino */ - uint32_t highest_version; - - /* List of data fragments which make up the file */ - struct rb_root fragtree; - - /* There may be one datanode which isn't referenced by any of the - above fragments, if it contains a metadata update but no actual - data - or if this is a directory inode */ - /* This also holds the _only_ dnode for symlinks/device nodes, - etc. */ - struct jffs2_full_dnode *metadata; - - /* Directory entries */ - struct jffs2_full_dirent *dents; - - /* The target path if this is the inode of a symlink */ - unsigned char *target; - - /* Some stuff we just have to keep in-core at all times, for each inode. */ - struct jffs2_inode_cache *inocache; - - uint16_t flags; - uint8_t usercompr; -#if !defined (__ECOS) -#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,2) - struct inode vfs_inode; -#endif -#endif -}; - -#endif /* _JFFS2_FS_I */ diff --git a/include/linux/jffs2_fs_sb.h b/include/linux/jffs2_fs_sb.h deleted file mode 100644 index 4bcfb5570221..000000000000 --- a/include/linux/jffs2_fs_sb.h +++ /dev/null @@ -1,122 +0,0 @@ -/* $Id: jffs2_fs_sb.h,v 1.54 2005/09/21 13:37:34 dedekind Exp $ */ - -#ifndef _JFFS2_FS_SB -#define _JFFS2_FS_SB - -#include <linux/types.h> -#include <linux/spinlock.h> -#include <linux/workqueue.h> -#include <linux/completion.h> -#include <asm/semaphore.h> -#include <linux/timer.h> -#include <linux/wait.h> -#include <linux/list.h> -#include <linux/rwsem.h> - -#define JFFS2_SB_FLAG_RO 1 -#define JFFS2_SB_FLAG_SCANNING 2 /* Flash scanning is in progress */ -#define JFFS2_SB_FLAG_BUILDING 4 /* File system building is in progress */ - -struct jffs2_inodirty; - -/* A struct for the overall file system control. Pointers to - jffs2_sb_info structs are named `c' in the source code. - Nee jffs_control -*/ -struct jffs2_sb_info { - struct mtd_info *mtd; - - uint32_t highest_ino; - uint32_t checked_ino; - - unsigned int flags; - - struct task_struct *gc_task; /* GC task struct */ - struct completion gc_thread_start; /* GC thread start completion */ - struct completion gc_thread_exit; /* GC thread exit completion port */ - - struct semaphore alloc_sem; /* Used to protect all the following - fields, and also to protect against - out-of-order writing of nodes. And GC. */ - uint32_t cleanmarker_size; /* Size of an _inline_ CLEANMARKER - (i.e. zero for OOB CLEANMARKER */ - - uint32_t flash_size; - uint32_t used_size; - uint32_t dirty_size; - uint32_t wasted_size; - uint32_t free_size; - uint32_t erasing_size; - uint32_t bad_size; - uint32_t sector_size; - uint32_t unchecked_size; - - uint32_t nr_free_blocks; - uint32_t nr_erasing_blocks; - - /* Number of free blocks there must be before we... */ - uint8_t resv_blocks_write; /* ... allow a normal filesystem write */ - uint8_t resv_blocks_deletion; /* ... allow a normal filesystem deletion */ - uint8_t resv_blocks_gctrigger; /* ... wake up the GC thread */ - uint8_t resv_blocks_gcbad; /* ... pick a block from the bad_list to GC */ - uint8_t resv_blocks_gcmerge; /* ... merge pages when garbage collecting */ - - uint32_t nospc_dirty_size; - - uint32_t nr_blocks; - struct jffs2_eraseblock *blocks; /* The whole array of blocks. Used for getting blocks - * from the offset (blocks[ofs / sector_size]) */ - struct jffs2_eraseblock *nextblock; /* The block we're currently filling */ - - struct jffs2_eraseblock *gcblock; /* The block we're currently garbage-collecting */ - - struct list_head clean_list; /* Blocks 100% full of clean data */ - struct list_head very_dirty_list; /* Blocks with lots of dirty space */ - struct list_head dirty_list; /* Blocks with some dirty space */ - struct list_head erasable_list; /* Blocks which are completely dirty, and need erasing */ - struct list_head erasable_pending_wbuf_list; /* Blocks which need erasing but only after the current wbuf is flushed */ - struct list_head erasing_list; /* Blocks which are currently erasing */ - struct list_head erase_pending_list; /* Blocks which need erasing now */ - struct list_head erase_complete_list; /* Blocks which are erased and need the clean marker written to them */ - struct list_head free_list; /* Blocks which are free and ready to be used */ - struct list_head bad_list; /* Bad blocks. */ - struct list_head bad_used_list; /* Bad blocks with valid data in. */ - - spinlock_t erase_completion_lock; /* Protect free_list and erasing_list - against erase completion handler */ - wait_queue_head_t erase_wait; /* For waiting for erases to complete */ - - wait_queue_head_t inocache_wq; - struct jffs2_inode_cache **inocache_list; - spinlock_t inocache_lock; - - /* Sem to allow jffs2_garbage_collect_deletion_dirent to - drop the erase_completion_lock while it's holding a pointer - to an obsoleted node. I don't like this. Alternatives welcomed. */ - struct semaphore erase_free_sem; - - uint32_t wbuf_pagesize; /* 0 for NOR and other flashes with no wbuf */ - -#ifdef CONFIG_JFFS2_FS_WRITEBUFFER - /* Write-behind buffer for NAND flash */ - unsigned char *wbuf; - uint32_t wbuf_ofs; - uint32_t wbuf_len; - struct jffs2_inodirty *wbuf_inodes; - - struct rw_semaphore wbuf_sem; /* Protects the write buffer */ - - /* Information about out-of-band area usage... */ - struct nand_oobinfo *oobinfo; - uint32_t badblock_pos; - uint32_t fsdata_pos; - uint32_t fsdata_len; -#endif - - struct jffs2_summary *summary; /* Summary information */ - - /* OS-private pointer for getting back to master superblock info */ - void *os_priv; -}; - -#endif /* _JFFS2_FB_SB */ diff --git a/include/linux/m48t86.h b/include/linux/m48t86.h index 9065199319d0..915d6b4f0f89 100644 --- a/include/linux/m48t86.h +++ b/include/linux/m48t86.h @@ -11,6 +11,6 @@ struct m48t86_ops { - void (*writeb)(unsigned char value, unsigned long addr); - unsigned char (*readb)(unsigned long addr); + void (*writebyte)(unsigned char value, unsigned long addr); + unsigned char (*readbyte)(unsigned long addr); }; diff --git a/include/linux/mempolicy.h b/include/linux/mempolicy.h index 8dfdd352bccd..72440f0a443d 100644 --- a/include/linux/mempolicy.h +++ b/include/linux/mempolicy.h @@ -35,6 +35,7 @@ #include <linux/nodemask.h> struct vm_area_struct; +struct mm_struct; #ifdef CONFIG_NUMA diff --git a/include/linux/mmzone.h b/include/linux/mmzone.h index 230180c3eb61..9742e3c16222 100644 --- a/include/linux/mmzone.h +++ b/include/linux/mmzone.h @@ -14,6 +14,7 @@ #include <linux/seqlock.h> #include <linux/nodemask.h> #include <asm/atomic.h> +#include <asm/page.h> /* Free memory management - zoned buddy allocator. */ #ifndef CONFIG_FORCE_MAX_ZONEORDER diff --git a/include/linux/module.h b/include/linux/module.h index 05e7dd17b7d0..c2d89e037af0 100644 --- a/include/linux/module.h +++ b/include/linux/module.h @@ -556,13 +556,4 @@ static inline void module_remove_driver(struct device_driver *driver) #define __MODULE_STRING(x) __stringify(x) -/* Use symbol_get and symbol_put instead. You'll thank me. */ -#define HAVE_INTER_MODULE -extern void __deprecated inter_module_register(const char *, - struct module *, const void *); -extern void __deprecated inter_module_unregister(const char *); -extern const void * __deprecated inter_module_get_request(const char *, - const char *); -extern void __deprecated inter_module_put(const char *); - #endif /* _LINUX_MODULE_H */ diff --git a/include/linux/mtd/inftl.h b/include/linux/mtd/inftl.h index d7eaa40e5ab0..6977780e548f 100644 --- a/include/linux/mtd/inftl.h +++ b/include/linux/mtd/inftl.h @@ -46,7 +46,7 @@ struct INFTLrecord { unsigned int nb_blocks; /* number of physical blocks */ unsigned int nb_boot_blocks; /* number of blocks used by the bios */ struct erase_info instr; - struct nand_oobinfo oobinfo; + struct nand_ecclayout oobinfo; }; int INFTL_mount(struct INFTLrecord *s); diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index 012a47df1960..9b7a2b525d63 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h @@ -55,18 +55,69 @@ struct mtd_erase_region_info { u_int32_t numblocks; /* Number of blocks of erasesize in this region */ }; +/* + * oob operation modes + * + * MTD_OOB_PLACE: oob data are placed at the given offset + * MTD_OOB_AUTO: oob data are automatically placed at the free areas + * which are defined by the ecclayout + * MTD_OOB_RAW: mode to read raw data+oob in one chunk. The oob data + * is inserted into the data. Thats a raw image of the + * flash contents. + */ +typedef enum { + MTD_OOB_PLACE, + MTD_OOB_AUTO, + MTD_OOB_RAW, +} mtd_oob_mode_t; + +/** + * struct mtd_oob_ops - oob operation operands + * @mode: operation mode + * + * @len: number of bytes to write/read. When a data buffer is given + * (datbuf != NULL) this is the number of data bytes. When + + no data buffer is available this is the number of oob bytes. + * + * @retlen: number of bytes written/read. When a data buffer is given + * (datbuf != NULL) this is the number of data bytes. When + + no data buffer is available this is the number of oob bytes. + * + * @ooblen: number of oob bytes per page + * @ooboffs: offset of oob data in the oob area (only relevant when + * mode = MTD_OOB_PLACE) + * @datbuf: data buffer - if NULL only oob data are read/written + * @oobbuf: oob data buffer + */ +struct mtd_oob_ops { + mtd_oob_mode_t mode; + size_t len; + size_t retlen; + size_t ooblen; + uint32_t ooboffs; + uint8_t *datbuf; + uint8_t *oobbuf; +}; + struct mtd_info { u_char type; u_int32_t flags; u_int32_t size; // Total size of the MTD - /* "Major" erase size for the device. Naïve users may take this + /* "Major" erase size for the device. Naïve users may take this * to be the only erase size available, or may use the more detailed * information below if they desire */ u_int32_t erasesize; + /* Minimal writable flash unit size. In case of NOR flash it is 1 (even + * though individual bits can be cleared), in case of NAND flash it is + * one NAND page (or half, or one-fourths of it), in case of ECC-ed NOR + * it is of ECC block size, etc. It is illegal to have writesize = 0. + * Any driver registering a struct mtd_info must ensure a writesize of + * 1 or larger. + */ + u_int32_t writesize; - u_int32_t oobblock; // Size of OOB blocks (e.g. 512) u_int32_t oobsize; // Amount of OOB data per block (e.g. 16) u_int32_t ecctype; u_int32_t eccsize; @@ -78,7 +129,6 @@ struct mtd_info { * MTD_PROGRAM_REGIONS flag is set. * (Maybe we should have an union for those?) */ -#define MTD_PROGREGION_SIZE(mtd) (mtd)->oobblock #define MTD_PROGREGION_CTRLMODE_VALID(mtd) (mtd)->oobsize #define MTD_PROGREGION_CTRLMODE_INVALID(mtd) (mtd)->ecctype @@ -86,9 +136,8 @@ struct mtd_info { char *name; int index; - // oobinfo is a nand_oobinfo structure, which can be set by iotcl (MEMSETOOBINFO) - struct nand_oobinfo oobinfo; - u_int32_t oobavail; // Number of bytes in OOB area available for fs + /* ecc layout structure pointer - read only ! */ + struct nand_ecclayout *ecclayout; /* Data for variable erase regions. If numeraseregions is zero, * it means that the whole device has erasesize as given above. @@ -111,11 +160,10 @@ struct mtd_info { int (*read) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf); int (*write) (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf); - int (*read_ecc) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf, u_char *eccbuf, struct nand_oobinfo *oobsel); - int (*write_ecc) (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf, u_char *eccbuf, struct nand_oobinfo *oobsel); - - int (*read_oob) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf); - int (*write_oob) (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf); + int (*read_oob) (struct mtd_info *mtd, loff_t from, + struct mtd_oob_ops *ops); + int (*write_oob) (struct mtd_info *mtd, loff_t to, + struct mtd_oob_ops *ops); /* * Methods to access the protection register area, present in some @@ -129,17 +177,11 @@ struct mtd_info { int (*write_user_prot_reg) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf); int (*lock_user_prot_reg) (struct mtd_info *mtd, loff_t from, size_t len); - /* kvec-based read/write methods. We need these especially for NAND flash, - with its limited number of write cycles per erase. + /* kvec-based read/write methods. NB: The 'count' parameter is the number of _vectors_, each of which contains an (ofs, len) tuple. */ - int (*readv) (struct mtd_info *mtd, struct kvec *vecs, unsigned long count, loff_t from, size_t *retlen); - int (*readv_ecc) (struct mtd_info *mtd, struct kvec *vecs, unsigned long count, loff_t from, - size_t *retlen, u_char *eccbuf, struct nand_oobinfo *oobsel); int (*writev) (struct mtd_info *mtd, const struct kvec *vecs, unsigned long count, loff_t to, size_t *retlen); - int (*writev_ecc) (struct mtd_info *mtd, const struct kvec *vecs, unsigned long count, loff_t to, - size_t *retlen, u_char *eccbuf, struct nand_oobinfo *oobsel); /* Sync */ void (*sync) (struct mtd_info *mtd); @@ -158,6 +200,9 @@ struct mtd_info { struct notifier_block reboot_notifier; /* default mode before reboot */ + /* ECC status information */ + struct mtd_ecc_stats ecc_stats; + void *priv; struct module *owner; @@ -191,20 +236,6 @@ int default_mtd_writev(struct mtd_info *mtd, const struct kvec *vecs, int default_mtd_readv(struct mtd_info *mtd, struct kvec *vecs, unsigned long count, loff_t from, size_t *retlen); -#define MTD_ERASE(mtd, args...) (*(mtd->erase))(mtd, args) -#define MTD_POINT(mtd, a,b,c,d) (*(mtd->point))(mtd, a,b,c, (u_char **)(d)) -#define MTD_UNPOINT(mtd, arg) (*(mtd->unpoint))(mtd, (u_char *)arg) -#define MTD_READ(mtd, args...) (*(mtd->read))(mtd, args) -#define MTD_WRITE(mtd, args...) (*(mtd->write))(mtd, args) -#define MTD_READV(mtd, args...) (*(mtd->readv))(mtd, args) -#define MTD_WRITEV(mtd, args...) (*(mtd->writev))(mtd, args) -#define MTD_READECC(mtd, args...) (*(mtd->read_ecc))(mtd, args) -#define MTD_WRITEECC(mtd, args...) (*(mtd->write_ecc))(mtd, args) -#define MTD_READOOB(mtd, args...) (*(mtd->read_oob))(mtd, args) -#define MTD_WRITEOOB(mtd, args...) (*(mtd->write_oob))(mtd, args) -#define MTD_SYNC(mtd) do { if (mtd->sync) (*(mtd->sync))(mtd); } while (0) - - #ifdef CONFIG_MTD_PARTITIONS void mtd_erase_callback(struct erase_info *instr); #else @@ -225,7 +256,7 @@ static inline void mtd_erase_callback(struct erase_info *instr) #ifdef CONFIG_MTD_DEBUG #define DEBUG(n, args...) \ - do { \ + do { \ if (n <= CONFIG_MTD_DEBUG_VERBOSE) \ printk(KERN_INFO args); \ } while(0) diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 4b99d285803f..66559272ebcb 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -11,47 +11,11 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * - * Info: - * Contains standard defines and IDs for NAND flash devices + * Info: + * Contains standard defines and IDs for NAND flash devices * - * Changelog: - * 01-31-2000 DMW Created - * 09-18-2000 SJH Moved structure out of the Disk-On-Chip drivers - * so it can be used by other NAND flash device - * drivers. I also changed the copyright since none - * of the original contents of this file are specific - * to DoC devices. David can whack me with a baseball - * bat later if I did something naughty. - * 10-11-2000 SJH Added private NAND flash structure for driver - * 10-24-2000 SJH Added prototype for 'nand_scan' function - * 10-29-2001 TG changed nand_chip structure to support - * hardwarespecific function for accessing control lines - * 02-21-2002 TG added support for different read/write adress and - * ready/busy line access function - * 02-26-2002 TG added chip_delay to nand_chip structure to optimize - * command delay times for different chips - * 04-28-2002 TG OOB config defines moved from nand.c to avoid duplicate - * defines in jffs2/wbuf.c - * 08-07-2002 TG forced bad block location to byte 5 of OOB, even if - * CONFIG_MTD_NAND_ECC_JFFS2 is not set - * 08-10-2002 TG extensions to nand_chip structure to support HW-ECC - * - * 08-29-2002 tglx nand_chip structure: data_poi for selecting - * internal / fs-driver buffer - * support for 6byte/512byte hardware ECC - * read_ecc, write_ecc extended for different oob-layout - * oob layout selections: NAND_NONE_OOB, NAND_JFFS2_OOB, - * NAND_YAFFS_OOB - * 11-25-2002 tglx Added Manufacturer code FUJITSU, NATIONAL - * Split manufacturer and device ID structures - * - * 02-08-2004 tglx added option field to nand structure for chip anomalities - * 05-25-2004 tglx added bad block table support, ST-MICRO manufacturer id - * update of nand_chip structure description - * 01-17-2005 dmarlin added extended commands for AG-AND device and added option - * for BBT_AUTO_REFRESH. - * 01-20-2005 dmarlin added optional pointer to hardware specific callback for - * extra error status checks. + * Changelog: + * See git changelog. */ #ifndef __LINUX_MTD_NAND_H #define __LINUX_MTD_NAND_H @@ -66,10 +30,6 @@ extern int nand_scan (struct mtd_info *mtd, int max_chips); /* Free resources held by the NAND device */ extern void nand_release (struct mtd_info *mtd); -/* Read raw data from the device without ECC */ -extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_t len, size_t ooblen); - - /* The maximum number of NAND chips in an array */ #define NAND_MAX_CHIPS 8 @@ -78,44 +38,45 @@ extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_ * adjust this accordingly. */ #define NAND_MAX_OOBSIZE 64 +#define NAND_MAX_PAGESIZE 2048 /* * Constants for hardware specific CLE/ALE/NCE function -*/ + * + * These are bits which can be or'ed to set/clear multiple + * bits in one go. + */ /* Select the chip by setting nCE to low */ -#define NAND_CTL_SETNCE 1 -/* Deselect the chip by setting nCE to high */ -#define NAND_CTL_CLRNCE 2 +#define NAND_NCE 0x01 /* Select the command latch by setting CLE to high */ -#define NAND_CTL_SETCLE 3 -/* Deselect the command latch by setting CLE to low */ -#define NAND_CTL_CLRCLE 4 +#define NAND_CLE 0x02 /* Select the address latch by setting ALE to high */ -#define NAND_CTL_SETALE 5 -/* Deselect the address latch by setting ALE to low */ -#define NAND_CTL_CLRALE 6 -/* Set write protection by setting WP to high. Not used! */ -#define NAND_CTL_SETWP 7 -/* Clear write protection by setting WP to low. Not used! */ -#define NAND_CTL_CLRWP 8 +#define NAND_ALE 0x04 + +#define NAND_CTRL_CLE (NAND_NCE | NAND_CLE) +#define NAND_CTRL_ALE (NAND_NCE | NAND_ALE) +#define NAND_CTRL_CHANGE 0x80 /* * Standard NAND flash commands */ #define NAND_CMD_READ0 0 #define NAND_CMD_READ1 1 +#define NAND_CMD_RNDOUT 5 #define NAND_CMD_PAGEPROG 0x10 #define NAND_CMD_READOOB 0x50 #define NAND_CMD_ERASE1 0x60 #define NAND_CMD_STATUS 0x70 #define NAND_CMD_STATUS_MULTI 0x71 #define NAND_CMD_SEQIN 0x80 +#define NAND_CMD_RNDIN 0x85 #define NAND_CMD_READID 0x90 #define NAND_CMD_ERASE2 0xd0 #define NAND_CMD_RESET 0xff /* Extended commands for large page devices */ #define NAND_CMD_READSTART 0x30 +#define NAND_CMD_RNDOUTSTART 0xE0 #define NAND_CMD_CACHEDPROG 0x15 /* Extended commands for AG-AND device */ @@ -137,6 +98,8 @@ extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_ #define NAND_CMD_STATUS_RESET 0x7f #define NAND_CMD_STATUS_CLEAR 0xff +#define NAND_CMD_NONE -1 + /* Status bits */ #define NAND_STATUS_FAIL 0x01 #define NAND_STATUS_FAIL_N1 0x02 @@ -147,21 +110,12 @@ extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_ /* * Constants for ECC_MODES */ - -/* No ECC. Usage is not recommended ! */ -#define NAND_ECC_NONE 0 -/* Software ECC 3 byte ECC per 256 Byte data */ -#define NAND_ECC_SOFT 1 -/* Hardware ECC 3 byte ECC per 256 Byte data */ -#define NAND_ECC_HW3_256 2 -/* Hardware ECC 3 byte ECC per 512 Byte data */ -#define NAND_ECC_HW3_512 3 -/* Hardware ECC 3 byte ECC per 512 Byte data */ -#define NAND_ECC_HW6_512 4 -/* Hardware ECC 8 byte ECC per 512 Byte data */ -#define NAND_ECC_HW8_512 6 -/* Hardware ECC 12 byte ECC per 2048 Byte data */ -#define NAND_ECC_HW12_2048 7 +typedef enum { + NAND_ECC_NONE, + NAND_ECC_SOFT, + NAND_ECC_HW, + NAND_ECC_HW_SYNDROME, +} nand_ecc_modes_t; /* * Constants for Hardware ECC @@ -200,6 +154,10 @@ extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_ * bits from adjacent blocks from 'leaking' in altering data. * This happens with the Renesas AG-AND chips, possibly others. */ #define BBT_AUTO_REFRESH 0x00000080 +/* Chip does not require ready check on read. True + * for all large page devices, as they do not support + * autoincrement.*/ +#define NAND_NO_READRDY 0x00000100 /* Options valid for Samsung large page devices */ #define NAND_SAMSUNG_LP_OPTIONS \ @@ -218,18 +176,12 @@ extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_ /* Use a flash based bad block table. This option is passed to the * default bad block table function. */ #define NAND_USE_FLASH_BBT 0x00010000 -/* The hw ecc generator provides a syndrome instead a ecc value on read - * This can only work if we have the ecc bytes directly behind the - * data bytes. Applies for DOC and AG-AND Renesas HW Reed Solomon generators */ -#define NAND_HWECC_SYNDROME 0x00020000 /* This option skips the bbt scan during initialization. */ -#define NAND_SKIP_BBTSCAN 0x00040000 +#define NAND_SKIP_BBTSCAN 0x00020000 /* Options set by nand scan */ -/* Nand scan has allocated oob_buf */ -#define NAND_OOBBUF_ALLOC 0x40000000 -/* Nand scan has allocated data_buf */ -#define NAND_DATABUF_ALLOC 0x80000000 +/* Nand scan has allocated controller struct */ +#define NAND_CONTROLLER_ALLOC 0x80000000 /* @@ -263,45 +215,102 @@ struct nand_hw_control { }; /** + * struct nand_ecc_ctrl - Control structure for ecc + * @mode: ecc mode + * @steps: number of ecc steps per page + * @size: data bytes per ecc step + * @bytes: ecc bytes per step + * @total: total number of ecc bytes per page + * @prepad: padding information for syndrome based ecc generators + * @postpad: padding information for syndrome based ecc generators + * @hwctl: function to control hardware ecc generator. Must only + * be provided if an hardware ECC is available + * @calculate: function for ecc calculation or readback from ecc hardware + * @correct: function for ecc correction, matching to ecc generator (sw/hw) + * @read_page: function to read a page according to the ecc generator requirements + * @write_page: function to write a page according to the ecc generator requirements + */ +struct nand_ecc_ctrl { + nand_ecc_modes_t mode; + int steps; + int size; + int bytes; + int total; + int prepad; + int postpad; + struct nand_ecclayout *layout; + void (*hwctl)(struct mtd_info *mtd, int mode); + int (*calculate)(struct mtd_info *mtd, + const uint8_t *dat, + uint8_t *ecc_code); + int (*correct)(struct mtd_info *mtd, uint8_t *dat, + uint8_t *read_ecc, + uint8_t *calc_ecc); + int (*read_page)(struct mtd_info *mtd, + struct nand_chip *chip, + uint8_t *buf); + void (*write_page)(struct mtd_info *mtd, + struct nand_chip *chip, + const uint8_t *buf); + int (*read_oob)(struct mtd_info *mtd, + struct nand_chip *chip, + int page, + int sndcmd); + int (*write_oob)(struct mtd_info *mtd, + struct nand_chip *chip, + int page); +}; + +/** + * struct nand_buffers - buffer structure for read/write + * @ecccalc: buffer for calculated ecc + * @ecccode: buffer for ecc read from flash + * @oobwbuf: buffer for write oob data + * @databuf: buffer for data - dynamically sized + * @oobrbuf: buffer to read oob data + * + * Do not change the order of buffers. databuf and oobrbuf must be in + * consecutive order. + */ +struct nand_buffers { + uint8_t ecccalc[NAND_MAX_OOBSIZE]; + uint8_t ecccode[NAND_MAX_OOBSIZE]; + uint8_t oobwbuf[NAND_MAX_OOBSIZE]; + uint8_t databuf[NAND_MAX_PAGESIZE]; + uint8_t oobrbuf[NAND_MAX_OOBSIZE]; +}; + +/** * struct nand_chip - NAND Private Flash Chip Data * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device * @read_byte: [REPLACEABLE] read one byte from the chip - * @write_byte: [REPLACEABLE] write one byte to the chip * @read_word: [REPLACEABLE] read one word from the chip - * @write_word: [REPLACEABLE] write one word to the chip * @write_buf: [REPLACEABLE] write data from the buffer to the chip * @read_buf: [REPLACEABLE] read data from the chip into the buffer * @verify_buf: [REPLACEABLE] verify buffer contents against the chip data * @select_chip: [REPLACEABLE] select chip nr * @block_bad: [REPLACEABLE] check, if the block is bad * @block_markbad: [REPLACEABLE] mark the block bad - * @hwcontrol: [BOARDSPECIFIC] hardwarespecific function for accesing control-lines + * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific funtion for controlling + * ALE/CLE/nCE. Also used to write command and address * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line * If set to NULL no access to ready/busy is available and the ready/busy information * is read from the chip status register * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready - * @calculate_ecc: [REPLACEABLE] function for ecc calculation or readback from ecc hardware - * @correct_data: [REPLACEABLE] function for ecc correction, matching to ecc generator (sw/hw) - * @enable_hwecc: [BOARDSPECIFIC] function to enable (reset) hardware ecc generator. Must only - * be provided if a hardware ECC is available + * @ecc: [BOARDSPECIFIC] ecc control ctructure * @erase_cmd: [INTERN] erase command write function, selectable due to AND support * @scan_bbt: [REPLACEABLE] function to scan bad block table - * @eccmode: [BOARDSPECIFIC] mode of ecc, see defines - * @eccsize: [INTERN] databytes used per ecc-calculation - * @eccbytes: [INTERN] number of ecc bytes per ecc-calculation step - * @eccsteps: [INTERN] number of ecc calculation steps per page * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR) - * @chip_lock: [INTERN] spinlock used to protect access to this structure and the chip * @wq: [INTERN] wait queue to sleep on if a NAND operation is in progress - * @state: [INTERN] the current state of the NAND device + * @state: [INTERN] the current state of the NAND device * @page_shift: [INTERN] number of address bits in a page (column address bits) * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry * @chip_shift: [INTERN] number of address bits in one chip - * @data_buf: [INTERN] internal buffer for one page + oob - * @oob_buf: [INTERN] oob buffer for one eraseblock + * @datbuf: [INTERN] internal buffer for one page + oob + * @oobbuf: [INTERN] oob buffer for one eraseblock * @oobdirty: [INTERN] indicates that oob_buf must be reinitialized * @data_poi: [INTERN] pointer to a data buffer * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about @@ -311,12 +320,13 @@ struct nand_hw_control { * @chipsize: [INTERN] the size of one chip for multichip arrays * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 * @pagebuf: [INTERN] holds the pagenumber which is currently in data_buf - * @autooob: [REPLACEABLE] the default (auto)placement scheme + * @ecclayout: [REPLACEABLE] the default ecc placement scheme * @bbt: [INTERN] bad block table pointer * @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup * @bbt_md: [REPLACEABLE] bad block table mirror descriptor * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan - * @controller: [OPTIONAL] a pointer to a hardware controller structure which is shared among multiple independend devices + * @controller: [REPLACEABLE] a pointer to a hardware controller structure + * which is shared among multiple independend devices * @priv: [OPTIONAL] pointer to private chip date * @errstat: [OPTIONAL] hardware specific function to perform additional error status checks * (determine if errors are correctable) @@ -324,58 +334,57 @@ struct nand_hw_control { struct nand_chip { void __iomem *IO_ADDR_R; - void __iomem *IO_ADDR_W; + void __iomem *IO_ADDR_W; - u_char (*read_byte)(struct mtd_info *mtd); - void (*write_byte)(struct mtd_info *mtd, u_char byte); + uint8_t (*read_byte)(struct mtd_info *mtd); u16 (*read_word)(struct mtd_info *mtd); - void (*write_word)(struct mtd_info *mtd, u16 word); - - void (*write_buf)(struct mtd_info *mtd, const u_char *buf, int len); - void (*read_buf)(struct mtd_info *mtd, u_char *buf, int len); - int (*verify_buf)(struct mtd_info *mtd, const u_char *buf, int len); + void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); + void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); + int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); void (*select_chip)(struct mtd_info *mtd, int chip); int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip); int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); - void (*hwcontrol)(struct mtd_info *mtd, int cmd); - int (*dev_ready)(struct mtd_info *mtd); - void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr); - int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this, int state); - int (*calculate_ecc)(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code); - int (*correct_data)(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc); - void (*enable_hwecc)(struct mtd_info *mtd, int mode); + void (*cmd_ctrl)(struct mtd_info *mtd, int dat, + unsigned int ctrl); + int (*dev_ready)(struct mtd_info *mtd); + void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr); + int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this); void (*erase_cmd)(struct mtd_info *mtd, int page); int (*scan_bbt)(struct mtd_info *mtd); - int eccmode; - int eccsize; - int eccbytes; - int eccsteps; - int chip_delay; - spinlock_t chip_lock; - wait_queue_head_t wq; - nand_state_t state; - int page_shift; + int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page); + + int chip_delay; + unsigned int options; + + int page_shift; int phys_erase_shift; int bbt_erase_shift; int chip_shift; - u_char *data_buf; - u_char *oob_buf; - int oobdirty; - u_char *data_poi; - unsigned int options; - int badblockpos; int numchips; unsigned long chipsize; int pagemask; int pagebuf; - struct nand_oobinfo *autooob; + int badblockpos; + + nand_state_t state; + + uint8_t *oob_poi; + struct nand_hw_control *controller; + struct nand_ecclayout *ecclayout; + + struct nand_ecc_ctrl ecc; + struct nand_buffers buffers; + struct nand_hw_control hwcontrol; + + struct mtd_oob_ops ops; + uint8_t *bbt; struct nand_bbt_descr *bbt_td; struct nand_bbt_descr *bbt_md; + struct nand_bbt_descr *badblock_pattern; - struct nand_hw_control *controller; + void *priv; - int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page); }; /* @@ -387,19 +396,19 @@ struct nand_chip { #define NAND_MFR_NATIONAL 0x8f #define NAND_MFR_RENESAS 0x07 #define NAND_MFR_STMICRO 0x20 -#define NAND_MFR_HYNIX 0xad +#define NAND_MFR_HYNIX 0xad /** * struct nand_flash_dev - NAND Flash Device ID Structure * - * @name: Identify the device type - * @id: device ID code - * @pagesize: Pagesize in bytes. Either 256 or 512 or 0 + * @name: Identify the device type + * @id: device ID code + * @pagesize: Pagesize in bytes. Either 256 or 512 or 0 * If the pagesize is 0, then the real pagesize * and the eraseize are determined from the * extended id bytes in the chip - * @erasesize: Size of an erase block in the flash device. - * @chipsize: Total chipsize in Mega Bytes + * @erasesize: Size of an erase block in the flash device. + * @chipsize: Total chipsize in Mega Bytes * @options: Bitfield to store chip relevant options */ struct nand_flash_dev { @@ -414,7 +423,7 @@ struct nand_flash_dev { /** * struct nand_manufacturers - NAND Flash Manufacturer ID Structure * @name: Manufacturer name - * @id: manufacturer ID code of device. + * @id: manufacturer ID code of device. */ struct nand_manufacturers { int id; @@ -454,7 +463,7 @@ struct nand_bbt_descr { int veroffs; uint8_t version[NAND_MAX_CHIPS]; int len; - int maxblocks; + int maxblocks; int reserved_block_code; uint8_t *pattern; }; @@ -493,14 +502,14 @@ struct nand_bbt_descr { /* The maximum number of blocks to scan for a bbt */ #define NAND_BBT_SCAN_MAXBLOCKS 4 -extern int nand_scan_bbt (struct mtd_info *mtd, struct nand_bbt_descr *bd); -extern int nand_update_bbt (struct mtd_info *mtd, loff_t offs); -extern int nand_default_bbt (struct mtd_info *mtd); -extern int nand_isbad_bbt (struct mtd_info *mtd, loff_t offs, int allowbbt); -extern int nand_erase_nand (struct mtd_info *mtd, struct erase_info *instr, int allowbbt); -extern int nand_do_read_ecc (struct mtd_info *mtd, loff_t from, size_t len, - size_t * retlen, u_char * buf, u_char * oob_buf, - struct nand_oobinfo *oobsel, int flags); +extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd); +extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs); +extern int nand_default_bbt(struct mtd_info *mtd); +extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt); +extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, + int allowbbt); +extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len, + size_t * retlen, uint8_t * buf); /* * Constants for oob configuration @@ -508,4 +517,53 @@ extern int nand_do_read_ecc (struct mtd_info *mtd, loff_t from, size_t len, #define NAND_SMALL_BADBLOCK_POS 5 #define NAND_LARGE_BADBLOCK_POS 0 +/** + * struct platform_nand_chip - chip level device structure + * + * @nr_chips: max. number of chips to scan for + * @chip_offs: chip number offset + * @nr_partitions: number of partitions pointed to by partitions (or zero) + * @partitions: mtd partition list + * @chip_delay: R/B delay value in us + * @options: Option flags, e.g. 16bit buswidth + * @ecclayout: ecc layout info structure + * @priv: hardware controller specific settings + */ +struct platform_nand_chip { + int nr_chips; + int chip_offset; + int nr_partitions; + struct mtd_partition *partitions; + struct nand_ecclayout *ecclayout; + int chip_delay; + unsigned int options; + void *priv; +}; + +/** + * struct platform_nand_ctrl - controller level device structure + * + * @hwcontrol: platform specific hardware control structure + * @dev_ready: platform specific function to read ready/busy pin + * @select_chip: platform specific chip select function + * @priv_data: private data to transport driver specific settings + * + * All fields are optional and depend on the hardware driver requirements + */ +struct platform_nand_ctrl { + void (*hwcontrol)(struct mtd_info *mtd, int cmd); + int (*dev_ready)(struct mtd_info *mtd); + void (*select_chip)(struct mtd_info *mtd, int chip); + void *priv; +}; + +/* Some helpers to access the data structures */ +static inline +struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd->priv; + + return chip->priv; +} + #endif /* __LINUX_MTD_NAND_H */ diff --git a/include/linux/mtd/ndfc.h b/include/linux/mtd/ndfc.h new file mode 100644 index 000000000000..d0558a982628 --- /dev/null +++ b/include/linux/mtd/ndfc.h @@ -0,0 +1,67 @@ +/* + * linux/include/linux/mtd/ndfc.h + * + * Copyright (c) 2006 Thomas Gleixner <tglx@linutronix.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Info: + * Contains defines, datastructures for ndfc nand controller + * + */ +#ifndef __LINUX_MTD_NDFC_H +#define __LINUX_MTD_NDFC_H + +/* NDFC Register definitions */ +#define NDFC_CMD 0x00 +#define NDFC_ALE 0x04 +#define NDFC_DATA 0x08 +#define NDFC_ECC 0x10 +#define NDFC_BCFG0 0x30 +#define NDFC_BCFG1 0x34 +#define NDFC_BCFG2 0x38 +#define NDFC_BCFG3 0x3c +#define NDFC_CCR 0x40 +#define NDFC_STAT 0x44 +#define NDFC_HWCTL 0x48 +#define NDFC_REVID 0x50 + +#define NDFC_STAT_IS_READY 0x01000000 + +#define NDFC_CCR_RESET_CE 0x80000000 /* CE Reset */ +#define NDFC_CCR_RESET_ECC 0x40000000 /* ECC Reset */ +#define NDFC_CCR_RIE 0x20000000 /* Interrupt Enable on Device Rdy */ +#define NDFC_CCR_REN 0x10000000 /* Enable wait for Rdy in LinearR */ +#define NDFC_CCR_ROMEN 0x08000000 /* Enable ROM In LinearR */ +#define NDFC_CCR_ARE 0x04000000 /* Auto-Read Enable */ +#define NDFC_CCR_BS(x) (((x) & 0x3) << 24) /* Select Bank on CE[x] */ +#define NDFC_CCR_BS_MASK 0x03000000 /* Select Bank */ +#define NDFC_CCR_ARAC0 0x00000000 /* 3 Addr, 1 Col 2 Row 512b page */ +#define NDFC_CCR_ARAC1 0x00001000 /* 4 Addr, 1 Col 3 Row 512b page */ +#define NDFC_CCR_ARAC2 0x00002000 /* 4 Addr, 2 Col 2 Row 2K page */ +#define NDFC_CCR_ARAC3 0x00003000 /* 5 Addr, 2 Col 3 Row 2K page */ +#define NDFC_CCR_ARAC_MASK 0x00003000 /* Auto-Read mode Addr Cycles */ +#define NDFC_CCR_RPG 0x0000C000 /* Auto-Read Page */ +#define NDFC_CCR_EBCC 0x00000004 /* EBC Configuration Completed */ +#define NDFC_CCR_DHC 0x00000002 /* Direct Hardware Control Enable */ + +#define NDFC_BxCFG_EN 0x80000000 /* Bank Enable */ +#define NDFC_BxCFG_CED 0x40000000 /* nCE Style */ +#define NDFC_BxCFG_SZ_MASK 0x08000000 /* Bank Size */ +#define NDFC_BxCFG_SZ_8BIT 0x00000000 /* 8bit */ +#define NDFC_BxCFG_SZ_16BIT 0x08000000 /* 16bit */ + +#define NDFC_MAX_BANKS 4 + +struct ndfc_controller_settings { + uint32_t ccr_settings; + uint64_t ndfc_erpn; +}; + +struct ndfc_chip_settings { + uint32_t bank_settings; +}; + +#endif diff --git a/include/linux/mtd/nftl.h b/include/linux/mtd/nftl.h index d35d2c21ff3e..bcf2fb3fa4a7 100644 --- a/include/linux/mtd/nftl.h +++ b/include/linux/mtd/nftl.h @@ -37,7 +37,7 @@ struct NFTLrecord { unsigned int nb_blocks; /* number of physical blocks */ unsigned int nb_boot_blocks; /* number of blocks used by the bios */ struct erase_info instr; - struct nand_oobinfo oobinfo; + struct nand_ecclayout oobinfo; }; int NFTL_mount(struct NFTLrecord *s); diff --git a/include/linux/mtd/onenand.h b/include/linux/mtd/onenand.h index 7419b5fab133..9ce9a48db444 100644 --- a/include/linux/mtd/onenand.h +++ b/include/linux/mtd/onenand.h @@ -35,6 +35,8 @@ typedef enum { FL_SYNCING, FL_UNLOCKING, FL_LOCKING, + FL_RESETING, + FL_OTPING, FL_PM_SUSPENDED, } onenand_state_t; @@ -75,7 +77,7 @@ struct onenand_bufferram { * @param chip_lock [INTERN] spinlock used to protect access to this structure and the chip * @param wq [INTERN] wait queue to sleep on if a OneNAND operation is in progress * @param state [INTERN] the current state of the OneNAND device - * @param autooob [REPLACEABLE] the default (auto)placement scheme + * @param ecclayout [REPLACEABLE] the default ecc placement scheme * @param bbm [REPLACEABLE] pointer to Bad Block Management * @param priv [OPTIONAL] pointer to private chip date */ @@ -111,9 +113,9 @@ struct onenand_chip { onenand_state_t state; unsigned char *page_buf; - struct nand_oobinfo *autooob; + struct nand_ecclayout *ecclayout; - void *bbm; + void *bbm; void *priv; }; @@ -130,6 +132,9 @@ struct onenand_chip { #define ONENAND_SET_SYS_CFG1(v, this) \ (this->write_word(v, this->base + ONENAND_REG_SYS_CFG1)) +/* Check byte access in OneNAND */ +#define ONENAND_CHECK_BYTE_ACCESS(addr) (addr & 0x1) + /* * Options bits */ diff --git a/include/linux/mtd/onenand_regs.h b/include/linux/mtd/onenand_regs.h index d7832ef8ed63..4a72818d2545 100644 --- a/include/linux/mtd/onenand_regs.h +++ b/include/linux/mtd/onenand_regs.h @@ -112,6 +112,7 @@ #define ONENAND_CMD_LOCK_TIGHT (0x2C) #define ONENAND_CMD_ERASE (0x94) #define ONENAND_CMD_RESET (0xF0) +#define ONENAND_CMD_OTP_ACCESS (0x65) #define ONENAND_CMD_READID (0x90) /* NOTE: Those are not *REAL* commands */ @@ -152,6 +153,8 @@ #define ONENAND_CTRL_ERASE (1 << 11) #define ONENAND_CTRL_ERROR (1 << 10) #define ONENAND_CTRL_RSTB (1 << 7) +#define ONENAND_CTRL_OTP_L (1 << 6) +#define ONENAND_CTRL_OTP_BL (1 << 5) /* * Interrupt Status Register F241h (R) @@ -177,4 +180,9 @@ #define ONENAND_ECC_2BIT (1 << 1) #define ONENAND_ECC_2BIT_ALL (0xAAAA) +/* + * One-Time Programmable (OTP) + */ +#define ONENAND_OTP_LOCK_OFFSET (14) + #endif /* __ONENAND_REG_H */ diff --git a/include/linux/mtd/partitions.h b/include/linux/mtd/partitions.h index b03f512d51b9..da6b3d6f12a7 100644 --- a/include/linux/mtd/partitions.h +++ b/include/linux/mtd/partitions.h @@ -41,7 +41,7 @@ struct mtd_partition { u_int32_t size; /* partition size */ u_int32_t offset; /* offset within the master MTD space */ u_int32_t mask_flags; /* master MTD flags to mask out for this partition */ - struct nand_oobinfo *oobsel; /* out of band layout for this partition (NAND only)*/ + struct nand_ecclayout *ecclayout; /* out of band layout for this partition (NAND only)*/ struct mtd_info **mtdp; /* pointer to store the MTD object */ }; diff --git a/include/linux/mtd/physmap.h b/include/linux/mtd/physmap.h index bffaade1111e..86831e3594f6 100644 --- a/include/linux/mtd/physmap.h +++ b/include/linux/mtd/physmap.h @@ -15,32 +15,26 @@ */ #ifndef __LINUX_MTD_PHYSMAP__ - - -#if defined(CONFIG_MTD_PHYSMAP) +#define __LINUX_MTD_PHYSMAP__ #include <linux/mtd/mtd.h> #include <linux/mtd/map.h> #include <linux/mtd/partitions.h> -/* - * The map_info for physmap. Board can override size, buswidth, phys, - * (*set_vpp)(), etc in their initial setup routine. - */ -extern struct map_info physmap_map; +struct physmap_flash_data { + unsigned int width; + void (*set_vpp)(struct map_info *, int); + unsigned int nr_parts; + struct mtd_partition *parts; +}; /* * Board needs to specify the exact mapping during their setup time. */ -static inline void physmap_configure(unsigned long addr, unsigned long size, int bankwidth, void (*set_vpp)(struct map_info *, int) ) -{ - physmap_map.phys = addr; - physmap_map.size = size; - physmap_map.bankwidth = bankwidth; - physmap_map.set_vpp = set_vpp; -} +void physmap_configure(unsigned long addr, unsigned long size, + int bankwidth, void (*set_vpp)(struct map_info *, int) ); -#if defined(CONFIG_MTD_PARTITIONS) +#ifdef CONFIG_MTD_PARTITIONS /* * Machines that wish to do flash partition may want to call this function in @@ -54,7 +48,5 @@ static inline void physmap_configure(unsigned long addr, unsigned long size, int void physmap_set_partitions(struct mtd_partition *parts, int num_parts); #endif /* defined(CONFIG_MTD_PARTITIONS) */ -#endif /* defined(CONFIG_MTD) */ #endif /* __LINUX_MTD_PHYSMAP__ */ - diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h index cebe677e153b..5e8e2d50429a 100644 --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h @@ -36,6 +36,7 @@ #include <linux/device.h> #include <linux/percpu.h> +#include <linux/dmaengine.h> struct divert_blk; struct vlan_group; @@ -310,6 +311,9 @@ struct net_device #define NETIF_F_LLTX 4096 /* LockLess TX */ #define NETIF_F_UFO 8192 /* Can offload UDP Large Send*/ +#define NETIF_F_GEN_CSUM (NETIF_F_NO_CSUM | NETIF_F_HW_CSUM) +#define NETIF_F_ALL_CSUM (NETIF_F_IP_CSUM | NETIF_F_GEN_CSUM) + struct net_device *next_sched; /* Interface index. Unique device identifier */ @@ -405,7 +409,7 @@ struct net_device * One part is mostly used on xmit path (device) */ /* hard_start_xmit synchronizer */ - spinlock_t xmit_lock ____cacheline_aligned_in_smp; + spinlock_t _xmit_lock ____cacheline_aligned_in_smp; /* cpu id of processor entered to hard_start_xmit or -1, if nobody entered there. */ @@ -592,6 +596,9 @@ struct softnet_data struct sk_buff *completion_queue; struct net_device backlog_dev; /* Sorry. 8) */ +#ifdef CONFIG_NET_DMA + struct dma_chan *net_dma; +#endif }; DECLARE_PER_CPU(struct softnet_data,softnet_data); @@ -888,11 +895,43 @@ static inline void __netif_rx_complete(struct net_device *dev) clear_bit(__LINK_STATE_RX_SCHED, &dev->state); } +static inline void netif_tx_lock(struct net_device *dev) +{ + spin_lock(&dev->_xmit_lock); + dev->xmit_lock_owner = smp_processor_id(); +} + +static inline void netif_tx_lock_bh(struct net_device *dev) +{ + spin_lock_bh(&dev->_xmit_lock); + dev->xmit_lock_owner = smp_processor_id(); +} + +static inline int netif_tx_trylock(struct net_device *dev) +{ + int err = spin_trylock(&dev->_xmit_lock); + if (!err) + dev->xmit_lock_owner = smp_processor_id(); + return err; +} + +static inline void netif_tx_unlock(struct net_device *dev) +{ + dev->xmit_lock_owner = -1; + spin_unlock(&dev->_xmit_lock); +} + +static inline void netif_tx_unlock_bh(struct net_device *dev) +{ + dev->xmit_lock_owner = -1; + spin_unlock_bh(&dev->_xmit_lock); +} + static inline void netif_tx_disable(struct net_device *dev) { - spin_lock_bh(&dev->xmit_lock); + netif_tx_lock_bh(dev); netif_stop_queue(dev); - spin_unlock_bh(&dev->xmit_lock); + netif_tx_unlock_bh(dev); } /* These functions live elsewhere (drivers/net/net_init.c, but related) */ diff --git a/include/linux/netfilter/nf_conntrack_common.h b/include/linux/netfilter/nf_conntrack_common.h index 3ff88c878308..d2e4bd7a7a14 100644 --- a/include/linux/netfilter/nf_conntrack_common.h +++ b/include/linux/netfilter/nf_conntrack_common.h @@ -69,6 +69,10 @@ enum ip_conntrack_status { /* Connection is dying (removed from lists), can not be unset. */ IPS_DYING_BIT = 9, IPS_DYING = (1 << IPS_DYING_BIT), + + /* Connection has fixed timeout. */ + IPS_FIXED_TIMEOUT_BIT = 10, + IPS_FIXED_TIMEOUT = (1 << IPS_FIXED_TIMEOUT_BIT), }; /* Connection tracking event bits */ diff --git a/include/linux/netfilter/nfnetlink_conntrack.h b/include/linux/netfilter/nfnetlink_conntrack.h index 668ec946c8e2..b5883ccee295 100644 --- a/include/linux/netfilter/nfnetlink_conntrack.h +++ b/include/linux/netfilter/nfnetlink_conntrack.h @@ -27,13 +27,15 @@ enum ctattr_type { CTA_STATUS, CTA_PROTOINFO, CTA_HELP, - CTA_NAT, + CTA_NAT_SRC, +#define CTA_NAT CTA_NAT_SRC /* backwards compatibility */ CTA_TIMEOUT, CTA_MARK, CTA_COUNTERS_ORIG, CTA_COUNTERS_REPLY, CTA_USE, CTA_ID, + CTA_NAT_DST, __CTA_MAX }; #define CTA_MAX (__CTA_MAX - 1) diff --git a/include/linux/netfilter/xt_CONNSECMARK.h b/include/linux/netfilter/xt_CONNSECMARK.h new file mode 100644 index 000000000000..c6bd75469ba2 --- /dev/null +++ b/include/linux/netfilter/xt_CONNSECMARK.h @@ -0,0 +1,13 @@ +#ifndef _XT_CONNSECMARK_H_target +#define _XT_CONNSECMARK_H_target + +enum { + CONNSECMARK_SAVE = 1, + CONNSECMARK_RESTORE, +}; + +struct xt_connsecmark_target_info { + u_int8_t mode; +}; + +#endif /*_XT_CONNSECMARK_H_target */ diff --git a/include/linux/netfilter/xt_SECMARK.h b/include/linux/netfilter/xt_SECMARK.h new file mode 100644 index 000000000000..c53fbffa997d --- /dev/null +++ b/include/linux/netfilter/xt_SECMARK.h @@ -0,0 +1,26 @@ +#ifndef _XT_SECMARK_H_target +#define _XT_SECMARK_H_target + +/* + * This is intended for use by various security subsystems (but not + * at the same time). + * + * 'mode' refers to the specific security subsystem which the + * packets are being marked for. + */ +#define SECMARK_MODE_SEL 0x01 /* SELinux */ +#define SECMARK_SELCTX_MAX 256 + +struct xt_secmark_target_selinux_info { + u_int32_t selsid; + char selctx[SECMARK_SELCTX_MAX]; +}; + +struct xt_secmark_target_info { + u_int8_t mode; + union { + struct xt_secmark_target_selinux_info sel; + } u; +}; + +#endif /*_XT_SECMARK_H_target */ diff --git a/include/linux/netfilter/xt_quota.h b/include/linux/netfilter/xt_quota.h new file mode 100644 index 000000000000..acd7fd77bbee --- /dev/null +++ b/include/linux/netfilter/xt_quota.h @@ -0,0 +1,16 @@ +#ifndef _XT_QUOTA_H +#define _XT_QUOTA_H + +enum xt_quota_flags { + XT_QUOTA_INVERT = 0x1, +}; +#define XT_QUOTA_MASK 0x1 + +struct xt_quota_info { + u_int32_t flags; + u_int32_t pad; + aligned_u64 quota; + struct xt_quota_info *master; +}; + +#endif /* _XT_QUOTA_H */ diff --git a/include/linux/netfilter/xt_statistic.h b/include/linux/netfilter/xt_statistic.h new file mode 100644 index 000000000000..c344e9916e23 --- /dev/null +++ b/include/linux/netfilter/xt_statistic.h @@ -0,0 +1,32 @@ +#ifndef _XT_STATISTIC_H +#define _XT_STATISTIC_H + +enum xt_statistic_mode { + XT_STATISTIC_MODE_RANDOM, + XT_STATISTIC_MODE_NTH, + __XT_STATISTIC_MODE_MAX +}; +#define XT_STATISTIC_MODE_MAX (__XT_STATISTIC_MODE_MAX - 1) + +enum xt_statistic_flags { + XT_STATISTIC_INVERT = 0x1, +}; +#define XT_STATISTIC_MASK 0x1 + +struct xt_statistic_info { + u_int16_t mode; + u_int16_t flags; + union { + struct { + u_int32_t probability; + } random; + struct { + u_int32_t every; + u_int32_t packet; + u_int32_t count; + } nth; + } u; + struct xt_statistic_info *master __attribute__((aligned(8))); +}; + +#endif /* _XT_STATISTIC_H */ diff --git a/include/linux/netfilter_ipv4/ip_conntrack.h b/include/linux/netfilter_ipv4/ip_conntrack.h index 4255bfec0920..51dbec1892c8 100644 --- a/include/linux/netfilter_ipv4/ip_conntrack.h +++ b/include/linux/netfilter_ipv4/ip_conntrack.h @@ -120,6 +120,10 @@ struct ip_conntrack u_int32_t mark; #endif +#ifdef CONFIG_IP_NF_CONNTRACK_SECMARK + u_int32_t secmark; +#endif + /* Traversed often, so hopefully in different cacheline to top */ /* These are my tuples; original and reply */ struct ip_conntrack_tuple_hash tuplehash[IP_CT_DIR_MAX]; @@ -153,6 +157,7 @@ struct ip_conntrack_expect unsigned int flags; #ifdef CONFIG_IP_NF_NAT_NEEDED + u_int32_t saved_ip; /* This is the original per-proto part, used to map the * expected connection the way the recipient expects. */ union ip_conntrack_manip_proto saved_proto; @@ -292,6 +297,7 @@ static inline int is_dying(struct ip_conntrack *ct) } extern unsigned int ip_conntrack_htable_size; +extern int ip_conntrack_checksum; #define CONNTRACK_STAT_INC(count) (__get_cpu_var(ip_conntrack_stat).count++) diff --git a/include/linux/netfilter_ipv4/ip_conntrack_h323.h b/include/linux/netfilter_ipv4/ip_conntrack_h323.h index eace86bd2adb..3cbff7379002 100644 --- a/include/linux/netfilter_ipv4/ip_conntrack_h323.h +++ b/include/linux/netfilter_ipv4/ip_conntrack_h323.h @@ -71,6 +71,13 @@ extern int (*nat_h245_hook) (struct sk_buff ** pskb, struct ip_conntrack * ct, unsigned char **data, int dataoff, TransportAddress * addr, u_int16_t port, struct ip_conntrack_expect * exp); +extern int (*nat_callforwarding_hook) (struct sk_buff ** pskb, + struct ip_conntrack * ct, + enum ip_conntrack_info ctinfo, + unsigned char **data, int dataoff, + TransportAddress * addr, + u_int16_t port, + struct ip_conntrack_expect * exp); extern int (*nat_q931_hook) (struct sk_buff ** pskb, struct ip_conntrack * ct, enum ip_conntrack_info ctinfo, unsigned char **data, TransportAddress * addr, diff --git a/include/linux/netfilter_ipv4/ip_conntrack_helper_h323_types.h b/include/linux/netfilter_ipv4/ip_conntrack_helper_h323_types.h index cc98f7aa5abe..3d4a773799fc 100644 --- a/include/linux/netfilter_ipv4/ip_conntrack_helper_h323_types.h +++ b/include/linux/netfilter_ipv4/ip_conntrack_helper_h323_types.h @@ -1,4 +1,4 @@ -/* Generated by Jing Min Zhao's ASN.1 parser, Mar 15 2006 +/* Generated by Jing Min Zhao's ASN.1 parser, Apr 20 2006 * * Copyright (c) 2006 Jing Min Zhao <zhaojingmin@users.sourceforge.net> * @@ -412,6 +412,7 @@ typedef struct Facility_UUIE { /* SEQUENCE */ eFacility_UUIE_destinationInfo = (1 << 14), eFacility_UUIE_h245SecurityMode = (1 << 13), } options; + TransportAddress alternativeAddress; FacilityReason reason; TransportAddress h245Address; Facility_UUIE_fastStart fastStart; diff --git a/include/linux/netfilter_ipv4/ip_conntrack_sip.h b/include/linux/netfilter_ipv4/ip_conntrack_sip.h new file mode 100644 index 000000000000..913dad66c0fb --- /dev/null +++ b/include/linux/netfilter_ipv4/ip_conntrack_sip.h @@ -0,0 +1,44 @@ +#ifndef __IP_CONNTRACK_SIP_H__ +#define __IP_CONNTRACK_SIP_H__ +#ifdef __KERNEL__ + +#define SIP_PORT 5060 +#define SIP_TIMEOUT 3600 + +#define POS_VIA 0 +#define POS_CONTACT 1 +#define POS_CONTENT 2 +#define POS_MEDIA 3 +#define POS_OWNER 4 +#define POS_CONNECTION 5 +#define POS_REQ_HEADER 6 +#define POS_SDP_HEADER 7 + +struct sip_header_nfo { + const char *lname; + const char *sname; + const char *ln_str; + size_t lnlen; + size_t snlen; + size_t ln_strlen; + int (*match_len)(const char *, const char *, int *); +}; + +extern unsigned int (*ip_nat_sip_hook)(struct sk_buff **pskb, + enum ip_conntrack_info ctinfo, + struct ip_conntrack *ct, + const char **dptr); +extern unsigned int (*ip_nat_sdp_hook)(struct sk_buff **pskb, + enum ip_conntrack_info ctinfo, + struct ip_conntrack_expect *exp, + const char *dptr); + +extern int ct_sip_get_info(const char *dptr, size_t dlen, + unsigned int *matchoff, + unsigned int *matchlen, + struct sip_header_nfo *hnfo); +extern int ct_sip_lnlen(const char *line, const char *limit); +extern const char *ct_sip_search(const char *needle, const char *haystack, + size_t needle_len, size_t haystack_len); +#endif /* __KERNEL__ */ +#endif /* __IP_CONNTRACK_SIP_H__ */ diff --git a/include/linux/pci-acpi.h b/include/linux/pci-acpi.h index 4877e35ae202..936ef82ed76a 100644 --- a/include/linux/pci-acpi.h +++ b/include/linux/pci-acpi.h @@ -50,7 +50,7 @@ extern acpi_status pci_osc_control_set(acpi_handle handle, u32 flags); extern acpi_status pci_osc_support_set(u32 flags); #else -#if !defined(acpi_status) +#if !defined(AE_ERROR) typedef u32 acpi_status; #define AE_ERROR (acpi_status) (0x0001) #endif diff --git a/include/linux/pci.h b/include/linux/pci.h index fee8275df6d8..6c4bc773f7b7 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -441,6 +441,7 @@ struct pci_dev *pci_find_device_reverse (unsigned int vendor, unsigned int devic struct pci_dev *pci_find_slot (unsigned int bus, unsigned int devfn); int pci_find_capability (struct pci_dev *dev, int cap); int pci_find_next_capability (struct pci_dev *dev, u8 pos, int cap); +int pci_find_ext_capability (struct pci_dev *dev, int cap); struct pci_bus * pci_find_next_bus(const struct pci_bus *from); struct pci_dev *pci_get_device (unsigned int vendor, unsigned int device, struct pci_dev *from); @@ -661,6 +662,7 @@ static inline int pci_register_driver(struct pci_driver *drv) { return 0;} static inline void pci_unregister_driver(struct pci_driver *drv) { } static inline int pci_find_capability (struct pci_dev *dev, int cap) {return 0; } static inline int pci_find_next_capability (struct pci_dev *dev, u8 post, int cap) { return 0; } +static inline int pci_find_ext_capability (struct pci_dev *dev, int cap) {return 0; } static inline const struct pci_device_id *pci_match_device(const struct pci_device_id *ids, const struct pci_dev *dev) { return NULL; } /* Power management related routines */ diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index d6fe048376ab..bcfe9d4f56ae 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -935,6 +935,7 @@ #define PCI_DEVICE_ID_PLX_DJINN_ITOO 0x1151 #define PCI_DEVICE_ID_PLX_R753 0x1152 #define PCI_DEVICE_ID_PLX_OLITEC 0x1187 +#define PCI_DEVICE_ID_PLX_PCI200SYN 0x3196 #define PCI_DEVICE_ID_PLX_9050 0x9050 #define PCI_DEVICE_ID_PLX_9080 0x9080 #define PCI_DEVICE_ID_PLX_GTEK_SERIAL2 0xa001 @@ -1182,6 +1183,14 @@ #define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1100 0x034E #define PCI_DEVICE_ID_NVIDIA_NVENET_14 0x0372 #define PCI_DEVICE_ID_NVIDIA_NVENET_15 0x0373 +#define PCI_DEVICE_ID_NVIDIA_NVENET_16 0x03E5 +#define PCI_DEVICE_ID_NVIDIA_NVENET_17 0x03E6 +#define PCI_DEVICE_ID_NVIDIA_NVENET_18 0x03EE +#define PCI_DEVICE_ID_NVIDIA_NVENET_19 0x03EF +#define PCI_DEVICE_ID_NVIDIA_NVENET_20 0x0450 +#define PCI_DEVICE_ID_NVIDIA_NVENET_21 0x0451 +#define PCI_DEVICE_ID_NVIDIA_NVENET_22 0x0452 +#define PCI_DEVICE_ID_NVIDIA_NVENET_23 0x0453 #define PCI_VENDOR_ID_IMS 0x10e0 #define PCI_DEVICE_ID_IMS_TT128 0x9128 @@ -1231,6 +1240,7 @@ #define PCI_DEVICE_ID_VIA_8380_0 0x0204 #define PCI_DEVICE_ID_VIA_3238_0 0x0238 #define PCI_DEVICE_ID_VIA_PT880 0x0258 +#define PCI_DEVICE_ID_VIA_PT880ULTRA 0x0308 #define PCI_DEVICE_ID_VIA_PX8X0_0 0x0259 #define PCI_DEVICE_ID_VIA_3269_0 0x0269 #define PCI_DEVICE_ID_VIA_K8T800PRO_0 0x0282 @@ -1826,6 +1836,7 @@ #define PCI_VENDOR_ID_SAMSUNG 0x144d +#define PCI_VENDOR_ID_MYRICOM 0x14c1 #define PCI_VENDOR_ID_TITAN 0x14D2 #define PCI_DEVICE_ID_TITAN_010L 0x8001 @@ -1886,6 +1897,7 @@ #define PCI_DEVICE_ID_TIGON3_5751F 0x167e #define PCI_DEVICE_ID_TIGON3_5787M 0x1693 #define PCI_DEVICE_ID_TIGON3_5782 0x1696 +#define PCI_DEVICE_ID_TIGON3_5786 0x169a #define PCI_DEVICE_ID_TIGON3_5787 0x169b #define PCI_DEVICE_ID_TIGON3_5788 0x169c #define PCI_DEVICE_ID_TIGON3_5789 0x169d @@ -2042,6 +2054,7 @@ #define PCI_DEVICE_ID_INTEL_80960_RP 0x1960 #define PCI_DEVICE_ID_INTEL_82840_HB 0x1a21 #define PCI_DEVICE_ID_INTEL_82845_HB 0x1a30 +#define PCI_DEVICE_ID_INTEL_IOAT 0x1a38 #define PCI_DEVICE_ID_INTEL_82801AA_0 0x2410 #define PCI_DEVICE_ID_INTEL_82801AA_1 0x2411 #define PCI_DEVICE_ID_INTEL_82801AA_3 0x2413 diff --git a/include/linux/pfkeyv2.h b/include/linux/pfkeyv2.h index bac0fb389cf1..d5dd471da225 100644 --- a/include/linux/pfkeyv2.h +++ b/include/linux/pfkeyv2.h @@ -159,7 +159,7 @@ struct sadb_spirange { struct sadb_x_kmprivate { uint16_t sadb_x_kmprivate_len; uint16_t sadb_x_kmprivate_exttype; - u_int32_t sadb_x_kmprivate_reserved; + uint32_t sadb_x_kmprivate_reserved; } __attribute__((packed)); /* sizeof(struct sadb_x_kmprivate) == 8 */ diff --git a/include/linux/rbtree.h b/include/linux/rbtree.h index 4b7cc4fe366d..f37006f21664 100644 --- a/include/linux/rbtree.h +++ b/include/linux/rbtree.h @@ -99,19 +99,36 @@ static inline struct page * rb_insert_page_cache(struct inode * inode, struct rb_node { - struct rb_node *rb_parent; - int rb_color; + unsigned long rb_parent_color; #define RB_RED 0 #define RB_BLACK 1 struct rb_node *rb_right; struct rb_node *rb_left; -}; +} __attribute__((aligned(sizeof(long)))); + /* The alignment might seem pointless, but allegedly CRIS needs it */ struct rb_root { struct rb_node *rb_node; }; + +#define rb_parent(r) ((struct rb_node *)((r)->rb_parent_color & ~3)) +#define rb_color(r) ((r)->rb_parent_color & 1) +#define rb_is_red(r) (!rb_color(r)) +#define rb_is_black(r) rb_color(r) +#define rb_set_red(r) do { (r)->rb_parent_color &= ~1; } while (0) +#define rb_set_black(r) do { (r)->rb_parent_color |= 1; } while (0) + +static inline void rb_set_parent(struct rb_node *rb, struct rb_node *p) +{ + rb->rb_parent_color = (rb->rb_parent_color & 3) | (unsigned long)p; +} +static inline void rb_set_color(struct rb_node *rb, int color) +{ + rb->rb_parent_color = (rb->rb_parent_color & ~1) | color; +} + #define RB_ROOT (struct rb_root) { NULL, } #define rb_entry(ptr, type, member) container_of(ptr, type, member) @@ -131,8 +148,7 @@ extern void rb_replace_node(struct rb_node *victim, struct rb_node *new, static inline void rb_link_node(struct rb_node * node, struct rb_node * parent, struct rb_node ** rb_link) { - node->rb_parent = parent; - node->rb_color = RB_RED; + node->rb_parent_color = (unsigned long )parent; node->rb_left = node->rb_right = NULL; *rb_link = node; diff --git a/include/linux/security.h b/include/linux/security.h index 1bab48f6aeac..4dfb1b84a9b3 100644 --- a/include/linux/security.h +++ b/include/linux/security.h @@ -805,31 +805,37 @@ struct swap_info_struct; * used by the XFRM system. * @sec_ctx contains the security context information being provided by * the user-level policy update program (e.g., setkey). - * Allocate a security structure to the xp->selector.security field. + * Allocate a security structure to the xp->security field. * The security field is initialized to NULL when the xfrm_policy is * allocated. * Return 0 if operation was successful (memory to allocate, legal context) * @xfrm_policy_clone_security: * @old contains an existing xfrm_policy in the SPD. * @new contains a new xfrm_policy being cloned from old. - * Allocate a security structure to the new->selector.security field - * that contains the information from the old->selector.security field. + * Allocate a security structure to the new->security field + * that contains the information from the old->security field. * Return 0 if operation was successful (memory to allocate). * @xfrm_policy_free_security: * @xp contains the xfrm_policy - * Deallocate xp->selector.security. + * Deallocate xp->security. + * @xfrm_policy_delete_security: + * @xp contains the xfrm_policy. + * Authorize deletion of xp->security. * @xfrm_state_alloc_security: * @x contains the xfrm_state being added to the Security Association * Database by the XFRM system. * @sec_ctx contains the security context information being provided by * the user-level SA generation program (e.g., setkey or racoon). - * Allocate a security structure to the x->sel.security field. The + * Allocate a security structure to the x->security field. The * security field is initialized to NULL when the xfrm_state is * allocated. * Return 0 if operation was successful (memory to allocate, legal context). * @xfrm_state_free_security: * @x contains the xfrm_state. - * Deallocate x>sel.security. + * Deallocate x->security. + * @xfrm_state_delete_security: + * @x contains the xfrm_state. + * Authorize deletion of x->security. * @xfrm_policy_lookup: * @xp contains the xfrm_policy for which the access control is being * checked. @@ -1298,8 +1304,10 @@ struct security_operations { int (*xfrm_policy_alloc_security) (struct xfrm_policy *xp, struct xfrm_user_sec_ctx *sec_ctx); int (*xfrm_policy_clone_security) (struct xfrm_policy *old, struct xfrm_policy *new); void (*xfrm_policy_free_security) (struct xfrm_policy *xp); + int (*xfrm_policy_delete_security) (struct xfrm_policy *xp); int (*xfrm_state_alloc_security) (struct xfrm_state *x, struct xfrm_user_sec_ctx *sec_ctx); void (*xfrm_state_free_security) (struct xfrm_state *x); + int (*xfrm_state_delete_security) (struct xfrm_state *x); int (*xfrm_policy_lookup)(struct xfrm_policy *xp, u32 sk_sid, u8 dir); #endif /* CONFIG_SECURITY_NETWORK_XFRM */ @@ -2934,11 +2942,21 @@ static inline void security_xfrm_policy_free(struct xfrm_policy *xp) security_ops->xfrm_policy_free_security(xp); } +static inline int security_xfrm_policy_delete(struct xfrm_policy *xp) +{ + return security_ops->xfrm_policy_delete_security(xp); +} + static inline int security_xfrm_state_alloc(struct xfrm_state *x, struct xfrm_user_sec_ctx *sec_ctx) { return security_ops->xfrm_state_alloc_security(x, sec_ctx); } +static inline int security_xfrm_state_delete(struct xfrm_state *x) +{ + return security_ops->xfrm_state_delete_security(x); +} + static inline void security_xfrm_state_free(struct xfrm_state *x) { security_ops->xfrm_state_free_security(x); @@ -2963,6 +2981,11 @@ static inline void security_xfrm_policy_free(struct xfrm_policy *xp) { } +static inline int security_xfrm_policy_delete(struct xfrm_policy *xp) +{ + return 0; +} + static inline int security_xfrm_state_alloc(struct xfrm_state *x, struct xfrm_user_sec_ctx *sec_ctx) { return 0; @@ -2972,6 +2995,11 @@ static inline void security_xfrm_state_free(struct xfrm_state *x) { } +static inline int security_xfrm_state_delete(struct xfrm_state *x) +{ + return 0; +} + static inline int security_xfrm_policy_lookup(struct xfrm_policy *xp, u32 sk_sid, u8 dir) { return 0; diff --git a/include/linux/selinux.h b/include/linux/selinux.h index 4047bcde4484..aad4e390d6a5 100644 --- a/include/linux/selinux.h +++ b/include/linux/selinux.h @@ -118,6 +118,27 @@ void selinux_get_ipc_sid(const struct kern_ipc_perm *ipcp, u32 *sid); */ void selinux_get_task_sid(struct task_struct *tsk, u32 *sid); +/** + * selinux_string_to_sid - map a security context string to a security ID + * @str: the security context string to be mapped + * @sid: ID value returned via this. + * + * Returns 0 if successful, with the SID stored in sid. A value + * of zero for sid indicates no SID could be determined (but no error + * occurred). + */ +int selinux_string_to_sid(char *str, u32 *sid); + +/** + * selinux_relabel_packet_permission - check permission to relabel a packet + * @sid: ID value to be applied to network packet (via SECMARK, most likely) + * + * Returns 0 if the current task is allowed to label packets with the + * supplied security ID. Note that it is implicit that the packet is always + * being relabeled from the default unlabled value, and that the access + * control decision is made in the AVC. + */ +int selinux_relabel_packet_permission(u32 sid); #else @@ -172,6 +193,17 @@ static inline void selinux_get_task_sid(struct task_struct *tsk, u32 *sid) *sid = 0; } +static inline int selinux_string_to_sid(const char *str, u32 *sid) +{ + *sid = 0; + return 0; +} + +static inline int selinux_relabel_packet_permission(u32 sid) +{ + return 0; +} + #endif /* CONFIG_SECURITY_SELINUX */ #endif /* _LINUX_SELINUX_H */ diff --git a/include/linux/skbuff.h b/include/linux/skbuff.h index 4dc65b55812e..66f8819f9568 100644 --- a/include/linux/skbuff.h +++ b/include/linux/skbuff.h @@ -28,6 +28,7 @@ #include <linux/net.h> #include <linux/textsearch.h> #include <net/checksum.h> +#include <linux/dmaengine.h> #define HAVE_ALLOC_SKB /* For the drivers to know */ #define HAVE_ALIGNABLE_SKB /* Ditto 8) */ @@ -208,6 +209,7 @@ enum { * @nf_bridge: Saved data about a bridged frame - see br_netfilter.c * @tc_index: Traffic control index * @tc_verd: traffic control verdict + * @secmark: security marking */ struct sk_buff { @@ -284,6 +286,12 @@ struct sk_buff { __u16 tc_verd; /* traffic control verdict */ #endif #endif +#ifdef CONFIG_NET_DMA + dma_cookie_t dma_cookie; +#endif +#ifdef CONFIG_NETWORK_SECMARK + __u32 secmark; +#endif /* These elements must be at the end, see alloc_skb() for details. */ @@ -966,15 +974,16 @@ static inline void skb_reserve(struct sk_buff *skb, int len) #define NET_SKB_PAD 16 #endif -extern int ___pskb_trim(struct sk_buff *skb, unsigned int len, int realloc); +extern int ___pskb_trim(struct sk_buff *skb, unsigned int len); static inline void __skb_trim(struct sk_buff *skb, unsigned int len) { - if (!skb->data_len) { - skb->len = len; - skb->tail = skb->data + len; - } else - ___pskb_trim(skb, len, 0); + if (unlikely(skb->data_len)) { + WARN_ON(1); + return; + } + skb->len = len; + skb->tail = skb->data + len; } /** @@ -984,6 +993,7 @@ static inline void __skb_trim(struct sk_buff *skb, unsigned int len) * * Cut the length of a buffer down by removing data from the tail. If * the buffer is already under the length specified it is not modified. + * The skb must be linear. */ static inline void skb_trim(struct sk_buff *skb, unsigned int len) { @@ -994,12 +1004,10 @@ static inline void skb_trim(struct sk_buff *skb, unsigned int len) static inline int __pskb_trim(struct sk_buff *skb, unsigned int len) { - if (!skb->data_len) { - skb->len = len; - skb->tail = skb->data+len; - return 0; - } - return ___pskb_trim(skb, len, 1); + if (skb->data_len) + return ___pskb_trim(skb, len); + __skb_trim(skb, len); + return 0; } static inline int pskb_trim(struct sk_buff *skb, unsigned int len) @@ -1160,18 +1168,34 @@ static inline int skb_can_coalesce(struct sk_buff *skb, int i, return 0; } +static inline int __skb_linearize(struct sk_buff *skb) +{ + return __pskb_pull_tail(skb, skb->data_len) ? 0 : -ENOMEM; +} + /** * skb_linearize - convert paged skb to linear one * @skb: buffer to linarize - * @gfp: allocation mode * * If there is no free memory -ENOMEM is returned, otherwise zero * is returned and the old skb data released. */ -extern int __skb_linearize(struct sk_buff *skb, gfp_t gfp); -static inline int skb_linearize(struct sk_buff *skb, gfp_t gfp) +static inline int skb_linearize(struct sk_buff *skb) +{ + return skb_is_nonlinear(skb) ? __skb_linearize(skb) : 0; +} + +/** + * skb_linearize_cow - make sure skb is linear and writable + * @skb: buffer to process + * + * If there is no free memory -ENOMEM is returned, otherwise zero + * is returned and the old skb data released. + */ +static inline int skb_linearize_cow(struct sk_buff *skb) { - return __skb_linearize(skb, gfp); + return skb_is_nonlinear(skb) || skb_cloned(skb) ? + __skb_linearize(skb) : 0; } /** @@ -1395,5 +1419,23 @@ static inline void nf_reset(struct sk_buff *skb) static inline void nf_reset(struct sk_buff *skb) {} #endif /* CONFIG_NETFILTER */ +#ifdef CONFIG_NETWORK_SECMARK +static inline void skb_copy_secmark(struct sk_buff *to, const struct sk_buff *from) +{ + to->secmark = from->secmark; +} + +static inline void skb_init_secmark(struct sk_buff *skb) +{ + skb->secmark = 0; +} +#else +static inline void skb_copy_secmark(struct sk_buff *to, const struct sk_buff *from) +{ } + +static inline void skb_init_secmark(struct sk_buff *skb) +{ } +#endif + #endif /* __KERNEL__ */ #endif /* _LINUX_SKBUFF_H */ diff --git a/include/linux/sysctl.h b/include/linux/sysctl.h index 76eaeff76f82..cee944dbdcd4 100644 --- a/include/linux/sysctl.h +++ b/include/linux/sysctl.h @@ -313,6 +313,7 @@ enum NET_NF_CONNTRACK_FRAG6_TIMEOUT=29, NET_NF_CONNTRACK_FRAG6_LOW_THRESH=30, NET_NF_CONNTRACK_FRAG6_HIGH_THRESH=31, + NET_NF_CONNTRACK_CHECKSUM=32, }; /* /proc/sys/net/ipv4 */ @@ -403,6 +404,8 @@ enum NET_TCP_MTU_PROBING=113, NET_TCP_BASE_MSS=114, NET_IPV4_TCP_WORKAROUND_SIGNED_WINDOWS=115, + NET_TCP_DMA_COPYBREAK=116, + NET_TCP_SLOW_START_AFTER_IDLE=117, }; enum { @@ -491,6 +494,7 @@ enum NET_IPV4_NF_CONNTRACK_SCTP_TIMEOUT_SHUTDOWN_RECD=25, NET_IPV4_NF_CONNTRACK_SCTP_TIMEOUT_SHUTDOWN_ACK_SENT=26, NET_IPV4_NF_CONNTRACK_COUNT=27, + NET_IPV4_NF_CONNTRACK_CHECKSUM=28, }; /* /proc/sys/net/ipv6 */ diff --git a/include/linux/tcp.h b/include/linux/tcp.h index a8b24eff5b5f..420a689c3fb4 100644 --- a/include/linux/tcp.h +++ b/include/linux/tcp.h @@ -18,6 +18,7 @@ #define _LINUX_TCP_H #include <linux/types.h> +#include <linux/dmaengine.h> #include <asm/byteorder.h> struct tcphdr { @@ -232,6 +233,13 @@ struct tcp_sock { struct iovec *iov; int memory; int len; +#ifdef CONFIG_NET_DMA + /* members for async copy */ + struct dma_chan *dma_chan; + int wakeup; + struct dma_pinned_list *pinned_list; + dma_cookie_t dma_cookie; +#endif } ucopy; __u32 snd_wl1; /* Sequence for window update */ diff --git a/include/linux/vt_kern.h b/include/linux/vt_kern.h index 6ef527bb6235..940d0261a545 100644 --- a/include/linux/vt_kern.h +++ b/include/linux/vt_kern.h @@ -72,11 +72,6 @@ int con_copy_unimap(struct vc_data *dst_vc, struct vc_data *src_vc); int vt_waitactive(int vt); void change_console(struct vc_data *new_vc); void reset_vc(struct vc_data *vc); -#ifdef CONFIG_VT -int is_console_suspend_safe(void); -#else -static inline int is_console_suspend_safe(void) { return 1; } -#endif /* * vc_screen.c shares this temporary buffer with the console write code so that diff --git a/include/linux/xfrm.h b/include/linux/xfrm.h index 6b42cc474c01..46a15c7a1a13 100644 --- a/include/linux/xfrm.h +++ b/include/linux/xfrm.h @@ -118,6 +118,10 @@ enum XFRM_SHARE_UNIQUE /* Use once */ }; +#define XFRM_MODE_TRANSPORT 0 +#define XFRM_MODE_TUNNEL 1 +#define XFRM_MODE_MAX 2 + /* Netlink configuration messages. */ enum { XFRM_MSG_BASE = 0x10, diff --git a/include/mtd/mtd-abi.h b/include/mtd/mtd-abi.h index 9fd8c720a803..31329fce1ff5 100644 --- a/include/mtd/mtd-abi.h +++ b/include/mtd/mtd-abi.h @@ -29,28 +29,17 @@ struct mtd_oob_buf { #define MTD_ROM 2 #define MTD_NORFLASH 3 #define MTD_NANDFLASH 4 -#define MTD_PEROM 5 #define MTD_DATAFLASH 6 -#define MTD_OTHER 14 -#define MTD_UNKNOWN 15 - -#define MTD_CLEAR_BITS 1 // Bits can be cleared (flash) -#define MTD_SET_BITS 2 // Bits can be set -#define MTD_ERASEABLE 4 // Has an erase function -#define MTD_WRITEB_WRITEABLE 8 // Direct IO is possible -#define MTD_VOLATILE 16 // Set for RAMs -#define MTD_XIP 32 // eXecute-In-Place possible -#define MTD_OOB 64 // Out-of-band data (NAND flash) -#define MTD_ECC 128 // Device capable of automatic ECC -#define MTD_NO_VIRTBLOCKS 256 // Virtual blocks not allowed -#define MTD_PROGRAM_REGIONS 512 // Configurable Programming Regions + +#define MTD_WRITEABLE 0x400 /* Device is writeable */ +#define MTD_BIT_WRITEABLE 0x800 /* Single bits can be flipped */ +#define MTD_NO_ERASE 0x1000 /* No erase necessary */ // Some common devices / combinations of capabilities #define MTD_CAP_ROM 0 -#define MTD_CAP_RAM (MTD_CLEAR_BITS|MTD_SET_BITS|MTD_WRITEB_WRITEABLE) -#define MTD_CAP_NORFLASH (MTD_CLEAR_BITS|MTD_ERASEABLE) -#define MTD_CAP_NANDFLASH (MTD_CLEAR_BITS|MTD_ERASEABLE|MTD_OOB) -#define MTD_WRITEABLE (MTD_CLEAR_BITS|MTD_SET_BITS) +#define MTD_CAP_RAM (MTD_WRITEABLE | MTD_BIT_WRITEABLE | MTD_NO_ERASE) +#define MTD_CAP_NORFLASH (MTD_WRITEABLE | MTD_BIT_WRITEABLE) +#define MTD_CAP_NANDFLASH (MTD_WRITEABLE) // Types of automatic ECC/Checksum available @@ -75,7 +64,7 @@ struct mtd_info_user { uint32_t flags; uint32_t size; // Total size of the MTD uint32_t erasesize; - uint32_t oobblock; // Size of OOB blocks (e.g. 512) + uint32_t writesize; uint32_t oobsize; // Amount of OOB data per block (e.g. 16) uint32_t ecctype; uint32_t eccsize; @@ -95,12 +84,12 @@ struct otp_info { uint32_t locked; }; -#define MEMGETINFO _IOR('M', 1, struct mtd_info_user) -#define MEMERASE _IOW('M', 2, struct erase_info_user) -#define MEMWRITEOOB _IOWR('M', 3, struct mtd_oob_buf) -#define MEMREADOOB _IOWR('M', 4, struct mtd_oob_buf) -#define MEMLOCK _IOW('M', 5, struct erase_info_user) -#define MEMUNLOCK _IOW('M', 6, struct erase_info_user) +#define MEMGETINFO _IOR('M', 1, struct mtd_info_user) +#define MEMERASE _IOW('M', 2, struct erase_info_user) +#define MEMWRITEOOB _IOWR('M', 3, struct mtd_oob_buf) +#define MEMREADOOB _IOWR('M', 4, struct mtd_oob_buf) +#define MEMLOCK _IOW('M', 5, struct erase_info_user) +#define MEMUNLOCK _IOW('M', 6, struct erase_info_user) #define MEMGETREGIONCOUNT _IOR('M', 7, int) #define MEMGETREGIONINFO _IOWR('M', 8, struct region_info_user) #define MEMSETOOBSEL _IOW('M', 9, struct nand_oobinfo) @@ -110,8 +99,15 @@ struct otp_info { #define OTPSELECT _IOR('M', 13, int) #define OTPGETREGIONCOUNT _IOW('M', 14, int) #define OTPGETREGIONINFO _IOW('M', 15, struct otp_info) -#define OTPLOCK _IOR('M', 16, struct otp_info) +#define OTPLOCK _IOR('M', 16, struct otp_info) +#define ECCGETLAYOUT _IOR('M', 17, struct nand_ecclayout) +#define ECCGETSTATS _IOR('M', 18, struct mtd_ecc_stats) +#define MTDFILEMODE _IO('M', 19) +/* + * Obsolete legacy interface. Keep it in order not to break userspace + * interfaces + */ struct nand_oobinfo { uint32_t useecc; uint32_t eccbytes; @@ -119,4 +115,46 @@ struct nand_oobinfo { uint32_t eccpos[32]; }; +struct nand_oobfree { + uint32_t offset; + uint32_t length; +}; + +#define MTD_MAX_OOBFREE_ENTRIES 8 +/* + * ECC layout control structure. Exported to userspace for + * diagnosis and to allow creation of raw images + */ +struct nand_ecclayout { + uint32_t eccbytes; + uint32_t eccpos[64]; + uint32_t oobavail; + struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES]; +}; + +/** + * struct mtd_ecc_stats - error correction status + * + * @corrected: number of corrected bits + * @failed: number of uncorrectable errors + * @badblocks: number of bad blocks in this partition + * @bbtblocks: number of blocks reserved for bad block tables + */ +struct mtd_ecc_stats { + uint32_t corrected; + uint32_t failed; + uint32_t badblocks; + uint32_t bbtblocks; +}; + +/* + * Read/write file modes for access to MTD + */ +enum mtd_file_modes { + MTD_MODE_NORMAL = MTD_OTP_OFF, + MTD_MODE_OTP_FACTORY = MTD_OTP_FACTORY, + MTD_MODE_OTP_USER = MTD_OTP_USER, + MTD_MODE_RAW, +}; + #endif /* __MTD_ABI_H__ */ diff --git a/include/mtd/mtd-user.h b/include/mtd/mtd-user.h index 1c13fc7161fe..713f34d3e62e 100644 --- a/include/mtd/mtd-user.h +++ b/include/mtd/mtd-user.h @@ -16,5 +16,6 @@ typedef struct mtd_info_user mtd_info_t; typedef struct erase_info_user erase_info_t; typedef struct region_info_user region_info_t; typedef struct nand_oobinfo nand_oobinfo_t; +typedef struct nand_ecclayout nand_ecclayout_t; #endif /* __MTD_USER_H__ */ diff --git a/include/net/compat.h b/include/net/compat.h index da680272cf6e..9859b60280d5 100644 --- a/include/net/compat.h +++ b/include/net/compat.h @@ -2,6 +2,8 @@ #define NET_COMPAT_H +struct sock; + #if defined(CONFIG_COMPAT) #include <linux/compat.h> @@ -22,7 +24,6 @@ struct compat_cmsghdr { compat_int_t cmsg_type; }; -struct sock; extern int compat_sock_get_timestamp(struct sock *, struct timeval __user *); #else /* defined(CONFIG_COMPAT) */ diff --git a/include/net/ieee80211.h b/include/net/ieee80211.h index d5926bfb1fc9..d5147770ad47 100644 --- a/include/net/ieee80211.h +++ b/include/net/ieee80211.h @@ -29,7 +29,7 @@ #include <linux/kernel.h> /* ARRAY_SIZE */ #include <linux/wireless.h> -#define IEEE80211_VERSION "git-1.1.7" +#define IEEE80211_VERSION "git-1.1.13" #define IEEE80211_DATA_LEN 2304 /* Maximum size for the MA-UNITDATA primitive, 802.11 standard section @@ -104,6 +104,9 @@ #define IEEE80211_SCTL_FRAG 0x000F #define IEEE80211_SCTL_SEQ 0xFFF0 +/* QOS control */ +#define IEEE80211_QCTL_TID 0x000F + /* debug macros */ #ifdef CONFIG_IEEE80211_DEBUG @@ -1075,6 +1078,7 @@ struct ieee80211_device { int (*handle_management) (struct net_device * dev, struct ieee80211_network * network, u16 type); + int (*is_qos_active) (struct net_device *dev, struct sk_buff *skb); /* Typical STA methods */ int (*handle_auth) (struct net_device * dev, @@ -1243,7 +1247,8 @@ extern int ieee80211_set_encryption(struct ieee80211_device *ieee); extern int ieee80211_xmit(struct sk_buff *skb, struct net_device *dev); extern void ieee80211_txb_free(struct ieee80211_txb *); extern int ieee80211_tx_frame(struct ieee80211_device *ieee, - struct ieee80211_hdr *frame, int len); + struct ieee80211_hdr *frame, int hdr_len, + int total_len, int encrypt_mpdu); /* ieee80211_rx.c */ extern int ieee80211_rx(struct ieee80211_device *ieee, struct sk_buff *skb, diff --git a/include/net/ieee80211softmac.h b/include/net/ieee80211softmac.h index 052ed596a4e4..7a483ab4022f 100644 --- a/include/net/ieee80211softmac.h +++ b/include/net/ieee80211softmac.h @@ -86,6 +86,9 @@ struct ieee80211softmac_assoc_info { /* BSSID we're trying to associate to */ char bssid[ETH_ALEN]; + + /* Rates supported by the network */ + struct ieee80211softmac_ratesinfo supported_rates; /* some flags. * static_essid is valid if the essid is constant, @@ -132,23 +135,26 @@ enum { struct ieee80211softmac_txrates { /* The Bit-Rate to be used for multicast frames. */ u8 mcast_rate; - /* The Bit-Rate to be used for multicast fallback - * (If the device supports fallback and hardware-retry) - */ - u8 mcast_fallback; + + /* The Bit-Rate to be used for multicast management frames. */ + u8 mgt_mcast_rate; + /* The Bit-Rate to be used for any other (normal) data packet. */ u8 default_rate; /* The Bit-Rate to be used for default fallback * (If the device supports fallback and hardware-retry) */ u8 default_fallback; + + /* This is the rate that the user asked for */ + u8 user_rate; }; /* Bits for txrates_change callback. */ #define IEEE80211SOFTMAC_TXRATECHG_DEFAULT (1 << 0) /* default_rate */ #define IEEE80211SOFTMAC_TXRATECHG_DEFAULT_FBACK (1 << 1) /* default_fallback */ #define IEEE80211SOFTMAC_TXRATECHG_MCAST (1 << 2) /* mcast_rate */ -#define IEEE80211SOFTMAC_TXRATECHG_MCAST_FBACK (1 << 3) /* mcast_fallback */ +#define IEEE80211SOFTMAC_TXRATECHG_MGT_MCAST (1 << 3) /* mgt_mcast_rate */ struct ieee80211softmac_device { /* 802.11 structure for data stuff */ @@ -250,6 +256,28 @@ extern void ieee80211softmac_fragment_lost(struct net_device *dev, * Note that the rates need to be sorted. */ extern void ieee80211softmac_set_rates(struct net_device *dev, u8 count, u8 *rates); +/* Helper function which advises you the rate at which a frame should be + * transmitted at. */ +static inline u8 ieee80211softmac_suggest_txrate(struct ieee80211softmac_device *mac, + int is_multicast, + int is_mgt) +{ + struct ieee80211softmac_txrates *txrates = &mac->txrates; + + if (!mac->associated) + return txrates->mgt_mcast_rate; + + /* We are associated, sending unicast frame */ + if (!is_multicast) + return txrates->default_rate; + + /* We are associated, sending multicast frame */ + if (is_mgt) + return txrates->mgt_mcast_rate; + else + return txrates->mcast_rate; +} + /* Start the SoftMAC. Call this after you initialized the device * and it is ready to run. */ @@ -282,7 +310,7 @@ extern void ieee80211softmac_stop(struct net_device *dev); * - context set to the context data you want passed * The return value is 0, or an error. */ -typedef void (*notify_function_ptr)(struct net_device *dev, void *context); +typedef void (*notify_function_ptr)(struct net_device *dev, int event_type, void *context); #define ieee80211softmac_notify(dev, event, fun, context) ieee80211softmac_notify_gfp(dev, event, fun, context, GFP_KERNEL); #define ieee80211softmac_notify_atomic(dev, event, fun, context) ieee80211softmac_notify_gfp(dev, event, fun, context, GFP_ATOMIC); diff --git a/include/net/ieee80211softmac_wx.h b/include/net/ieee80211softmac_wx.h index 3e0be453ecea..4ee3ad57283f 100644 --- a/include/net/ieee80211softmac_wx.h +++ b/include/net/ieee80211softmac_wx.h @@ -91,4 +91,9 @@ ieee80211softmac_wx_get_genie(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra); +extern int +ieee80211softmac_wx_set_mlme(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, + char *extra); #endif /* _IEEE80211SOFTMAC_WX */ diff --git a/include/net/ip.h b/include/net/ip.h index 3900fccf60c7..98f908400771 100644 --- a/include/net/ip.h +++ b/include/net/ip.h @@ -146,7 +146,6 @@ void ip_send_reply(struct sock *sk, struct sk_buff *skb, struct ip_reply_arg *ar struct ipv4_config { int log_martians; - int autoconfig; int no_pmtu_disc; }; diff --git a/include/net/llc_if.h b/include/net/llc_if.h index 090eaa0d71f9..c608812a8e89 100644 --- a/include/net/llc_if.h +++ b/include/net/llc_if.h @@ -16,6 +16,7 @@ #include <linux/if.h> #include <linux/if_arp.h> #include <linux/llc.h> +#include <linux/etherdevice.h> #include <net/llc.h> #define LLC_DATAUNIT_PRIM 1 @@ -61,8 +62,6 @@ #define LLC_STATUS_CONFLICT 7 /* disconnect conn */ #define LLC_STATUS_RESET_DONE 8 /* */ -extern u8 llc_mac_null_var[IFHWADDRLEN]; - /** * llc_mac_null - determines if a address is a null mac address * @mac: Mac address to test if null. @@ -70,16 +69,20 @@ extern u8 llc_mac_null_var[IFHWADDRLEN]; * Determines if a given address is a null mac address. Returns 0 if the * address is not a null mac, 1 if the address is a null mac. */ -static __inline__ int llc_mac_null(u8 *mac) +static inline int llc_mac_null(const u8 *mac) { - return !memcmp(mac, llc_mac_null_var, IFHWADDRLEN); + return is_zero_ether_addr(mac); } -static __inline__ int llc_addrany(struct llc_addr *addr) +static inline int llc_addrany(const struct llc_addr *addr) { return llc_mac_null(addr->mac) && !addr->lsap; } +static inline int llc_mac_multicast(const u8 *mac) +{ + return is_multicast_ether_addr(mac); +} /** * llc_mac_match - determines if two mac addresses are the same * @mac1: First mac address to compare. @@ -89,9 +92,9 @@ static __inline__ int llc_addrany(struct llc_addr *addr) * is not a complete match up to len, 1 if a complete match up to len is * found. */ -static __inline__ int llc_mac_match(u8 *mac1, u8 *mac2) +static inline int llc_mac_match(const u8 *mac1, const u8 *mac2) { - return !memcmp(mac1, mac2, IFHWADDRLEN); + return !compare_ether_addr(mac1, mac2); } extern int llc_establish_connection(struct sock *sk, u8 *lmac, diff --git a/include/net/netdma.h b/include/net/netdma.h new file mode 100644 index 000000000000..19760eb131aa --- /dev/null +++ b/include/net/netdma.h @@ -0,0 +1,44 @@ +/* + * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., 59 + * Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * The full GNU General Public License is included in this distribution in the + * file called COPYING. + */ +#ifndef NETDMA_H +#define NETDMA_H +#include <linux/config.h> +#ifdef CONFIG_NET_DMA +#include <linux/dmaengine.h> +#include <linux/skbuff.h> + +static inline struct dma_chan *get_softnet_dma(void) +{ + struct dma_chan *chan; + rcu_read_lock(); + chan = rcu_dereference(__get_cpu_var(softnet_data.net_dma)); + if (chan) + dma_chan_get(chan); + rcu_read_unlock(); + return chan; +} + +int dma_skb_copy_datagram_iovec(struct dma_chan* chan, + const struct sk_buff *skb, int offset, struct iovec *to, + size_t len, struct dma_pinned_list *pinned_list); + +#endif /* CONFIG_NET_DMA */ +#endif /* NETDMA_H */ diff --git a/include/net/netfilter/nf_conntrack.h b/include/net/netfilter/nf_conntrack.h index fc00aa31e282..1fbd8193d5f1 100644 --- a/include/net/netfilter/nf_conntrack.h +++ b/include/net/netfilter/nf_conntrack.h @@ -113,6 +113,10 @@ struct nf_conn u_int32_t mark; #endif +#ifdef CONFIG_NF_CONNTRACK_SECMARK + u_int32_t secmark; +#endif + /* Storage reserved for other modules: */ union nf_conntrack_proto proto; @@ -284,6 +288,7 @@ static inline int nf_ct_is_dying(struct nf_conn *ct) } extern unsigned int nf_conntrack_htable_size; +extern int nf_conntrack_checksum; #define NF_CT_STAT_INC(count) (__get_cpu_var(nf_conntrack_stat).count++) diff --git a/include/net/netfilter/nf_conntrack_compat.h b/include/net/netfilter/nf_conntrack_compat.h index 3cac19fb3648..f1b1482d7200 100644 --- a/include/net/netfilter/nf_conntrack_compat.h +++ b/include/net/netfilter/nf_conntrack_compat.h @@ -20,6 +20,19 @@ static inline u_int32_t *nf_ct_get_mark(const struct sk_buff *skb, } #endif /* CONFIG_IP_NF_CONNTRACK_MARK */ +#ifdef CONFIG_IP_NF_CONNTRACK_SECMARK +static inline u_int32_t *nf_ct_get_secmark(const struct sk_buff *skb, + u_int32_t *ctinfo) +{ + struct ip_conntrack *ct = ip_conntrack_get(skb, ctinfo); + + if (ct) + return &ct->secmark; + else + return NULL; +} +#endif /* CONFIG_IP_NF_CONNTRACK_SECMARK */ + #ifdef CONFIG_IP_NF_CT_ACCT static inline struct ip_conntrack_counter * nf_ct_get_counters(const struct sk_buff *skb) @@ -70,6 +83,19 @@ static inline u_int32_t *nf_ct_get_mark(const struct sk_buff *skb, } #endif /* CONFIG_NF_CONNTRACK_MARK */ +#ifdef CONFIG_NF_CONNTRACK_SECMARK +static inline u_int32_t *nf_ct_get_secmark(const struct sk_buff *skb, + u_int32_t *ctinfo) +{ + struct nf_conn *ct = nf_ct_get(skb, ctinfo); + + if (ct) + return &ct->secmark; + else + return NULL; +} +#endif /* CONFIG_NF_CONNTRACK_MARK */ + #ifdef CONFIG_NF_CT_ACCT static inline struct ip_conntrack_counter * nf_ct_get_counters(const struct sk_buff *skb) diff --git a/include/net/raw.h b/include/net/raw.h index 481b20190b12..e4af59781949 100644 --- a/include/net/raw.h +++ b/include/net/raw.h @@ -35,7 +35,7 @@ extern rwlock_t raw_v4_lock; extern struct sock *__raw_v4_lookup(struct sock *sk, unsigned short num, - unsigned long raddr, unsigned long laddr, + __be32 raddr, __be32 laddr, int dif); extern int raw_v4_input(struct sk_buff *skb, struct iphdr *iph, int hash); diff --git a/include/net/sctp/sctp.h b/include/net/sctp/sctp.h index a9663b49ea54..237f82b05e40 100644 --- a/include/net/sctp/sctp.h +++ b/include/net/sctp/sctp.h @@ -254,7 +254,7 @@ extern int sctp_debug_flag; #define SCTP_DEBUG_PRINTK_IPADDR(whatever...) #define SCTP_ENABLE_DEBUG #define SCTP_DISABLE_DEBUG -#define SCTP_ASSERT(expr, str, func) +#define SCTP_ASSERT(expr, str, func) BUG_ON(!(expr)) #endif /* SCTP_DEBUG */ diff --git a/include/net/sctp/structs.h b/include/net/sctp/structs.h index 7f4fea173fb1..5f69158c1006 100644 --- a/include/net/sctp/structs.h +++ b/include/net/sctp/structs.h @@ -555,7 +555,8 @@ struct sctp_af { int (*to_addr_param) (const union sctp_addr *, union sctp_addr_param *); int (*addr_valid) (union sctp_addr *, - struct sctp_sock *); + struct sctp_sock *, + const struct sk_buff *); sctp_scope_t (*scope) (union sctp_addr *); void (*inaddr_any) (union sctp_addr *, unsigned short); int (*is_any) (const union sctp_addr *); diff --git a/include/net/sock.h b/include/net/sock.h index d27e748a8259..d10dfecb6cbd 100644 --- a/include/net/sock.h +++ b/include/net/sock.h @@ -131,6 +131,7 @@ struct sock_common { * @sk_receive_queue: incoming packets * @sk_wmem_alloc: transmit queue bytes committed * @sk_write_queue: Packet sending queue + * @sk_async_wait_queue: DMA copied packets * @sk_omem_alloc: "o" is "option" or "other" * @sk_wmem_queued: persistent queue size * @sk_forward_alloc: space allocated forward @@ -204,6 +205,7 @@ struct sock { atomic_t sk_omem_alloc; struct sk_buff_head sk_receive_queue; struct sk_buff_head sk_write_queue; + struct sk_buff_head sk_async_wait_queue; int sk_wmem_queued; int sk_forward_alloc; gfp_t sk_allocation; @@ -870,10 +872,7 @@ static inline int sk_filter(struct sock *sk, struct sk_buff *skb, int needlock) if (filter) { unsigned int pkt_len = sk_run_filter(skb, filter->insns, filter->len); - if (!pkt_len) - err = -EPERM; - else - skb_trim(skb, pkt_len); + err = pkt_len ? pskb_trim(skb, pkt_len) : -EPERM; } if (needlock) @@ -1270,11 +1269,22 @@ sock_recv_timestamp(struct msghdr *msg, struct sock *sk, struct sk_buff *skb) * This routine must be called with interrupts disabled or with the socket * locked so that the sk_buff queue operation is ok. */ -static inline void sk_eat_skb(struct sock *sk, struct sk_buff *skb) +#ifdef CONFIG_NET_DMA +static inline void sk_eat_skb(struct sock *sk, struct sk_buff *skb, int copied_early) +{ + __skb_unlink(skb, &sk->sk_receive_queue); + if (!copied_early) + __kfree_skb(skb); + else + __skb_queue_tail(&sk->sk_async_wait_queue, skb); +} +#else +static inline void sk_eat_skb(struct sock *sk, struct sk_buff *skb, int copied_early) { __skb_unlink(skb, &sk->sk_receive_queue); __kfree_skb(skb); } +#endif extern void sock_enable_timestamp(struct sock *sk); extern int sock_get_timestamp(struct sock *, struct timeval __user *); diff --git a/include/net/tcp.h b/include/net/tcp.h index 9e88dcd5f134..5f4eb5c79689 100644 --- a/include/net/tcp.h +++ b/include/net/tcp.h @@ -27,6 +27,7 @@ #include <linux/cache.h> #include <linux/percpu.h> #include <linux/skbuff.h> +#include <linux/dmaengine.h> #include <net/inet_connection_sock.h> #include <net/inet_timewait_sock.h> @@ -217,6 +218,7 @@ extern int sysctl_tcp_adv_win_scale; extern int sysctl_tcp_tw_reuse; extern int sysctl_tcp_frto; extern int sysctl_tcp_low_latency; +extern int sysctl_tcp_dma_copybreak; extern int sysctl_tcp_nometrics_save; extern int sysctl_tcp_moderate_rcvbuf; extern int sysctl_tcp_tso_win_divisor; @@ -224,6 +226,7 @@ extern int sysctl_tcp_abc; extern int sysctl_tcp_mtu_probing; extern int sysctl_tcp_base_mss; extern int sysctl_tcp_workaround_signed_windows; +extern int sysctl_tcp_slow_start_after_idle; extern atomic_t tcp_memory_allocated; extern atomic_t tcp_sockets_allocated; @@ -292,6 +295,8 @@ extern int tcp_rcv_established(struct sock *sk, extern void tcp_rcv_space_adjust(struct sock *sk); +extern void tcp_cleanup_rbuf(struct sock *sk, int copied); + extern int tcp_twsk_unique(struct sock *sk, struct sock *sktw, void *twp); @@ -627,7 +632,7 @@ struct tcp_congestion_ops { /* return slow start threshold (required) */ u32 (*ssthresh)(struct sock *sk); /* lower bound for congestion window (optional) */ - u32 (*min_cwnd)(struct sock *sk); + u32 (*min_cwnd)(const struct sock *sk); /* do new cwnd calculation (required) */ void (*cong_avoid)(struct sock *sk, u32 ack, u32 rtt, u32 in_flight, int good_ack); @@ -662,7 +667,7 @@ extern struct tcp_congestion_ops tcp_init_congestion_ops; extern u32 tcp_reno_ssthresh(struct sock *sk); extern void tcp_reno_cong_avoid(struct sock *sk, u32 ack, u32 rtt, u32 in_flight, int flag); -extern u32 tcp_reno_min_cwnd(struct sock *sk); +extern u32 tcp_reno_min_cwnd(const struct sock *sk); extern struct tcp_congestion_ops tcp_reno; static inline void tcp_set_ca_state(struct sock *sk, const u8 ca_state) @@ -816,6 +821,12 @@ static inline void tcp_prequeue_init(struct tcp_sock *tp) tp->ucopy.len = 0; tp->ucopy.memory = 0; skb_queue_head_init(&tp->ucopy.prequeue); +#ifdef CONFIG_NET_DMA + tp->ucopy.dma_chan = NULL; + tp->ucopy.wakeup = 0; + tp->ucopy.pinned_list = NULL; + tp->ucopy.dma_cookie = 0; +#endif } /* Packet is added to VJ-style prequeue for processing in process diff --git a/include/net/xfrm.h b/include/net/xfrm.h index afa508d92c93..9c5ee9f20b65 100644 --- a/include/net/xfrm.h +++ b/include/net/xfrm.h @@ -20,6 +20,8 @@ #include <net/ip6_fib.h> #define XFRM_ALIGN8(len) (((len) + 7) & ~7) +#define MODULE_ALIAS_XFRM_MODE(family, encap) \ + MODULE_ALIAS("xfrm-mode-" __stringify(family) "-" __stringify(encap)) extern struct sock *xfrm_nl; extern u32 sysctl_xfrm_aevent_etime; @@ -164,6 +166,7 @@ struct xfrm_state /* Reference to data common to all the instances of this * transformer. */ struct xfrm_type *type; + struct xfrm_mode *mode; /* Security context */ struct xfrm_sec_ctx *security; @@ -204,8 +207,8 @@ struct xfrm_type; struct xfrm_dst; struct xfrm_policy_afinfo { unsigned short family; - rwlock_t lock; - struct xfrm_type_map *type_map; + struct xfrm_type *type_map[IPPROTO_MAX]; + struct xfrm_mode *mode_map[XFRM_MODE_MAX]; struct dst_ops *dst_ops; void (*garbage_collect)(void); int (*dst_lookup)(struct xfrm_dst **dst, struct flowi *fl); @@ -232,7 +235,6 @@ extern int __xfrm_state_delete(struct xfrm_state *x); struct xfrm_state_afinfo { unsigned short family; - rwlock_t lock; struct list_head *state_bydst; struct list_head *state_byspi; int (*init_flags)(struct xfrm_state *x); @@ -264,16 +266,24 @@ struct xfrm_type u32 (*get_max_size)(struct xfrm_state *, int size); }; -struct xfrm_type_map { - rwlock_t lock; - struct xfrm_type *map[256]; -}; - extern int xfrm_register_type(struct xfrm_type *type, unsigned short family); extern int xfrm_unregister_type(struct xfrm_type *type, unsigned short family); extern struct xfrm_type *xfrm_get_type(u8 proto, unsigned short family); extern void xfrm_put_type(struct xfrm_type *type); +struct xfrm_mode { + int (*input)(struct xfrm_state *x, struct sk_buff *skb); + int (*output)(struct sk_buff *skb); + + struct module *owner; + unsigned int encap; +}; + +extern int xfrm_register_mode(struct xfrm_mode *mode, int family); +extern int xfrm_unregister_mode(struct xfrm_mode *mode, int family); +extern struct xfrm_mode *xfrm_get_mode(unsigned int encap, int family); +extern void xfrm_put_mode(struct xfrm_mode *mode); + struct xfrm_tmpl { /* id in template is interpreted as: diff --git a/include/rdma/ib_addr.h b/include/rdma/ib_addr.h new file mode 100644 index 000000000000..fcb5ba87dcc5 --- /dev/null +++ b/include/rdma/ib_addr.h @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2005 Voltaire Inc. All rights reserved. + * Copyright (c) 2005 Intel Corporation. All rights reserved. + * + * This Software is licensed under one of the following licenses: + * + * 1) under the terms of the "Common Public License 1.0" a copy of which is + * available from the Open Source Initiative, see + * http://www.opensource.org/licenses/cpl.php. + * + * 2) under the terms of the "The BSD License" a copy of which is + * available from the Open Source Initiative, see + * http://www.opensource.org/licenses/bsd-license.php. + * + * 3) under the terms of the "GNU General Public License (GPL) Version 2" a + * copy of which is available from the Open Source Initiative, see + * http://www.opensource.org/licenses/gpl-license.php. + * + * Licensee has the right to choose one of the above licenses. + * + * Redistributions of source code must retain the above copyright + * notice and one of the license notices. + * + * Redistributions in binary form must reproduce both the above copyright + * notice, one of the license notices in the documentation + * and/or other materials provided with the distribution. + * + */ + +#if !defined(IB_ADDR_H) +#define IB_ADDR_H + +#include <linux/in.h> +#include <linux/in6.h> +#include <linux/netdevice.h> +#include <linux/socket.h> +#include <rdma/ib_verbs.h> + +struct rdma_dev_addr { + unsigned char src_dev_addr[MAX_ADDR_LEN]; + unsigned char dst_dev_addr[MAX_ADDR_LEN]; + unsigned char broadcast[MAX_ADDR_LEN]; + enum ib_node_type dev_type; +}; + +/** + * rdma_translate_ip - Translate a local IP address to an RDMA hardware + * address. + */ +int rdma_translate_ip(struct sockaddr *addr, struct rdma_dev_addr *dev_addr); + +/** + * rdma_resolve_ip - Resolve source and destination IP addresses to + * RDMA hardware addresses. + * @src_addr: An optional source address to use in the resolution. If a + * source address is not provided, a usable address will be returned via + * the callback. + * @dst_addr: The destination address to resolve. + * @addr: A reference to a data location that will receive the resolved + * addresses. The data location must remain valid until the callback has + * been invoked. + * @timeout_ms: Amount of time to wait for the address resolution to complete. + * @callback: Call invoked once address resolution has completed, timed out, + * or been canceled. A status of 0 indicates success. + * @context: User-specified context associated with the call. + */ +int rdma_resolve_ip(struct sockaddr *src_addr, struct sockaddr *dst_addr, + struct rdma_dev_addr *addr, int timeout_ms, + void (*callback)(int status, struct sockaddr *src_addr, + struct rdma_dev_addr *addr, void *context), + void *context); + +void rdma_addr_cancel(struct rdma_dev_addr *addr); + +static inline int ip_addr_size(struct sockaddr *addr) +{ + return addr->sa_family == AF_INET6 ? + sizeof(struct sockaddr_in6) : sizeof(struct sockaddr_in); +} + +static inline u16 ib_addr_get_pkey(struct rdma_dev_addr *dev_addr) +{ + return ((u16)dev_addr->broadcast[8] << 8) | (u16)dev_addr->broadcast[9]; +} + +static inline void ib_addr_set_pkey(struct rdma_dev_addr *dev_addr, u16 pkey) +{ + dev_addr->broadcast[8] = pkey >> 8; + dev_addr->broadcast[9] = (unsigned char) pkey; +} + +static inline union ib_gid *ib_addr_get_sgid(struct rdma_dev_addr *dev_addr) +{ + return (union ib_gid *) (dev_addr->src_dev_addr + 4); +} + +static inline void ib_addr_set_sgid(struct rdma_dev_addr *dev_addr, + union ib_gid *gid) +{ + memcpy(dev_addr->src_dev_addr + 4, gid, sizeof *gid); +} + +static inline union ib_gid *ib_addr_get_dgid(struct rdma_dev_addr *dev_addr) +{ + return (union ib_gid *) (dev_addr->dst_dev_addr + 4); +} + +static inline void ib_addr_set_dgid(struct rdma_dev_addr *dev_addr, + union ib_gid *gid) +{ + memcpy(dev_addr->dst_dev_addr + 4, gid, sizeof *gid); +} + +#endif /* IB_ADDR_H */ diff --git a/include/rdma/ib_cache.h b/include/rdma/ib_cache.h index 5bf9834f7dca..f179d233ffc3 100644 --- a/include/rdma/ib_cache.h +++ b/include/rdma/ib_cache.h @@ -102,4 +102,17 @@ int ib_find_cached_pkey(struct ib_device *device, u16 pkey, u16 *index); +/** + * ib_get_cached_lmc - Returns a cached lmc table entry + * @device: The device to query. + * @port_num: The port number of the device to query. + * @lmc: The lmc value for the specified port for that device. + * + * ib_get_cached_lmc() fetches the specified lmc table entry stored in + * the local software cache. + */ +int ib_get_cached_lmc(struct ib_device *device, + u8 port_num, + u8 *lmc); + #endif /* _IB_CACHE_H */ diff --git a/include/rdma/ib_cm.h b/include/rdma/ib_cm.h index 0a9fcd59eb43..c9b4738be9d6 100644 --- a/include/rdma/ib_cm.h +++ b/include/rdma/ib_cm.h @@ -32,7 +32,7 @@ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * - * $Id: ib_cm.h 2730 2005-06-28 16:43:03Z sean.hefty $ + * $Id: ib_cm.h 4311 2005-12-05 18:42:01Z sean.hefty $ */ #if !defined(IB_CM_H) #define IB_CM_H @@ -102,7 +102,8 @@ enum ib_cm_data_size { IB_CM_APR_INFO_LENGTH = 72, IB_CM_SIDR_REQ_PRIVATE_DATA_SIZE = 216, IB_CM_SIDR_REP_PRIVATE_DATA_SIZE = 136, - IB_CM_SIDR_REP_INFO_LENGTH = 72 + IB_CM_SIDR_REP_INFO_LENGTH = 72, + IB_CM_COMPARE_SIZE = 64 }; struct ib_cm_id; @@ -238,7 +239,6 @@ struct ib_cm_sidr_rep_event_param { u32 qpn; void *info; u8 info_len; - }; struct ib_cm_event { @@ -317,6 +317,15 @@ void ib_destroy_cm_id(struct ib_cm_id *cm_id); #define IB_SERVICE_ID_AGN_MASK __constant_cpu_to_be64(0xFF00000000000000ULL) #define IB_CM_ASSIGN_SERVICE_ID __constant_cpu_to_be64(0x0200000000000000ULL) +#define IB_CMA_SERVICE_ID __constant_cpu_to_be64(0x0000000001000000ULL) +#define IB_CMA_SERVICE_ID_MASK __constant_cpu_to_be64(0xFFFFFFFFFF000000ULL) +#define IB_SDP_SERVICE_ID __constant_cpu_to_be64(0x0000000000010000ULL) +#define IB_SDP_SERVICE_ID_MASK __constant_cpu_to_be64(0xFFFFFFFFFFFF0000ULL) + +struct ib_cm_compare_data { + u8 data[IB_CM_COMPARE_SIZE]; + u8 mask[IB_CM_COMPARE_SIZE]; +}; /** * ib_cm_listen - Initiates listening on the specified service ID for @@ -330,10 +339,12 @@ void ib_destroy_cm_id(struct ib_cm_id *cm_id); * range of service IDs. If set to 0, the service ID is matched * exactly. This parameter is ignored if %service_id is set to * IB_CM_ASSIGN_SERVICE_ID. + * @compare_data: This parameter is optional. It specifies data that must + * appear in the private data of a connection request for the specified + * listen request. */ -int ib_cm_listen(struct ib_cm_id *cm_id, - __be64 service_id, - __be64 service_mask); +int ib_cm_listen(struct ib_cm_id *cm_id, __be64 service_id, __be64 service_mask, + struct ib_cm_compare_data *compare_data); struct ib_cm_req_param { struct ib_sa_path_rec *primary_path; @@ -535,7 +546,6 @@ struct ib_cm_sidr_req_param { const void *private_data; u8 private_data_len; u8 max_cm_retries; - u16 pkey; }; /** @@ -559,7 +569,7 @@ struct ib_cm_sidr_rep_param { }; /** - * ib_send_cm_sidr_rep - Sends a service ID resolution request to the + * ib_send_cm_sidr_rep - Sends a service ID resolution reply to the * remote node. * @cm_id: Communication identifier associated with the received service ID * resolution request. diff --git a/include/rdma/ib_marshall.h b/include/rdma/ib_marshall.h new file mode 100644 index 000000000000..66bf4d7d0dfb --- /dev/null +++ b/include/rdma/ib_marshall.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2005 Intel Corporation. All rights reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the + * OpenIB.org BSD license below: + * + * Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * - Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * + * - Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#if !defined(IB_USER_MARSHALL_H) +#define IB_USER_MARSHALL_H + +#include <rdma/ib_verbs.h> +#include <rdma/ib_sa.h> +#include <rdma/ib_user_verbs.h> +#include <rdma/ib_user_sa.h> + +void ib_copy_qp_attr_to_user(struct ib_uverbs_qp_attr *dst, + struct ib_qp_attr *src); + +void ib_copy_path_rec_to_user(struct ib_user_path_rec *dst, + struct ib_sa_path_rec *src); + +void ib_copy_path_rec_from_user(struct ib_sa_path_rec *dst, + struct ib_user_path_rec *src); + +#endif /* IB_USER_MARSHALL_H */ diff --git a/include/rdma/ib_sa.h b/include/rdma/ib_sa.h index ad63c215efe5..c99e4420fd7e 100644 --- a/include/rdma/ib_sa.h +++ b/include/rdma/ib_sa.h @@ -370,5 +370,12 @@ ib_sa_mcmember_rec_delete(struct ib_device *device, u8 port_num, context, query); } +/** + * ib_init_ah_from_path - Initialize address handle attributes based on an SA + * path record. + */ +int ib_init_ah_from_path(struct ib_device *device, u8 port_num, + struct ib_sa_path_rec *rec, + struct ib_ah_attr *ah_attr); #endif /* IB_SA_H */ diff --git a/include/rdma/ib_smi.h b/include/rdma/ib_smi.h index 87f60737f695..f29af135ba83 100644 --- a/include/rdma/ib_smi.h +++ b/include/rdma/ib_smi.h @@ -85,6 +85,42 @@ struct ib_smp { #define IB_SMP_ATTR_LED_INFO __constant_htons(0x0031) #define IB_SMP_ATTR_VENDOR_MASK __constant_htons(0xFF00) +struct ib_port_info { + __be64 mkey; + __be64 gid_prefix; + __be16 lid; + __be16 sm_lid; + __be32 cap_mask; + __be16 diag_code; + __be16 mkey_lease_period; + u8 local_port_num; + u8 link_width_enabled; + u8 link_width_supported; + u8 link_width_active; + u8 linkspeed_portstate; /* 4 bits, 4 bits */ + u8 portphysstate_linkdown; /* 4 bits, 4 bits */ + u8 mkeyprot_resv_lmc; /* 2 bits, 3, 3 */ + u8 linkspeedactive_enabled; /* 4 bits, 4 bits */ + u8 neighbormtu_mastersmsl; /* 4 bits, 4 bits */ + u8 vlcap_inittype; /* 4 bits, 4 bits */ + u8 vl_high_limit; + u8 vl_arb_high_cap; + u8 vl_arb_low_cap; + u8 inittypereply_mtucap; /* 4 bits, 4 bits */ + u8 vlstallcnt_hoqlife; /* 3 bits, 5 bits */ + u8 operationalvl_pei_peo_fpi_fpo; /* 4 bits, 1, 1, 1, 1 */ + __be16 mkey_violations; + __be16 pkey_violations; + __be16 qkey_violations; + u8 guid_cap; + u8 clientrereg_resv_subnetto; /* 1 bit, 2 bits, 5 */ + u8 resv_resptimevalue; /* 3 bits, 5 bits */ + u8 localphyerrors_overrunerrors; /* 4 bits, 4 bits */ + __be16 max_credit_hint; + u8 resv; + u8 link_roundtrip_latency[3]; +}; + static inline u8 ib_get_smp_direction(struct ib_smp *smp) { diff --git a/include/rdma/ib_user_cm.h b/include/rdma/ib_user_cm.h index 19be116047f6..066c20b7cdfb 100644 --- a/include/rdma/ib_user_cm.h +++ b/include/rdma/ib_user_cm.h @@ -30,13 +30,13 @@ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * - * $Id: ib_user_cm.h 2576 2005-06-09 17:00:30Z libor $ + * $Id: ib_user_cm.h 4019 2005-11-11 00:33:09Z sean.hefty $ */ #ifndef IB_USER_CM_H #define IB_USER_CM_H -#include <linux/types.h> +#include <rdma/ib_user_sa.h> #define IB_USER_CM_ABI_VERSION 4 @@ -110,58 +110,6 @@ struct ib_ucm_init_qp_attr { __u32 qp_state; }; -struct ib_ucm_ah_attr { - __u8 grh_dgid[16]; - __u32 grh_flow_label; - __u16 dlid; - __u16 reserved; - __u8 grh_sgid_index; - __u8 grh_hop_limit; - __u8 grh_traffic_class; - __u8 sl; - __u8 src_path_bits; - __u8 static_rate; - __u8 is_global; - __u8 port_num; -}; - -struct ib_ucm_init_qp_attr_resp { - __u32 qp_attr_mask; - __u32 qp_state; - __u32 cur_qp_state; - __u32 path_mtu; - __u32 path_mig_state; - __u32 qkey; - __u32 rq_psn; - __u32 sq_psn; - __u32 dest_qp_num; - __u32 qp_access_flags; - - struct ib_ucm_ah_attr ah_attr; - struct ib_ucm_ah_attr alt_ah_attr; - - /* ib_qp_cap */ - __u32 max_send_wr; - __u32 max_recv_wr; - __u32 max_send_sge; - __u32 max_recv_sge; - __u32 max_inline_data; - - __u16 pkey_index; - __u16 alt_pkey_index; - __u8 en_sqd_async_notify; - __u8 sq_draining; - __u8 max_rd_atomic; - __u8 max_dest_rd_atomic; - __u8 min_rnr_timer; - __u8 port_num; - __u8 timeout; - __u8 retry_cnt; - __u8 rnr_retry; - __u8 alt_port_num; - __u8 alt_timeout; -}; - struct ib_ucm_listen { __be64 service_id; __be64 service_mask; @@ -180,28 +128,6 @@ struct ib_ucm_private_data { __u8 reserved[3]; }; -struct ib_ucm_path_rec { - __u8 dgid[16]; - __u8 sgid[16]; - __be16 dlid; - __be16 slid; - __u32 raw_traffic; - __be32 flow_label; - __u32 reversible; - __u32 mtu; - __be16 pkey; - __u8 hop_limit; - __u8 traffic_class; - __u8 numb_path; - __u8 sl; - __u8 mtu_selector; - __u8 rate_selector; - __u8 rate; - __u8 packet_life_time_selector; - __u8 packet_life_time; - __u8 preference; -}; - struct ib_ucm_req { __u32 id; __u32 qpn; @@ -274,7 +200,7 @@ struct ib_ucm_sidr_req { __be64 sid; __u64 data; __u64 path; - __u16 pkey; + __u16 reserved_pkey; __u8 len; __u8 max_cm_retries; __u8 reserved[4]; @@ -304,8 +230,8 @@ struct ib_ucm_event_get { }; struct ib_ucm_req_event_resp { - struct ib_ucm_path_rec primary_path; - struct ib_ucm_path_rec alternate_path; + struct ib_user_path_rec primary_path; + struct ib_user_path_rec alternate_path; __be64 remote_ca_guid; __u32 remote_qkey; __u32 remote_qpn; @@ -349,7 +275,7 @@ struct ib_ucm_mra_event_resp { }; struct ib_ucm_lap_event_resp { - struct ib_ucm_path_rec path; + struct ib_user_path_rec path; }; struct ib_ucm_apr_event_resp { diff --git a/include/rdma/ib_user_sa.h b/include/rdma/ib_user_sa.h new file mode 100644 index 000000000000..659120157e14 --- /dev/null +++ b/include/rdma/ib_user_sa.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2005 Intel Corporation. All rights reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the + * OpenIB.org BSD license below: + * + * Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * - Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * + * - Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef IB_USER_SA_H +#define IB_USER_SA_H + +#include <linux/types.h> + +struct ib_user_path_rec { + __u8 dgid[16]; + __u8 sgid[16]; + __be16 dlid; + __be16 slid; + __u32 raw_traffic; + __be32 flow_label; + __u32 reversible; + __u32 mtu; + __be16 pkey; + __u8 hop_limit; + __u8 traffic_class; + __u8 numb_path; + __u8 sl; + __u8 mtu_selector; + __u8 rate_selector; + __u8 rate; + __u8 packet_life_time_selector; + __u8 packet_life_time; + __u8 preference; +}; + +#endif /* IB_USER_SA_H */ diff --git a/include/rdma/ib_user_verbs.h b/include/rdma/ib_user_verbs.h index 338ed4333063..7b5372010f4b 100644 --- a/include/rdma/ib_user_verbs.h +++ b/include/rdma/ib_user_verbs.h @@ -32,7 +32,7 @@ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * - * $Id: ib_user_verbs.h 2708 2005-06-24 17:27:21Z roland $ + * $Id: ib_user_verbs.h 4019 2005-11-11 00:33:09Z sean.hefty $ */ #ifndef IB_USER_VERBS_H @@ -323,6 +323,64 @@ struct ib_uverbs_destroy_cq_resp { __u32 async_events_reported; }; +struct ib_uverbs_global_route { + __u8 dgid[16]; + __u32 flow_label; + __u8 sgid_index; + __u8 hop_limit; + __u8 traffic_class; + __u8 reserved; +}; + +struct ib_uverbs_ah_attr { + struct ib_uverbs_global_route grh; + __u16 dlid; + __u8 sl; + __u8 src_path_bits; + __u8 static_rate; + __u8 is_global; + __u8 port_num; + __u8 reserved; +}; + +struct ib_uverbs_qp_attr { + __u32 qp_attr_mask; + __u32 qp_state; + __u32 cur_qp_state; + __u32 path_mtu; + __u32 path_mig_state; + __u32 qkey; + __u32 rq_psn; + __u32 sq_psn; + __u32 dest_qp_num; + __u32 qp_access_flags; + + struct ib_uverbs_ah_attr ah_attr; + struct ib_uverbs_ah_attr alt_ah_attr; + + /* ib_qp_cap */ + __u32 max_send_wr; + __u32 max_recv_wr; + __u32 max_send_sge; + __u32 max_recv_sge; + __u32 max_inline_data; + + __u16 pkey_index; + __u16 alt_pkey_index; + __u8 en_sqd_async_notify; + __u8 sq_draining; + __u8 max_rd_atomic; + __u8 max_dest_rd_atomic; + __u8 min_rnr_timer; + __u8 port_num; + __u8 timeout; + __u8 retry_cnt; + __u8 rnr_retry; + __u8 alt_port_num; + __u8 alt_timeout; + __u8 reserved[5]; +}; + struct ib_uverbs_create_qp { __u64 response; __u64 user_handle; @@ -541,26 +599,6 @@ struct ib_uverbs_post_srq_recv_resp { __u32 bad_wr; }; -struct ib_uverbs_global_route { - __u8 dgid[16]; - __u32 flow_label; - __u8 sgid_index; - __u8 hop_limit; - __u8 traffic_class; - __u8 reserved; -}; - -struct ib_uverbs_ah_attr { - struct ib_uverbs_global_route grh; - __u16 dlid; - __u8 sl; - __u8 src_path_bits; - __u8 static_rate; - __u8 is_global; - __u8 port_num; - __u8 reserved; -}; - struct ib_uverbs_create_ah { __u64 response; __u64 user_handle; diff --git a/include/rdma/ib_verbs.h b/include/rdma/ib_verbs.h index 6bbf1b364400..ee1f3a355666 100644 --- a/include/rdma/ib_verbs.h +++ b/include/rdma/ib_verbs.h @@ -260,7 +260,8 @@ enum ib_event_type { IB_EVENT_SM_CHANGE, IB_EVENT_SRQ_ERR, IB_EVENT_SRQ_LIMIT_REACHED, - IB_EVENT_QP_LAST_WQE_REACHED + IB_EVENT_QP_LAST_WQE_REACHED, + IB_EVENT_CLIENT_REREGISTER }; struct ib_event { @@ -696,8 +697,12 @@ struct ib_ucontext { struct ib_uobject { u64 user_handle; /* handle given to us by userspace */ struct ib_ucontext *context; /* associated user context */ + void *object; /* containing object */ struct list_head list; /* link to context's list */ u32 id; /* index into kernel idr */ + struct kref ref; + struct rw_semaphore mutex; /* protects .live */ + int live; }; struct ib_umem { @@ -827,6 +832,7 @@ struct ib_cache { struct ib_event_handler event_handler; struct ib_pkey_cache **pkey_cache; struct ib_gid_cache **gid_cache; + u8 *lmc_cache; }; struct ib_device { @@ -1086,6 +1092,20 @@ int ib_dealloc_pd(struct ib_pd *pd); struct ib_ah *ib_create_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr); /** + * ib_init_ah_from_wc - Initializes address handle attributes from a + * work completion. + * @device: Device on which the received message arrived. + * @port_num: Port on which the received message arrived. + * @wc: Work completion associated with the received message. + * @grh: References the received global route header. This parameter is + * ignored unless the work completion indicates that the GRH is valid. + * @ah_attr: Returned attributes that can be used when creating an address + * handle for replying to the message. + */ +int ib_init_ah_from_wc(struct ib_device *device, u8 port_num, struct ib_wc *wc, + struct ib_grh *grh, struct ib_ah_attr *ah_attr); + +/** * ib_create_ah_from_wc - Creates an address handle associated with the * sender of the specified work completion. * @pd: The protection domain associated with the address handle. diff --git a/include/rdma/rdma_cm.h b/include/rdma/rdma_cm.h new file mode 100644 index 000000000000..402c63d7226b --- /dev/null +++ b/include/rdma/rdma_cm.h @@ -0,0 +1,256 @@ +/* + * Copyright (c) 2005 Voltaire Inc. All rights reserved. + * Copyright (c) 2005 Intel Corporation. All rights reserved. + * + * This Software is licensed under one of the following licenses: + * + * 1) under the terms of the "Common Public License 1.0" a copy of which is + * available from the Open Source Initiative, see + * http://www.opensource.org/licenses/cpl.php. + * + * 2) under the terms of the "The BSD License" a copy of which is + * available from the Open Source Initiative, see + * http://www.opensource.org/licenses/bsd-license.php. + * + * 3) under the terms of the "GNU General Public License (GPL) Version 2" a + * copy of which is available from the Open Source Initiative, see + * http://www.opensource.org/licenses/gpl-license.php. + * + * Licensee has the right to choose one of the above licenses. + * + * Redistributions of source code must retain the above copyright + * notice and one of the license notices. + * + * Redistributions in binary form must reproduce both the above copyright + * notice, one of the license notices in the documentation + * and/or other materials provided with the distribution. + * + */ + +#if !defined(RDMA_CM_H) +#define RDMA_CM_H + +#include <linux/socket.h> +#include <linux/in6.h> +#include <rdma/ib_addr.h> +#include <rdma/ib_sa.h> + +/* + * Upon receiving a device removal event, users must destroy the associated + * RDMA identifier and release all resources allocated with the device. + */ +enum rdma_cm_event_type { + RDMA_CM_EVENT_ADDR_RESOLVED, + RDMA_CM_EVENT_ADDR_ERROR, + RDMA_CM_EVENT_ROUTE_RESOLVED, + RDMA_CM_EVENT_ROUTE_ERROR, + RDMA_CM_EVENT_CONNECT_REQUEST, + RDMA_CM_EVENT_CONNECT_RESPONSE, + RDMA_CM_EVENT_CONNECT_ERROR, + RDMA_CM_EVENT_UNREACHABLE, + RDMA_CM_EVENT_REJECTED, + RDMA_CM_EVENT_ESTABLISHED, + RDMA_CM_EVENT_DISCONNECTED, + RDMA_CM_EVENT_DEVICE_REMOVAL, +}; + +enum rdma_port_space { + RDMA_PS_SDP = 0x0001, + RDMA_PS_TCP = 0x0106, + RDMA_PS_UDP = 0x0111, + RDMA_PS_SCTP = 0x0183 +}; + +struct rdma_addr { + struct sockaddr src_addr; + u8 src_pad[sizeof(struct sockaddr_in6) - + sizeof(struct sockaddr)]; + struct sockaddr dst_addr; + u8 dst_pad[sizeof(struct sockaddr_in6) - + sizeof(struct sockaddr)]; + struct rdma_dev_addr dev_addr; +}; + +struct rdma_route { + struct rdma_addr addr; + struct ib_sa_path_rec *path_rec; + int num_paths; +}; + +struct rdma_cm_event { + enum rdma_cm_event_type event; + int status; + void *private_data; + u8 private_data_len; +}; + +struct rdma_cm_id; + +/** + * rdma_cm_event_handler - Callback used to report user events. + * + * Notes: Users may not call rdma_destroy_id from this callback to destroy + * the passed in id, or a corresponding listen id. Returning a + * non-zero value from the callback will destroy the passed in id. + */ +typedef int (*rdma_cm_event_handler)(struct rdma_cm_id *id, + struct rdma_cm_event *event); + +struct rdma_cm_id { + struct ib_device *device; + void *context; + struct ib_qp *qp; + rdma_cm_event_handler event_handler; + struct rdma_route route; + enum rdma_port_space ps; + u8 port_num; +}; + +/** + * rdma_create_id - Create an RDMA identifier. + * + * @event_handler: User callback invoked to report events associated with the + * returned rdma_id. + * @context: User specified context associated with the id. + * @ps: RDMA port space. + */ +struct rdma_cm_id *rdma_create_id(rdma_cm_event_handler event_handler, + void *context, enum rdma_port_space ps); + +void rdma_destroy_id(struct rdma_cm_id *id); + +/** + * rdma_bind_addr - Bind an RDMA identifier to a source address and + * associated RDMA device, if needed. + * + * @id: RDMA identifier. + * @addr: Local address information. Wildcard values are permitted. + * + * This associates a source address with the RDMA identifier before calling + * rdma_listen. If a specific local address is given, the RDMA identifier will + * be bound to a local RDMA device. + */ +int rdma_bind_addr(struct rdma_cm_id *id, struct sockaddr *addr); + +/** + * rdma_resolve_addr - Resolve destination and optional source addresses + * from IP addresses to an RDMA address. If successful, the specified + * rdma_cm_id will be bound to a local device. + * + * @id: RDMA identifier. + * @src_addr: Source address information. This parameter may be NULL. + * @dst_addr: Destination address information. + * @timeout_ms: Time to wait for resolution to complete. + */ +int rdma_resolve_addr(struct rdma_cm_id *id, struct sockaddr *src_addr, + struct sockaddr *dst_addr, int timeout_ms); + +/** + * rdma_resolve_route - Resolve the RDMA address bound to the RDMA identifier + * into route information needed to establish a connection. + * + * This is called on the client side of a connection. + * Users must have first called rdma_resolve_addr to resolve a dst_addr + * into an RDMA address before calling this routine. + */ +int rdma_resolve_route(struct rdma_cm_id *id, int timeout_ms); + +/** + * rdma_create_qp - Allocate a QP and associate it with the specified RDMA + * identifier. + * + * QPs allocated to an rdma_cm_id will automatically be transitioned by the CMA + * through their states. + */ +int rdma_create_qp(struct rdma_cm_id *id, struct ib_pd *pd, + struct ib_qp_init_attr *qp_init_attr); + +/** + * rdma_destroy_qp - Deallocate the QP associated with the specified RDMA + * identifier. + * + * Users must destroy any QP associated with an RDMA identifier before + * destroying the RDMA ID. + */ +void rdma_destroy_qp(struct rdma_cm_id *id); + +/** + * rdma_init_qp_attr - Initializes the QP attributes for use in transitioning + * to a specified QP state. + * @id: Communication identifier associated with the QP attributes to + * initialize. + * @qp_attr: On input, specifies the desired QP state. On output, the + * mandatory and desired optional attributes will be set in order to + * modify the QP to the specified state. + * @qp_attr_mask: The QP attribute mask that may be used to transition the + * QP to the specified state. + * + * Users must set the @qp_attr->qp_state to the desired QP state. This call + * will set all required attributes for the given transition, along with + * known optional attributes. Users may override the attributes returned from + * this call before calling ib_modify_qp. + * + * Users that wish to have their QP automatically transitioned through its + * states can associate a QP with the rdma_cm_id by calling rdma_create_qp(). + */ +int rdma_init_qp_attr(struct rdma_cm_id *id, struct ib_qp_attr *qp_attr, + int *qp_attr_mask); + +struct rdma_conn_param { + const void *private_data; + u8 private_data_len; + u8 responder_resources; + u8 initiator_depth; + u8 flow_control; + u8 retry_count; /* ignored when accepting */ + u8 rnr_retry_count; + /* Fields below ignored if a QP is created on the rdma_cm_id. */ + u8 srq; + u32 qp_num; + enum ib_qp_type qp_type; +}; + +/** + * rdma_connect - Initiate an active connection request. + * + * Users must have resolved a route for the rdma_cm_id to connect with + * by having called rdma_resolve_route before calling this routine. + */ +int rdma_connect(struct rdma_cm_id *id, struct rdma_conn_param *conn_param); + +/** + * rdma_listen - This function is called by the passive side to + * listen for incoming connection requests. + * + * Users must have bound the rdma_cm_id to a local address by calling + * rdma_bind_addr before calling this routine. + */ +int rdma_listen(struct rdma_cm_id *id, int backlog); + +/** + * rdma_accept - Called to accept a connection request or response. + * @id: Connection identifier associated with the request. + * @conn_param: Information needed to establish the connection. This must be + * provided if accepting a connection request. If accepting a connection + * response, this parameter must be NULL. + * + * Typically, this routine is only called by the listener to accept a connection + * request. It must also be called on the active side of a connection if the + * user is performing their own QP transitions. + */ +int rdma_accept(struct rdma_cm_id *id, struct rdma_conn_param *conn_param); + +/** + * rdma_reject - Called to reject a connection request or response. + */ +int rdma_reject(struct rdma_cm_id *id, const void *private_data, + u8 private_data_len); + +/** + * rdma_disconnect - This function disconnects the associated QP and + * transitions it into the error state. + */ +int rdma_disconnect(struct rdma_cm_id *id); + +#endif /* RDMA_CM_H */ + diff --git a/include/rdma/rdma_cm_ib.h b/include/rdma/rdma_cm_ib.h new file mode 100644 index 000000000000..e8c3af1804d4 --- /dev/null +++ b/include/rdma/rdma_cm_ib.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2006 Intel Corporation. All rights reserved. + * + * This Software is licensed under one of the following licenses: + * + * 1) under the terms of the "Common Public License 1.0" a copy of which is + * available from the Open Source Initiative, see + * http://www.opensource.org/licenses/cpl.php. + * + * 2) under the terms of the "The BSD License" a copy of which is + * available from the Open Source Initiative, see + * http://www.opensource.org/licenses/bsd-license.php. + * + * 3) under the terms of the "GNU General Public License (GPL) Version 2" a + * copy of which is available from the Open Source Initiative, see + * http://www.opensource.org/licenses/gpl-license.php. + * + * Licensee has the right to choose one of the above licenses. + * + * Redistributions of source code must retain the above copyright + * notice and one of the license notices. + * + * Redistributions in binary form must reproduce both the above copyright + * notice, one of the license notices in the documentation + * and/or other materials provided with the distribution. + * + */ + +#if !defined(RDMA_CM_IB_H) +#define RDMA_CM_IB_H + +#include <rdma/rdma_cm.h> + +/** + * rdma_set_ib_paths - Manually sets the path records used to establish a + * connection. + * @id: Connection identifier associated with the request. + * @path_rec: Reference to the path record + * + * This call permits a user to specify routing information for rdma_cm_id's + * bound to Infiniband devices. It is called on the client side of a + * connection and replaces the call to rdma_resolve_route. + */ +int rdma_set_ib_paths(struct rdma_cm_id *id, + struct ib_sa_path_rec *path_rec, int num_paths); + +#endif /* RDMA_CM_IB_H */ diff --git a/include/scsi/srp.h b/include/scsi/srp.h index 637f77eccf0c..ad178fa78f66 100644 --- a/include/scsi/srp.h +++ b/include/scsi/srp.h @@ -87,6 +87,11 @@ enum srp_login_rej_reason { SRP_LOGIN_REJ_CHANNEL_LIMIT_REACHED = 0x00010006 }; +enum { + SRP_REV10_IB_IO_CLASS = 0xff00, + SRP_REV16A_IB_IO_CLASS = 0x0100 +}; + struct srp_direct_buf { __be64 va; __be32 key; |
