diff options
Diffstat (limited to 'include')
271 files changed, 5357 insertions, 4127 deletions
diff --git a/include/asm-alpha/bug.h b/include/asm-alpha/bug.h index ae1e0a5fa492..39a3e2a5017d 100644 --- a/include/asm-alpha/bug.h +++ b/include/asm-alpha/bug.h @@ -1,6 +1,7 @@ #ifndef _ALPHA_BUG_H #define _ALPHA_BUG_H +#ifdef CONFIG_BUG #include <asm/pal.h> /* ??? Would be nice to use .gprel32 here, but we can't be sure that the @@ -10,6 +11,8 @@ : : "i" (PAL_bugchk), "i"(__LINE__), "i"(__FILE__)) #define HAVE_ARCH_BUG +#endif + #include <asm-generic/bug.h> #endif diff --git a/include/asm-alpha/errno.h b/include/asm-alpha/errno.h index c85ab6b9d6c6..69e2655249d2 100644 --- a/include/asm-alpha/errno.h +++ b/include/asm-alpha/errno.h @@ -116,4 +116,8 @@ #define EKEYREVOKED 134 /* Key has been revoked */ #define EKEYREJECTED 135 /* Key was rejected by service */ +/* for robust mutexes */ +#define EOWNERDEAD 136 /* Owner died */ +#define ENOTRECOVERABLE 137 /* State not recoverable */ + #endif diff --git a/include/asm-alpha/siginfo.h b/include/asm-alpha/siginfo.h index 86bcab59c52b..9822362a8424 100644 --- a/include/asm-alpha/siginfo.h +++ b/include/asm-alpha/siginfo.h @@ -4,8 +4,6 @@ #define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int)) #define __ARCH_SI_TRAPNO -#define SIGEV_PAD_SIZE ((SIGEV_MAX_SIZE/sizeof(int)) - 4) - #include <asm-generic/siginfo.h> #endif diff --git a/include/asm-alpha/signal.h b/include/asm-alpha/signal.h index 25f98bc5576f..1a2c52a056fb 100644 --- a/include/asm-alpha/signal.h +++ b/include/asm-alpha/signal.h @@ -109,34 +109,11 @@ typedef unsigned long sigset_t; #define MINSIGSTKSZ 4096 #define SIGSTKSZ 16384 - -#ifdef __KERNEL__ -/* - * These values of sa_flags are used only by the kernel as part of the - * irq handling routines. - * - * SA_INTERRUPT is also used by the irq handling routines. - * SA_SHIRQ is for shared interrupt support on PCI and EISA. - */ -#define SA_PROBE SA_ONESHOT -#define SA_SAMPLE_RANDOM SA_RESTART -#define SA_SHIRQ 0x40000000 -#endif - #define SIG_BLOCK 1 /* for blocking signals */ #define SIG_UNBLOCK 2 /* for unblocking signals */ #define SIG_SETMASK 3 /* for setting the signal mask */ -/* Type of a signal handler. */ -typedef void __signalfn_t(int); -typedef __signalfn_t __user *__sighandler_t; - -typedef void __restorefn_t(void); -typedef __restorefn_t __user *__sigrestore_t; - -#define SIG_DFL ((__sighandler_t)0) /* default signal handling */ -#define SIG_IGN ((__sighandler_t)1) /* ignore signal */ -#define SIG_ERR ((__sighandler_t)-1) /* error return from signal */ +#include <asm-generic/signal.h> #ifdef __KERNEL__ struct osf_sigaction { diff --git a/include/asm-arm/arch-cl7500/vmalloc.h b/include/asm-arm/arch-cl7500/vmalloc.h index 91883def4889..ba8d7a84456a 100644 --- a/include/asm-arm/arch-cl7500/vmalloc.h +++ b/include/asm-arm/arch-cl7500/vmalloc.h @@ -1,15 +1,4 @@ /* * linux/include/asm-arm/arch-cl7500/vmalloc.h */ - -/* - * Just any arbitrary offset to the start of the vmalloc VM area: the - * current 8MB value just means that there will be a 8MB "hole" after the - * physical memory until the kernel virtual memory starts. That means that - * any out-of-bounds memory accesses will hopefully be caught. - * The vmalloc() routines leaves a hole of 4kB between each vmalloced - * area for the same reason. ;) - */ -#define VMALLOC_OFFSET (8*1024*1024) -#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) #define VMALLOC_END (PAGE_OFFSET + 0x1c000000) diff --git a/include/asm-arm/arch-clps711x/vmalloc.h b/include/asm-arm/arch-clps711x/vmalloc.h index 42571ed5e493..a5dfe96abc96 100644 --- a/include/asm-arm/arch-clps711x/vmalloc.h +++ b/include/asm-arm/arch-clps711x/vmalloc.h @@ -17,15 +17,4 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ - -/* - * Just any arbitrary offset to the start of the vmalloc VM area: the - * current 8MB value just means that there will be a 8MB "hole" after the - * physical memory until the kernel virtual memory starts. That means that - * any out-of-bounds memory accesses will hopefully be caught. - * The vmalloc() routines leaves a hole of 4kB between each vmalloced - * area for the same reason. ;) - */ -#define VMALLOC_OFFSET (8*1024*1024) -#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) #define VMALLOC_END (PAGE_OFFSET + 0x10000000) diff --git a/include/asm-arm/arch-ebsa110/vmalloc.h b/include/asm-arm/arch-ebsa110/vmalloc.h index 759659be109f..26674ba4683c 100644 --- a/include/asm-arm/arch-ebsa110/vmalloc.h +++ b/include/asm-arm/arch-ebsa110/vmalloc.h @@ -7,15 +7,4 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ - -/* - * Just any arbitrary offset to the start of the vmalloc VM area: the - * current 8MB value just means that there will be a 8MB "hole" after the - * physical memory until the kernel virtual memory starts. That means that - * any out-of-bounds memory accesses will hopefully be caught. - * The vmalloc() routines leaves a hole of 4kB between each vmalloced - * area for the same reason. ;) - */ -#define VMALLOC_OFFSET (8*1024*1024) -#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) #define VMALLOC_END (PAGE_OFFSET + 0x1f000000) diff --git a/include/asm-arm/arch-ebsa285/vmalloc.h b/include/asm-arm/arch-ebsa285/vmalloc.h index def705a3c209..d1ca955ce434 100644 --- a/include/asm-arm/arch-ebsa285/vmalloc.h +++ b/include/asm-arm/arch-ebsa285/vmalloc.h @@ -8,17 +8,6 @@ #include <linux/config.h> -/* - * Just any arbitrary offset to the start of the vmalloc VM area: the - * current 8MB value just means that there will be a 8MB "hole" after the - * physical memory until the kernel virtual memory starts. That means that - * any out-of-bounds memory accesses will hopefully be caught. - * The vmalloc() routines leaves a hole of 4kB between each vmalloced - * area for the same reason. ;) - */ -#define VMALLOC_OFFSET (8*1024*1024) -#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) - #ifdef CONFIG_ARCH_FOOTBRIDGE #define VMALLOC_END (PAGE_OFFSET + 0x30000000) #else diff --git a/include/asm-arm/arch-epxa10db/vmalloc.h b/include/asm-arm/arch-epxa10db/vmalloc.h index d31ef8584760..546fb7d2b6ad 100644 --- a/include/asm-arm/arch-epxa10db/vmalloc.h +++ b/include/asm-arm/arch-epxa10db/vmalloc.h @@ -17,15 +17,4 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ - -/* - * Just any arbitrary offset to the start of the vmalloc VM area: the - * current 8MB value just means that there will be a 8MB "hole" after the - * physical memory until the kernel virtual memory starts. That means that - * any out-of-bounds memory accesses will hopefully be caught. - * The vmalloc() routines leaves a hole of 4kB between each vmalloced - * area for the same reason. ;) - */ -#define VMALLOC_OFFSET (8*1024*1024) -#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) #define VMALLOC_END (PAGE_OFFSET + 0x10000000) diff --git a/include/asm-arm/arch-h720x/vmalloc.h b/include/asm-arm/arch-h720x/vmalloc.h index 4af523a5e189..b4693cb821ef 100644 --- a/include/asm-arm/arch-h720x/vmalloc.h +++ b/include/asm-arm/arch-h720x/vmalloc.h @@ -5,17 +5,6 @@ #ifndef __ARCH_ARM_VMALLOC_H #define __ARCH_ARM_VMALLOC_H -/* - * Just any arbitrary offset to the start of the vmalloc VM area: the - * current 8MB value just means that there will be a 8MB "hole" after the - * physical memory until the kernel virtual memory starts. That means that - * any out-of-bounds memory accesses will hopefully be caught. - * The vmalloc() routines leaves a hole of 4kB between each vmalloced - * area for the same reason. ;) - */ -#define VMALLOC_OFFSET (8*1024*1024) -#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) -#define VMALLOC_VMADDR(x) ((unsigned long)(x)) #define VMALLOC_END (PAGE_OFFSET + 0x10000000) #endif diff --git a/include/asm-arm/arch-imx/imxfb.h b/include/asm-arm/arch-imx/imxfb.h new file mode 100644 index 000000000000..2346d454ab9c --- /dev/null +++ b/include/asm-arm/arch-imx/imxfb.h @@ -0,0 +1,35 @@ +/* + * This structure describes the machine which we are running on. + */ +struct imxfb_mach_info { + u_long pixclock; + + u_short xres; + u_short yres; + + u_char bpp; + u_char hsync_len; + u_char left_margin; + u_char right_margin; + + u_char vsync_len; + u_char upper_margin; + u_char lower_margin; + u_char sync; + + u_int cmap_greyscale:1, + cmap_inverse:1, + cmap_static:1, + unused:29; + + u_int pcr; + u_int pwmr; + u_int lscr1; + + u_char * fixed_screen_cpu; + dma_addr_t fixed_screen_dma; + + void (*lcd_power)(int); + void (*backlight_power)(int); +}; +void set_imx_fb_info(struct imxfb_mach_info *hard_imx_fb_info); diff --git a/include/asm-arm/arch-imx/vmalloc.h b/include/asm-arm/arch-imx/vmalloc.h index 252038f48163..cb6169127068 100644 --- a/include/asm-arm/arch-imx/vmalloc.h +++ b/include/asm-arm/arch-imx/vmalloc.h @@ -17,16 +17,4 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ - -/* - * Just any arbitrary offset to the start of the vmalloc VM area: the - * current 8MB value just means that there will be a 8MB "hole" after the - * physical memory until the kernel virtual memory starts. That means that - * any out-of-bounds memory accesses will hopefully be caught. - * The vmalloc() routines leaves a hole of 4kB between each vmalloced - * area for the same reason. ;) - */ -#define VMALLOC_OFFSET (8*1024*1024) -#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) -#define VMALLOC_VMADDR(x) ((unsigned long)(x)) #define VMALLOC_END (PAGE_OFFSET + 0x10000000) diff --git a/include/asm-arm/arch-integrator/cm.h b/include/asm-arm/arch-integrator/cm.h index d31c1a71f781..1ab353e23595 100644 --- a/include/asm-arm/arch-integrator/cm.h +++ b/include/asm-arm/arch-integrator/cm.h @@ -24,9 +24,9 @@ void cm_control(u32, u32); #define CM_CTRL_LCDBIASDN (1 << 10) #define CM_CTRL_LCDMUXSEL_MASK (7 << 11) #define CM_CTRL_LCDMUXSEL_GENLCD (1 << 11) -#define CM_CTRL_LCDMUXSEL_SHARPLCD1 (3 << 11) -#define CM_CTRL_LCDMUXSEL_SHARPLCD2 (4 << 11) -#define CM_CTRL_LCDMUXSEL_VGA (7 << 11) +#define CM_CTRL_LCDMUXSEL_VGA_16BPP (2 << 11) +#define CM_CTRL_LCDMUXSEL_SHARPLCD (3 << 11) +#define CM_CTRL_LCDMUXSEL_VGA_8421BPP (4 << 11) #define CM_CTRL_LCDEN0 (1 << 14) #define CM_CTRL_LCDEN1 (1 << 15) #define CM_CTRL_STATIC1 (1 << 16) diff --git a/include/asm-arm/arch-integrator/platform.h b/include/asm-arm/arch-integrator/platform.h index 6b67e41669f4..bd364f5a99bc 100644 --- a/include/asm-arm/arch-integrator/platform.h +++ b/include/asm-arm/arch-integrator/platform.h @@ -20,14 +20,14 @@ * * Copyright © ARM Limited 1998. All rights reserved. * ***********************************************************************/ /* ************************************************************************ - * + * * Integrator address map - * + * * NOTE: This is a multi-hosted header file for use with uHAL and * supported debuggers. - * + * * $Id: platform.s,v 1.32 2000/02/18 10:51:39 asims Exp $ - * + * * ***********************************************************************/ #ifndef __address_h @@ -40,22 +40,22 @@ * Memory definitions * ------------------------------------------------------------------------ * Integrator memory map - * + * */ #define INTEGRATOR_BOOT_ROM_LO 0x00000000 #define INTEGRATOR_BOOT_ROM_HI 0x20000000 #define INTEGRATOR_BOOT_ROM_BASE INTEGRATOR_BOOT_ROM_HI /* Normal position */ #define INTEGRATOR_BOOT_ROM_SIZE SZ_512K -/* +/* * New Core Modules have different amounts of SSRAM, the amount of SSRAM * fitted can be found in HDR_STAT. - * + * * The symbol INTEGRATOR_SSRAM_SIZE is kept, however this now refers to * the minimum amount of SSRAM fitted on any core module. - * + * * New Core Modules also alias the SSRAM. - * + * */ #define INTEGRATOR_SSRAM_BASE 0x00000000 #define INTEGRATOR_SSRAM_ALIAS_BASE 0x10800000 @@ -67,9 +67,9 @@ #define INTEGRATOR_MBRD_SSRAM_BASE 0x28000000 #define INTEGRATOR_MBRD_SSRAM_SIZE SZ_512K -/* +/* * SDRAM is a SIMM therefore the size is not known. - * + * */ #define INTEGRATOR_SDRAM_BASE 0x00040000 @@ -79,9 +79,9 @@ #define INTEGRATOR_HDR2_SDRAM_BASE 0xA0000000 #define INTEGRATOR_HDR3_SDRAM_BASE 0xB0000000 -/* +/* * Logic expansion modules - * + * */ #define INTEGRATOR_LOGIC_MODULES_BASE 0xC0000000 #define INTEGRATOR_LOGIC_MODULE0_BASE 0xC0000000 @@ -92,7 +92,7 @@ /* ------------------------------------------------------------------------ * Integrator header card registers * ------------------------------------------------------------------------ - * + * */ #define INTEGRATOR_HDR_ID_OFFSET 0x00 #define INTEGRATOR_HDR_PROC_OFFSET 0x04 @@ -185,12 +185,12 @@ /* ------------------------------------------------------------------------ * Integrator system registers * ------------------------------------------------------------------------ - * + * */ -/* +/* * System Controller - * + * */ #define INTEGRATOR_SC_ID_OFFSET 0x00 #define INTEGRATOR_SC_OSC_OFFSET 0x04 @@ -230,11 +230,11 @@ #define INTEGRATOR_SC_CTRL_URTS1 (1 << 6) #define INTEGRATOR_SC_CTRL_UDTR1 (1 << 7) -/* +/* * External Bus Interface - * + * */ -#define INTEGRATOR_EBI_BASE 0x12000000 +#define INTEGRATOR_EBI_BASE 0x12000000 #define INTEGRATOR_EBI_CSR0_OFFSET 0x00 #define INTEGRATOR_EBI_CSR1_OFFSET 0x04 @@ -279,9 +279,9 @@ #define INTEGRATOR_KBD_BASE 0x18000000 /* Keyboard */ #define INTEGRATOR_MOUSE_BASE 0x19000000 /* Mouse */ -/* +/* * LED's & Switches - * + * */ #define INTEGRATOR_DBG_ALPHA_OFFSET 0x00 #define INTEGRATOR_DBG_LEDS_OFFSET 0x04 @@ -300,7 +300,7 @@ * ------------------------------------------------------------------------ */ /* PS2 Keyboard interface */ -#define KMI0_BASE INTEGRATOR_KBD_BASE +#define KMI0_BASE INTEGRATOR_KBD_BASE /* PS2 Mouse interface */ #define KMI1_BASE INTEGRATOR_MOUSE_BASE @@ -313,7 +313,7 @@ * This represents a fairly liberal usage of address space. Even though * the V3 only has two windows (therefore we need to map stuff on the fly), * we maintain the same addresses, even if they're not mapped. - * + * */ #define PHYS_PCI_MEM_BASE 0x40000000 /* 512M to xxx */ /* unused 256M from A0000000-AFFFFFFF might be used for I2O ??? @@ -326,7 +326,7 @@ */ #define PHYS_PCI_V3_BASE 0x62000000 -#define PCI_DRAMSIZE INTEGRATOR_SSRAM_SIZE +#define PCI_DRAMSIZE INTEGRATOR_SSRAM_SIZE /* 'export' these to UHAL */ #define UHAL_PCI_IO PCI_IO_BASE @@ -334,7 +334,7 @@ #define UHAL_PCI_ALLOC_IO_BASE 0x00004000 #define UHAL_PCI_ALLOC_MEM_BASE PCI_MEM_BASE #define UHAL_PCI_MAX_SLOT 20 - + /* ======================================================================== * Start of uHAL definitions * ======================================================================== @@ -343,17 +343,17 @@ /* ------------------------------------------------------------------------ * Integrator Interrupt Controllers * ------------------------------------------------------------------------ - * - * Offsets from interrupt controller base - * + * + * Offsets from interrupt controller base + * * System Controller interrupt controller base is - * + * * INTEGRATOR_IC_BASE + (header_number << 6) - * + * * Core Module interrupt controller base is - * - * INTEGRATOR_HDR_IC - * + * + * INTEGRATOR_HDR_IC + * */ #define IRQ_STATUS 0 #define IRQ_RAW_STATUS 0x04 @@ -374,22 +374,22 @@ /* ------------------------------------------------------------------------ * Interrupts * ------------------------------------------------------------------------ - * - * + * + * * Each Core Module has two interrupts controllers, one on the core module * itself and one in the system controller on the motherboard. The * READ_INT macro in target.s reads both interrupt controllers and returns * a 32 bit bitmask, bits 0 to 23 are interrupts from the system controller * and bits 24 to 31 are from the core module. - * + * * The following definitions relate to the bitmask returned by READ_INT. - * + * */ /* ------------------------------------------------------------------------ * LED's - The header LED is not accessible via the uHAL API * ------------------------------------------------------------------------ - * + * */ #define GREEN_LED 0x01 #define YELLOW_LED 0x02 @@ -399,44 +399,44 @@ #define LED_BANK INTEGRATOR_DBG_LEDS -/* +/* * Memory definitions - run uHAL out of SSRAM. - * + * */ #define uHAL_MEMORY_SIZE INTEGRATOR_SSRAM_SIZE -/* +/* * Application Flash - * + * */ #define FLASH_BASE INTEGRATOR_FLASH_BASE #define FLASH_SIZE INTEGRATOR_FLASH_SIZE #define FLASH_END (FLASH_BASE + FLASH_SIZE - 1) #define FLASH_BLOCK_SIZE SZ_128K -/* +/* * Boot Flash - * + * */ #define EPROM_BASE INTEGRATOR_BOOT_ROM_HI #define EPROM_SIZE INTEGRATOR_BOOT_ROM_SIZE #define EPROM_END (EPROM_BASE + EPROM_SIZE - 1) -/* +/* * Clean base - dummy - * + * */ #define CLEAN_BASE EPROM_BASE -/* +/* * Timer definitions - * + * * Only use timer 1 & 2 * (both run at 24MHz and will need the clock divider set to 16). - * + * * Timer 0 runs at bus frequency and therefore could vary and currently * uHAL can't handle that. - * + * */ #define INTEGRATOR_TIMER0_BASE INTEGRATOR_CT_BASE @@ -447,9 +447,9 @@ #define MAX_PERIOD 699050 #define TICKS_PER_uSEC 24 -/* - * These are useconds NOT ticks. - * +/* + * These are useconds NOT ticks. + * */ #define mSEC_1 1000 #define mSEC_5 (mSEC_1 * 5) diff --git a/include/asm-arm/arch-integrator/vmalloc.h b/include/asm-arm/arch-integrator/vmalloc.h index 50e9aee79486..170cccece523 100644 --- a/include/asm-arm/arch-integrator/vmalloc.h +++ b/include/asm-arm/arch-integrator/vmalloc.h @@ -17,15 +17,4 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ - -/* - * Just any arbitrary offset to the start of the vmalloc VM area: the - * current 8MB value just means that there will be a 8MB "hole" after the - * physical memory until the kernel virtual memory starts. That means that - * any out-of-bounds memory accesses will hopefully be caught. - * The vmalloc() routines leaves a hole of 4kB between each vmalloced - * area for the same reason. ;) - */ -#define VMALLOC_OFFSET (8*1024*1024) -#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) #define VMALLOC_END (PAGE_OFFSET + 0x10000000) diff --git a/include/asm-arm/arch-iop3xx/vmalloc.h b/include/asm-arm/arch-iop3xx/vmalloc.h index dc1d2a957164..0f2f6847f93c 100644 --- a/include/asm-arm/arch-iop3xx/vmalloc.h +++ b/include/asm-arm/arch-iop3xx/vmalloc.h @@ -10,9 +10,6 @@ * The vmalloc() routines leaves a hole of 4kB between each vmalloced * area for the same reason. ;) */ -#define VMALLOC_OFFSET (8*1024*1024) -#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) -#define VMALLOC_VMADDR(x) ((unsigned long)(x)) //#define VMALLOC_END (0xe8000000) /* increase usable physical RAM to ~992M per RMK */ #define VMALLOC_END (0xfe000000) diff --git a/include/asm-arm/arch-ixp2000/platform.h b/include/asm-arm/arch-ixp2000/platform.h index 509e44d528d8..901bba6d02b4 100644 --- a/include/asm-arm/arch-ixp2000/platform.h +++ b/include/asm-arm/arch-ixp2000/platform.h @@ -121,6 +121,7 @@ unsigned long ixp2000_gettimeoffset(void); struct pci_sys_data; +u32 *ixp2000_pci_config_addr(unsigned int bus, unsigned int devfn, int where); void ixp2000_pci_preinit(void); int ixp2000_pci_setup(int, struct pci_sys_data*); struct pci_bus* ixp2000_pci_scan_bus(int, struct pci_sys_data*); diff --git a/include/asm-arm/arch-ixp2000/vmalloc.h b/include/asm-arm/arch-ixp2000/vmalloc.h index 2e4bcbcf31f0..473dff4ec561 100644 --- a/include/asm-arm/arch-ixp2000/vmalloc.h +++ b/include/asm-arm/arch-ixp2000/vmalloc.h @@ -17,7 +17,4 @@ * The vmalloc() routines leaves a hole of 4kB between each vmalloced * area for the same reason. ;) */ -#define VMALLOC_OFFSET (8*1024*1024) -#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) -#define VMALLOC_VMADDR(x) ((unsigned long)(x)) #define VMALLOC_END 0xfaffefff diff --git a/include/asm-arm/arch-ixp4xx/vmalloc.h b/include/asm-arm/arch-ixp4xx/vmalloc.h index da46e560ad6f..050d46e6b126 100644 --- a/include/asm-arm/arch-ixp4xx/vmalloc.h +++ b/include/asm-arm/arch-ixp4xx/vmalloc.h @@ -1,17 +1,5 @@ /* * linux/include/asm-arm/arch-ixp4xx/vmalloc.h */ - -/* - * Just any arbitrary offset to the start of the vmalloc VM area: the - * current 8MB value just means that there will be a 8MB "hole" after the - * physical memory until the kernel virtual memory starts. That means that - * any out-of-bounds memory accesses will hopefully be caught. - * The vmalloc() routines leaves a hole of 4kB between each vmalloced - * area for the same reason. ;) - */ -#define VMALLOC_OFFSET (8*1024*1024) -#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) -#define VMALLOC_VMADDR(x) ((unsigned long)(x)) #define VMALLOC_END (0xFF000000) diff --git a/include/asm-arm/arch-l7200/vmalloc.h b/include/asm-arm/arch-l7200/vmalloc.h index edeaebe1f14a..816231eedaac 100644 --- a/include/asm-arm/arch-l7200/vmalloc.h +++ b/include/asm-arm/arch-l7200/vmalloc.h @@ -1,15 +1,4 @@ /* * linux/include/asm-arm/arch-l7200/vmalloc.h */ - -/* - * Just any arbitrary offset to the start of the vmalloc VM area: the - * current 8MB value just means that there will be a 8MB "hole" after the - * physical memory until the kernel virtual memory starts. That means that - * any out-of-bounds memory accesses will hopefully be caught. - * The vmalloc() routines leaves a hole of 4kB between each vmalloced - * area for the same reason. ;) - */ -#define VMALLOC_OFFSET (8*1024*1024) -#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) #define VMALLOC_END (PAGE_OFFSET + 0x10000000) diff --git a/include/asm-arm/arch-lh7a40x/vmalloc.h b/include/asm-arm/arch-lh7a40x/vmalloc.h index 5ac607925bea..8163e45109b9 100644 --- a/include/asm-arm/arch-lh7a40x/vmalloc.h +++ b/include/asm-arm/arch-lh7a40x/vmalloc.h @@ -7,15 +7,4 @@ * version 2 as published by the Free Software Foundation. * */ - -/* - * Just any arbitrary offset to the start of the vmalloc VM area: the - * current 8MB value just means that there will be a 8MB "hole" after - * the physical memory until the kernel virtual memory starts. That - * means that any out-of-bounds memory accesses will hopefully be - * caught. The vmalloc() routines leaves a hole of 4kB (one page) - * between each vmalloced area for the same reason. ;) - */ -#define VMALLOC_OFFSET (8*1024*1024) -#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) #define VMALLOC_END (0xe8000000) diff --git a/include/asm-arm/arch-omap/vmalloc.h b/include/asm-arm/arch-omap/vmalloc.h index c6a83581a2fc..5b8bd8dae8be 100644 --- a/include/asm-arm/arch-omap/vmalloc.h +++ b/include/asm-arm/arch-omap/vmalloc.h @@ -17,17 +17,5 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ - -/* - * Just any arbitrary offset to the start of the vmalloc VM area: the - * current 8MB value just means that there will be a 8MB "hole" after the - * physical memory until the kernel virtual memory starts. That means that - * any out-of-bounds memory accesses will hopefully be caught. - * The vmalloc() routines leaves a hole of 4kB between each vmalloced - * area for the same reason. ;) - */ -#define VMALLOC_OFFSET (8*1024*1024) -#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) -#define VMALLOC_VMADDR(x) ((unsigned long)(x)) #define VMALLOC_END (PAGE_OFFSET + 0x10000000) diff --git a/include/asm-arm/arch-pxa/vmalloc.h b/include/asm-arm/arch-pxa/vmalloc.h index 3381af6ddb0d..5bb450c7aa2c 100644 --- a/include/asm-arm/arch-pxa/vmalloc.h +++ b/include/asm-arm/arch-pxa/vmalloc.h @@ -8,15 +8,4 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ - -/* - * Just any arbitrary offset to the start of the vmalloc VM area: the - * current 8MB value just means that there will be a 8MB "hole" after the - * physical memory until the kernel virtual memory starts. That means that - * any out-of-bounds memory accesses will hopefully be caught. - * The vmalloc() routines leaves a hole of 4kB between each vmalloced - * area for the same reason. ;) - */ -#define VMALLOC_OFFSET (8*1024*1024) -#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) #define VMALLOC_END (0xe8000000) diff --git a/include/asm-arm/arch-rpc/vmalloc.h b/include/asm-arm/arch-rpc/vmalloc.h index a13c27f37d71..077046bb2f36 100644 --- a/include/asm-arm/arch-rpc/vmalloc.h +++ b/include/asm-arm/arch-rpc/vmalloc.h @@ -7,15 +7,4 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ - -/* - * Just any arbitrary offset to the start of the vmalloc VM area: the - * current 8MB value just means that there will be a 8MB "hole" after the - * physical memory until the kernel virtual memory starts. That means that - * any out-of-bounds memory accesses will hopefully be caught. - * The vmalloc() routines leaves a hole of 4kB between each vmalloced - * area for the same reason. ;) - */ -#define VMALLOC_OFFSET (8*1024*1024) -#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) #define VMALLOC_END (PAGE_OFFSET + 0x1c000000) diff --git a/include/asm-arm/arch-s3c2410/regs-iis.h b/include/asm-arm/arch-s3c2410/regs-iis.h index 7ae8e1f45bc1..385b07d510da 100644 --- a/include/asm-arm/arch-s3c2410/regs-iis.h +++ b/include/asm-arm/arch-s3c2410/regs-iis.h @@ -14,6 +14,7 @@ * 26-06-2003 BJD Finished off definitions for register addresses * 12-03-2004 BJD Updated include protection * 07-03-2005 BJD Added FIFO size flags and S3C2440 MPLL + * 05-04-2005 LCVR Added IISFCON definitions for the S3C2400 */ #ifndef __ASM_ARCH_REGS_IIS_H @@ -68,5 +69,14 @@ #define S3C2410_IISFCON_RXMASK (0x3f) #define S3C2410_IISFCON_RXSHIFT (0) +#define S3C2400_IISFCON_TXDMA (1<<11) +#define S3C2400_IISFCON_RXDMA (1<<10) +#define S3C2400_IISFCON_TXENABLE (1<<9) +#define S3C2400_IISFCON_RXENABLE (1<<8) +#define S3C2400_IISFCON_TXMASK (0x07 << 4) +#define S3C2400_IISFCON_TXSHIFT (4) +#define S3C2400_IISFCON_RXMASK (0x07) +#define S3C2400_IISFCON_RXSHIFT (0) + #define S3C2410_IISFIFO (0x10) #endif /* __ASM_ARCH_REGS_IIS_H */ diff --git a/include/asm-arm/arch-s3c2410/regs-mem.h b/include/asm-arm/arch-s3c2410/regs-mem.h index 1a1328ac0d79..a2d7d0cec042 100644 --- a/include/asm-arm/arch-s3c2410/regs-mem.h +++ b/include/asm-arm/arch-s3c2410/regs-mem.h @@ -12,6 +12,7 @@ * Changelog: * 29-Sep-2004 BJD Initial include for Linux * 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA + * 04-Apr-2005 LCVR Added S3C2400 DRAM/BANKSIZE_MASK definitions * */ @@ -183,6 +184,12 @@ #define S3C2410_REFRESH_TRP_3clk (1<<20) #define S3C2410_REFRESH_TRP_4clk (2<<20) +#define S3C2400_REFRESH_DRAM_TRP_MASK (3<<20) +#define S3C2400_REFRESH_DRAM_TRP_1_5clk (0<<20) +#define S3C2400_REFRESH_DRAM_TRP_2_5clk (1<<20) +#define S3C2400_REFRESH_DRAM_TRP_3_5clk (2<<20) +#define S3C2400_REFRESH_DRAM_TRP_4_5clk (3<<20) + #define S3C2410_REFRESH_TSRC_MASK (3<<18) #define S3C2410_REFRESH_TSRC_4clk (0<<18) #define S3C2410_REFRESH_TSRC_5clk (1<<18) @@ -205,6 +212,7 @@ #define S3C2410_BANKSIZE_4M (0x5 << 0) #define S3C2410_BANKSIZE_2M (0x4 << 0) #define S3C2410_BANKSIZE_MASK (0x7 << 0) +#define S3C2400_BANKSIZE_MASK (0x4 << 0) #define S3C2410_BANKSIZE_SCLK_EN (1<<4) #define S3C2410_BANKSIZE_SCKE_EN (1<<5) #define S3C2410_BANKSIZE_BURST (1<<7) diff --git a/include/asm-arm/arch-s3c2410/regs-spi.h b/include/asm-arm/arch-s3c2410/regs-spi.h index cb502a88158b..338217858c73 100644 --- a/include/asm-arm/arch-s3c2410/regs-spi.h +++ b/include/asm-arm/arch-s3c2410/regs-spi.h @@ -12,6 +12,7 @@ * 20-04-2004 KF Created file * 04-10-2004 BJD Removed VA address (no longer mapped) * tidied file for submission + * 03-04-2005 LCVR Added S3C2400_SPPIN_nCS definition */ #ifndef __ASM_ARCH_REGS_SPI_H @@ -46,6 +47,7 @@ #define S3C2410_SPPIN_ENMUL (1<<2) /* Multi Master Error detect */ #define S3C2410_SPPIN_RESERVED (1<<1) +#define S3C2400_SPPIN_nCS (1<<1) /* SPI Card Select */ #define S3C2410_SPPIN_KEEP (1<<0) /* Master Out keep */ diff --git a/include/asm-arm/arch-s3c2410/uncompress.h b/include/asm-arm/arch-s3c2410/uncompress.h index ad4252e27799..d7a4a8354fa9 100644 --- a/include/asm-arm/arch-s3c2410/uncompress.h +++ b/include/asm-arm/arch-s3c2410/uncompress.h @@ -16,6 +16,7 @@ * 12-Oct-2004 BJD Take account of debug uart configuration * 15-Nov-2004 BJD Fixed uart configuration * 22-Feb-2005 BJD Added watchdog to uncompress + * 04-Apr-2005 LCVR Added support to S3C2400 (no cpuid at GSTATUS1) */ #ifndef __ASM_ARCH_UNCOMPRESS_H @@ -69,9 +70,12 @@ uart_rd(unsigned int reg) static void putc(char ch) { - int cpuid = *((volatile unsigned int *)S3C2410_GSTATUS1); + int cpuid = S3C2410_GSTATUS1_2410; +#ifndef CONFIG_CPU_S3C2400 + cpuid = *((volatile unsigned int *)S3C2410_GSTATUS1); cpuid &= S3C2410_GSTATUS1_IDMASK; +#endif if (ch == '\n') putc('\r'); /* expand newline to \r\n */ diff --git a/include/asm-arm/arch-s3c2410/vmalloc.h b/include/asm-arm/arch-s3c2410/vmalloc.h index 5fe72ad70904..33963cd5461b 100644 --- a/include/asm-arm/arch-s3c2410/vmalloc.h +++ b/include/asm-arm/arch-s3c2410/vmalloc.h @@ -19,18 +19,6 @@ #ifndef __ASM_ARCH_VMALLOC_H #define __ASM_ARCH_VMALLOC_H -/* - * Just any arbitrary offset to the start of the vmalloc VM area: the - * current 8MB value just means that there will be a 8MB "hole" after the - * physical memory until the kernel virtual memory starts. That means that - * any out-of-bounds memory accesses will hopefully be caught. - * The vmalloc() routines leaves a hole of 4kB between each vmalloced - * area for the same reason. ;) - */ - -#define VMALLOC_OFFSET (8*1024*1024) -#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) -#define VMALLOC_VMADDR(x) ((unsigned long)(x)) #define VMALLOC_END (0xE0000000) #endif /* __ASM_ARCH_VMALLOC_H */ diff --git a/include/asm-arm/arch-sa1100/vmalloc.h b/include/asm-arm/arch-sa1100/vmalloc.h index 135bc9493c06..2fb1c6f3aa1b 100644 --- a/include/asm-arm/arch-sa1100/vmalloc.h +++ b/include/asm-arm/arch-sa1100/vmalloc.h @@ -1,15 +1,4 @@ /* * linux/include/asm-arm/arch-sa1100/vmalloc.h */ - -/* - * Just any arbitrary offset to the start of the vmalloc VM area: the - * current 8MB value just means that there will be a 8MB "hole" after the - * physical memory until the kernel virtual memory starts. That means that - * any out-of-bounds memory accesses will hopefully be caught. - * The vmalloc() routines leaves a hole of 4kB between each vmalloced - * area for the same reason. ;) - */ -#define VMALLOC_OFFSET (8*1024*1024) -#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) #define VMALLOC_END (0xe8000000) diff --git a/include/asm-arm/arch-shark/vmalloc.h b/include/asm-arm/arch-shark/vmalloc.h index 1cc20098f690..10db5d188231 100644 --- a/include/asm-arm/arch-shark/vmalloc.h +++ b/include/asm-arm/arch-shark/vmalloc.h @@ -1,15 +1,4 @@ /* * linux/include/asm-arm/arch-rpc/vmalloc.h */ - -/* - * Just any arbitrary offset to the start of the vmalloc VM area: the - * current 8MB value just means that there will be a 8MB "hole" after the - * physical memory until the kernel virtual memory starts. That means that - * any out-of-bounds memory accesses will hopefully be caught. - * The vmalloc() routines leaves a hole of 4kB between each vmalloced - * area for the same reason. ;) - */ -#define VMALLOC_OFFSET (8*1024*1024) -#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) #define VMALLOC_END (PAGE_OFFSET + 0x10000000) diff --git a/include/asm-arm/arch-versatile/vmalloc.h b/include/asm-arm/arch-versatile/vmalloc.h index adfb34829bfc..ac780df62156 100644 --- a/include/asm-arm/arch-versatile/vmalloc.h +++ b/include/asm-arm/arch-versatile/vmalloc.h @@ -18,16 +18,4 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ - -/* - * Just any arbitrary offset to the start of the vmalloc VM area: the - * current 8MB value just means that there will be a 8MB "hole" after the - * physical memory until the kernel virtual memory starts. That means that - * any out-of-bounds memory accesses will hopefully be caught. - * The vmalloc() routines leaves a hole of 4kB between each vmalloced - * area for the same reason. ;) - */ -#define VMALLOC_OFFSET (8*1024*1024) -#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) -#define VMALLOC_VMADDR(x) ((unsigned long)(x)) #define VMALLOC_END (PAGE_OFFSET + 0x18000000) diff --git a/include/asm-arm/bug.h b/include/asm-arm/bug.h index 5e91b90a8181..24d11672eb60 100644 --- a/include/asm-arm/bug.h +++ b/include/asm-arm/bug.h @@ -3,6 +3,7 @@ #include <linux/config.h> +#ifdef CONFIG_BUG #ifdef CONFIG_DEBUG_BUGVERBOSE extern volatile void __bug(const char *file, int line, void *data); @@ -17,6 +18,8 @@ extern volatile void __bug(const char *file, int line, void *data); #endif #define HAVE_ARCH_BUG +#endif + #include <asm-generic/bug.h> #endif diff --git a/include/asm-arm/hardware/amba_clcd.h b/include/asm-arm/hardware/amba_clcd.h index 2149be7c7023..ce4cf5c1c05d 100644 --- a/include/asm-arm/hardware/amba_clcd.h +++ b/include/asm-arm/hardware/amba_clcd.h @@ -153,7 +153,7 @@ struct clcd_fb { static inline void clcdfb_decode(struct clcd_fb *fb, struct clcd_regs *regs) { - u32 val; + u32 val, cpl; /* * Program the CLCD controller registers and start the CLCD @@ -164,7 +164,10 @@ static inline void clcdfb_decode(struct clcd_fb *fb, struct clcd_regs *regs) val |= (fb->fb.var.left_margin - 1) << 24; regs->tim0 = val; - val = fb->fb.var.yres - 1; + val = fb->fb.var.yres; + if (fb->panel->cntl & CNTL_LCDDUAL) + val /= 2; + val -= 1; val |= (fb->fb.var.vsync_len - 1) << 10; val |= fb->fb.var.lower_margin << 16; val |= fb->fb.var.upper_margin << 24; @@ -174,13 +177,17 @@ static inline void clcdfb_decode(struct clcd_fb *fb, struct clcd_regs *regs) val |= fb->fb.var.sync & FB_SYNC_HOR_HIGH_ACT ? 0 : TIM2_IHS; val |= fb->fb.var.sync & FB_SYNC_VERT_HIGH_ACT ? 0 : TIM2_IVS; - if (fb->panel->cntl & CNTL_LCDTFT) - val |= (fb->fb.var.xres_virtual - 1) << 16; - else if (fb->panel->cntl & CNTL_LCDBW) - printk("what value for CPL for stnmono panels?"); - else - val |= ((fb->fb.var.xres_virtual * 8 / 3) - 1) << 16; - regs->tim2 = val; + cpl = fb->fb.var.xres_virtual; + if (fb->panel->cntl & CNTL_LCDTFT) /* TFT */ + /* / 1 */; + else if (!fb->fb.var.grayscale) /* STN color */ + cpl = cpl * 8 / 3; + else if (fb->panel->cntl & CNTL_LCDMONO8) /* STN monochrome, 8bit */ + cpl /= 8; + else /* STN monochrome, 4bit */ + cpl /= 4; + + regs->tim2 = val | ((cpl - 1) << 16); regs->tim3 = fb->panel->tim3; @@ -204,7 +211,7 @@ static inline void clcdfb_decode(struct clcd_fb *fb, struct clcd_regs *regs) case 16: val |= CNTL_LCDBPP16; break; - case 24: + case 32: val |= CNTL_LCDBPP24; break; } @@ -215,8 +222,8 @@ static inline void clcdfb_decode(struct clcd_fb *fb, struct clcd_regs *regs) static inline int clcdfb_check(struct clcd_fb *fb, struct fb_var_screeninfo *var) { - var->xres_virtual = var->xres = (var->xres + 7) & ~7; - var->yres_virtual = var->yres; + var->xres_virtual = var->xres = (var->xres + 15) & ~15; + var->yres_virtual = var->yres = (var->yres + 1) & ~1; #define CHECK(e,l,h) (var->e < l || var->e > h) if (CHECK(right_margin, (5+1), 256) || /* back porch */ diff --git a/include/asm-arm/hardware/clock.h b/include/asm-arm/hardware/clock.h index 4983449ff2c7..19da861e523d 100644 --- a/include/asm-arm/hardware/clock.h +++ b/include/asm-arm/hardware/clock.h @@ -26,10 +26,13 @@ struct clk; /** * clk_get - lookup and obtain a reference to a clock producer. * @dev: device for clock "consumer" - * @id: device ID + * @id: clock comsumer ID * * Returns a struct clk corresponding to the clock producer, or - * valid IS_ERR() condition containing errno. + * valid IS_ERR() condition containing errno. The implementation + * uses @dev and @id to determine the clock consumer, and thereby + * the clock producer. (IOW, @id may be identical strings, but + * clk_get may return different clock producers depending on @dev.) */ struct clk *clk_get(struct device *dev, const char *id); diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h index 69bc7a3e8160..658ffa384fda 100644 --- a/include/asm-arm/io.h +++ b/include/asm-arm/io.h @@ -99,12 +99,16 @@ extern void __readwrite_bug(const char *fn); */ #ifdef __io #define outb(v,p) __raw_writeb(v,__io(p)) -#define outw(v,p) __raw_writew(cpu_to_le16(v),__io(p)) -#define outl(v,p) __raw_writel(cpu_to_le32(v),__io(p)) +#define outw(v,p) __raw_writew((__force __u16) \ + cpu_to_le16(v),__io(p)) +#define outl(v,p) __raw_writel((__force __u32) \ + cpu_to_le32(v),__io(p)) -#define inb(p) ({ unsigned int __v = __raw_readb(__io(p)); __v; }) -#define inw(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; }) -#define inl(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; }) +#define inb(p) ({ __u8 __v = __raw_readb(__io(p)); __v; }) +#define inw(p) ({ __u16 __v = le16_to_cpu((__force __le16) \ + __raw_readw(__io(p))); __v; }) +#define inl(p) ({ __u32 __v = le32_to_cpu((__force __le32) \ + __raw_readl(__io(p))); __v; }) #define outsb(p,d,l) __raw_writesb(__io(p),d,l) #define outsw(p,d,l) __raw_writesw(__io(p),d,l) @@ -149,9 +153,11 @@ extern void _memset_io(void __iomem *, int, size_t); * IO port primitives for more information. */ #ifdef __mem_pci -#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; }) -#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; }) -#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; }) +#define readb(c) ({ __u8 __v = __raw_readb(__mem_pci(c)); __v; }) +#define readw(c) ({ __u16 __v = le16_to_cpu((__force __le16) \ + __raw_readw(__mem_pci(c))); __v; }) +#define readl(c) ({ __u32 __v = le32_to_cpu((__force __le32) \ + __raw_readl(__mem_pci(c))); __v; }) #define readb_relaxed(addr) readb(addr) #define readw_relaxed(addr) readw(addr) #define readl_relaxed(addr) readl(addr) @@ -161,8 +167,10 @@ extern void _memset_io(void __iomem *, int, size_t); #define readsl(p,d,l) __raw_readsl(__mem_pci(p),d,l) #define writeb(v,c) __raw_writeb(v,__mem_pci(c)) -#define writew(v,c) __raw_writew(cpu_to_le16(v),__mem_pci(c)) -#define writel(v,c) __raw_writel(cpu_to_le32(v),__mem_pci(c)) +#define writew(v,c) __raw_writew((__force __u16) \ + cpu_to_le16(v),__mem_pci(c)) +#define writel(v,c) __raw_writel((__force __u32) \ + cpu_to_le32(v),__mem_pci(c)) #define writesb(p,d,l) __raw_writesb(__mem_pci(p),d,l) #define writesw(p,d,l) __raw_writesw(__mem_pci(p),d,l) diff --git a/include/asm-arm/pgtable.h b/include/asm-arm/pgtable.h index 2df4eacf4fa9..a9892eb42a23 100644 --- a/include/asm-arm/pgtable.h +++ b/include/asm-arm/pgtable.h @@ -17,6 +17,23 @@ #include <asm/arch/vmalloc.h> /* + * Just any arbitrary offset to the start of the vmalloc VM area: the + * current 8MB value just means that there will be a 8MB "hole" after the + * physical memory until the kernel virtual memory starts. That means that + * any out-of-bounds memory accesses will hopefully be caught. + * The vmalloc() routines leaves a hole of 4kB between each vmalloced + * area for the same reason. ;) + * + * Note that platforms may override VMALLOC_START, but they must provide + * VMALLOC_END. VMALLOC_END defines the (exclusive) limit of this space, + * which may not overlap IO space. + */ +#ifndef VMALLOC_START +#define VMALLOC_OFFSET (8*1024*1024) +#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) +#endif + +/* * Hardware-wise, we have a two level page table structure, where the first * level has 4096 entries, and the second level has 256 entries. Each entry * is one 32-bit word. Most of the bits in the second level entry are used diff --git a/include/asm-arm/processor.h b/include/asm-arm/processor.h index 4a9845997a75..7d4118e09054 100644 --- a/include/asm-arm/processor.h +++ b/include/asm-arm/processor.h @@ -23,8 +23,6 @@ #include <asm/procinfo.h> #include <asm/types.h> -#define KERNEL_STACK_SIZE PAGE_SIZE - union debug_insn { u32 arm; u16 thumb; @@ -87,8 +85,9 @@ unsigned long get_wchan(struct task_struct *p); */ extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags); -#define KSTK_EIP(tsk) (((unsigned long *)(4096+(unsigned long)(tsk)->thread_info))[1019]) -#define KSTK_ESP(tsk) (((unsigned long *)(4096+(unsigned long)(tsk)->thread_info))[1017]) +#define KSTK_REGS(tsk) (((struct pt_regs *)(THREAD_START_SP + (unsigned long)(tsk)->thread_info)) - 1) +#define KSTK_EIP(tsk) KSTK_REGS(tsk)->ARM_pc +#define KSTK_ESP(tsk) KSTK_REGS(tsk)->ARM_sp /* * Prefetching support - only ARMv5. diff --git a/include/asm-arm/rtc.h b/include/asm-arm/rtc.h index aa7e16b2e225..370dfe77589d 100644 --- a/include/asm-arm/rtc.h +++ b/include/asm-arm/rtc.h @@ -18,9 +18,9 @@ struct rtc_ops { void (*release)(void); int (*ioctl)(unsigned int, unsigned long); - void (*read_time)(struct rtc_time *); + int (*read_time)(struct rtc_time *); int (*set_time)(struct rtc_time *); - void (*read_alarm)(struct rtc_wkalrm *); + int (*read_alarm)(struct rtc_wkalrm *); int (*set_alarm)(struct rtc_wkalrm *); int (*proc)(char *buf); }; diff --git a/include/asm-arm/signal.h b/include/asm-arm/signal.h index b033e5fd60fa..46e69ae395af 100644 --- a/include/asm-arm/signal.h +++ b/include/asm-arm/signal.h @@ -114,34 +114,10 @@ typedef unsigned long sigset_t; #define SIGSTKSZ 8192 #ifdef __KERNEL__ - -/* - * These values of sa_flags are used only by the kernel as part of the - * irq handling routines. - * - * SA_INTERRUPT is also used by the irq handling routines. - * SA_SHIRQ is for shared interrupt support on PCI and EISA. - */ -#define SA_PROBE 0x80000000 -#define SA_SAMPLE_RANDOM 0x10000000 #define SA_IRQNOMASK 0x08000000 -#define SA_SHIRQ 0x04000000 #endif -#define SIG_BLOCK 0 /* for blocking signals */ -#define SIG_UNBLOCK 1 /* for unblocking signals */ -#define SIG_SETMASK 2 /* for setting the signal mask */ - -/* Type of a signal handler. */ -typedef void __signalfn_t(int); -typedef __signalfn_t __user *__sighandler_t; - -typedef void __restorefn_t(void); -typedef __restorefn_t __user *__sigrestore_t; - -#define SIG_DFL ((__sighandler_t)0) /* default signal handling */ -#define SIG_IGN ((__sighandler_t)1) /* ignore signal */ -#define SIG_ERR ((__sighandler_t)-1) /* error return from signal */ +#include <asm-generic/signal.h> #ifdef __KERNEL__ struct old_sigaction { diff --git a/include/asm-arm/string.h b/include/asm-arm/string.h index 2a8ab162412f..e50c4a39b699 100644 --- a/include/asm-arm/string.h +++ b/include/asm-arm/string.h @@ -29,15 +29,22 @@ extern void __memzero(void *ptr, __kernel_size_t n); #define memset(p,v,n) \ ({ \ - if ((n) != 0) { \ + void *__p = (p); size_t __n = n; \ + if ((__n) != 0) { \ if (__builtin_constant_p((v)) && (v) == 0) \ - __memzero((p),(n)); \ + __memzero((__p),(__n)); \ else \ - memset((p),(v),(n)); \ + memset((__p),(v),(__n)); \ } \ - (p); \ + (__p); \ }) -#define memzero(p,n) ({ if ((n) != 0) __memzero((p),(n)); (p); }) +#define memzero(p,n) \ + ({ \ + void *__p = (p); size_t __n = n; \ + if ((__n) != 0) \ + __memzero((__p),(__n)); \ + (__p); \ + }) #endif diff --git a/include/asm-arm/thread_info.h b/include/asm-arm/thread_info.h index a61618fb433c..66c585c50cf9 100644 --- a/include/asm-arm/thread_info.h +++ b/include/asm-arm/thread_info.h @@ -14,6 +14,10 @@ #include <asm/fpstate.h> +#define THREAD_SIZE_ORDER 1 +#define THREAD_SIZE 8192 +#define THREAD_START_SP (THREAD_SIZE - 8) + #ifndef __ASSEMBLY__ struct task_struct; @@ -77,8 +81,6 @@ struct thread_info { #define init_thread_info (init_thread_union.thread_info) #define init_stack (init_thread_union.stack) -#define THREAD_SIZE 8192 - /* * how to get the thread information struct from C */ diff --git a/include/asm-arm/unistd.h b/include/asm-arm/unistd.h index a19ec09eaa01..ace27480886e 100644 --- a/include/asm-arm/unistd.h +++ b/include/asm-arm/unistd.h @@ -359,8 +359,7 @@ #define __ARM_NR_cacheflush (__ARM_NR_BASE+2) #define __ARM_NR_usr26 (__ARM_NR_BASE+3) #define __ARM_NR_usr32 (__ARM_NR_BASE+4) - -#define __ARM_NR_set_tls (__ARM_NR_BASE+0x800) +#define __ARM_NR_set_tls (__ARM_NR_BASE+5) #define __sys2(x) #x #define __sys1(x) __sys2(x) diff --git a/include/asm-arm26/bug.h b/include/asm-arm26/bug.h index 920b70533368..7177c7399967 100644 --- a/include/asm-arm26/bug.h +++ b/include/asm-arm26/bug.h @@ -3,6 +3,7 @@ #include <linux/config.h> +#ifdef CONFIG_BUG #ifdef CONFIG_DEBUG_BUGVERBOSE extern volatile void __bug(const char *file, int line, void *data); /* give file/line information */ @@ -12,6 +13,8 @@ extern volatile void __bug(const char *file, int line, void *data); #endif #define HAVE_ARCH_BUG +#endif + #include <asm-generic/bug.h> #endif diff --git a/include/asm-arm26/signal.h b/include/asm-arm26/signal.h index 6f62e51a2e5a..dedb29280303 100644 --- a/include/asm-arm26/signal.h +++ b/include/asm-arm26/signal.h @@ -114,30 +114,10 @@ typedef unsigned long sigset_t; #define SIGSTKSZ 8192 #ifdef __KERNEL__ - -/* - * These values of sa_flags are used only by the kernel as part of the - * irq handling routines. - * - * SA_INTERRUPT is also used by the irq handling routines. - * SA_SHIRQ is for shared interrupt support on PCI and EISA. - */ -#define SA_PROBE 0x80000000 -#define SA_SAMPLE_RANDOM 0x10000000 #define SA_IRQNOMASK 0x08000000 -#define SA_SHIRQ 0x04000000 #endif -#define SIG_BLOCK 0 /* for blocking signals */ -#define SIG_UNBLOCK 1 /* for unblocking signals */ -#define SIG_SETMASK 2 /* for setting the signal mask */ - -/* Type of a signal handler. */ -typedef void (*__sighandler_t)(int); - -#define SIG_DFL ((__sighandler_t)0) /* default signal handling */ -#define SIG_IGN ((__sighandler_t)1) /* ignore signal */ -#define SIG_ERR ((__sighandler_t)-1) /* error return from signal */ +#include <asm-generic/signal.h> #ifdef __KERNEL__ struct old_sigaction { diff --git a/include/asm-cris/page.h b/include/asm-cris/page.h index ddd8915e41e6..c767da1ef8f5 100644 --- a/include/asm-cris/page.h +++ b/include/asm-cris/page.h @@ -77,10 +77,6 @@ typedef struct { unsigned long pgprot; } pgprot_t; printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__); \ } while (0) -#define PAGE_BUG(page) do { \ - BUG(); \ -} while (0) - /* Pure 2^n version of get_order */ static inline int get_order(unsigned long size) { diff --git a/include/asm-cris/signal.h b/include/asm-cris/signal.h index 3f187ec4800a..dfe039593a78 100644 --- a/include/asm-cris/signal.h +++ b/include/asm-cris/signal.h @@ -108,30 +108,7 @@ typedef unsigned long sigset_t; #define MINSIGSTKSZ 2048 #define SIGSTKSZ 8192 -#ifdef __KERNEL__ - -/* - * These values of sa_flags are used only by the kernel as part of the - * irq handling routines. - * - * SA_INTERRUPT is also used by the irq handling routines. - * SA_SHIRQ is for shared interrupt support - */ -#define SA_PROBE SA_ONESHOT -#define SA_SAMPLE_RANDOM SA_RESTART -#define SA_SHIRQ 0x04000000 -#endif - -#define SIG_BLOCK 0 /* for blocking signals */ -#define SIG_UNBLOCK 1 /* for unblocking signals */ -#define SIG_SETMASK 2 /* for setting the signal mask */ - -/* Type of a signal handler. */ -typedef void (*__sighandler_t)(int); - -#define SIG_DFL ((__sighandler_t)0) /* default signal handling */ -#define SIG_IGN ((__sighandler_t)1) /* ignore signal */ -#define SIG_ERR ((__sighandler_t)-1) /* error return from signal */ +#include <asm-generic/signal.h> #ifdef __KERNEL__ struct old_sigaction { diff --git a/include/asm-frv/bug.h b/include/asm-frv/bug.h index 011860b28818..074c0d5770eb 100644 --- a/include/asm-frv/bug.h +++ b/include/asm-frv/bug.h @@ -13,6 +13,7 @@ #include <linux/config.h> +#ifdef CONFIG_BUG /* * Tell the user there is some problem. */ @@ -45,6 +46,7 @@ do { \ #define HAVE_ARCH_KGDB_BAD_PAGE #define kgdb_bad_page(page) do { kgdb_raise(SIGABRT); } while(0) #endif +#endif #include <asm-generic/bug.h> diff --git a/include/asm-frv/pgtable.h b/include/asm-frv/pgtable.h index 3c6d42a22dfe..d0a9c2f9c13e 100644 --- a/include/asm-frv/pgtable.h +++ b/include/asm-frv/pgtable.h @@ -349,9 +349,9 @@ static inline pmd_t *pmd_offset(pud_t *dir, unsigned long address) /* * Define this to warn about kernel memory accesses that are - * done without a 'verify_area(VERIFY_WRITE,..)' + * done without a 'access_ok(VERIFY_WRITE,..)' */ -#undef TEST_VERIFY_AREA +#undef TEST_ACCESS_OK #define pte_present(x) (pte_val(x) & _PAGE_PRESENT) #define pte_clear(mm,addr,xp) do { set_pte_at(mm, addr, xp, __pte(0)); } while (0) diff --git a/include/asm-frv/signal.h b/include/asm-frv/signal.h index f18952f86a80..d407bde57eca 100644 --- a/include/asm-frv/signal.h +++ b/include/asm-frv/signal.h @@ -107,30 +107,7 @@ typedef unsigned long sigset_t; #define MINSIGSTKSZ 2048 #define SIGSTKSZ 8192 -#ifdef __KERNEL__ - -/* - * These values of sa_flags are used only by the kernel as part of the - * irq handling routines. - * - * SA_INTERRUPT is also used by the irq handling routines. - * SA_SHIRQ is for shared interrupt support on PCI and EISA. - */ -#define SA_PROBE SA_ONESHOT -#define SA_SAMPLE_RANDOM SA_RESTART -#define SA_SHIRQ 0x04000000 -#endif - -#define SIG_BLOCK 0 /* for blocking signals */ -#define SIG_UNBLOCK 1 /* for unblocking signals */ -#define SIG_SETMASK 2 /* for setting the signal mask */ - -/* Type of a signal handler. */ -typedef void (*__sighandler_t)(int); - -#define SIG_DFL ((__sighandler_t)0) /* default signal handling */ -#define SIG_IGN ((__sighandler_t)1) /* ignore signal */ -#define SIG_ERR ((__sighandler_t)-1) /* error return from signal */ +#include <asm-generic/signal.h> #ifdef __KERNEL__ struct old_sigaction { diff --git a/include/asm-generic/bug.h b/include/asm-generic/bug.h index e5913c3b715a..400c2b41896e 100644 --- a/include/asm-generic/bug.h +++ b/include/asm-generic/bug.h @@ -4,6 +4,7 @@ #include <linux/compiler.h> #include <linux/config.h> +#ifdef CONFIG_BUG #ifndef HAVE_ARCH_BUG #define BUG() do { \ printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__); \ @@ -11,13 +12,6 @@ } while (0) #endif -#ifndef HAVE_ARCH_PAGE_BUG -#define PAGE_BUG(page) do { \ - printk("page BUG for page at %p\n", page); \ - BUG(); \ -} while (0) -#endif - #ifndef HAVE_ARCH_BUG_ON #define BUG_ON(condition) do { if (unlikely((condition)!=0)) BUG(); } while(0) #endif @@ -31,4 +25,18 @@ } while (0) #endif +#else /* !CONFIG_BUG */ +#ifndef HAVE_ARCH_BUG +#define BUG() +#endif + +#ifndef HAVE_ARCH_BUG_ON +#define BUG_ON(condition) do { if (condition) ; } while(0) +#endif + +#ifndef HAVE_ARCH_WARN_ON +#define WARN_ON(condition) do { if (condition) ; } while(0) +#endif +#endif + #endif diff --git a/include/asm-generic/errno.h b/include/asm-generic/errno.h index 4dd2384bc38d..e8852c092fea 100644 --- a/include/asm-generic/errno.h +++ b/include/asm-generic/errno.h @@ -102,4 +102,8 @@ #define EKEYREVOKED 128 /* Key has been revoked */ #define EKEYREJECTED 129 /* Key was rejected by service */ +/* for robust mutexes */ +#define EOWNERDEAD 130 /* Owner died */ +#define ENOTRECOVERABLE 131 /* State not recoverable */ + #endif diff --git a/include/asm-generic/resource.h b/include/asm-generic/resource.h index b1fcda9eac23..cfe3692b23e5 100644 --- a/include/asm-generic/resource.h +++ b/include/asm-generic/resource.h @@ -41,8 +41,11 @@ #define RLIMIT_LOCKS 10 /* maximum file locks held */ #define RLIMIT_SIGPENDING 11 /* max number of pending signals */ #define RLIMIT_MSGQUEUE 12 /* maximum bytes in POSIX mqueues */ +#define RLIMIT_NICE 13 /* max nice prio allowed to raise to + 0-39 for nice level 19 .. -20 */ +#define RLIMIT_RTPRIO 14 /* maximum realtime priority */ -#define RLIM_NLIMITS 13 +#define RLIM_NLIMITS 15 /* * SuS says limits have to be unsigned. @@ -81,6 +84,8 @@ [RLIMIT_LOCKS] = { RLIM_INFINITY, RLIM_INFINITY }, \ [RLIMIT_SIGPENDING] = { 0, 0 }, \ [RLIMIT_MSGQUEUE] = { MQ_BYTES_MAX, MQ_BYTES_MAX }, \ + [RLIMIT_NICE] = { 0, 0 }, \ + [RLIMIT_RTPRIO] = { 0, 0 }, \ } #endif /* __KERNEL__ */ diff --git a/include/asm-generic/sections.h b/include/asm-generic/sections.h index 976ac29598b7..195ccdc069e6 100644 --- a/include/asm-generic/sections.h +++ b/include/asm-generic/sections.h @@ -8,6 +8,8 @@ extern char _data[], _sdata[], _edata[]; extern char __bss_start[], __bss_stop[]; extern char __init_begin[], __init_end[]; extern char _sinittext[], _einittext[]; +extern char _sextratext[] __attribute__((weak)); +extern char _eextratext[] __attribute__((weak)); extern char _end[]; #endif /* _ASM_GENERIC_SECTIONS_H_ */ diff --git a/include/asm-generic/siginfo.h b/include/asm-generic/siginfo.h index 9cac8e8dde51..8786e01e0db8 100644 --- a/include/asm-generic/siginfo.h +++ b/include/asm-generic/siginfo.h @@ -236,11 +236,18 @@ typedef struct siginfo { #define SIGEV_THREAD 2 /* deliver via thread creation */ #define SIGEV_THREAD_ID 4 /* deliver to thread */ -#define SIGEV_MAX_SIZE 64 -#ifndef SIGEV_PAD_SIZE -#define SIGEV_PAD_SIZE ((SIGEV_MAX_SIZE/sizeof(int)) - 3) +/* + * This works because the alignment is ok on all current architectures + * but we leave open this being overridden in the future + */ +#ifndef __ARCH_SIGEV_PREAMBLE_SIZE +#define __ARCH_SIGEV_PREAMBLE_SIZE (sizeof(int) * 2 + sizeof(sigval_t)) #endif +#define SIGEV_MAX_SIZE 64 +#define SIGEV_PAD_SIZE ((SIGEV_MAX_SIZE - __ARCH_SIGEV_PREAMBLE_SIZE) \ + / sizeof(int)) + typedef struct sigevent { sigval_t sigev_value; int sigev_signo; diff --git a/include/asm-generic/signal.h b/include/asm-generic/signal.h new file mode 100644 index 000000000000..9418d6e9b8cd --- /dev/null +++ b/include/asm-generic/signal.h @@ -0,0 +1,21 @@ +#ifndef SIG_BLOCK +#define SIG_BLOCK 0 /* for blocking signals */ +#endif +#ifndef SIG_UNBLOCK +#define SIG_UNBLOCK 1 /* for unblocking signals */ +#endif +#ifndef SIG_SETMASK +#define SIG_SETMASK 2 /* for setting the signal mask */ +#endif + +#ifndef __ASSEMBLY__ +typedef void __signalfn_t(int); +typedef __signalfn_t __user *__sighandler_t; + +typedef void __restorefn_t(void); +typedef __restorefn_t __user *__sigrestore_t; + +#define SIG_DFL ((__force __sighandler_t)0) /* default signal handling */ +#define SIG_IGN ((__force __sighandler_t)1) /* ignore signal */ +#define SIG_ERR ((__force __sighandler_t)-1) /* error return from signal */ +#endif diff --git a/include/asm-generic/unaligned.h b/include/asm-generic/unaligned.h index c856a43e3b45..6c90f0f36eec 100644 --- a/include/asm-generic/unaligned.h +++ b/include/asm-generic/unaligned.h @@ -76,46 +76,47 @@ static inline void __ustw(__u16 val, __u16 *addr) ptr->x = val; } -static inline unsigned long __get_unaligned(const void *ptr, size_t size) -{ - unsigned long val; - switch (size) { - case 1: - val = *(const __u8 *)ptr; - break; - case 2: - val = __uldw((const __u16 *)ptr); - break; - case 4: - val = __uldl((const __u32 *)ptr); - break; - case 8: - val = __uldq((const __u64 *)ptr); - break; - default: - bad_unaligned_access_length(); - }; - return val; -} - -static inline void __put_unaligned(unsigned long val, void *ptr, size_t size) -{ - switch (size) { - case 1: - *(__u8 *)ptr = val; - break; - case 2: - __ustw(val, (__u16 *)ptr); - break; - case 4: - __ustl(val, (__u32 *)ptr); - break; - case 8: - __ustq(val, (__u64 *)ptr); - break; - default: - bad_unaligned_access_length(); - }; -} +#define __get_unaligned(ptr, size) ({ \ + const void *__gu_p = ptr; \ + unsigned long val; \ + switch (size) { \ + case 1: \ + val = *(const __u8 *)__gu_p; \ + break; \ + case 2: \ + val = __uldw(__gu_p); \ + break; \ + case 4: \ + val = __uldl(__gu_p); \ + break; \ + case 8: \ + val = __uldq(__gu_p); \ + break; \ + default: \ + bad_unaligned_access_length(); \ + }; \ + val; \ +}) + +#define __put_unaligned(val, ptr, size) \ +do { \ + void *__gu_p = ptr; \ + switch (size) { \ + case 1: \ + *(__u8 *)__gu_p = val; \ + break; \ + case 2: \ + __ustw(val, __gu_p); \ + break; \ + case 4: \ + __ustl(val, __gu_p); \ + break; \ + case 8: \ + __ustq(val, __gu_p); \ + break; \ + default: \ + bad_unaligned_access_length(); \ + }; \ +} while(0) #endif /* _ASM_GENERIC_UNALIGNED_H */ diff --git a/include/asm-h8300/signal.h b/include/asm-h8300/signal.h index 3a08544a473e..8eccdc176163 100644 --- a/include/asm-h8300/signal.h +++ b/include/asm-h8300/signal.h @@ -107,29 +107,7 @@ typedef unsigned long sigset_t; #define MINSIGSTKSZ 2048 #define SIGSTKSZ 8192 -#ifdef __KERNEL__ -/* - * These values of sa_flags are used only by the kernel as part of the - * irq handling routines. - * - * SA_INTERRUPT is also used by the irq handling routines. - * SA_SHIRQ is for shared interrupt support on PCI and EISA. - */ -#define SA_PROBE SA_ONESHOT -#define SA_SAMPLE_RANDOM SA_RESTART -#define SA_SHIRQ 0x04000000 -#endif - -#define SIG_BLOCK 0 /* for blocking signals */ -#define SIG_UNBLOCK 1 /* for unblocking signals */ -#define SIG_SETMASK 2 /* for setting the signal mask */ - -/* Type of a signal handler. */ -typedef void (*__sighandler_t)(int); - -#define SIG_DFL ((__sighandler_t)0) /* default signal handling */ -#define SIG_IGN ((__sighandler_t)1) /* ignore signal */ -#define SIG_ERR ((__sighandler_t)-1) /* error return from signal */ +#include <asm-generic/signal.h> #ifdef __KERNEL__ struct old_sigaction { diff --git a/include/asm-i386/apic.h b/include/asm-i386/apic.h index e1de67483f38..a5810cf7b578 100644 --- a/include/asm-i386/apic.h +++ b/include/asm-i386/apic.h @@ -109,7 +109,6 @@ extern int APIC_init_uniprocessor (void); extern void disable_APIC_timer(void); extern void enable_APIC_timer(void); -extern int check_nmi_watchdog (void); extern void enable_NMI_through_LVT0 (void * dummy); extern unsigned int nmi_watchdog; diff --git a/include/asm-i386/bug.h b/include/asm-i386/bug.h index 706eb511c330..8f79de19eb94 100644 --- a/include/asm-i386/bug.h +++ b/include/asm-i386/bug.h @@ -9,6 +9,8 @@ * undefined" opcode for parsing in the trap handler. */ +#ifdef CONFIG_BUG +#define HAVE_ARCH_BUG #ifdef CONFIG_DEBUG_BUGVERBOSE #define BUG() \ __asm__ __volatile__( "ud2\n" \ @@ -18,8 +20,7 @@ #else #define BUG() __asm__ __volatile__("ud2\n") #endif +#endif -#define HAVE_ARCH_BUG #include <asm-generic/bug.h> - #endif diff --git a/include/asm-i386/checksum.h b/include/asm-i386/checksum.h index d76a5f081c91..641342002bcd 100644 --- a/include/asm-i386/checksum.h +++ b/include/asm-i386/checksum.h @@ -33,7 +33,7 @@ asmlinkage unsigned int csum_partial_copy_generic(const unsigned char *src, unsi * passed in an incorrect kernel address to one of these functions. * * If you use these functions directly please don't forget the - * verify_area(). + * access_ok(). */ static __inline__ unsigned int csum_partial_copy_nocheck (const unsigned char *src, unsigned char *dst, diff --git a/include/asm-i386/cpufeature.h b/include/asm-i386/cpufeature.h index e147cabd3bfe..ff1187e80c32 100644 --- a/include/asm-i386/cpufeature.h +++ b/include/asm-i386/cpufeature.h @@ -87,8 +87,8 @@ #define X86_FEATURE_XCRYPT_EN (5*32+ 7) /* on-CPU crypto enabled */ /* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */ -#define X86_FEATURE_LAHF_LM (5*32+ 0) /* LAHF/SAHF in long mode */ -#define X86_FEATURE_CMP_LEGACY (5*32+ 1) /* If yes HyperThreading not valid */ +#define X86_FEATURE_LAHF_LM (6*32+ 0) /* LAHF/SAHF in long mode */ +#define X86_FEATURE_CMP_LEGACY (6*32+ 1) /* If yes HyperThreading not valid */ #define cpu_has(c, bit) test_bit(bit, (c)->x86_capability) #define boot_cpu_has(bit) test_bit(bit, boot_cpu_data.x86_capability) diff --git a/include/asm-i386/e820.h b/include/asm-i386/e820.h index 5c285aee7294..edf65be21a92 100644 --- a/include/asm-i386/e820.h +++ b/include/asm-i386/e820.h @@ -13,7 +13,7 @@ #define __E820_HEADER #define E820MAP 0x2d0 /* our map */ -#define E820MAX 32 /* number of entries in E820MAP */ +#define E820MAX 128 /* number of entries in E820MAP */ #define E820NR 0x1e8 /* # entries in E820MAP */ #define E820_RAM 1 diff --git a/include/asm-i386/floppy.h b/include/asm-i386/floppy.h index f4782284807a..79727afb94c9 100644 --- a/include/asm-i386/floppy.h +++ b/include/asm-i386/floppy.h @@ -257,7 +257,7 @@ static int hard_dma_setup(char *addr, unsigned long size, int mode, int io) return 0; } -struct fd_routine_l { +static struct fd_routine_l { int (*_request_dma)(unsigned int dmanr, const char * device_id); void (*_free_dma)(unsigned int dmanr); int (*_get_dma_residue)(unsigned int dummy); diff --git a/include/asm-i386/hpet.h b/include/asm-i386/hpet.h index 6e20b079f1d3..16ef9f996e3f 100644 --- a/include/asm-i386/hpet.h +++ b/include/asm-i386/hpet.h @@ -92,6 +92,7 @@ extern unsigned long hpet_tick; /* hpet clks count per tick */ extern unsigned long hpet_address; /* hpet memory map physical address */ +extern int hpet_use_timer; extern int hpet_rtc_timer_init(void); extern int hpet_enable(void); diff --git a/include/asm-i386/module.h b/include/asm-i386/module.h index 508865e26308..eb7f2b4234aa 100644 --- a/include/asm-i386/module.h +++ b/include/asm-i386/module.h @@ -52,8 +52,8 @@ struct mod_arch_specific #define MODULE_PROC_FAMILY "CYRIXIII " #elif defined CONFIG_MVIAC3_2 #define MODULE_PROC_FAMILY "VIAC3-2 " -#elif CONFIG_MGEODE -#define MODULE_PROC_FAMILY "GEODE " +#elif CONFIG_MGEODEGX1 +#define MODULE_PROC_FAMILY "GEODEGX1 " #else #error unknown processor family #endif diff --git a/include/asm-i386/pgtable.h b/include/asm-i386/pgtable.h index 5c725425d863..8d60c2b4b003 100644 --- a/include/asm-i386/pgtable.h +++ b/include/asm-i386/pgtable.h @@ -193,9 +193,9 @@ extern unsigned long long __PAGE_KERNEL, __PAGE_KERNEL_EXEC; /* * Define this if things work differently on an i386 and an i486: * it will (on an i486) warn about kernel memory accesses that are - * done without a 'verify_area(VERIFY_WRITE,..)' + * done without a 'access_ok(VERIFY_WRITE,..)' */ -#undef TEST_VERIFY_AREA +#undef TEST_ACCESS_OK /* The boot page tables (all created as a single array) */ extern unsigned long pg0[]; diff --git a/include/asm-i386/setup.h b/include/asm-i386/setup.h index 8814b54c75d4..7a32184d54bf 100644 --- a/include/asm-i386/setup.h +++ b/include/asm-i386/setup.h @@ -16,7 +16,7 @@ #define MAXMEM_PFN PFN_DOWN(MAXMEM) #define MAX_NONPAE_PFN (1 << 20) -#define PARAM_SIZE 2048 +#define PARAM_SIZE 4096 #define COMMAND_LINE_SIZE 256 #define OLD_CL_MAGIC_ADDR 0x90020 diff --git a/include/asm-i386/signal.h b/include/asm-i386/signal.h index 7ef343b6812d..cbb47d34aa31 100644 --- a/include/asm-i386/signal.h +++ b/include/asm-i386/signal.h @@ -110,34 +110,7 @@ typedef unsigned long sigset_t; #define MINSIGSTKSZ 2048 #define SIGSTKSZ 8192 -#ifdef __KERNEL__ - -/* - * These values of sa_flags are used only by the kernel as part of the - * irq handling routines. - * - * SA_INTERRUPT is also used by the irq handling routines. - * SA_SHIRQ is for shared interrupt support on PCI and EISA. - */ -#define SA_PROBE SA_ONESHOT -#define SA_SAMPLE_RANDOM SA_RESTART -#define SA_SHIRQ 0x04000000 -#endif - -#define SIG_BLOCK 0 /* for blocking signals */ -#define SIG_UNBLOCK 1 /* for unblocking signals */ -#define SIG_SETMASK 2 /* for setting the signal mask */ - -/* Type of a signal handler. */ -typedef void __signalfn_t(int); -typedef __signalfn_t __user *__sighandler_t; - -typedef void __restorefn_t(void); -typedef __restorefn_t __user *__sigrestore_t; - -#define SIG_DFL ((__sighandler_t)0) /* default signal handling */ -#define SIG_IGN ((__sighandler_t)1) /* ignore signal */ -#define SIG_ERR ((__sighandler_t)-1) /* error return from signal */ +#include <asm-generic/signal.h> #ifdef __KERNEL__ struct old_sigaction { diff --git a/include/asm-i386/string.h b/include/asm-i386/string.h index 1679983d053f..6a78ac58c194 100644 --- a/include/asm-i386/string.h +++ b/include/asm-i386/string.h @@ -198,47 +198,80 @@ static inline void * __memcpy(void * to, const void * from, size_t n) int d0, d1, d2; __asm__ __volatile__( "rep ; movsl\n\t" - "testb $2,%b4\n\t" - "je 1f\n\t" - "movsw\n" - "1:\ttestb $1,%b4\n\t" - "je 2f\n\t" - "movsb\n" - "2:" + "movl %4,%%ecx\n\t" + "andl $3,%%ecx\n\t" +#if 1 /* want to pay 2 byte penalty for a chance to skip microcoded rep? */ + "jz 1f\n\t" +#endif + "rep ; movsb\n\t" + "1:" : "=&c" (d0), "=&D" (d1), "=&S" (d2) - :"0" (n/4), "q" (n),"1" ((long) to),"2" ((long) from) + : "0" (n/4), "g" (n), "1" ((long) to), "2" ((long) from) : "memory"); return (to); } /* - * This looks horribly ugly, but the compiler can optimize it totally, + * This looks ugly, but the compiler can optimize it totally, * as the count is constant. */ static inline void * __constant_memcpy(void * to, const void * from, size_t n) { - if (n <= 128) - return __builtin_memcpy(to, from, n); - -#define COMMON(x) \ -__asm__ __volatile__( \ - "rep ; movsl" \ - x \ - : "=&c" (d0), "=&D" (d1), "=&S" (d2) \ - : "0" (n/4),"1" ((long) to),"2" ((long) from) \ - : "memory"); -{ - int d0, d1, d2; + long esi, edi; + if (!n) return to; +#if 1 /* want to do small copies with non-string ops? */ + switch (n) { + case 1: *(char*)to = *(char*)from; return to; + case 2: *(short*)to = *(short*)from; return to; + case 4: *(int*)to = *(int*)from; return to; +#if 1 /* including those doable with two moves? */ + case 3: *(short*)to = *(short*)from; + *((char*)to+2) = *((char*)from+2); return to; + case 5: *(int*)to = *(int*)from; + *((char*)to+4) = *((char*)from+4); return to; + case 6: *(int*)to = *(int*)from; + *((short*)to+2) = *((short*)from+2); return to; + case 8: *(int*)to = *(int*)from; + *((int*)to+1) = *((int*)from+1); return to; +#endif + } +#endif + esi = (long) from; + edi = (long) to; + if (n >= 5*4) { + /* large block: use rep prefix */ + int ecx; + __asm__ __volatile__( + "rep ; movsl" + : "=&c" (ecx), "=&D" (edi), "=&S" (esi) + : "0" (n/4), "1" (edi),"2" (esi) + : "memory" + ); + } else { + /* small block: don't clobber ecx + smaller code */ + if (n >= 4*4) __asm__ __volatile__("movsl" + :"=&D"(edi),"=&S"(esi):"0"(edi),"1"(esi):"memory"); + if (n >= 3*4) __asm__ __volatile__("movsl" + :"=&D"(edi),"=&S"(esi):"0"(edi),"1"(esi):"memory"); + if (n >= 2*4) __asm__ __volatile__("movsl" + :"=&D"(edi),"=&S"(esi):"0"(edi),"1"(esi):"memory"); + if (n >= 1*4) __asm__ __volatile__("movsl" + :"=&D"(edi),"=&S"(esi):"0"(edi),"1"(esi):"memory"); + } switch (n % 4) { - case 0: COMMON(""); return to; - case 1: COMMON("\n\tmovsb"); return to; - case 2: COMMON("\n\tmovsw"); return to; - default: COMMON("\n\tmovsw\n\tmovsb"); return to; + /* tail */ + case 0: return to; + case 1: __asm__ __volatile__("movsb" + :"=&D"(edi),"=&S"(esi):"0"(edi),"1"(esi):"memory"); + return to; + case 2: __asm__ __volatile__("movsw" + :"=&D"(edi),"=&S"(esi):"0"(edi),"1"(esi):"memory"); + return to; + default: __asm__ __volatile__("movsw\n\tmovsb" + :"=&D"(edi),"=&S"(esi):"0"(edi),"1"(esi):"memory"); + return to; } } - -#undef COMMON -} #define __HAVE_ARCH_MEMCPY diff --git a/include/asm-i386/system.h b/include/asm-i386/system.h index 6f74d4c44a0e..3db717a244f0 100644 --- a/include/asm-i386/system.h +++ b/include/asm-i386/system.h @@ -81,7 +81,7 @@ static inline unsigned long _get_base(char * addr) #define loadsegment(seg,value) \ asm volatile("\n" \ "1:\t" \ - "movl %0,%%" #seg "\n" \ + "mov %0,%%" #seg "\n" \ "2:\n" \ ".section .fixup,\"ax\"\n" \ "3:\t" \ @@ -93,13 +93,13 @@ static inline unsigned long _get_base(char * addr) ".align 4\n\t" \ ".long 1b,3b\n" \ ".previous" \ - : :"m" (*(unsigned int *)&(value))) + : :"m" (value)) /* * Save a segment register away */ #define savesegment(seg, value) \ - asm volatile("movl %%" #seg ",%0":"=m" (*(int *)&(value))) + asm volatile("mov %%" #seg ",%0":"=m" (value)) /* * Clear and set 'TS' bit respectively diff --git a/include/asm-ia64/bitops.h b/include/asm-ia64/bitops.h index 925d54cee475..7232528e2d0c 100644 --- a/include/asm-ia64/bitops.h +++ b/include/asm-ia64/bitops.h @@ -314,8 +314,8 @@ __ffs (unsigned long x) #ifdef __KERNEL__ /* - * find_last_zero_bit - find the last zero bit in a 64 bit quantity - * @x: The value to search + * Return bit number of last (most-significant) bit set. Undefined + * for x==0. Bits are numbered from 0..63 (e.g., ia64_fls(9) == 3). */ static inline unsigned long ia64_fls (unsigned long x) @@ -327,10 +327,23 @@ ia64_fls (unsigned long x) return exp - 0xffff; } +/* + * Find the last (most significant) bit set. Returns 0 for x==0 and + * bits are numbered from 1..32 (e.g., fls(9) == 4). + */ static inline int -fls (int x) +fls (int t) { - return ia64_fls((unsigned int) x); + unsigned long x = t & 0xffffffffu; + + if (!x) + return 0; + x |= x >> 1; + x |= x >> 2; + x |= x >> 4; + x |= x >> 8; + x |= x >> 16; + return ia64_popcnt(x); } /* diff --git a/include/asm-ia64/bug.h b/include/asm-ia64/bug.h index 2c0cd51e8856..3aa0a0a5474b 100644 --- a/include/asm-ia64/bug.h +++ b/include/asm-ia64/bug.h @@ -1,6 +1,7 @@ #ifndef _ASM_IA64_BUG_H #define _ASM_IA64_BUG_H +#ifdef CONFIG_BUG #if (__GNUC__ > 3) || (__GNUC__ == 3 && __GNUC_MINOR__ >= 1) # define ia64_abort() __builtin_trap() #else @@ -8,8 +9,10 @@ #endif #define BUG() do { printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__); ia64_abort(); } while (0) -/* should this BUG should be made generic? */ +/* should this BUG be made generic? */ #define HAVE_ARCH_BUG +#endif + #include <asm-generic/bug.h> #endif diff --git a/include/asm-ia64/gcc_intrin.h b/include/asm-ia64/gcc_intrin.h index 7c357dfbae50..4fb4e439b05c 100644 --- a/include/asm-ia64/gcc_intrin.h +++ b/include/asm-ia64/gcc_intrin.h @@ -133,13 +133,17 @@ register unsigned long ia64_r13 asm ("r13") __attribute_used__; ia64_intri_res; \ }) -#define ia64_popcnt(x) \ -({ \ +#if __GNUC__ >= 4 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 4) +# define ia64_popcnt(x) __builtin_popcountl(x) +#else +# define ia64_popcnt(x) \ + ({ \ __u64 ia64_intri_res; \ asm ("popcnt %0=%1" : "=r" (ia64_intri_res) : "r" (x)); \ \ ia64_intri_res; \ -}) + }) +#endif #define ia64_getf_exp(x) \ ({ \ diff --git a/include/asm-ia64/hw_irq.h b/include/asm-ia64/hw_irq.h index 041ab8c51a64..cd4e06b74ab6 100644 --- a/include/asm-ia64/hw_irq.h +++ b/include/asm-ia64/hw_irq.h @@ -81,6 +81,7 @@ extern __u8 isa_irq_to_vector_map[16]; extern struct hw_interrupt_type irq_type_ia64_lsapic; /* CPU-internal interrupt controller */ +extern int assign_irq_vector_nopanic (int irq); /* allocate a free vector without panic */ extern int assign_irq_vector (int irq); /* allocate a free vector */ extern void free_irq_vector (int vector); extern void ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect); diff --git a/include/asm-ia64/pal.h b/include/asm-ia64/pal.h index 5dd477ffb88e..2303a10ee595 100644 --- a/include/asm-ia64/pal.h +++ b/include/asm-ia64/pal.h @@ -67,6 +67,7 @@ #define PAL_REGISTER_INFO 39 /* return AR and CR register information*/ #define PAL_SHUTDOWN 40 /* enter processor shutdown state */ #define PAL_PREFETCH_VISIBILITY 41 /* Make Processor Prefetches Visible */ +#define PAL_LOGICAL_TO_PHYSICAL 42 /* returns information on logical to physical processor mapping */ #define PAL_COPY_PAL 256 /* relocate PAL procedures and PAL PMI */ #define PAL_HALT_INFO 257 /* return the low power capabilities of processor */ @@ -1559,6 +1560,73 @@ ia64_pal_prefetch_visibility (s64 trans_type) return iprv.status; } +/* data structure for getting information on logical to physical mappings */ +typedef union pal_log_overview_u { + struct { + u64 num_log :16, /* Total number of logical + * processors on this die + */ + tpc :8, /* Threads per core */ + reserved3 :8, /* Reserved */ + cpp :8, /* Cores per processor */ + reserved2 :8, /* Reserved */ + ppid :8, /* Physical processor ID */ + reserved1 :8; /* Reserved */ + } overview_bits; + u64 overview_data; +} pal_log_overview_t; + +typedef union pal_proc_n_log_info1_u{ + struct { + u64 tid :16, /* Thread id */ + reserved2 :16, /* Reserved */ + cid :16, /* Core id */ + reserved1 :16; /* Reserved */ + } ppli1_bits; + u64 ppli1_data; +} pal_proc_n_log_info1_t; + +typedef union pal_proc_n_log_info2_u { + struct { + u64 la :16, /* Logical address */ + reserved :48; /* Reserved */ + } ppli2_bits; + u64 ppli2_data; +} pal_proc_n_log_info2_t; + +typedef struct pal_logical_to_physical_s +{ + pal_log_overview_t overview; + pal_proc_n_log_info1_t ppli1; + pal_proc_n_log_info2_t ppli2; +} pal_logical_to_physical_t; + +#define overview_num_log overview.overview_bits.num_log +#define overview_tpc overview.overview_bits.tpc +#define overview_cpp overview.overview_bits.cpp +#define overview_ppid overview.overview_bits.ppid +#define log1_tid ppli1.ppli1_bits.tid +#define log1_cid ppli1.ppli1_bits.cid +#define log2_la ppli2.ppli2_bits.la + +/* Get information on logical to physical processor mappings. */ +static inline s64 +ia64_pal_logical_to_phys(u64 proc_number, pal_logical_to_physical_t *mapping) +{ + struct ia64_pal_retval iprv; + + PAL_CALL(iprv, PAL_LOGICAL_TO_PHYSICAL, proc_number, 0, 0); + + if (iprv.status == PAL_STATUS_SUCCESS) + { + if (proc_number == 0) + mapping->overview.overview_data = iprv.v0; + mapping->ppli1.ppli1_data = iprv.v1; + mapping->ppli2.ppli2_data = iprv.v2; + } + + return iprv.status; +} #endif /* __ASSEMBLY__ */ #endif /* _ASM_IA64_PAL_H */ diff --git a/include/asm-ia64/perfmon.h b/include/asm-ia64/perfmon.h index 136c60e6bfcc..ed5416c5b1ac 100644 --- a/include/asm-ia64/perfmon.h +++ b/include/asm-ia64/perfmon.h @@ -254,6 +254,18 @@ extern int pfm_mod_write_dbrs(struct task_struct *task, void *req, unsigned int #define PFM_CPUINFO_DCR_PP 0x2 /* if set the system wide session has started */ #define PFM_CPUINFO_EXCL_IDLE 0x4 /* the system wide session excludes the idle task */ +/* + * sysctl control structure. visible to sampling formats + */ +typedef struct { + int debug; /* turn on/off debugging via syslog */ + int debug_ovfl; /* turn on/off debug printk in overflow handler */ + int fastctxsw; /* turn on/off fast (unsecure) ctxsw */ + int expert_mode; /* turn on/off value checking */ +} pfm_sysctl_t; +extern pfm_sysctl_t pfm_sysctl; + + #endif /* __KERNEL__ */ #endif /* _ASM_IA64_PERFMON_H */ diff --git a/include/asm-ia64/pgalloc.h b/include/asm-ia64/pgalloc.h index 0f05dc8bd460..a5f214554afd 100644 --- a/include/asm-ia64/pgalloc.h +++ b/include/asm-ia64/pgalloc.h @@ -22,146 +22,124 @@ #include <asm/mmu_context.h> -/* - * Very stupidly, we used to get new pgd's and pmd's, init their contents - * to point to the NULL versions of the next level page table, later on - * completely re-init them the same way, then free them up. This wasted - * a lot of work and caused unnecessary memory traffic. How broken... - * We fix this by caching them. - */ -#define pgd_quicklist (local_cpu_data->pgd_quick) -#define pmd_quicklist (local_cpu_data->pmd_quick) -#define pgtable_cache_size (local_cpu_data->pgtable_cache_sz) +DECLARE_PER_CPU(unsigned long *, __pgtable_quicklist); +#define pgtable_quicklist __ia64_per_cpu_var(__pgtable_quicklist) +DECLARE_PER_CPU(long, __pgtable_quicklist_size); +#define pgtable_quicklist_size __ia64_per_cpu_var(__pgtable_quicklist_size) -static inline pgd_t* -pgd_alloc_one_fast (struct mm_struct *mm) +static inline long pgtable_quicklist_total_size(void) +{ + long ql_size = 0; + int cpuid; + + for_each_online_cpu(cpuid) { + ql_size += per_cpu(__pgtable_quicklist_size, cpuid); + } + return ql_size; +} + +static inline void *pgtable_quicklist_alloc(void) { unsigned long *ret = NULL; preempt_disable(); - ret = pgd_quicklist; + ret = pgtable_quicklist; if (likely(ret != NULL)) { - pgd_quicklist = (unsigned long *)(*ret); + pgtable_quicklist = (unsigned long *)(*ret); ret[0] = 0; - --pgtable_cache_size; - } else - ret = NULL; - - preempt_enable(); + --pgtable_quicklist_size; + preempt_enable(); + } else { + preempt_enable(); + ret = (unsigned long *)__get_free_page(GFP_KERNEL | __GFP_ZERO); + } - return (pgd_t *) ret; + return ret; } -static inline pgd_t* -pgd_alloc (struct mm_struct *mm) +static inline void pgtable_quicklist_free(void *pgtable_entry) { - /* the VM system never calls pgd_alloc_one_fast(), so we do it here. */ - pgd_t *pgd = pgd_alloc_one_fast(mm); +#ifdef CONFIG_NUMA + unsigned long nid = page_to_nid(virt_to_page(pgtable_entry)); - if (unlikely(pgd == NULL)) { - pgd = (pgd_t *)__get_free_page(GFP_KERNEL|__GFP_ZERO); + if (unlikely(nid != numa_node_id())) { + free_page((unsigned long)pgtable_entry); + return; } - return pgd; -} +#endif -static inline void -pgd_free (pgd_t *pgd) -{ preempt_disable(); - *(unsigned long *)pgd = (unsigned long) pgd_quicklist; - pgd_quicklist = (unsigned long *) pgd; - ++pgtable_cache_size; + *(unsigned long *)pgtable_entry = (unsigned long)pgtable_quicklist; + pgtable_quicklist = (unsigned long *)pgtable_entry; + ++pgtable_quicklist_size; preempt_enable(); } -static inline void -pud_populate (struct mm_struct *mm, pud_t *pud_entry, pmd_t *pmd) +static inline pgd_t *pgd_alloc(struct mm_struct *mm) { - pud_val(*pud_entry) = __pa(pmd); + return pgtable_quicklist_alloc(); } -static inline pmd_t* -pmd_alloc_one_fast (struct mm_struct *mm, unsigned long addr) +static inline void pgd_free(pgd_t * pgd) { - unsigned long *ret = NULL; - - preempt_disable(); - - ret = (unsigned long *)pmd_quicklist; - if (likely(ret != NULL)) { - pmd_quicklist = (unsigned long *)(*ret); - ret[0] = 0; - --pgtable_cache_size; - } - - preempt_enable(); - - return (pmd_t *)ret; + pgtable_quicklist_free(pgd); } -static inline pmd_t* -pmd_alloc_one (struct mm_struct *mm, unsigned long addr) +static inline void +pud_populate(struct mm_struct *mm, pud_t * pud_entry, pmd_t * pmd) { - pmd_t *pmd = (pmd_t *)__get_free_page(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO); + pud_val(*pud_entry) = __pa(pmd); +} - return pmd; +static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr) +{ + return pgtable_quicklist_alloc(); } -static inline void -pmd_free (pmd_t *pmd) +static inline void pmd_free(pmd_t * pmd) { - preempt_disable(); - *(unsigned long *)pmd = (unsigned long) pmd_quicklist; - pmd_quicklist = (unsigned long *) pmd; - ++pgtable_cache_size; - preempt_enable(); + pgtable_quicklist_free(pmd); } #define __pmd_free_tlb(tlb, pmd) pmd_free(pmd) static inline void -pmd_populate (struct mm_struct *mm, pmd_t *pmd_entry, struct page *pte) +pmd_populate(struct mm_struct *mm, pmd_t * pmd_entry, struct page *pte) { pmd_val(*pmd_entry) = page_to_phys(pte); } static inline void -pmd_populate_kernel (struct mm_struct *mm, pmd_t *pmd_entry, pte_t *pte) +pmd_populate_kernel(struct mm_struct *mm, pmd_t * pmd_entry, pte_t * pte) { pmd_val(*pmd_entry) = __pa(pte); } -static inline struct page * -pte_alloc_one (struct mm_struct *mm, unsigned long addr) +static inline struct page *pte_alloc_one(struct mm_struct *mm, + unsigned long addr) { - struct page *pte = alloc_pages(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO, 0); - - return pte; + return virt_to_page(pgtable_quicklist_alloc()); } -static inline pte_t * -pte_alloc_one_kernel (struct mm_struct *mm, unsigned long addr) +static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, + unsigned long addr) { - pte_t *pte = (pte_t *)__get_free_page(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO); - - return pte; + return pgtable_quicklist_alloc(); } -static inline void -pte_free (struct page *pte) +static inline void pte_free(struct page *pte) { - __free_page(pte); + pgtable_quicklist_free(page_address(pte)); } -static inline void -pte_free_kernel (pte_t *pte) +static inline void pte_free_kernel(pte_t * pte) { - free_page((unsigned long) pte); + pgtable_quicklist_free(pte); } -#define __pte_free_tlb(tlb, pte) tlb_remove_page((tlb), (pte)) +#define __pte_free_tlb(tlb, pte) pte_free(pte) -extern void check_pgt_cache (void); +extern void check_pgt_cache(void); -#endif /* _ASM_IA64_PGALLOC_H */ +#endif /* _ASM_IA64_PGALLOC_H */ diff --git a/include/asm-ia64/processor.h b/include/asm-ia64/processor.h index 2807f8d766d4..9e1ba8b7fb68 100644 --- a/include/asm-ia64/processor.h +++ b/include/asm-ia64/processor.h @@ -137,9 +137,6 @@ struct cpuinfo_ia64 { __u64 nsec_per_cyc; /* (1000000000<<IA64_NSEC_PER_CYC_SHIFT)/itc_freq */ __u64 unimpl_va_mask; /* mask of unimplemented virtual address bits (from PAL) */ __u64 unimpl_pa_mask; /* mask of unimplemented physical address bits (from PAL) */ - __u64 *pgd_quick; - __u64 *pmd_quick; - __u64 pgtable_cache_sz; __u64 itc_freq; /* frequency of ITC counter */ __u64 proc_freq; /* frequency of processor */ __u64 cyc_per_usec; /* itc_freq/1000000 */ @@ -151,6 +148,13 @@ struct cpuinfo_ia64 { #ifdef CONFIG_SMP __u64 loops_per_jiffy; int cpu; + __u32 socket_id; /* physical processor socket id */ + __u16 core_id; /* core id */ + __u16 thread_id; /* thread id */ + __u16 num_log; /* Total number of logical processors on + * this socket that were successfully booted */ + __u8 cores_per_socket; /* Cores per processor socket */ + __u8 threads_per_core; /* Threads per core */ #endif /* CPUID-derived information: */ diff --git a/include/asm-ia64/sal.h b/include/asm-ia64/sal.h index ea1ed377de4c..29df88bdd2bc 100644 --- a/include/asm-ia64/sal.h +++ b/include/asm-ia64/sal.h @@ -91,6 +91,7 @@ extern spinlock_t sal_lock; #define SAL_PCI_CONFIG_READ 0x01000010 #define SAL_PCI_CONFIG_WRITE 0x01000011 #define SAL_FREQ_BASE 0x01000012 +#define SAL_PHYSICAL_ID_INFO 0x01000013 #define SAL_UPDATE_PAL 0x01000020 @@ -815,6 +816,17 @@ ia64_sal_update_pal (u64 param_buf, u64 scratch_buf, u64 scratch_buf_size, return isrv.status; } +/* Get physical processor die mapping in the platform. */ +static inline s64 +ia64_sal_physical_id_info(u16 *splid) +{ + struct ia64_sal_retval isrv; + SAL_CALL(isrv, SAL_PHYSICAL_ID_INFO, 0, 0, 0, 0, 0, 0, 0); + if (splid) + *splid = isrv.v0; + return isrv.status; +} + extern unsigned long sal_platform_features; extern int (*salinfo_platform_oemdata)(const u8 *, u8 **, u64 *); @@ -832,6 +844,44 @@ extern int ia64_sal_oemcall_nolock(struct ia64_sal_retval *, u64, u64, u64, u64, u64, u64, u64, u64); extern int ia64_sal_oemcall_reentrant(struct ia64_sal_retval *, u64, u64, u64, u64, u64, u64, u64, u64); +#ifdef CONFIG_HOTPLUG_CPU +/* + * System Abstraction Layer Specification + * Section 3.2.5.1: OS_BOOT_RENDEZ to SAL return State. + * Note: region regs are stored first in head.S _start. Hence they must + * stay up front. + */ +struct sal_to_os_boot { + u64 rr[8]; /* Region Registers */ + u64 br[6]; /* br0: return addr into SAL boot rendez routine */ + u64 gr1; /* SAL:GP */ + u64 gr12; /* SAL:SP */ + u64 gr13; /* SAL: Task Pointer */ + u64 fpsr; + u64 pfs; + u64 rnat; + u64 unat; + u64 bspstore; + u64 dcr; /* Default Control Register */ + u64 iva; + u64 pta; + u64 itv; + u64 pmv; + u64 cmcv; + u64 lrr[2]; + u64 gr[4]; + u64 pr; /* Predicate registers */ + u64 lc; /* Loop Count */ + struct ia64_fpreg fp[20]; +}; + +/* + * Global array allocated for NR_CPUS at boot time + */ +extern struct sal_to_os_boot sal_boot_rendez_state[NR_CPUS]; + +extern void ia64_jump_to_sal(struct sal_to_os_boot *); +#endif extern void ia64_sal_handler_init(void *entry_point, void *gpval); diff --git a/include/asm-ia64/siginfo.h b/include/asm-ia64/siginfo.h index d55f139cbcdc..9294e4b0c8bc 100644 --- a/include/asm-ia64/siginfo.h +++ b/include/asm-ia64/siginfo.h @@ -8,9 +8,7 @@ * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co */ -#define SI_PAD_SIZE ((SI_MAX_SIZE/sizeof(int)) - 4) - -#define SIGEV_PAD_SIZE ((SIGEV_MAX_SIZE/sizeof(int)) - 4) +#define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int)) #define HAVE_ARCH_SIGINFO_T #define HAVE_ARCH_COPY_SIGINFO diff --git a/include/asm-ia64/signal.h b/include/asm-ia64/signal.h index 660a759744dd..608168d713d3 100644 --- a/include/asm-ia64/signal.h +++ b/include/asm-ia64/signal.h @@ -114,27 +114,11 @@ #define _NSIG_BPW 64 #define _NSIG_WORDS (_NSIG / _NSIG_BPW) -/* - * These values of sa_flags are used only by the kernel as part of the - * irq handling routines. - * - * SA_INTERRUPT is also used by the irq handling routines. - * SA_SHIRQ is for shared interrupt support on PCI and EISA. - */ -#define SA_PROBE SA_ONESHOT -#define SA_SAMPLE_RANDOM SA_RESTART -#define SA_SHIRQ 0x04000000 #define SA_PERCPU_IRQ 0x02000000 #endif /* __KERNEL__ */ -#define SIG_BLOCK 0 /* for blocking signals */ -#define SIG_UNBLOCK 1 /* for unblocking signals */ -#define SIG_SETMASK 2 /* for setting the signal mask */ - -#define SIG_DFL ((__sighandler_t)0) /* default signal handling */ -#define SIG_IGN ((__sighandler_t)1) /* ignore signal */ -#define SIG_ERR ((__sighandler_t)-1) /* error return from signal */ +#include <asm-generic/signal.h> # ifndef __ASSEMBLY__ @@ -143,9 +127,6 @@ /* Avoid too many header ordering problems. */ struct siginfo; -/* Type of a signal handler. */ -typedef void __user (*__sighandler_t)(int); - typedef struct sigaltstack { void __user *ss_sp; int ss_flags; diff --git a/include/asm-ia64/smp.h b/include/asm-ia64/smp.h index c4a227acfeb0..3ba1a061e4ae 100644 --- a/include/asm-ia64/smp.h +++ b/include/asm-ia64/smp.h @@ -56,6 +56,10 @@ extern struct smp_boot_data { extern char no_int_routing __devinitdata; extern cpumask_t cpu_online_map; +extern cpumask_t cpu_core_map[NR_CPUS]; +extern cpumask_t cpu_sibling_map[NR_CPUS]; +extern int smp_num_siblings; +extern int smp_num_cpucores; extern void __iomem *ipi_base_addr; extern unsigned char smp_int_redirect; @@ -124,6 +128,7 @@ extern int smp_call_function_single (int cpuid, void (*func) (void *info), void extern void smp_send_reschedule (int cpu); extern void lock_ipi_calllock(void); extern void unlock_ipi_calllock(void); +extern void identify_siblings (struct cpuinfo_ia64 *); #else diff --git a/include/asm-ia64/sn/addrs.h b/include/asm-ia64/sn/addrs.h index c916bd22767a..1bfdfb4d7b01 100644 --- a/include/asm-ia64/sn/addrs.h +++ b/include/asm-ia64/sn/addrs.h @@ -136,6 +136,7 @@ */ #define CAC_BASE (CACHED | AS_CAC_SPACE) #define AMO_BASE (UNCACHED | AS_AMO_SPACE) +#define AMO_PHYS_BASE (UNCACHED_PHYS | AS_AMO_SPACE) #define GET_BASE (CACHED | AS_GET_SPACE) /* @@ -154,12 +155,20 @@ * the chiplet id is zero. If we implement TIO-TIO dma, we might need * to insert a chiplet id into this macro. However, it is our belief * right now that this chiplet id will be ICE, which is also zero. + * Nasid starts on bit 40. */ -#define PHYS_TO_TIODMA(x) ( (((u64)(x) & NASID_MASK) << 2) | NODE_OFFSET(x)) +#define PHYS_TO_TIODMA(x) ( (((u64)(NASID_GET(x))) << 40) | NODE_OFFSET(x)) #define PHYS_TO_DMA(x) ( (((u64)(x) & NASID_MASK) >> 2) | NODE_OFFSET(x)) /* + * Macros to test for address type. + */ +#define IS_AMO_ADDRESS(x) (((u64)(x) & (REGION_BITS | AS_MASK)) == AMO_BASE) +#define IS_AMO_PHYS_ADDRESS(x) (((u64)(x) & (REGION_BITS | AS_MASK)) == AMO_PHYS_BASE) + + +/* * The following definitions pertain to the IO special address * space. They define the location of the big and little windows * of any given node. @@ -168,7 +177,10 @@ #define TIO_BWIN_SIZE_BITS 30 /* big window size: 1G */ #define NODE_SWIN_BASE(n, w) ((w == 0) ? NODE_BWIN_BASE((n), SWIN0_BIGWIN) \ : RAW_NODE_SWIN_BASE(n, w)) +#define TIO_SWIN_BASE(n, w) (TIO_IO_BASE(n) + \ + ((u64) (w) << TIO_SWIN_SIZE_BITS)) #define NODE_IO_BASE(n) (GLOBAL_MMR_SPACE | NASID_SPACE(n)) +#define TIO_IO_BASE(n) (UNCACHED | NASID_SPACE(n)) #define BWIN_SIZE (1UL << BWIN_SIZE_BITS) #define NODE_BWIN_BASE0(n) (NODE_IO_BASE(n) + BWIN_SIZE) #define NODE_BWIN_BASE(n, w) (NODE_BWIN_BASE0(n) + ((u64) (w) << BWIN_SIZE_BITS)) diff --git a/include/asm-ia64/sn/arch.h b/include/asm-ia64/sn/arch.h index 7c349f07916a..635fdce854a8 100644 --- a/include/asm-ia64/sn/arch.h +++ b/include/asm-ia64/sn/arch.h @@ -5,7 +5,7 @@ * * SGI specific setup. * - * Copyright (C) 1995-1997,1999,2001-2004 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1995-1997,1999,2001-2005 Silicon Graphics, Inc. All rights reserved. * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org) */ #ifndef _ASM_IA64_SN_ARCH_H @@ -47,6 +47,21 @@ DECLARE_PER_CPU(struct sn_hub_info_s, __sn_hub_info); #define MAX_COMPACT_NODES 2048 #define CPUS_PER_NODE 4 + +/* + * Compact node ID to nasid mappings kept in the per-cpu data areas of each + * cpu. + */ +DECLARE_PER_CPU(short, __sn_cnodeid_to_nasid[MAX_NUMNODES]); +#define sn_cnodeid_to_nasid (&__get_cpu_var(__sn_cnodeid_to_nasid[0])) + + + +extern u8 sn_partition_id; +extern u8 sn_system_size; +extern u8 sn_sharing_domain_size; +extern u8 sn_region_size; + extern void sn_flush_all_caches(long addr, long bytes); #endif /* _ASM_IA64_SN_ARCH_H */ diff --git a/include/asm-ia64/sn/bte.h b/include/asm-ia64/sn/bte.h index 0ec27f99c181..f50da3d91d07 100644 --- a/include/asm-ia64/sn/bte.h +++ b/include/asm-ia64/sn/bte.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (c) 2000-2004 Silicon Graphics, Inc. All Rights Reserved. + * Copyright (c) 2000-2005 Silicon Graphics, Inc. All Rights Reserved. */ @@ -13,8 +13,12 @@ #include <linux/timer.h> #include <linux/spinlock.h> #include <linux/cache.h> +#include <asm/sn/pda.h> #include <asm/sn/types.h> +#include <asm/sn/shub_mmr.h> +#define IBCT_NOTIFY (0x1UL << 4) +#define IBCT_ZFIL_MODE (0x1UL << 0) /* #define BTE_DEBUG */ /* #define BTE_DEBUG_VERBOSE */ @@ -39,8 +43,36 @@ /* Define hardware */ -#define BTES_PER_NODE 2 +#define BTES_PER_NODE (is_shub2() ? 4 : 2) +#define MAX_BTES_PER_NODE 4 +#define BTE2OFF_CTRL (0) +#define BTE2OFF_SRC (SH2_BT_ENG_SRC_ADDR_0 - SH2_BT_ENG_CSR_0) +#define BTE2OFF_DEST (SH2_BT_ENG_DEST_ADDR_0 - SH2_BT_ENG_CSR_0) +#define BTE2OFF_NOTIFY (SH2_BT_ENG_NOTIF_ADDR_0 - SH2_BT_ENG_CSR_0) + +#define BTE_BASE_ADDR(interface) \ + (is_shub2() ? (interface == 0) ? SH2_BT_ENG_CSR_0 : \ + (interface == 1) ? SH2_BT_ENG_CSR_1 : \ + (interface == 2) ? SH2_BT_ENG_CSR_2 : \ + SH2_BT_ENG_CSR_3 \ + : (interface == 0) ? IIO_IBLS0 : IIO_IBLS1) + +#define BTE_SOURCE_ADDR(base) \ + (is_shub2() ? base + (BTE2OFF_SRC/8) \ + : base + (BTEOFF_SRC/8)) + +#define BTE_DEST_ADDR(base) \ + (is_shub2() ? base + (BTE2OFF_DEST/8) \ + : base + (BTEOFF_DEST/8)) + +#define BTE_CTRL_ADDR(base) \ + (is_shub2() ? base + (BTE2OFF_CTRL/8) \ + : base + (BTEOFF_CTRL/8)) + +#define BTE_NOTIF_ADDR(base) \ + (is_shub2() ? base + (BTE2OFF_NOTIFY/8) \ + : base + (BTEOFF_NOTIFY/8)) /* Define hardware modes */ #define BTE_NOTIFY (IBCT_NOTIFY) @@ -68,14 +100,18 @@ #define BTE_LNSTAT_STORE(_bte, _x) \ HUB_S(_bte->bte_base_addr, (_x)) #define BTE_SRC_STORE(_bte, _x) \ - HUB_S(_bte->bte_base_addr + (BTEOFF_SRC/8), (_x)) + HUB_S(_bte->bte_source_addr, (_x)) #define BTE_DEST_STORE(_bte, _x) \ - HUB_S(_bte->bte_base_addr + (BTEOFF_DEST/8), (_x)) + HUB_S(_bte->bte_destination_addr, (_x)) #define BTE_CTRL_STORE(_bte, _x) \ - HUB_S(_bte->bte_base_addr + (BTEOFF_CTRL/8), (_x)) + HUB_S(_bte->bte_control_addr, (_x)) #define BTE_NOTIF_STORE(_bte, _x) \ - HUB_S(_bte->bte_base_addr + (BTEOFF_NOTIFY/8), (_x)) + HUB_S(_bte->bte_notify_addr, (_x)) +#define BTE_START_TRANSFER(_bte, _len, _mode) \ + is_shub2() ? BTE_CTRL_STORE(_bte, IBLS_BUSY | (_mode << 24) | _len) \ + : BTE_LNSTAT_STORE(_bte, _len); \ + BTE_CTRL_STORE(_bte, _mode) /* Possible results from bte_copy and bte_unaligned_copy */ /* The following error codes map into the BTE hardware codes @@ -110,6 +146,10 @@ typedef enum { struct bteinfo_s { volatile u64 notify ____cacheline_aligned; u64 *bte_base_addr ____cacheline_aligned; + u64 *bte_source_addr; + u64 *bte_destination_addr; + u64 *bte_control_addr; + u64 *bte_notify_addr; spinlock_t spinlock; cnodeid_t bte_cnode; /* cnode */ int bte_error_count; /* Number of errors encountered */ @@ -117,6 +157,7 @@ struct bteinfo_s { int cleanup_active; /* Interface is locked for cleanup */ volatile bte_result_t bh_error; /* error while processing */ volatile u64 *most_rcnt_na; + struct bteinfo_s *btes_to_try[MAX_BTES_PER_NODE]; }; diff --git a/include/asm-ia64/sn/fetchop.h b/include/asm-ia64/sn/fetchop.h deleted file mode 100644 index 5f4ad8f4b5d2..000000000000 --- a/include/asm-ia64/sn/fetchop.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (c) 2001-2004 Silicon Graphics, Inc. All rights reserved. - */ - -#ifndef _ASM_IA64_SN_FETCHOP_H -#define _ASM_IA64_SN_FETCHOP_H - -#include <linux/config.h> - -#define FETCHOP_BASENAME "sgi_fetchop" -#define FETCHOP_FULLNAME "/dev/sgi_fetchop" - - - -#define FETCHOP_VAR_SIZE 64 /* 64 byte per fetchop variable */ - -#define FETCHOP_LOAD 0 -#define FETCHOP_INCREMENT 8 -#define FETCHOP_DECREMENT 16 -#define FETCHOP_CLEAR 24 - -#define FETCHOP_STORE 0 -#define FETCHOP_AND 24 -#define FETCHOP_OR 32 - -#define FETCHOP_CLEAR_CACHE 56 - -#define FETCHOP_LOAD_OP(addr, op) ( \ - *(volatile long *)((char*) (addr) + (op))) - -#define FETCHOP_STORE_OP(addr, op, x) ( \ - *(volatile long *)((char*) (addr) + (op)) = (long) (x)) - -#ifdef __KERNEL__ - -/* - * Convert a region 6 (kaddr) address to the address of the fetchop variable - */ -#define FETCHOP_KADDR_TO_MSPEC_ADDR(kaddr) TO_MSPEC(kaddr) - - -/* - * Each Atomic Memory Operation (AMO formerly known as fetchop) - * variable is 64 bytes long. The first 8 bytes are used. The - * remaining 56 bytes are unaddressable due to the operation taking - * that portion of the address. - * - * NOTE: The AMO_t _MUST_ be placed in either the first or second half - * of the cache line. The cache line _MUST NOT_ be used for anything - * other than additional AMO_t entries. This is because there are two - * addresses which reference the same physical cache line. One will - * be a cached entry with the memory type bits all set. This address - * may be loaded into processor cache. The AMO_t will be referenced - * uncached via the memory special memory type. If any portion of the - * cached cache-line is modified, when that line is flushed, it will - * overwrite the uncached value in physical memory and lead to - * inconsistency. - */ -typedef struct { - u64 variable; - u64 unused[7]; -} AMO_t; - - -/* - * The following APIs are externalized to the kernel to allocate/free pages of - * fetchop variables. - * fetchop_kalloc_page - Allocate/initialize 1 fetchop page on the - * specified cnode. - * fetchop_kfree_page - Free a previously allocated fetchop page - */ - -unsigned long fetchop_kalloc_page(int nid); -void fetchop_kfree_page(unsigned long maddr); - - -#endif /* __KERNEL__ */ - -#endif /* _ASM_IA64_SN_FETCHOP_H */ - diff --git a/include/asm-ia64/sn/geo.h b/include/asm-ia64/sn/geo.h index f566343d25f8..84b254603b8d 100644 --- a/include/asm-ia64/sn/geo.h +++ b/include/asm-ia64/sn/geo.h @@ -18,32 +18,34 @@ #define GEOID_SIZE 8 /* Would 16 be better? The size can be different on different platforms. */ -#define MAX_SLABS 0xe /* slabs per module */ +#define MAX_SLOTS 0xf /* slots per module */ +#define MAX_SLABS 0xf /* slabs per slot */ typedef unsigned char geo_type_t; /* Fields common to all substructures */ -typedef struct geo_any_s { +typedef struct geo_common_s { moduleid_t module; /* The module (box) this h/w lives in */ geo_type_t type; /* What type of h/w is named by this geoid_t */ - slabid_t slab; /* The logical assembly within the module */ -} geo_any_t; + slabid_t slab:4; /* slab (ASIC), 0 .. 15 within slot */ + slotid_t slot:4; /* slot (Blade), 0 .. 15 within module */ +} geo_common_t; /* Additional fields for particular types of hardware */ typedef struct geo_node_s { - geo_any_t any; /* No additional fields needed */ + geo_common_t common; /* No additional fields needed */ } geo_node_t; typedef struct geo_rtr_s { - geo_any_t any; /* No additional fields needed */ + geo_common_t common; /* No additional fields needed */ } geo_rtr_t; typedef struct geo_iocntl_s { - geo_any_t any; /* No additional fields needed */ + geo_common_t common; /* No additional fields needed */ } geo_iocntl_t; typedef struct geo_pcicard_s { - geo_iocntl_t any; + geo_iocntl_t common; char bus; /* Bus/widget number */ char slot; /* PCI slot number */ } geo_pcicard_t; @@ -62,14 +64,14 @@ typedef struct geo_mem_s { typedef union geoid_u { - geo_any_t any; - geo_node_t node; + geo_common_t common; + geo_node_t node; geo_iocntl_t iocntl; geo_pcicard_t pcicard; - geo_rtr_t rtr; - geo_cpu_t cpu; - geo_mem_t mem; - char padsize[GEOID_SIZE]; + geo_rtr_t rtr; + geo_cpu_t cpu; + geo_mem_t mem; + char padsize[GEOID_SIZE]; } geoid_t; @@ -104,19 +106,26 @@ typedef union geoid_u { #define INVALID_CNODEID ((cnodeid_t)-1) #define INVALID_PNODEID ((pnodeid_t)-1) #define INVALID_SLAB (slabid_t)-1 +#define INVALID_SLOT (slotid_t)-1 #define INVALID_MODULE ((moduleid_t)-1) #define INVALID_PARTID ((partid_t)-1) static inline slabid_t geo_slab(geoid_t g) { - return (g.any.type == GEO_TYPE_INVALID) ? - INVALID_SLAB : g.any.slab; + return (g.common.type == GEO_TYPE_INVALID) ? + INVALID_SLAB : g.common.slab; +} + +static inline slotid_t geo_slot(geoid_t g) +{ + return (g.common.type == GEO_TYPE_INVALID) ? + INVALID_SLOT : g.common.slot; } static inline moduleid_t geo_module(geoid_t g) { - return (g.any.type == GEO_TYPE_INVALID) ? - INVALID_MODULE : g.any.module; + return (g.common.type == GEO_TYPE_INVALID) ? + INVALID_MODULE : g.common.module; } extern geoid_t cnodeid_get_geoid(cnodeid_t cnode); diff --git a/include/asm-ia64/sn/l1.h b/include/asm-ia64/sn/l1.h index d5dbd55e44b5..08050d37b662 100644 --- a/include/asm-ia64/sn/l1.h +++ b/include/asm-ia64/sn/l1.h @@ -29,8 +29,9 @@ #define L1_BRICKTYPE_CHI_CG 0x76 /* v */ #define L1_BRICKTYPE_X 0x78 /* x */ #define L1_BRICKTYPE_X2 0x79 /* y */ -#define L1_BRICKTYPE_SA 0x5e /* ^ */ /* TIO bringup brick */ +#define L1_BRICKTYPE_SA 0x5e /* ^ */ #define L1_BRICKTYPE_PA 0x6a /* j */ #define L1_BRICKTYPE_IA 0x6b /* k */ +#define L1_BRICKTYPE_ATHENA 0x2b /* + */ #endif /* _ASM_IA64_SN_L1_H */ diff --git a/include/asm-ia64/sn/nodepda.h b/include/asm-ia64/sn/nodepda.h index 2fbde33656e6..7138b1eafd6b 100644 --- a/include/asm-ia64/sn/nodepda.h +++ b/include/asm-ia64/sn/nodepda.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_IA64_SN_NODEPDA_H #define _ASM_IA64_SN_NODEPDA_H @@ -13,7 +13,6 @@ #include <asm/irq.h> #include <asm/sn/arch.h> #include <asm/sn/intr.h> -#include <asm/sn/pda.h> #include <asm/sn/bte.h> /* @@ -43,7 +42,7 @@ struct nodepda_s { /* * The BTEs on this node are shared by the local cpus */ - struct bteinfo_s bte_if[BTES_PER_NODE]; /* Virtual Interface */ + struct bteinfo_s bte_if[MAX_BTES_PER_NODE]; /* Virtual Interface */ struct timer_list bte_recovery_timer; spinlock_t bte_recovery_lock; @@ -67,20 +66,18 @@ typedef struct nodepda_s nodepda_t; * The next set of definitions provides this. * Routines are expected to use * - * nodepda -> to access node PDA for the node on which code is running - * subnodepda -> to access subnode PDA for the subnode on which code is running - * - * NODEPDA(cnode) -> to access node PDA for cnodeid - * SUBNODEPDA(cnode,sn) -> to access subnode PDA for cnodeid/subnode + * sn_nodepda - to access node PDA for the node on which code is running + * NODEPDA(cnodeid) - to access node PDA for cnodeid */ -#define nodepda pda->p_nodepda /* Ptr to this node's PDA */ -#define NODEPDA(cnode) (nodepda->pernode_pdaindr[cnode]) +DECLARE_PER_CPU(struct nodepda_s *, __sn_nodepda); +#define sn_nodepda (__get_cpu_var(__sn_nodepda)) +#define NODEPDA(cnodeid) (sn_nodepda->pernode_pdaindr[cnodeid]) /* * Check if given a compact node id the corresponding node has all the * cpus disabled. */ -#define is_headless_node(cnode) (nr_cpus_node(cnode) == 0) +#define is_headless_node(cnodeid) (nr_cpus_node(cnodeid) == 0) #endif /* _ASM_IA64_SN_NODEPDA_H */ diff --git a/include/asm-ia64/sn/pcibus_provider_defs.h b/include/asm-ia64/sn/pcibus_provider_defs.h new file mode 100644 index 000000000000..04e27d5b3820 --- /dev/null +++ b/include/asm-ia64/sn/pcibus_provider_defs.h @@ -0,0 +1,52 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved. + */ +#ifndef _ASM_IA64_SN_PCI_PCIBUS_PROVIDER_H +#define _ASM_IA64_SN_PCI_PCIBUS_PROVIDER_H + +/* + * SN pci asic types. Do not ever renumber these or reuse values. The + * values must agree with what prom thinks they are. + */ + +#define PCIIO_ASIC_TYPE_UNKNOWN 0 +#define PCIIO_ASIC_TYPE_PPB 1 +#define PCIIO_ASIC_TYPE_PIC 2 +#define PCIIO_ASIC_TYPE_TIOCP 3 +#define PCIIO_ASIC_TYPE_TIOCA 4 + +#define PCIIO_ASIC_MAX_TYPES 5 + +/* + * Common pciio bus provider data. There should be one of these as the + * first field in any pciio based provider soft structure (e.g. pcibr_soft + * tioca_soft, etc). + */ + +struct pcibus_bussoft { + uint32_t bs_asic_type; /* chipset type */ + uint32_t bs_xid; /* xwidget id */ + uint64_t bs_persist_busnum; /* Persistent Bus Number */ + uint64_t bs_legacy_io; /* legacy io pio addr */ + uint64_t bs_legacy_mem; /* legacy mem pio addr */ + uint64_t bs_base; /* widget base */ + struct xwidget_info *bs_xwidget_info; +}; + +/* + * SN pci bus indirection + */ + +struct sn_pcibus_provider { + dma_addr_t (*dma_map)(struct pci_dev *, unsigned long, size_t); + dma_addr_t (*dma_map_consistent)(struct pci_dev *, unsigned long, size_t); + void (*dma_unmap)(struct pci_dev *, dma_addr_t, int); + void * (*bus_fixup)(struct pcibus_bussoft *); +}; + +extern struct sn_pcibus_provider *sn_pci_provider[]; +#endif /* _ASM_IA64_SN_PCI_PCIBUS_PROVIDER_H */ diff --git a/include/asm-ia64/sn/pcidev.h b/include/asm-ia64/sn/pcidev.h new file mode 100644 index 000000000000..ed4031d80811 --- /dev/null +++ b/include/asm-ia64/sn/pcidev.h @@ -0,0 +1,58 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved. + */ +#ifndef _ASM_IA64_SN_PCI_PCIDEV_H +#define _ASM_IA64_SN_PCI_PCIDEV_H + +#include <linux/pci.h> + +extern struct sn_irq_info **sn_irq; + +#define SN_PCIDEV_INFO(pci_dev) \ + ((struct pcidev_info *)(pci_dev)->sysdata) + +/* + * Given a pci_bus, return the sn pcibus_bussoft struct. Note that + * this only works for root busses, not for busses represented by PPB's. + */ + +#define SN_PCIBUS_BUSSOFT(pci_bus) \ + ((struct pcibus_bussoft *)(PCI_CONTROLLER((pci_bus))->platform_data)) + +/* + * Given a struct pci_dev, return the sn pcibus_bussoft struct. Note + * that this is not equivalent to SN_PCIBUS_BUSSOFT(pci_dev->bus) due + * due to possible PPB's in the path. + */ + +#define SN_PCIDEV_BUSSOFT(pci_dev) \ + (SN_PCIDEV_INFO(pci_dev)->pdi_host_pcidev_info->pdi_pcibus_info) + +#define SN_PCIDEV_BUSPROVIDER(pci_dev) \ + (SN_PCIDEV_INFO(pci_dev)->pdi_provider) + +#define PCIIO_BUS_NONE 255 /* bus 255 reserved */ +#define PCIIO_SLOT_NONE 255 +#define PCIIO_FUNC_NONE 255 +#define PCIIO_VENDOR_ID_NONE (-1) + +struct pcidev_info { + uint64_t pdi_pio_mapped_addr[7]; /* 6 BARs PLUS 1 ROM */ + uint64_t pdi_slot_host_handle; /* Bus and devfn Host pci_dev */ + + struct pcibus_bussoft *pdi_pcibus_info; /* Kernel common bus soft */ + struct pcidev_info *pdi_host_pcidev_info; /* Kernel Host pci_dev */ + struct pci_dev *pdi_linux_pcidev; /* Kernel pci_dev */ + + struct sn_irq_info *pdi_sn_irq_info; + struct sn_pcibus_provider *pdi_provider; /* sn pci ops */ +}; + +extern void sn_irq_fixup(struct pci_dev *pci_dev, + struct sn_irq_info *sn_irq_info); + +#endif /* _ASM_IA64_SN_PCI_PCIDEV_H */ diff --git a/include/asm-ia64/sn/pda.h b/include/asm-ia64/sn/pda.h index e940d3647c80..ea5590c76ca4 100644 --- a/include/asm-ia64/sn/pda.h +++ b/include/asm-ia64/sn/pda.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_IA64_SN_PDA_H #define _ASM_IA64_SN_PDA_H @@ -11,7 +11,6 @@ #include <linux/cache.h> #include <asm/percpu.h> #include <asm/system.h> -#include <asm/sn/bte.h> /* @@ -25,14 +24,6 @@ typedef struct pda_s { - /* Having a pointer in the begining of PDA tends to increase - * the chance of having this pointer in cache. (Yes something - * else gets pushed out). Doing this reduces the number of memory - * access to all nodepda variables to be one - */ - struct nodepda_s *p_nodepda; /* Pointer to Per node PDA */ - struct subnodepda_s *p_subnodepda; /* Pointer to CPU subnode PDA */ - /* * Support for SN LEDs */ @@ -50,7 +41,6 @@ typedef struct pda_s { unsigned long sn_soft_irr[4]; unsigned long sn_in_service_ivecs[4]; - short cnodeid_to_nasid_table[MAX_NUMNODES]; int sn_lb_int_war_ticks; int sn_last_irq; int sn_first_irq; diff --git a/include/asm-ia64/sn/shub_mmr.h b/include/asm-ia64/sn/shub_mmr.h index 5c2fcf13d5ce..323fa0cd8d83 100644 --- a/include/asm-ia64/sn/shub_mmr.h +++ b/include/asm-ia64/sn/shub_mmr.h @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (c) 2001-2004 Silicon Graphics, Inc. All rights reserved. + * Copyright (c) 2001-2005 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_IA64_SN_SHUB_MMR_H @@ -129,6 +129,23 @@ #define SH_EVENT_OCCURRED_II_INT1_SHFT 30 #define SH_EVENT_OCCURRED_II_INT1_MASK 0x0000000040000000 +/* SH2_EVENT_OCCURRED_EXTIO_INT2 */ +/* Description: Pending SHUB 2 EXT IO INT2 */ +#define SH2_EVENT_OCCURRED_EXTIO_INT2_SHFT 33 +#define SH2_EVENT_OCCURRED_EXTIO_INT2_MASK 0x0000000200000000 + +/* SH2_EVENT_OCCURRED_EXTIO_INT3 */ +/* Description: Pending SHUB 2 EXT IO INT3 */ +#define SH2_EVENT_OCCURRED_EXTIO_INT3_SHFT 34 +#define SH2_EVENT_OCCURRED_EXTIO_INT3_MASK 0x0000000400000000 + +#define SH_ALL_INT_MASK \ + (SH_EVENT_OCCURRED_UART_INT_MASK | SH_EVENT_OCCURRED_IPI_INT_MASK | \ + SH_EVENT_OCCURRED_II_INT0_MASK | SH_EVENT_OCCURRED_II_INT1_MASK | \ + SH_EVENT_OCCURRED_II_INT1_MASK | SH2_EVENT_OCCURRED_EXTIO_INT2_MASK | \ + SH2_EVENT_OCCURRED_EXTIO_INT3_MASK) + + /* ==================================================================== */ /* LEDS */ /* ==================================================================== */ @@ -368,6 +385,17 @@ #define SH_EVENT_OCCURRED_RTC3_INT_MASK 0x0000000004000000 /* ==================================================================== */ +/* Register "SH_IPI_ACCESS" */ +/* CPU interrupt Access Permission Bits */ +/* ==================================================================== */ + +#define SH1_IPI_ACCESS 0x0000000110060480 +#define SH2_IPI_ACCESS0 0x0000000010060c00 +#define SH2_IPI_ACCESS1 0x0000000010060c80 +#define SH2_IPI_ACCESS2 0x0000000010060d00 +#define SH2_IPI_ACCESS3 0x0000000010060d80 + +/* ==================================================================== */ /* Register "SH_INT_CMPB" */ /* RTC Compare Value for Processor B */ /* ==================================================================== */ @@ -412,6 +440,19 @@ #define SH_INT_CMPD_REAL_TIME_CMPD_SHFT 0 #define SH_INT_CMPD_REAL_TIME_CMPD_MASK 0x007fffffffffffff +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC0" */ +/* privilege vector for acc=0 */ +/* ==================================================================== */ + +#define SH1_MD_DQLP_MMR_DIR_PRIVEC0 0x0000000100030300 + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC0" */ +/* privilege vector for acc=0 */ +/* ==================================================================== */ + +#define SH1_MD_DQRP_MMR_DIR_PRIVEC0 0x0000000100050300 /* ==================================================================== */ /* Some MMRs are functionally identical (or close enough) on both SHUB1 */ @@ -438,4 +479,22 @@ #define SH_INT_CMPC shubmmr(SH, INT_CMPC) #define SH_INT_CMPD shubmmr(SH, INT_CMPD) +/* ========================================================================== */ +/* Register "SH2_BT_ENG_CSR_0" */ +/* Engine 0 Control and Status Register */ +/* ========================================================================== */ + +#define SH2_BT_ENG_CSR_0 0x0000000030040000 +#define SH2_BT_ENG_SRC_ADDR_0 0x0000000030040080 +#define SH2_BT_ENG_DEST_ADDR_0 0x0000000030040100 +#define SH2_BT_ENG_NOTIF_ADDR_0 0x0000000030040180 + +/* ========================================================================== */ +/* BTE interfaces 1-3 */ +/* ========================================================================== */ + +#define SH2_BT_ENG_CSR_1 0x0000000030050000 +#define SH2_BT_ENG_CSR_2 0x0000000030060000 +#define SH2_BT_ENG_CSR_3 0x0000000030070000 + #endif /* _ASM_IA64_SN_SHUB_MMR_H */ diff --git a/include/asm-ia64/sn/shubio.h b/include/asm-ia64/sn/shubio.h index fbd880e6bb96..831b72111fdc 100644 --- a/include/asm-ia64/sn/shubio.h +++ b/include/asm-ia64/sn/shubio.h @@ -3,292 +3,287 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_IA64_SN_SHUBIO_H #define _ASM_IA64_SN_SHUBIO_H -#define HUB_WIDGET_ID_MAX 0xf -#define IIO_NUM_ITTES 7 -#define HUB_NUM_BIG_WINDOW (IIO_NUM_ITTES - 1) - -#define IIO_WID 0x00400000 /* Crosstalk Widget Identification */ - /* This register is also accessible from - * Crosstalk at address 0x0. */ -#define IIO_WSTAT 0x00400008 /* Crosstalk Widget Status */ -#define IIO_WCR 0x00400020 /* Crosstalk Widget Control Register */ -#define IIO_ILAPR 0x00400100 /* IO Local Access Protection Register */ -#define IIO_ILAPO 0x00400108 /* IO Local Access Protection Override */ -#define IIO_IOWA 0x00400110 /* IO Outbound Widget Access */ -#define IIO_IIWA 0x00400118 /* IO Inbound Widget Access */ -#define IIO_IIDEM 0x00400120 /* IO Inbound Device Error Mask */ -#define IIO_ILCSR 0x00400128 /* IO LLP Control and Status Register */ -#define IIO_ILLR 0x00400130 /* IO LLP Log Register */ -#define IIO_IIDSR 0x00400138 /* IO Interrupt Destination */ - -#define IIO_IGFX0 0x00400140 /* IO Graphics Node-Widget Map 0 */ -#define IIO_IGFX1 0x00400148 /* IO Graphics Node-Widget Map 1 */ - -#define IIO_ISCR0 0x00400150 /* IO Scratch Register 0 */ -#define IIO_ISCR1 0x00400158 /* IO Scratch Register 1 */ - -#define IIO_ITTE1 0x00400160 /* IO Translation Table Entry 1 */ -#define IIO_ITTE2 0x00400168 /* IO Translation Table Entry 2 */ -#define IIO_ITTE3 0x00400170 /* IO Translation Table Entry 3 */ -#define IIO_ITTE4 0x00400178 /* IO Translation Table Entry 4 */ -#define IIO_ITTE5 0x00400180 /* IO Translation Table Entry 5 */ -#define IIO_ITTE6 0x00400188 /* IO Translation Table Entry 6 */ -#define IIO_ITTE7 0x00400190 /* IO Translation Table Entry 7 */ - -#define IIO_IPRB0 0x00400198 /* IO PRB Entry 0 */ -#define IIO_IPRB8 0x004001A0 /* IO PRB Entry 8 */ -#define IIO_IPRB9 0x004001A8 /* IO PRB Entry 9 */ -#define IIO_IPRBA 0x004001B0 /* IO PRB Entry A */ -#define IIO_IPRBB 0x004001B8 /* IO PRB Entry B */ -#define IIO_IPRBC 0x004001C0 /* IO PRB Entry C */ -#define IIO_IPRBD 0x004001C8 /* IO PRB Entry D */ -#define IIO_IPRBE 0x004001D0 /* IO PRB Entry E */ -#define IIO_IPRBF 0x004001D8 /* IO PRB Entry F */ - -#define IIO_IXCC 0x004001E0 /* IO Crosstalk Credit Count Timeout */ -#define IIO_IMEM 0x004001E8 /* IO Miscellaneous Error Mask */ -#define IIO_IXTT 0x004001F0 /* IO Crosstalk Timeout Threshold */ -#define IIO_IECLR 0x004001F8 /* IO Error Clear Register */ -#define IIO_IBCR 0x00400200 /* IO BTE Control Register */ - -#define IIO_IXSM 0x00400208 /* IO Crosstalk Spurious Message */ -#define IIO_IXSS 0x00400210 /* IO Crosstalk Spurious Sideband */ - -#define IIO_ILCT 0x00400218 /* IO LLP Channel Test */ - -#define IIO_IIEPH1 0x00400220 /* IO Incoming Error Packet Header, Part 1 */ -#define IIO_IIEPH2 0x00400228 /* IO Incoming Error Packet Header, Part 2 */ - - -#define IIO_ISLAPR 0x00400230 /* IO SXB Local Access Protection Regster */ -#define IIO_ISLAPO 0x00400238 /* IO SXB Local Access Protection Override */ - -#define IIO_IWI 0x00400240 /* IO Wrapper Interrupt Register */ -#define IIO_IWEL 0x00400248 /* IO Wrapper Error Log Register */ -#define IIO_IWC 0x00400250 /* IO Wrapper Control Register */ -#define IIO_IWS 0x00400258 /* IO Wrapper Status Register */ -#define IIO_IWEIM 0x00400260 /* IO Wrapper Error Interrupt Masking Register */ - -#define IIO_IPCA 0x00400300 /* IO PRB Counter Adjust */ - -#define IIO_IPRTE0_A 0x00400308 /* IO PIO Read Address Table Entry 0, Part A */ -#define IIO_IPRTE1_A 0x00400310 /* IO PIO Read Address Table Entry 1, Part A */ -#define IIO_IPRTE2_A 0x00400318 /* IO PIO Read Address Table Entry 2, Part A */ -#define IIO_IPRTE3_A 0x00400320 /* IO PIO Read Address Table Entry 3, Part A */ -#define IIO_IPRTE4_A 0x00400328 /* IO PIO Read Address Table Entry 4, Part A */ -#define IIO_IPRTE5_A 0x00400330 /* IO PIO Read Address Table Entry 5, Part A */ -#define IIO_IPRTE6_A 0x00400338 /* IO PIO Read Address Table Entry 6, Part A */ -#define IIO_IPRTE7_A 0x00400340 /* IO PIO Read Address Table Entry 7, Part A */ - -#define IIO_IPRTE0_B 0x00400348 /* IO PIO Read Address Table Entry 0, Part B */ -#define IIO_IPRTE1_B 0x00400350 /* IO PIO Read Address Table Entry 1, Part B */ -#define IIO_IPRTE2_B 0x00400358 /* IO PIO Read Address Table Entry 2, Part B */ -#define IIO_IPRTE3_B 0x00400360 /* IO PIO Read Address Table Entry 3, Part B */ -#define IIO_IPRTE4_B 0x00400368 /* IO PIO Read Address Table Entry 4, Part B */ -#define IIO_IPRTE5_B 0x00400370 /* IO PIO Read Address Table Entry 5, Part B */ -#define IIO_IPRTE6_B 0x00400378 /* IO PIO Read Address Table Entry 6, Part B */ -#define IIO_IPRTE7_B 0x00400380 /* IO PIO Read Address Table Entry 7, Part B */ - -#define IIO_IPDR 0x00400388 /* IO PIO Deallocation Register */ -#define IIO_ICDR 0x00400390 /* IO CRB Entry Deallocation Register */ -#define IIO_IFDR 0x00400398 /* IO IOQ FIFO Depth Register */ -#define IIO_IIAP 0x004003A0 /* IO IIQ Arbitration Parameters */ -#define IIO_ICMR 0x004003A8 /* IO CRB Management Register */ -#define IIO_ICCR 0x004003B0 /* IO CRB Control Register */ -#define IIO_ICTO 0x004003B8 /* IO CRB Timeout */ -#define IIO_ICTP 0x004003C0 /* IO CRB Timeout Prescalar */ - -#define IIO_ICRB0_A 0x00400400 /* IO CRB Entry 0_A */ -#define IIO_ICRB0_B 0x00400408 /* IO CRB Entry 0_B */ -#define IIO_ICRB0_C 0x00400410 /* IO CRB Entry 0_C */ -#define IIO_ICRB0_D 0x00400418 /* IO CRB Entry 0_D */ -#define IIO_ICRB0_E 0x00400420 /* IO CRB Entry 0_E */ - -#define IIO_ICRB1_A 0x00400430 /* IO CRB Entry 1_A */ -#define IIO_ICRB1_B 0x00400438 /* IO CRB Entry 1_B */ -#define IIO_ICRB1_C 0x00400440 /* IO CRB Entry 1_C */ -#define IIO_ICRB1_D 0x00400448 /* IO CRB Entry 1_D */ -#define IIO_ICRB1_E 0x00400450 /* IO CRB Entry 1_E */ - -#define IIO_ICRB2_A 0x00400460 /* IO CRB Entry 2_A */ -#define IIO_ICRB2_B 0x00400468 /* IO CRB Entry 2_B */ -#define IIO_ICRB2_C 0x00400470 /* IO CRB Entry 2_C */ -#define IIO_ICRB2_D 0x00400478 /* IO CRB Entry 2_D */ -#define IIO_ICRB2_E 0x00400480 /* IO CRB Entry 2_E */ - -#define IIO_ICRB3_A 0x00400490 /* IO CRB Entry 3_A */ -#define IIO_ICRB3_B 0x00400498 /* IO CRB Entry 3_B */ -#define IIO_ICRB3_C 0x004004a0 /* IO CRB Entry 3_C */ -#define IIO_ICRB3_D 0x004004a8 /* IO CRB Entry 3_D */ -#define IIO_ICRB3_E 0x004004b0 /* IO CRB Entry 3_E */ - -#define IIO_ICRB4_A 0x004004c0 /* IO CRB Entry 4_A */ -#define IIO_ICRB4_B 0x004004c8 /* IO CRB Entry 4_B */ -#define IIO_ICRB4_C 0x004004d0 /* IO CRB Entry 4_C */ -#define IIO_ICRB4_D 0x004004d8 /* IO CRB Entry 4_D */ -#define IIO_ICRB4_E 0x004004e0 /* IO CRB Entry 4_E */ - -#define IIO_ICRB5_A 0x004004f0 /* IO CRB Entry 5_A */ -#define IIO_ICRB5_B 0x004004f8 /* IO CRB Entry 5_B */ -#define IIO_ICRB5_C 0x00400500 /* IO CRB Entry 5_C */ -#define IIO_ICRB5_D 0x00400508 /* IO CRB Entry 5_D */ -#define IIO_ICRB5_E 0x00400510 /* IO CRB Entry 5_E */ - -#define IIO_ICRB6_A 0x00400520 /* IO CRB Entry 6_A */ -#define IIO_ICRB6_B 0x00400528 /* IO CRB Entry 6_B */ -#define IIO_ICRB6_C 0x00400530 /* IO CRB Entry 6_C */ -#define IIO_ICRB6_D 0x00400538 /* IO CRB Entry 6_D */ -#define IIO_ICRB6_E 0x00400540 /* IO CRB Entry 6_E */ - -#define IIO_ICRB7_A 0x00400550 /* IO CRB Entry 7_A */ -#define IIO_ICRB7_B 0x00400558 /* IO CRB Entry 7_B */ -#define IIO_ICRB7_C 0x00400560 /* IO CRB Entry 7_C */ -#define IIO_ICRB7_D 0x00400568 /* IO CRB Entry 7_D */ -#define IIO_ICRB7_E 0x00400570 /* IO CRB Entry 7_E */ - -#define IIO_ICRB8_A 0x00400580 /* IO CRB Entry 8_A */ -#define IIO_ICRB8_B 0x00400588 /* IO CRB Entry 8_B */ -#define IIO_ICRB8_C 0x00400590 /* IO CRB Entry 8_C */ -#define IIO_ICRB8_D 0x00400598 /* IO CRB Entry 8_D */ -#define IIO_ICRB8_E 0x004005a0 /* IO CRB Entry 8_E */ - -#define IIO_ICRB9_A 0x004005b0 /* IO CRB Entry 9_A */ -#define IIO_ICRB9_B 0x004005b8 /* IO CRB Entry 9_B */ -#define IIO_ICRB9_C 0x004005c0 /* IO CRB Entry 9_C */ -#define IIO_ICRB9_D 0x004005c8 /* IO CRB Entry 9_D */ -#define IIO_ICRB9_E 0x004005d0 /* IO CRB Entry 9_E */ - -#define IIO_ICRBA_A 0x004005e0 /* IO CRB Entry A_A */ -#define IIO_ICRBA_B 0x004005e8 /* IO CRB Entry A_B */ -#define IIO_ICRBA_C 0x004005f0 /* IO CRB Entry A_C */ -#define IIO_ICRBA_D 0x004005f8 /* IO CRB Entry A_D */ -#define IIO_ICRBA_E 0x00400600 /* IO CRB Entry A_E */ - -#define IIO_ICRBB_A 0x00400610 /* IO CRB Entry B_A */ -#define IIO_ICRBB_B 0x00400618 /* IO CRB Entry B_B */ -#define IIO_ICRBB_C 0x00400620 /* IO CRB Entry B_C */ -#define IIO_ICRBB_D 0x00400628 /* IO CRB Entry B_D */ -#define IIO_ICRBB_E 0x00400630 /* IO CRB Entry B_E */ - -#define IIO_ICRBC_A 0x00400640 /* IO CRB Entry C_A */ -#define IIO_ICRBC_B 0x00400648 /* IO CRB Entry C_B */ -#define IIO_ICRBC_C 0x00400650 /* IO CRB Entry C_C */ -#define IIO_ICRBC_D 0x00400658 /* IO CRB Entry C_D */ -#define IIO_ICRBC_E 0x00400660 /* IO CRB Entry C_E */ - -#define IIO_ICRBD_A 0x00400670 /* IO CRB Entry D_A */ -#define IIO_ICRBD_B 0x00400678 /* IO CRB Entry D_B */ -#define IIO_ICRBD_C 0x00400680 /* IO CRB Entry D_C */ -#define IIO_ICRBD_D 0x00400688 /* IO CRB Entry D_D */ -#define IIO_ICRBD_E 0x00400690 /* IO CRB Entry D_E */ - -#define IIO_ICRBE_A 0x004006a0 /* IO CRB Entry E_A */ -#define IIO_ICRBE_B 0x004006a8 /* IO CRB Entry E_B */ -#define IIO_ICRBE_C 0x004006b0 /* IO CRB Entry E_C */ -#define IIO_ICRBE_D 0x004006b8 /* IO CRB Entry E_D */ -#define IIO_ICRBE_E 0x004006c0 /* IO CRB Entry E_E */ - -#define IIO_ICSML 0x00400700 /* IO CRB Spurious Message Low */ -#define IIO_ICSMM 0x00400708 /* IO CRB Spurious Message Middle */ -#define IIO_ICSMH 0x00400710 /* IO CRB Spurious Message High */ - -#define IIO_IDBSS 0x00400718 /* IO Debug Submenu Select */ - -#define IIO_IBLS0 0x00410000 /* IO BTE Length Status 0 */ -#define IIO_IBSA0 0x00410008 /* IO BTE Source Address 0 */ -#define IIO_IBDA0 0x00410010 /* IO BTE Destination Address 0 */ -#define IIO_IBCT0 0x00410018 /* IO BTE Control Terminate 0 */ -#define IIO_IBNA0 0x00410020 /* IO BTE Notification Address 0 */ -#define IIO_IBIA0 0x00410028 /* IO BTE Interrupt Address 0 */ -#define IIO_IBLS1 0x00420000 /* IO BTE Length Status 1 */ -#define IIO_IBSA1 0x00420008 /* IO BTE Source Address 1 */ -#define IIO_IBDA1 0x00420010 /* IO BTE Destination Address 1 */ -#define IIO_IBCT1 0x00420018 /* IO BTE Control Terminate 1 */ -#define IIO_IBNA1 0x00420020 /* IO BTE Notification Address 1 */ -#define IIO_IBIA1 0x00420028 /* IO BTE Interrupt Address 1 */ - -#define IIO_IPCR 0x00430000 /* IO Performance Control */ -#define IIO_IPPR 0x00430008 /* IO Performance Profiling */ - - -/************************************************************************ - * * +#define HUB_WIDGET_ID_MAX 0xf +#define IIO_NUM_ITTES 7 +#define HUB_NUM_BIG_WINDOW (IIO_NUM_ITTES - 1) + +#define IIO_WID 0x00400000 /* Crosstalk Widget Identification */ + /* This register is also accessible from + * Crosstalk at address 0x0. */ +#define IIO_WSTAT 0x00400008 /* Crosstalk Widget Status */ +#define IIO_WCR 0x00400020 /* Crosstalk Widget Control Register */ +#define IIO_ILAPR 0x00400100 /* IO Local Access Protection Register */ +#define IIO_ILAPO 0x00400108 /* IO Local Access Protection Override */ +#define IIO_IOWA 0x00400110 /* IO Outbound Widget Access */ +#define IIO_IIWA 0x00400118 /* IO Inbound Widget Access */ +#define IIO_IIDEM 0x00400120 /* IO Inbound Device Error Mask */ +#define IIO_ILCSR 0x00400128 /* IO LLP Control and Status Register */ +#define IIO_ILLR 0x00400130 /* IO LLP Log Register */ +#define IIO_IIDSR 0x00400138 /* IO Interrupt Destination */ + +#define IIO_IGFX0 0x00400140 /* IO Graphics Node-Widget Map 0 */ +#define IIO_IGFX1 0x00400148 /* IO Graphics Node-Widget Map 1 */ + +#define IIO_ISCR0 0x00400150 /* IO Scratch Register 0 */ +#define IIO_ISCR1 0x00400158 /* IO Scratch Register 1 */ + +#define IIO_ITTE1 0x00400160 /* IO Translation Table Entry 1 */ +#define IIO_ITTE2 0x00400168 /* IO Translation Table Entry 2 */ +#define IIO_ITTE3 0x00400170 /* IO Translation Table Entry 3 */ +#define IIO_ITTE4 0x00400178 /* IO Translation Table Entry 4 */ +#define IIO_ITTE5 0x00400180 /* IO Translation Table Entry 5 */ +#define IIO_ITTE6 0x00400188 /* IO Translation Table Entry 6 */ +#define IIO_ITTE7 0x00400190 /* IO Translation Table Entry 7 */ + +#define IIO_IPRB0 0x00400198 /* IO PRB Entry 0 */ +#define IIO_IPRB8 0x004001A0 /* IO PRB Entry 8 */ +#define IIO_IPRB9 0x004001A8 /* IO PRB Entry 9 */ +#define IIO_IPRBA 0x004001B0 /* IO PRB Entry A */ +#define IIO_IPRBB 0x004001B8 /* IO PRB Entry B */ +#define IIO_IPRBC 0x004001C0 /* IO PRB Entry C */ +#define IIO_IPRBD 0x004001C8 /* IO PRB Entry D */ +#define IIO_IPRBE 0x004001D0 /* IO PRB Entry E */ +#define IIO_IPRBF 0x004001D8 /* IO PRB Entry F */ + +#define IIO_IXCC 0x004001E0 /* IO Crosstalk Credit Count Timeout */ +#define IIO_IMEM 0x004001E8 /* IO Miscellaneous Error Mask */ +#define IIO_IXTT 0x004001F0 /* IO Crosstalk Timeout Threshold */ +#define IIO_IECLR 0x004001F8 /* IO Error Clear Register */ +#define IIO_IBCR 0x00400200 /* IO BTE Control Register */ + +#define IIO_IXSM 0x00400208 /* IO Crosstalk Spurious Message */ +#define IIO_IXSS 0x00400210 /* IO Crosstalk Spurious Sideband */ + +#define IIO_ILCT 0x00400218 /* IO LLP Channel Test */ + +#define IIO_IIEPH1 0x00400220 /* IO Incoming Error Packet Header, Part 1 */ +#define IIO_IIEPH2 0x00400228 /* IO Incoming Error Packet Header, Part 2 */ + +#define IIO_ISLAPR 0x00400230 /* IO SXB Local Access Protection Regster */ +#define IIO_ISLAPO 0x00400238 /* IO SXB Local Access Protection Override */ + +#define IIO_IWI 0x00400240 /* IO Wrapper Interrupt Register */ +#define IIO_IWEL 0x00400248 /* IO Wrapper Error Log Register */ +#define IIO_IWC 0x00400250 /* IO Wrapper Control Register */ +#define IIO_IWS 0x00400258 /* IO Wrapper Status Register */ +#define IIO_IWEIM 0x00400260 /* IO Wrapper Error Interrupt Masking Register */ + +#define IIO_IPCA 0x00400300 /* IO PRB Counter Adjust */ + +#define IIO_IPRTE0_A 0x00400308 /* IO PIO Read Address Table Entry 0, Part A */ +#define IIO_IPRTE1_A 0x00400310 /* IO PIO Read Address Table Entry 1, Part A */ +#define IIO_IPRTE2_A 0x00400318 /* IO PIO Read Address Table Entry 2, Part A */ +#define IIO_IPRTE3_A 0x00400320 /* IO PIO Read Address Table Entry 3, Part A */ +#define IIO_IPRTE4_A 0x00400328 /* IO PIO Read Address Table Entry 4, Part A */ +#define IIO_IPRTE5_A 0x00400330 /* IO PIO Read Address Table Entry 5, Part A */ +#define IIO_IPRTE6_A 0x00400338 /* IO PIO Read Address Table Entry 6, Part A */ +#define IIO_IPRTE7_A 0x00400340 /* IO PIO Read Address Table Entry 7, Part A */ + +#define IIO_IPRTE0_B 0x00400348 /* IO PIO Read Address Table Entry 0, Part B */ +#define IIO_IPRTE1_B 0x00400350 /* IO PIO Read Address Table Entry 1, Part B */ +#define IIO_IPRTE2_B 0x00400358 /* IO PIO Read Address Table Entry 2, Part B */ +#define IIO_IPRTE3_B 0x00400360 /* IO PIO Read Address Table Entry 3, Part B */ +#define IIO_IPRTE4_B 0x00400368 /* IO PIO Read Address Table Entry 4, Part B */ +#define IIO_IPRTE5_B 0x00400370 /* IO PIO Read Address Table Entry 5, Part B */ +#define IIO_IPRTE6_B 0x00400378 /* IO PIO Read Address Table Entry 6, Part B */ +#define IIO_IPRTE7_B 0x00400380 /* IO PIO Read Address Table Entry 7, Part B */ + +#define IIO_IPDR 0x00400388 /* IO PIO Deallocation Register */ +#define IIO_ICDR 0x00400390 /* IO CRB Entry Deallocation Register */ +#define IIO_IFDR 0x00400398 /* IO IOQ FIFO Depth Register */ +#define IIO_IIAP 0x004003A0 /* IO IIQ Arbitration Parameters */ +#define IIO_ICMR 0x004003A8 /* IO CRB Management Register */ +#define IIO_ICCR 0x004003B0 /* IO CRB Control Register */ +#define IIO_ICTO 0x004003B8 /* IO CRB Timeout */ +#define IIO_ICTP 0x004003C0 /* IO CRB Timeout Prescalar */ + +#define IIO_ICRB0_A 0x00400400 /* IO CRB Entry 0_A */ +#define IIO_ICRB0_B 0x00400408 /* IO CRB Entry 0_B */ +#define IIO_ICRB0_C 0x00400410 /* IO CRB Entry 0_C */ +#define IIO_ICRB0_D 0x00400418 /* IO CRB Entry 0_D */ +#define IIO_ICRB0_E 0x00400420 /* IO CRB Entry 0_E */ + +#define IIO_ICRB1_A 0x00400430 /* IO CRB Entry 1_A */ +#define IIO_ICRB1_B 0x00400438 /* IO CRB Entry 1_B */ +#define IIO_ICRB1_C 0x00400440 /* IO CRB Entry 1_C */ +#define IIO_ICRB1_D 0x00400448 /* IO CRB Entry 1_D */ +#define IIO_ICRB1_E 0x00400450 /* IO CRB Entry 1_E */ + +#define IIO_ICRB2_A 0x00400460 /* IO CRB Entry 2_A */ +#define IIO_ICRB2_B 0x00400468 /* IO CRB Entry 2_B */ +#define IIO_ICRB2_C 0x00400470 /* IO CRB Entry 2_C */ +#define IIO_ICRB2_D 0x00400478 /* IO CRB Entry 2_D */ +#define IIO_ICRB2_E 0x00400480 /* IO CRB Entry 2_E */ + +#define IIO_ICRB3_A 0x00400490 /* IO CRB Entry 3_A */ +#define IIO_ICRB3_B 0x00400498 /* IO CRB Entry 3_B */ +#define IIO_ICRB3_C 0x004004a0 /* IO CRB Entry 3_C */ +#define IIO_ICRB3_D 0x004004a8 /* IO CRB Entry 3_D */ +#define IIO_ICRB3_E 0x004004b0 /* IO CRB Entry 3_E */ + +#define IIO_ICRB4_A 0x004004c0 /* IO CRB Entry 4_A */ +#define IIO_ICRB4_B 0x004004c8 /* IO CRB Entry 4_B */ +#define IIO_ICRB4_C 0x004004d0 /* IO CRB Entry 4_C */ +#define IIO_ICRB4_D 0x004004d8 /* IO CRB Entry 4_D */ +#define IIO_ICRB4_E 0x004004e0 /* IO CRB Entry 4_E */ + +#define IIO_ICRB5_A 0x004004f0 /* IO CRB Entry 5_A */ +#define IIO_ICRB5_B 0x004004f8 /* IO CRB Entry 5_B */ +#define IIO_ICRB5_C 0x00400500 /* IO CRB Entry 5_C */ +#define IIO_ICRB5_D 0x00400508 /* IO CRB Entry 5_D */ +#define IIO_ICRB5_E 0x00400510 /* IO CRB Entry 5_E */ + +#define IIO_ICRB6_A 0x00400520 /* IO CRB Entry 6_A */ +#define IIO_ICRB6_B 0x00400528 /* IO CRB Entry 6_B */ +#define IIO_ICRB6_C 0x00400530 /* IO CRB Entry 6_C */ +#define IIO_ICRB6_D 0x00400538 /* IO CRB Entry 6_D */ +#define IIO_ICRB6_E 0x00400540 /* IO CRB Entry 6_E */ + +#define IIO_ICRB7_A 0x00400550 /* IO CRB Entry 7_A */ +#define IIO_ICRB7_B 0x00400558 /* IO CRB Entry 7_B */ +#define IIO_ICRB7_C 0x00400560 /* IO CRB Entry 7_C */ +#define IIO_ICRB7_D 0x00400568 /* IO CRB Entry 7_D */ +#define IIO_ICRB7_E 0x00400570 /* IO CRB Entry 7_E */ + +#define IIO_ICRB8_A 0x00400580 /* IO CRB Entry 8_A */ +#define IIO_ICRB8_B 0x00400588 /* IO CRB Entry 8_B */ +#define IIO_ICRB8_C 0x00400590 /* IO CRB Entry 8_C */ +#define IIO_ICRB8_D 0x00400598 /* IO CRB Entry 8_D */ +#define IIO_ICRB8_E 0x004005a0 /* IO CRB Entry 8_E */ + +#define IIO_ICRB9_A 0x004005b0 /* IO CRB Entry 9_A */ +#define IIO_ICRB9_B 0x004005b8 /* IO CRB Entry 9_B */ +#define IIO_ICRB9_C 0x004005c0 /* IO CRB Entry 9_C */ +#define IIO_ICRB9_D 0x004005c8 /* IO CRB Entry 9_D */ +#define IIO_ICRB9_E 0x004005d0 /* IO CRB Entry 9_E */ + +#define IIO_ICRBA_A 0x004005e0 /* IO CRB Entry A_A */ +#define IIO_ICRBA_B 0x004005e8 /* IO CRB Entry A_B */ +#define IIO_ICRBA_C 0x004005f0 /* IO CRB Entry A_C */ +#define IIO_ICRBA_D 0x004005f8 /* IO CRB Entry A_D */ +#define IIO_ICRBA_E 0x00400600 /* IO CRB Entry A_E */ + +#define IIO_ICRBB_A 0x00400610 /* IO CRB Entry B_A */ +#define IIO_ICRBB_B 0x00400618 /* IO CRB Entry B_B */ +#define IIO_ICRBB_C 0x00400620 /* IO CRB Entry B_C */ +#define IIO_ICRBB_D 0x00400628 /* IO CRB Entry B_D */ +#define IIO_ICRBB_E 0x00400630 /* IO CRB Entry B_E */ + +#define IIO_ICRBC_A 0x00400640 /* IO CRB Entry C_A */ +#define IIO_ICRBC_B 0x00400648 /* IO CRB Entry C_B */ +#define IIO_ICRBC_C 0x00400650 /* IO CRB Entry C_C */ +#define IIO_ICRBC_D 0x00400658 /* IO CRB Entry C_D */ +#define IIO_ICRBC_E 0x00400660 /* IO CRB Entry C_E */ + +#define IIO_ICRBD_A 0x00400670 /* IO CRB Entry D_A */ +#define IIO_ICRBD_B 0x00400678 /* IO CRB Entry D_B */ +#define IIO_ICRBD_C 0x00400680 /* IO CRB Entry D_C */ +#define IIO_ICRBD_D 0x00400688 /* IO CRB Entry D_D */ +#define IIO_ICRBD_E 0x00400690 /* IO CRB Entry D_E */ + +#define IIO_ICRBE_A 0x004006a0 /* IO CRB Entry E_A */ +#define IIO_ICRBE_B 0x004006a8 /* IO CRB Entry E_B */ +#define IIO_ICRBE_C 0x004006b0 /* IO CRB Entry E_C */ +#define IIO_ICRBE_D 0x004006b8 /* IO CRB Entry E_D */ +#define IIO_ICRBE_E 0x004006c0 /* IO CRB Entry E_E */ + +#define IIO_ICSML 0x00400700 /* IO CRB Spurious Message Low */ +#define IIO_ICSMM 0x00400708 /* IO CRB Spurious Message Middle */ +#define IIO_ICSMH 0x00400710 /* IO CRB Spurious Message High */ + +#define IIO_IDBSS 0x00400718 /* IO Debug Submenu Select */ + +#define IIO_IBLS0 0x00410000 /* IO BTE Length Status 0 */ +#define IIO_IBSA0 0x00410008 /* IO BTE Source Address 0 */ +#define IIO_IBDA0 0x00410010 /* IO BTE Destination Address 0 */ +#define IIO_IBCT0 0x00410018 /* IO BTE Control Terminate 0 */ +#define IIO_IBNA0 0x00410020 /* IO BTE Notification Address 0 */ +#define IIO_IBIA0 0x00410028 /* IO BTE Interrupt Address 0 */ +#define IIO_IBLS1 0x00420000 /* IO BTE Length Status 1 */ +#define IIO_IBSA1 0x00420008 /* IO BTE Source Address 1 */ +#define IIO_IBDA1 0x00420010 /* IO BTE Destination Address 1 */ +#define IIO_IBCT1 0x00420018 /* IO BTE Control Terminate 1 */ +#define IIO_IBNA1 0x00420020 /* IO BTE Notification Address 1 */ +#define IIO_IBIA1 0x00420028 /* IO BTE Interrupt Address 1 */ + +#define IIO_IPCR 0x00430000 /* IO Performance Control */ +#define IIO_IPPR 0x00430008 /* IO Performance Profiling */ + +/************************************************************************ + * * * Description: This register echoes some information from the * * LB_REV_ID register. It is available through Crosstalk as described * * above. The REV_NUM and MFG_NUM fields receive their values from * * the REVISION and MANUFACTURER fields in the LB_REV_ID register. * * The PART_NUM field's value is the Crosstalk device ID number that * * Steve Miller assigned to the SHub chip. * - * * + * * ************************************************************************/ typedef union ii_wid_u { - uint64_t ii_wid_regval; - struct { - uint64_t w_rsvd_1 : 1; - uint64_t w_mfg_num : 11; - uint64_t w_part_num : 16; - uint64_t w_rev_num : 4; - uint64_t w_rsvd : 32; + uint64_t ii_wid_regval; + struct { + uint64_t w_rsvd_1:1; + uint64_t w_mfg_num:11; + uint64_t w_part_num:16; + uint64_t w_rev_num:4; + uint64_t w_rsvd:32; } ii_wid_fld_s; } ii_wid_u_t; - /************************************************************************ - * * + * * * The fields in this register are set upon detection of an error * * and cleared by various mechanisms, as explained in the * * description. * - * * + * * ************************************************************************/ typedef union ii_wstat_u { - uint64_t ii_wstat_regval; - struct { - uint64_t w_pending : 4; - uint64_t w_xt_crd_to : 1; - uint64_t w_xt_tail_to : 1; - uint64_t w_rsvd_3 : 3; - uint64_t w_tx_mx_rty : 1; - uint64_t w_rsvd_2 : 6; - uint64_t w_llp_tx_cnt : 8; - uint64_t w_rsvd_1 : 8; - uint64_t w_crazy : 1; - uint64_t w_rsvd : 31; + uint64_t ii_wstat_regval; + struct { + uint64_t w_pending:4; + uint64_t w_xt_crd_to:1; + uint64_t w_xt_tail_to:1; + uint64_t w_rsvd_3:3; + uint64_t w_tx_mx_rty:1; + uint64_t w_rsvd_2:6; + uint64_t w_llp_tx_cnt:8; + uint64_t w_rsvd_1:8; + uint64_t w_crazy:1; + uint64_t w_rsvd:31; } ii_wstat_fld_s; } ii_wstat_u_t; - /************************************************************************ - * * + * * * Description: This is a read-write enabled register. It controls * * various aspects of the Crosstalk flow control. * - * * + * * ************************************************************************/ typedef union ii_wcr_u { - uint64_t ii_wcr_regval; - struct { - uint64_t w_wid : 4; - uint64_t w_tag : 1; - uint64_t w_rsvd_1 : 8; - uint64_t w_dst_crd : 3; - uint64_t w_f_bad_pkt : 1; - uint64_t w_dir_con : 1; - uint64_t w_e_thresh : 5; - uint64_t w_rsvd : 41; + uint64_t ii_wcr_regval; + struct { + uint64_t w_wid:4; + uint64_t w_tag:1; + uint64_t w_rsvd_1:8; + uint64_t w_dst_crd:3; + uint64_t w_f_bad_pkt:1; + uint64_t w_dir_con:1; + uint64_t w_e_thresh:5; + uint64_t w_rsvd:41; } ii_wcr_fld_s; } ii_wcr_u_t; - /************************************************************************ - * * + * * * Description: This register's value is a bit vector that guards * * access to local registers within the II as well as to external * * Crosstalk widgets. Each bit in the register corresponds to a * @@ -311,21 +306,18 @@ typedef union ii_wcr_u { * region ID bits are enabled in this same register. It can also be * * accessed through the IAlias space by the local processors. * * The reset value of this register allows access by all nodes. * - * * + * * ************************************************************************/ typedef union ii_ilapr_u { - uint64_t ii_ilapr_regval; - struct { - uint64_t i_region : 64; + uint64_t ii_ilapr_regval; + struct { + uint64_t i_region:64; } ii_ilapr_fld_s; } ii_ilapr_u_t; - - - /************************************************************************ - * * + * * * Description: A write to this register of the 64-bit value * * "SGIrules" in ASCII, will cause the bit in the ILAPR register * * corresponding to the region of the requestor to be set (allow * @@ -334,59 +326,54 @@ typedef union ii_ilapr_u { * This register can also be accessed through the IAlias space. * * However, this access will not change the access permissions in the * * ILAPR. * - * * + * * ************************************************************************/ typedef union ii_ilapo_u { - uint64_t ii_ilapo_regval; - struct { - uint64_t i_io_ovrride : 64; + uint64_t ii_ilapo_regval; + struct { + uint64_t i_io_ovrride:64; } ii_ilapo_fld_s; } ii_ilapo_u_t; - - /************************************************************************ - * * + * * * This register qualifies all the PIO and Graphics writes launched * * from the SHUB towards a widget. * - * * + * * ************************************************************************/ typedef union ii_iowa_u { - uint64_t ii_iowa_regval; - struct { - uint64_t i_w0_oac : 1; - uint64_t i_rsvd_1 : 7; - uint64_t i_wx_oac : 8; - uint64_t i_rsvd : 48; + uint64_t ii_iowa_regval; + struct { + uint64_t i_w0_oac:1; + uint64_t i_rsvd_1:7; + uint64_t i_wx_oac:8; + uint64_t i_rsvd:48; } ii_iowa_fld_s; } ii_iowa_u_t; - /************************************************************************ - * * + * * * Description: This register qualifies all the requests launched * * from a widget towards the Shub. This register is intended to be * * used by software in case of misbehaving widgets. * - * * - * * + * * + * * ************************************************************************/ typedef union ii_iiwa_u { - uint64_t ii_iiwa_regval; - struct { - uint64_t i_w0_iac : 1; - uint64_t i_rsvd_1 : 7; - uint64_t i_wx_iac : 8; - uint64_t i_rsvd : 48; + uint64_t ii_iiwa_regval; + struct { + uint64_t i_w0_iac:1; + uint64_t i_rsvd_1:7; + uint64_t i_wx_iac:8; + uint64_t i_rsvd:48; } ii_iiwa_fld_s; } ii_iiwa_u_t; - - /************************************************************************ - * * + * * * Description: This register qualifies all the operations launched * * from a widget towards the SHub. It allows individual access * * control for up to 8 devices per widget. A device refers to * @@ -401,72 +388,69 @@ typedef union ii_iiwa_u { * The bits in this field are set by writing a 1 to them. Incoming * * replies from Crosstalk are not subject to this access control * * mechanism. * - * * + * * ************************************************************************/ typedef union ii_iidem_u { - uint64_t ii_iidem_regval; - struct { - uint64_t i_w8_dxs : 8; - uint64_t i_w9_dxs : 8; - uint64_t i_wa_dxs : 8; - uint64_t i_wb_dxs : 8; - uint64_t i_wc_dxs : 8; - uint64_t i_wd_dxs : 8; - uint64_t i_we_dxs : 8; - uint64_t i_wf_dxs : 8; + uint64_t ii_iidem_regval; + struct { + uint64_t i_w8_dxs:8; + uint64_t i_w9_dxs:8; + uint64_t i_wa_dxs:8; + uint64_t i_wb_dxs:8; + uint64_t i_wc_dxs:8; + uint64_t i_wd_dxs:8; + uint64_t i_we_dxs:8; + uint64_t i_wf_dxs:8; } ii_iidem_fld_s; } ii_iidem_u_t; - /************************************************************************ - * * + * * * This register contains the various programmable fields necessary * * for controlling and observing the LLP signals. * - * * + * * ************************************************************************/ typedef union ii_ilcsr_u { - uint64_t ii_ilcsr_regval; - struct { - uint64_t i_nullto : 6; - uint64_t i_rsvd_4 : 2; - uint64_t i_wrmrst : 1; - uint64_t i_rsvd_3 : 1; - uint64_t i_llp_en : 1; - uint64_t i_bm8 : 1; - uint64_t i_llp_stat : 2; - uint64_t i_remote_power : 1; - uint64_t i_rsvd_2 : 1; - uint64_t i_maxrtry : 10; - uint64_t i_d_avail_sel : 2; - uint64_t i_rsvd_1 : 4; - uint64_t i_maxbrst : 10; - uint64_t i_rsvd : 22; + uint64_t ii_ilcsr_regval; + struct { + uint64_t i_nullto:6; + uint64_t i_rsvd_4:2; + uint64_t i_wrmrst:1; + uint64_t i_rsvd_3:1; + uint64_t i_llp_en:1; + uint64_t i_bm8:1; + uint64_t i_llp_stat:2; + uint64_t i_remote_power:1; + uint64_t i_rsvd_2:1; + uint64_t i_maxrtry:10; + uint64_t i_d_avail_sel:2; + uint64_t i_rsvd_1:4; + uint64_t i_maxbrst:10; + uint64_t i_rsvd:22; } ii_ilcsr_fld_s; } ii_ilcsr_u_t; - /************************************************************************ - * * + * * * This is simply a status registers that monitors the LLP error * - * rate. * - * * + * rate. * + * * ************************************************************************/ typedef union ii_illr_u { - uint64_t ii_illr_regval; - struct { - uint64_t i_sn_cnt : 16; - uint64_t i_cb_cnt : 16; - uint64_t i_rsvd : 32; + uint64_t ii_illr_regval; + struct { + uint64_t i_sn_cnt:16; + uint64_t i_cb_cnt:16; + uint64_t i_rsvd:32; } ii_illr_fld_s; } ii_illr_u_t; - /************************************************************************ - * * + * * * Description: All II-detected non-BTE error interrupts are * * specified via this register. * * NOTE: The PI interrupt register address is hardcoded in the II. If * @@ -476,107 +460,100 @@ typedef union ii_illr_u { * PI_ID==1, then the II sends the interrupt request to address * * offset 0x01A0_0090 within the local register address space of PI1 * * on the node specified by the NODE field. * - * * + * * ************************************************************************/ typedef union ii_iidsr_u { - uint64_t ii_iidsr_regval; - struct { - uint64_t i_level : 8; - uint64_t i_pi_id : 1; - uint64_t i_node : 11; - uint64_t i_rsvd_3 : 4; - uint64_t i_enable : 1; - uint64_t i_rsvd_2 : 3; - uint64_t i_int_sent : 2; - uint64_t i_rsvd_1 : 2; - uint64_t i_pi0_forward_int : 1; - uint64_t i_pi1_forward_int : 1; - uint64_t i_rsvd : 30; + uint64_t ii_iidsr_regval; + struct { + uint64_t i_level:8; + uint64_t i_pi_id:1; + uint64_t i_node:11; + uint64_t i_rsvd_3:4; + uint64_t i_enable:1; + uint64_t i_rsvd_2:3; + uint64_t i_int_sent:2; + uint64_t i_rsvd_1:2; + uint64_t i_pi0_forward_int:1; + uint64_t i_pi1_forward_int:1; + uint64_t i_rsvd:30; } ii_iidsr_fld_s; } ii_iidsr_u_t; - - /************************************************************************ - * * + * * * There are two instances of this register. This register is used * * for matching up the incoming responses from the graphics widget to * * the processor that initiated the graphics operation. The * * write-responses are converted to graphics credits and returned to * * the processor so that the processor interface can manage the flow * * control. * - * * + * * ************************************************************************/ typedef union ii_igfx0_u { - uint64_t ii_igfx0_regval; - struct { - uint64_t i_w_num : 4; - uint64_t i_pi_id : 1; - uint64_t i_n_num : 12; - uint64_t i_p_num : 1; - uint64_t i_rsvd : 46; + uint64_t ii_igfx0_regval; + struct { + uint64_t i_w_num:4; + uint64_t i_pi_id:1; + uint64_t i_n_num:12; + uint64_t i_p_num:1; + uint64_t i_rsvd:46; } ii_igfx0_fld_s; } ii_igfx0_u_t; - /************************************************************************ - * * + * * * There are two instances of this register. This register is used * * for matching up the incoming responses from the graphics widget to * * the processor that initiated the graphics operation. The * * write-responses are converted to graphics credits and returned to * * the processor so that the processor interface can manage the flow * * control. * - * * + * * ************************************************************************/ typedef union ii_igfx1_u { - uint64_t ii_igfx1_regval; - struct { - uint64_t i_w_num : 4; - uint64_t i_pi_id : 1; - uint64_t i_n_num : 12; - uint64_t i_p_num : 1; - uint64_t i_rsvd : 46; + uint64_t ii_igfx1_regval; + struct { + uint64_t i_w_num:4; + uint64_t i_pi_id:1; + uint64_t i_n_num:12; + uint64_t i_p_num:1; + uint64_t i_rsvd:46; } ii_igfx1_fld_s; } ii_igfx1_u_t; - /************************************************************************ - * * + * * * There are two instances of this registers. These registers are * * used as scratch registers for software use. * - * * + * * ************************************************************************/ typedef union ii_iscr0_u { - uint64_t ii_iscr0_regval; - struct { - uint64_t i_scratch : 64; + uint64_t ii_iscr0_regval; + struct { + uint64_t i_scratch:64; } ii_iscr0_fld_s; } ii_iscr0_u_t; - - /************************************************************************ - * * + * * * There are two instances of this registers. These registers are * * used as scratch registers for software use. * - * * + * * ************************************************************************/ typedef union ii_iscr1_u { - uint64_t ii_iscr1_regval; - struct { - uint64_t i_scratch : 64; + uint64_t ii_iscr1_regval; + struct { + uint64_t i_scratch:64; } ii_iscr1_fld_s; } ii_iscr1_u_t; - /************************************************************************ - * * + * * * Description: There are seven instances of translation table entry * * registers. Each register maps a Shub Big Window to a 48-bit * * address on Crosstalk. * @@ -599,23 +576,22 @@ typedef union ii_iscr1_u { * Crosstalk space addressable by the Shub is thus the lower * * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * * of this space can be accessed. * - * * + * * ************************************************************************/ typedef union ii_itte1_u { - uint64_t ii_itte1_regval; - struct { - uint64_t i_offset : 5; - uint64_t i_rsvd_1 : 3; - uint64_t i_w_num : 4; - uint64_t i_iosp : 1; - uint64_t i_rsvd : 51; + uint64_t ii_itte1_regval; + struct { + uint64_t i_offset:5; + uint64_t i_rsvd_1:3; + uint64_t i_w_num:4; + uint64_t i_iosp:1; + uint64_t i_rsvd:51; } ii_itte1_fld_s; } ii_itte1_u_t; - /************************************************************************ - * * + * * * Description: There are seven instances of translation table entry * * registers. Each register maps a Shub Big Window to a 48-bit * * address on Crosstalk. * @@ -638,23 +614,22 @@ typedef union ii_itte1_u { * Crosstalk space addressable by the Shub is thus the lower * * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * * of this space can be accessed. * - * * + * * ************************************************************************/ typedef union ii_itte2_u { - uint64_t ii_itte2_regval; - struct { - uint64_t i_offset : 5; - uint64_t i_rsvd_1 : 3; - uint64_t i_w_num : 4; - uint64_t i_iosp : 1; - uint64_t i_rsvd : 51; + uint64_t ii_itte2_regval; + struct { + uint64_t i_offset:5; + uint64_t i_rsvd_1:3; + uint64_t i_w_num:4; + uint64_t i_iosp:1; + uint64_t i_rsvd:51; } ii_itte2_fld_s; } ii_itte2_u_t; - /************************************************************************ - * * + * * * Description: There are seven instances of translation table entry * * registers. Each register maps a Shub Big Window to a 48-bit * * address on Crosstalk. * @@ -677,23 +652,22 @@ typedef union ii_itte2_u { * Crosstalk space addressable by the SHub is thus the lower * * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * * of this space can be accessed. * - * * + * * ************************************************************************/ typedef union ii_itte3_u { - uint64_t ii_itte3_regval; - struct { - uint64_t i_offset : 5; - uint64_t i_rsvd_1 : 3; - uint64_t i_w_num : 4; - uint64_t i_iosp : 1; - uint64_t i_rsvd : 51; + uint64_t ii_itte3_regval; + struct { + uint64_t i_offset:5; + uint64_t i_rsvd_1:3; + uint64_t i_w_num:4; + uint64_t i_iosp:1; + uint64_t i_rsvd:51; } ii_itte3_fld_s; } ii_itte3_u_t; - /************************************************************************ - * * + * * * Description: There are seven instances of translation table entry * * registers. Each register maps a SHub Big Window to a 48-bit * * address on Crosstalk. * @@ -716,23 +690,22 @@ typedef union ii_itte3_u { * Crosstalk space addressable by the SHub is thus the lower * * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * * of this space can be accessed. * - * * + * * ************************************************************************/ typedef union ii_itte4_u { - uint64_t ii_itte4_regval; - struct { - uint64_t i_offset : 5; - uint64_t i_rsvd_1 : 3; - uint64_t i_w_num : 4; - uint64_t i_iosp : 1; - uint64_t i_rsvd : 51; + uint64_t ii_itte4_regval; + struct { + uint64_t i_offset:5; + uint64_t i_rsvd_1:3; + uint64_t i_w_num:4; + uint64_t i_iosp:1; + uint64_t i_rsvd:51; } ii_itte4_fld_s; } ii_itte4_u_t; - /************************************************************************ - * * + * * * Description: There are seven instances of translation table entry * * registers. Each register maps a SHub Big Window to a 48-bit * * address on Crosstalk. * @@ -755,23 +728,22 @@ typedef union ii_itte4_u { * Crosstalk space addressable by the Shub is thus the lower * * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * * of this space can be accessed. * - * * + * * ************************************************************************/ typedef union ii_itte5_u { - uint64_t ii_itte5_regval; - struct { - uint64_t i_offset : 5; - uint64_t i_rsvd_1 : 3; - uint64_t i_w_num : 4; - uint64_t i_iosp : 1; - uint64_t i_rsvd : 51; + uint64_t ii_itte5_regval; + struct { + uint64_t i_offset:5; + uint64_t i_rsvd_1:3; + uint64_t i_w_num:4; + uint64_t i_iosp:1; + uint64_t i_rsvd:51; } ii_itte5_fld_s; } ii_itte5_u_t; - /************************************************************************ - * * + * * * Description: There are seven instances of translation table entry * * registers. Each register maps a Shub Big Window to a 48-bit * * address on Crosstalk. * @@ -794,23 +766,22 @@ typedef union ii_itte5_u { * Crosstalk space addressable by the Shub is thus the lower * * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * * of this space can be accessed. * - * * + * * ************************************************************************/ typedef union ii_itte6_u { - uint64_t ii_itte6_regval; - struct { - uint64_t i_offset : 5; - uint64_t i_rsvd_1 : 3; - uint64_t i_w_num : 4; - uint64_t i_iosp : 1; - uint64_t i_rsvd : 51; + uint64_t ii_itte6_regval; + struct { + uint64_t i_offset:5; + uint64_t i_rsvd_1:3; + uint64_t i_w_num:4; + uint64_t i_iosp:1; + uint64_t i_rsvd:51; } ii_itte6_fld_s; } ii_itte6_u_t; - /************************************************************************ - * * + * * * Description: There are seven instances of translation table entry * * registers. Each register maps a Shub Big Window to a 48-bit * * address on Crosstalk. * @@ -833,23 +804,22 @@ typedef union ii_itte6_u { * Crosstalk space addressable by the SHub is thus the lower * * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * * of this space can be accessed. * - * * + * * ************************************************************************/ typedef union ii_itte7_u { - uint64_t ii_itte7_regval; - struct { - uint64_t i_offset : 5; - uint64_t i_rsvd_1 : 3; - uint64_t i_w_num : 4; - uint64_t i_iosp : 1; - uint64_t i_rsvd : 51; + uint64_t ii_itte7_regval; + struct { + uint64_t i_offset:5; + uint64_t i_rsvd_1:3; + uint64_t i_w_num:4; + uint64_t i_iosp:1; + uint64_t i_rsvd:51; } ii_itte7_fld_s; } ii_itte7_u_t; - /************************************************************************ - * * + * * * Description: There are 9 instances of this register, one per * * actual widget in this implementation of SHub and Crossbow. * * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * @@ -868,33 +838,32 @@ typedef union ii_itte7_u { * register; the write will correct the C field and capture its new * * value in the internal register. Even if IECLR[E_PRB_x] is set, the * * SPUR_WR bit will persist if IPRBx hasn't yet been written. * - * . * - * * + * . * + * * ************************************************************************/ typedef union ii_iprb0_u { - uint64_t ii_iprb0_regval; - struct { - uint64_t i_c : 8; - uint64_t i_na : 14; - uint64_t i_rsvd_2 : 2; - uint64_t i_nb : 14; - uint64_t i_rsvd_1 : 2; - uint64_t i_m : 2; - uint64_t i_f : 1; - uint64_t i_of_cnt : 5; - uint64_t i_error : 1; - uint64_t i_rd_to : 1; - uint64_t i_spur_wr : 1; - uint64_t i_spur_rd : 1; - uint64_t i_rsvd : 11; - uint64_t i_mult_err : 1; + uint64_t ii_iprb0_regval; + struct { + uint64_t i_c:8; + uint64_t i_na:14; + uint64_t i_rsvd_2:2; + uint64_t i_nb:14; + uint64_t i_rsvd_1:2; + uint64_t i_m:2; + uint64_t i_f:1; + uint64_t i_of_cnt:5; + uint64_t i_error:1; + uint64_t i_rd_to:1; + uint64_t i_spur_wr:1; + uint64_t i_spur_rd:1; + uint64_t i_rsvd:11; + uint64_t i_mult_err:1; } ii_iprb0_fld_s; } ii_iprb0_u_t; - /************************************************************************ - * * + * * * Description: There are 9 instances of this register, one per * * actual widget in this implementation of SHub and Crossbow. * * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * @@ -913,33 +882,32 @@ typedef union ii_iprb0_u { * register; the write will correct the C field and capture its new * * value in the internal register. Even if IECLR[E_PRB_x] is set, the * * SPUR_WR bit will persist if IPRBx hasn't yet been written. * - * . * - * * + * . * + * * ************************************************************************/ typedef union ii_iprb8_u { - uint64_t ii_iprb8_regval; - struct { - uint64_t i_c : 8; - uint64_t i_na : 14; - uint64_t i_rsvd_2 : 2; - uint64_t i_nb : 14; - uint64_t i_rsvd_1 : 2; - uint64_t i_m : 2; - uint64_t i_f : 1; - uint64_t i_of_cnt : 5; - uint64_t i_error : 1; - uint64_t i_rd_to : 1; - uint64_t i_spur_wr : 1; - uint64_t i_spur_rd : 1; - uint64_t i_rsvd : 11; - uint64_t i_mult_err : 1; + uint64_t ii_iprb8_regval; + struct { + uint64_t i_c:8; + uint64_t i_na:14; + uint64_t i_rsvd_2:2; + uint64_t i_nb:14; + uint64_t i_rsvd_1:2; + uint64_t i_m:2; + uint64_t i_f:1; + uint64_t i_of_cnt:5; + uint64_t i_error:1; + uint64_t i_rd_to:1; + uint64_t i_spur_wr:1; + uint64_t i_spur_rd:1; + uint64_t i_rsvd:11; + uint64_t i_mult_err:1; } ii_iprb8_fld_s; } ii_iprb8_u_t; - /************************************************************************ - * * + * * * Description: There are 9 instances of this register, one per * * actual widget in this implementation of SHub and Crossbow. * * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * @@ -958,33 +926,32 @@ typedef union ii_iprb8_u { * register; the write will correct the C field and capture its new * * value in the internal register. Even if IECLR[E_PRB_x] is set, the * * SPUR_WR bit will persist if IPRBx hasn't yet been written. * - * . * - * * + * . * + * * ************************************************************************/ typedef union ii_iprb9_u { - uint64_t ii_iprb9_regval; - struct { - uint64_t i_c : 8; - uint64_t i_na : 14; - uint64_t i_rsvd_2 : 2; - uint64_t i_nb : 14; - uint64_t i_rsvd_1 : 2; - uint64_t i_m : 2; - uint64_t i_f : 1; - uint64_t i_of_cnt : 5; - uint64_t i_error : 1; - uint64_t i_rd_to : 1; - uint64_t i_spur_wr : 1; - uint64_t i_spur_rd : 1; - uint64_t i_rsvd : 11; - uint64_t i_mult_err : 1; + uint64_t ii_iprb9_regval; + struct { + uint64_t i_c:8; + uint64_t i_na:14; + uint64_t i_rsvd_2:2; + uint64_t i_nb:14; + uint64_t i_rsvd_1:2; + uint64_t i_m:2; + uint64_t i_f:1; + uint64_t i_of_cnt:5; + uint64_t i_error:1; + uint64_t i_rd_to:1; + uint64_t i_spur_wr:1; + uint64_t i_spur_rd:1; + uint64_t i_rsvd:11; + uint64_t i_mult_err:1; } ii_iprb9_fld_s; } ii_iprb9_u_t; - /************************************************************************ - * * + * * * Description: There are 9 instances of this register, one per * * actual widget in this implementation of SHub and Crossbow. * * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * @@ -1003,33 +970,32 @@ typedef union ii_iprb9_u { * register; the write will correct the C field and capture its new * * value in the internal register. Even if IECLR[E_PRB_x] is set, the * * SPUR_WR bit will persist if IPRBx hasn't yet been written. * - * * - * * + * * + * * ************************************************************************/ typedef union ii_iprba_u { - uint64_t ii_iprba_regval; - struct { - uint64_t i_c : 8; - uint64_t i_na : 14; - uint64_t i_rsvd_2 : 2; - uint64_t i_nb : 14; - uint64_t i_rsvd_1 : 2; - uint64_t i_m : 2; - uint64_t i_f : 1; - uint64_t i_of_cnt : 5; - uint64_t i_error : 1; - uint64_t i_rd_to : 1; - uint64_t i_spur_wr : 1; - uint64_t i_spur_rd : 1; - uint64_t i_rsvd : 11; - uint64_t i_mult_err : 1; + uint64_t ii_iprba_regval; + struct { + uint64_t i_c:8; + uint64_t i_na:14; + uint64_t i_rsvd_2:2; + uint64_t i_nb:14; + uint64_t i_rsvd_1:2; + uint64_t i_m:2; + uint64_t i_f:1; + uint64_t i_of_cnt:5; + uint64_t i_error:1; + uint64_t i_rd_to:1; + uint64_t i_spur_wr:1; + uint64_t i_spur_rd:1; + uint64_t i_rsvd:11; + uint64_t i_mult_err:1; } ii_iprba_fld_s; } ii_iprba_u_t; - /************************************************************************ - * * + * * * Description: There are 9 instances of this register, one per * * actual widget in this implementation of SHub and Crossbow. * * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * @@ -1048,33 +1014,32 @@ typedef union ii_iprba_u { * register; the write will correct the C field and capture its new * * value in the internal register. Even if IECLR[E_PRB_x] is set, the * * SPUR_WR bit will persist if IPRBx hasn't yet been written. * - * . * - * * + * . * + * * ************************************************************************/ typedef union ii_iprbb_u { - uint64_t ii_iprbb_regval; - struct { - uint64_t i_c : 8; - uint64_t i_na : 14; - uint64_t i_rsvd_2 : 2; - uint64_t i_nb : 14; - uint64_t i_rsvd_1 : 2; - uint64_t i_m : 2; - uint64_t i_f : 1; - uint64_t i_of_cnt : 5; - uint64_t i_error : 1; - uint64_t i_rd_to : 1; - uint64_t i_spur_wr : 1; - uint64_t i_spur_rd : 1; - uint64_t i_rsvd : 11; - uint64_t i_mult_err : 1; + uint64_t ii_iprbb_regval; + struct { + uint64_t i_c:8; + uint64_t i_na:14; + uint64_t i_rsvd_2:2; + uint64_t i_nb:14; + uint64_t i_rsvd_1:2; + uint64_t i_m:2; + uint64_t i_f:1; + uint64_t i_of_cnt:5; + uint64_t i_error:1; + uint64_t i_rd_to:1; + uint64_t i_spur_wr:1; + uint64_t i_spur_rd:1; + uint64_t i_rsvd:11; + uint64_t i_mult_err:1; } ii_iprbb_fld_s; } ii_iprbb_u_t; - /************************************************************************ - * * + * * * Description: There are 9 instances of this register, one per * * actual widget in this implementation of SHub and Crossbow. * * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * @@ -1093,33 +1058,32 @@ typedef union ii_iprbb_u { * register; the write will correct the C field and capture its new * * value in the internal register. Even if IECLR[E_PRB_x] is set, the * * SPUR_WR bit will persist if IPRBx hasn't yet been written. * - * . * - * * + * . * + * * ************************************************************************/ typedef union ii_iprbc_u { - uint64_t ii_iprbc_regval; - struct { - uint64_t i_c : 8; - uint64_t i_na : 14; - uint64_t i_rsvd_2 : 2; - uint64_t i_nb : 14; - uint64_t i_rsvd_1 : 2; - uint64_t i_m : 2; - uint64_t i_f : 1; - uint64_t i_of_cnt : 5; - uint64_t i_error : 1; - uint64_t i_rd_to : 1; - uint64_t i_spur_wr : 1; - uint64_t i_spur_rd : 1; - uint64_t i_rsvd : 11; - uint64_t i_mult_err : 1; + uint64_t ii_iprbc_regval; + struct { + uint64_t i_c:8; + uint64_t i_na:14; + uint64_t i_rsvd_2:2; + uint64_t i_nb:14; + uint64_t i_rsvd_1:2; + uint64_t i_m:2; + uint64_t i_f:1; + uint64_t i_of_cnt:5; + uint64_t i_error:1; + uint64_t i_rd_to:1; + uint64_t i_spur_wr:1; + uint64_t i_spur_rd:1; + uint64_t i_rsvd:11; + uint64_t i_mult_err:1; } ii_iprbc_fld_s; } ii_iprbc_u_t; - /************************************************************************ - * * + * * * Description: There are 9 instances of this register, one per * * actual widget in this implementation of SHub and Crossbow. * * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * @@ -1138,33 +1102,32 @@ typedef union ii_iprbc_u { * register; the write will correct the C field and capture its new * * value in the internal register. Even if IECLR[E_PRB_x] is set, the * * SPUR_WR bit will persist if IPRBx hasn't yet been written. * - * . * - * * + * . * + * * ************************************************************************/ typedef union ii_iprbd_u { - uint64_t ii_iprbd_regval; - struct { - uint64_t i_c : 8; - uint64_t i_na : 14; - uint64_t i_rsvd_2 : 2; - uint64_t i_nb : 14; - uint64_t i_rsvd_1 : 2; - uint64_t i_m : 2; - uint64_t i_f : 1; - uint64_t i_of_cnt : 5; - uint64_t i_error : 1; - uint64_t i_rd_to : 1; - uint64_t i_spur_wr : 1; - uint64_t i_spur_rd : 1; - uint64_t i_rsvd : 11; - uint64_t i_mult_err : 1; + uint64_t ii_iprbd_regval; + struct { + uint64_t i_c:8; + uint64_t i_na:14; + uint64_t i_rsvd_2:2; + uint64_t i_nb:14; + uint64_t i_rsvd_1:2; + uint64_t i_m:2; + uint64_t i_f:1; + uint64_t i_of_cnt:5; + uint64_t i_error:1; + uint64_t i_rd_to:1; + uint64_t i_spur_wr:1; + uint64_t i_spur_rd:1; + uint64_t i_rsvd:11; + uint64_t i_mult_err:1; } ii_iprbd_fld_s; } ii_iprbd_u_t; - /************************************************************************ - * * + * * * Description: There are 9 instances of this register, one per * * actual widget in this implementation of SHub and Crossbow. * * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * @@ -1183,33 +1146,32 @@ typedef union ii_iprbd_u { * register; the write will correct the C field and capture its new * * value in the internal register. Even if IECLR[E_PRB_x] is set, the * * SPUR_WR bit will persist if IPRBx hasn't yet been written. * - * . * - * * + * . * + * * ************************************************************************/ typedef union ii_iprbe_u { - uint64_t ii_iprbe_regval; - struct { - uint64_t i_c : 8; - uint64_t i_na : 14; - uint64_t i_rsvd_2 : 2; - uint64_t i_nb : 14; - uint64_t i_rsvd_1 : 2; - uint64_t i_m : 2; - uint64_t i_f : 1; - uint64_t i_of_cnt : 5; - uint64_t i_error : 1; - uint64_t i_rd_to : 1; - uint64_t i_spur_wr : 1; - uint64_t i_spur_rd : 1; - uint64_t i_rsvd : 11; - uint64_t i_mult_err : 1; + uint64_t ii_iprbe_regval; + struct { + uint64_t i_c:8; + uint64_t i_na:14; + uint64_t i_rsvd_2:2; + uint64_t i_nb:14; + uint64_t i_rsvd_1:2; + uint64_t i_m:2; + uint64_t i_f:1; + uint64_t i_of_cnt:5; + uint64_t i_error:1; + uint64_t i_rd_to:1; + uint64_t i_spur_wr:1; + uint64_t i_spur_rd:1; + uint64_t i_rsvd:11; + uint64_t i_mult_err:1; } ii_iprbe_fld_s; } ii_iprbe_u_t; - /************************************************************************ - * * + * * * Description: There are 9 instances of this register, one per * * actual widget in this implementation of Shub and Crossbow. * * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * @@ -1228,33 +1190,32 @@ typedef union ii_iprbe_u { * register; the write will correct the C field and capture its new * * value in the internal register. Even if IECLR[E_PRB_x] is set, the * * SPUR_WR bit will persist if IPRBx hasn't yet been written. * - * . * - * * + * . * + * * ************************************************************************/ typedef union ii_iprbf_u { - uint64_t ii_iprbf_regval; - struct { - uint64_t i_c : 8; - uint64_t i_na : 14; - uint64_t i_rsvd_2 : 2; - uint64_t i_nb : 14; - uint64_t i_rsvd_1 : 2; - uint64_t i_m : 2; - uint64_t i_f : 1; - uint64_t i_of_cnt : 5; - uint64_t i_error : 1; - uint64_t i_rd_to : 1; - uint64_t i_spur_wr : 1; - uint64_t i_spur_rd : 1; - uint64_t i_rsvd : 11; - uint64_t i_mult_err : 1; - } ii_iprbe_fld_s; + uint64_t ii_iprbf_regval; + struct { + uint64_t i_c:8; + uint64_t i_na:14; + uint64_t i_rsvd_2:2; + uint64_t i_nb:14; + uint64_t i_rsvd_1:2; + uint64_t i_m:2; + uint64_t i_f:1; + uint64_t i_of_cnt:5; + uint64_t i_error:1; + uint64_t i_rd_to:1; + uint64_t i_spur_wr:1; + uint64_t i_spur_rd:1; + uint64_t i_rsvd:11; + uint64_t i_mult_err:1; + } ii_iprbe_fld_s; } ii_iprbf_u_t; - /************************************************************************ - * * + * * * This register specifies the timeout value to use for monitoring * * Crosstalk credits which are used outbound to Crosstalk. An * * internal counter called the Crosstalk Credit Timeout Counter * @@ -1267,20 +1228,19 @@ typedef union ii_iprbf_u { * Crosstalk Credit Timeout has occurred. The internal counter is not * * readable from software, and stops counting at its maximum value, * * so it cannot cause more than one interrupt. * - * * + * * ************************************************************************/ typedef union ii_ixcc_u { - uint64_t ii_ixcc_regval; - struct { - uint64_t i_time_out : 26; - uint64_t i_rsvd : 38; + uint64_t ii_ixcc_regval; + struct { + uint64_t i_time_out:26; + uint64_t i_rsvd:38; } ii_ixcc_fld_s; } ii_ixcc_u_t; - /************************************************************************ - * * + * * * Description: This register qualifies all the PIO and DMA * * operations launched from widget 0 towards the SHub. In * * addition, it also qualifies accesses by the BTE streams. * @@ -1292,27 +1252,25 @@ typedef union ii_ixcc_u { * the Wx_IAC field. The bits in this field are set by writing a 1 to * * them. Incoming replies from Crosstalk are not subject to this * * access control mechanism. * - * * + * * ************************************************************************/ typedef union ii_imem_u { - uint64_t ii_imem_regval; - struct { - uint64_t i_w0_esd : 1; - uint64_t i_rsvd_3 : 3; - uint64_t i_b0_esd : 1; - uint64_t i_rsvd_2 : 3; - uint64_t i_b1_esd : 1; - uint64_t i_rsvd_1 : 3; - uint64_t i_clr_precise : 1; - uint64_t i_rsvd : 51; + uint64_t ii_imem_regval; + struct { + uint64_t i_w0_esd:1; + uint64_t i_rsvd_3:3; + uint64_t i_b0_esd:1; + uint64_t i_rsvd_2:3; + uint64_t i_b1_esd:1; + uint64_t i_rsvd_1:3; + uint64_t i_clr_precise:1; + uint64_t i_rsvd:51; } ii_imem_fld_s; } ii_imem_u_t; - - /************************************************************************ - * * + * * * Description: This register specifies the timeout value to use for * * monitoring Crosstalk tail flits coming into the Shub in the * * TAIL_TO field. An internal counter associated with this register * @@ -1332,90 +1290,87 @@ typedef union ii_imem_u { * the value in the RRSP_TO field, a Read Response Timeout has * * occurred, and error handling occurs as described in the Error * * Handling section of this document. * - * * + * * ************************************************************************/ typedef union ii_ixtt_u { - uint64_t ii_ixtt_regval; - struct { - uint64_t i_tail_to : 26; - uint64_t i_rsvd_1 : 6; - uint64_t i_rrsp_ps : 23; - uint64_t i_rrsp_to : 5; - uint64_t i_rsvd : 4; + uint64_t ii_ixtt_regval; + struct { + uint64_t i_tail_to:26; + uint64_t i_rsvd_1:6; + uint64_t i_rrsp_ps:23; + uint64_t i_rrsp_to:5; + uint64_t i_rsvd:4; } ii_ixtt_fld_s; } ii_ixtt_u_t; - /************************************************************************ - * * + * * * Writing a 1 to the fields of this register clears the appropriate * * error bits in other areas of SHub. Note that when the * * E_PRB_x bits are used to clear error bits in PRB registers, * * SPUR_RD and SPUR_WR may persist, because they require additional * * action to clear them. See the IPRBx and IXSS Register * * specifications. * - * * + * * ************************************************************************/ typedef union ii_ieclr_u { - uint64_t ii_ieclr_regval; - struct { - uint64_t i_e_prb_0 : 1; - uint64_t i_rsvd : 7; - uint64_t i_e_prb_8 : 1; - uint64_t i_e_prb_9 : 1; - uint64_t i_e_prb_a : 1; - uint64_t i_e_prb_b : 1; - uint64_t i_e_prb_c : 1; - uint64_t i_e_prb_d : 1; - uint64_t i_e_prb_e : 1; - uint64_t i_e_prb_f : 1; - uint64_t i_e_crazy : 1; - uint64_t i_e_bte_0 : 1; - uint64_t i_e_bte_1 : 1; - uint64_t i_reserved_1 : 10; - uint64_t i_spur_rd_hdr : 1; - uint64_t i_cam_intr_to : 1; - uint64_t i_cam_overflow : 1; - uint64_t i_cam_read_miss : 1; - uint64_t i_ioq_rep_underflow : 1; - uint64_t i_ioq_req_underflow : 1; - uint64_t i_ioq_rep_overflow : 1; - uint64_t i_ioq_req_overflow : 1; - uint64_t i_iiq_rep_overflow : 1; - uint64_t i_iiq_req_overflow : 1; - uint64_t i_ii_xn_rep_cred_overflow : 1; - uint64_t i_ii_xn_req_cred_overflow : 1; - uint64_t i_ii_xn_invalid_cmd : 1; - uint64_t i_xn_ii_invalid_cmd : 1; - uint64_t i_reserved_2 : 21; + uint64_t ii_ieclr_regval; + struct { + uint64_t i_e_prb_0:1; + uint64_t i_rsvd:7; + uint64_t i_e_prb_8:1; + uint64_t i_e_prb_9:1; + uint64_t i_e_prb_a:1; + uint64_t i_e_prb_b:1; + uint64_t i_e_prb_c:1; + uint64_t i_e_prb_d:1; + uint64_t i_e_prb_e:1; + uint64_t i_e_prb_f:1; + uint64_t i_e_crazy:1; + uint64_t i_e_bte_0:1; + uint64_t i_e_bte_1:1; + uint64_t i_reserved_1:10; + uint64_t i_spur_rd_hdr:1; + uint64_t i_cam_intr_to:1; + uint64_t i_cam_overflow:1; + uint64_t i_cam_read_miss:1; + uint64_t i_ioq_rep_underflow:1; + uint64_t i_ioq_req_underflow:1; + uint64_t i_ioq_rep_overflow:1; + uint64_t i_ioq_req_overflow:1; + uint64_t i_iiq_rep_overflow:1; + uint64_t i_iiq_req_overflow:1; + uint64_t i_ii_xn_rep_cred_overflow:1; + uint64_t i_ii_xn_req_cred_overflow:1; + uint64_t i_ii_xn_invalid_cmd:1; + uint64_t i_xn_ii_invalid_cmd:1; + uint64_t i_reserved_2:21; } ii_ieclr_fld_s; } ii_ieclr_u_t; - /************************************************************************ - * * + * * * This register controls both BTEs. SOFT_RESET is intended for * * recovery after an error. COUNT controls the total number of CRBs * * that both BTEs (combined) can use, which affects total BTE * * bandwidth. * - * * + * * ************************************************************************/ typedef union ii_ibcr_u { - uint64_t ii_ibcr_regval; - struct { - uint64_t i_count : 4; - uint64_t i_rsvd_1 : 4; - uint64_t i_soft_reset : 1; - uint64_t i_rsvd : 55; + uint64_t ii_ibcr_regval; + struct { + uint64_t i_count:4; + uint64_t i_rsvd_1:4; + uint64_t i_soft_reset:1; + uint64_t i_rsvd:55; } ii_ibcr_fld_s; } ii_ibcr_u_t; - /************************************************************************ - * * + * * * This register contains the header of a spurious read response * * received from Crosstalk. A spurious read response is defined as a * * read response received by II from a widget for which (1) the SIDN * @@ -1440,49 +1395,47 @@ typedef union ii_ibcr_u { * will be set. Any SPUR_RD bits in any other PRB registers indicate * * spurious messages from other widets which were detected after the * * header was captured.. * - * * + * * ************************************************************************/ typedef union ii_ixsm_u { - uint64_t ii_ixsm_regval; - struct { - uint64_t i_byte_en : 32; - uint64_t i_reserved : 1; - uint64_t i_tag : 3; - uint64_t i_alt_pactyp : 4; - uint64_t i_bo : 1; - uint64_t i_error : 1; - uint64_t i_vbpm : 1; - uint64_t i_gbr : 1; - uint64_t i_ds : 2; - uint64_t i_ct : 1; - uint64_t i_tnum : 5; - uint64_t i_pactyp : 4; - uint64_t i_sidn : 4; - uint64_t i_didn : 4; + uint64_t ii_ixsm_regval; + struct { + uint64_t i_byte_en:32; + uint64_t i_reserved:1; + uint64_t i_tag:3; + uint64_t i_alt_pactyp:4; + uint64_t i_bo:1; + uint64_t i_error:1; + uint64_t i_vbpm:1; + uint64_t i_gbr:1; + uint64_t i_ds:2; + uint64_t i_ct:1; + uint64_t i_tnum:5; + uint64_t i_pactyp:4; + uint64_t i_sidn:4; + uint64_t i_didn:4; } ii_ixsm_fld_s; } ii_ixsm_u_t; - /************************************************************************ - * * + * * * This register contains the sideband bits of a spurious read * * response received from Crosstalk. * - * * + * * ************************************************************************/ typedef union ii_ixss_u { - uint64_t ii_ixss_regval; - struct { - uint64_t i_sideband : 8; - uint64_t i_rsvd : 55; - uint64_t i_valid : 1; + uint64_t ii_ixss_regval; + struct { + uint64_t i_sideband:8; + uint64_t i_rsvd:55; + uint64_t i_valid:1; } ii_ixss_fld_s; } ii_ixss_u_t; - /************************************************************************ - * * + * * * This register enables software to access the II LLP's test port. * * Refer to the LLP 2.5 documentation for an explanation of the test * * port. Software can write to this register to program the values * @@ -1490,27 +1443,26 @@ typedef union ii_ixss_u { * TestMask and TestSeed). Similarly, software can read from this * * register to obtain the values of the test port's status outputs * * (TestCBerr, TestValid and TestData). * - * * + * * ************************************************************************/ typedef union ii_ilct_u { - uint64_t ii_ilct_regval; - struct { - uint64_t i_test_seed : 20; - uint64_t i_test_mask : 8; - uint64_t i_test_data : 20; - uint64_t i_test_valid : 1; - uint64_t i_test_cberr : 1; - uint64_t i_test_flit : 3; - uint64_t i_test_clear : 1; - uint64_t i_test_err_capture : 1; - uint64_t i_rsvd : 9; + uint64_t ii_ilct_regval; + struct { + uint64_t i_test_seed:20; + uint64_t i_test_mask:8; + uint64_t i_test_data:20; + uint64_t i_test_valid:1; + uint64_t i_test_cberr:1; + uint64_t i_test_flit:3; + uint64_t i_test_clear:1; + uint64_t i_test_err_capture:1; + uint64_t i_rsvd:9; } ii_ilct_fld_s; } ii_ilct_u_t; - /************************************************************************ - * * + * * * If the II detects an illegal incoming Duplonet packet (request or * * reply) when VALID==0 in the IIEPH1 register, then it saves the * * contents of the packet's header flit in the IIEPH1 and IIEPH2 * @@ -1526,575 +1478,549 @@ typedef union ii_ilct_u { * packet when VALID==1 in the IIEPH1 register, then it merely sets * * the OVERRUN bit to indicate that a subsequent error has happened, * * and does nothing further. * - * * + * * ************************************************************************/ typedef union ii_iieph1_u { - uint64_t ii_iieph1_regval; - struct { - uint64_t i_command : 7; - uint64_t i_rsvd_5 : 1; - uint64_t i_suppl : 14; - uint64_t i_rsvd_4 : 1; - uint64_t i_source : 14; - uint64_t i_rsvd_3 : 1; - uint64_t i_err_type : 4; - uint64_t i_rsvd_2 : 4; - uint64_t i_overrun : 1; - uint64_t i_rsvd_1 : 3; - uint64_t i_valid : 1; - uint64_t i_rsvd : 13; + uint64_t ii_iieph1_regval; + struct { + uint64_t i_command:7; + uint64_t i_rsvd_5:1; + uint64_t i_suppl:14; + uint64_t i_rsvd_4:1; + uint64_t i_source:14; + uint64_t i_rsvd_3:1; + uint64_t i_err_type:4; + uint64_t i_rsvd_2:4; + uint64_t i_overrun:1; + uint64_t i_rsvd_1:3; + uint64_t i_valid:1; + uint64_t i_rsvd:13; } ii_iieph1_fld_s; } ii_iieph1_u_t; - /************************************************************************ - * * + * * * This register holds the Address field from the header flit of an * * incoming erroneous Duplonet packet, along with the tail bit which * * accompanied this header flit. This register is essentially an * * extension of IIEPH1. Two registers were necessary because the 64 * * bits available in only a single register were insufficient to * * capture the entire header flit of an erroneous packet. * - * * + * * ************************************************************************/ typedef union ii_iieph2_u { - uint64_t ii_iieph2_regval; - struct { - uint64_t i_rsvd_0 : 3; - uint64_t i_address : 47; - uint64_t i_rsvd_1 : 10; - uint64_t i_tail : 1; - uint64_t i_rsvd : 3; + uint64_t ii_iieph2_regval; + struct { + uint64_t i_rsvd_0:3; + uint64_t i_address:47; + uint64_t i_rsvd_1:10; + uint64_t i_tail:1; + uint64_t i_rsvd:3; } ii_iieph2_fld_s; } ii_iieph2_u_t; - /******************************/ - - /************************************************************************ - * * + * * * This register's value is a bit vector that guards access from SXBs * * to local registers within the II as well as to external Crosstalk * * widgets * - * * + * * ************************************************************************/ typedef union ii_islapr_u { - uint64_t ii_islapr_regval; - struct { - uint64_t i_region : 64; + uint64_t ii_islapr_regval; + struct { + uint64_t i_region:64; } ii_islapr_fld_s; } ii_islapr_u_t; - /************************************************************************ - * * + * * * A write to this register of the 56-bit value "Pup+Bun" will cause * * the bit in the ISLAPR register corresponding to the region of the * * requestor to be set (access allowed). ( - * * + * * ************************************************************************/ typedef union ii_islapo_u { - uint64_t ii_islapo_regval; - struct { - uint64_t i_io_sbx_ovrride : 56; - uint64_t i_rsvd : 8; + uint64_t ii_islapo_regval; + struct { + uint64_t i_io_sbx_ovrride:56; + uint64_t i_rsvd:8; } ii_islapo_fld_s; } ii_islapo_u_t; /************************************************************************ - * * + * * * Determines how long the wrapper will wait aftr an interrupt is * * initially issued from the II before it times out the outstanding * * interrupt and drops it from the interrupt queue. * - * * + * * ************************************************************************/ typedef union ii_iwi_u { - uint64_t ii_iwi_regval; - struct { - uint64_t i_prescale : 24; - uint64_t i_rsvd : 8; - uint64_t i_timeout : 8; - uint64_t i_rsvd1 : 8; - uint64_t i_intrpt_retry_period : 8; - uint64_t i_rsvd2 : 8; + uint64_t ii_iwi_regval; + struct { + uint64_t i_prescale:24; + uint64_t i_rsvd:8; + uint64_t i_timeout:8; + uint64_t i_rsvd1:8; + uint64_t i_intrpt_retry_period:8; + uint64_t i_rsvd2:8; } ii_iwi_fld_s; } ii_iwi_u_t; /************************************************************************ - * * + * * * Log errors which have occurred in the II wrapper. The errors are * * cleared by writing to the IECLR register. * - * * + * * ************************************************************************/ typedef union ii_iwel_u { - uint64_t ii_iwel_regval; - struct { - uint64_t i_intr_timed_out : 1; - uint64_t i_rsvd : 7; - uint64_t i_cam_overflow : 1; - uint64_t i_cam_read_miss : 1; - uint64_t i_rsvd1 : 2; - uint64_t i_ioq_rep_underflow : 1; - uint64_t i_ioq_req_underflow : 1; - uint64_t i_ioq_rep_overflow : 1; - uint64_t i_ioq_req_overflow : 1; - uint64_t i_iiq_rep_overflow : 1; - uint64_t i_iiq_req_overflow : 1; - uint64_t i_rsvd2 : 6; - uint64_t i_ii_xn_rep_cred_over_under: 1; - uint64_t i_ii_xn_req_cred_over_under: 1; - uint64_t i_rsvd3 : 6; - uint64_t i_ii_xn_invalid_cmd : 1; - uint64_t i_xn_ii_invalid_cmd : 1; - uint64_t i_rsvd4 : 30; + uint64_t ii_iwel_regval; + struct { + uint64_t i_intr_timed_out:1; + uint64_t i_rsvd:7; + uint64_t i_cam_overflow:1; + uint64_t i_cam_read_miss:1; + uint64_t i_rsvd1:2; + uint64_t i_ioq_rep_underflow:1; + uint64_t i_ioq_req_underflow:1; + uint64_t i_ioq_rep_overflow:1; + uint64_t i_ioq_req_overflow:1; + uint64_t i_iiq_rep_overflow:1; + uint64_t i_iiq_req_overflow:1; + uint64_t i_rsvd2:6; + uint64_t i_ii_xn_rep_cred_over_under:1; + uint64_t i_ii_xn_req_cred_over_under:1; + uint64_t i_rsvd3:6; + uint64_t i_ii_xn_invalid_cmd:1; + uint64_t i_xn_ii_invalid_cmd:1; + uint64_t i_rsvd4:30; } ii_iwel_fld_s; } ii_iwel_u_t; /************************************************************************ - * * + * * * Controls the II wrapper. * - * * + * * ************************************************************************/ typedef union ii_iwc_u { - uint64_t ii_iwc_regval; - struct { - uint64_t i_dma_byte_swap : 1; - uint64_t i_rsvd : 3; - uint64_t i_cam_read_lines_reset : 1; - uint64_t i_rsvd1 : 3; - uint64_t i_ii_xn_cred_over_under_log: 1; - uint64_t i_rsvd2 : 19; - uint64_t i_xn_rep_iq_depth : 5; - uint64_t i_rsvd3 : 3; - uint64_t i_xn_req_iq_depth : 5; - uint64_t i_rsvd4 : 3; - uint64_t i_iiq_depth : 6; - uint64_t i_rsvd5 : 12; - uint64_t i_force_rep_cred : 1; - uint64_t i_force_req_cred : 1; + uint64_t ii_iwc_regval; + struct { + uint64_t i_dma_byte_swap:1; + uint64_t i_rsvd:3; + uint64_t i_cam_read_lines_reset:1; + uint64_t i_rsvd1:3; + uint64_t i_ii_xn_cred_over_under_log:1; + uint64_t i_rsvd2:19; + uint64_t i_xn_rep_iq_depth:5; + uint64_t i_rsvd3:3; + uint64_t i_xn_req_iq_depth:5; + uint64_t i_rsvd4:3; + uint64_t i_iiq_depth:6; + uint64_t i_rsvd5:12; + uint64_t i_force_rep_cred:1; + uint64_t i_force_req_cred:1; } ii_iwc_fld_s; } ii_iwc_u_t; /************************************************************************ - * * + * * * Status in the II wrapper. * - * * + * * ************************************************************************/ typedef union ii_iws_u { - uint64_t ii_iws_regval; - struct { - uint64_t i_xn_rep_iq_credits : 5; - uint64_t i_rsvd : 3; - uint64_t i_xn_req_iq_credits : 5; - uint64_t i_rsvd1 : 51; + uint64_t ii_iws_regval; + struct { + uint64_t i_xn_rep_iq_credits:5; + uint64_t i_rsvd:3; + uint64_t i_xn_req_iq_credits:5; + uint64_t i_rsvd1:51; } ii_iws_fld_s; } ii_iws_u_t; /************************************************************************ - * * + * * * Masks errors in the IWEL register. * - * * + * * ************************************************************************/ typedef union ii_iweim_u { - uint64_t ii_iweim_regval; - struct { - uint64_t i_intr_timed_out : 1; - uint64_t i_rsvd : 7; - uint64_t i_cam_overflow : 1; - uint64_t i_cam_read_miss : 1; - uint64_t i_rsvd1 : 2; - uint64_t i_ioq_rep_underflow : 1; - uint64_t i_ioq_req_underflow : 1; - uint64_t i_ioq_rep_overflow : 1; - uint64_t i_ioq_req_overflow : 1; - uint64_t i_iiq_rep_overflow : 1; - uint64_t i_iiq_req_overflow : 1; - uint64_t i_rsvd2 : 6; - uint64_t i_ii_xn_rep_cred_overflow : 1; - uint64_t i_ii_xn_req_cred_overflow : 1; - uint64_t i_rsvd3 : 6; - uint64_t i_ii_xn_invalid_cmd : 1; - uint64_t i_xn_ii_invalid_cmd : 1; - uint64_t i_rsvd4 : 30; + uint64_t ii_iweim_regval; + struct { + uint64_t i_intr_timed_out:1; + uint64_t i_rsvd:7; + uint64_t i_cam_overflow:1; + uint64_t i_cam_read_miss:1; + uint64_t i_rsvd1:2; + uint64_t i_ioq_rep_underflow:1; + uint64_t i_ioq_req_underflow:1; + uint64_t i_ioq_rep_overflow:1; + uint64_t i_ioq_req_overflow:1; + uint64_t i_iiq_rep_overflow:1; + uint64_t i_iiq_req_overflow:1; + uint64_t i_rsvd2:6; + uint64_t i_ii_xn_rep_cred_overflow:1; + uint64_t i_ii_xn_req_cred_overflow:1; + uint64_t i_rsvd3:6; + uint64_t i_ii_xn_invalid_cmd:1; + uint64_t i_xn_ii_invalid_cmd:1; + uint64_t i_rsvd4:30; } ii_iweim_fld_s; } ii_iweim_u_t; - /************************************************************************ - * * + * * * A write to this register causes a particular field in the * * corresponding widget's PRB entry to be adjusted up or down by 1. * * This counter should be used when recovering from error and reset * * conditions. Note that software would be capable of causing * * inadvertent overflow or underflow of these counters. * - * * + * * ************************************************************************/ typedef union ii_ipca_u { - uint64_t ii_ipca_regval; - struct { - uint64_t i_wid : 4; - uint64_t i_adjust : 1; - uint64_t i_rsvd_1 : 3; - uint64_t i_field : 2; - uint64_t i_rsvd : 54; + uint64_t ii_ipca_regval; + struct { + uint64_t i_wid:4; + uint64_t i_adjust:1; + uint64_t i_rsvd_1:3; + uint64_t i_field:2; + uint64_t i_rsvd:54; } ii_ipca_fld_s; } ii_ipca_u_t; - /************************************************************************ - * * + * * * There are 8 instances of this register. This register contains * * the information that the II has to remember once it has launched a * * PIO Read operation. The contents are used to form the correct * * Router Network packet and direct the Crosstalk reply to the * * appropriate processor. * - * * + * * ************************************************************************/ - typedef union ii_iprte0a_u { - uint64_t ii_iprte0a_regval; - struct { - uint64_t i_rsvd_1 : 54; - uint64_t i_widget : 4; - uint64_t i_to_cnt : 5; - uint64_t i_vld : 1; + uint64_t ii_iprte0a_regval; + struct { + uint64_t i_rsvd_1:54; + uint64_t i_widget:4; + uint64_t i_to_cnt:5; + uint64_t i_vld:1; } ii_iprte0a_fld_s; } ii_iprte0a_u_t; - /************************************************************************ - * * + * * * There are 8 instances of this register. This register contains * * the information that the II has to remember once it has launched a * * PIO Read operation. The contents are used to form the correct * * Router Network packet and direct the Crosstalk reply to the * * appropriate processor. * - * * + * * ************************************************************************/ typedef union ii_iprte1a_u { - uint64_t ii_iprte1a_regval; - struct { - uint64_t i_rsvd_1 : 54; - uint64_t i_widget : 4; - uint64_t i_to_cnt : 5; - uint64_t i_vld : 1; + uint64_t ii_iprte1a_regval; + struct { + uint64_t i_rsvd_1:54; + uint64_t i_widget:4; + uint64_t i_to_cnt:5; + uint64_t i_vld:1; } ii_iprte1a_fld_s; } ii_iprte1a_u_t; - /************************************************************************ - * * + * * * There are 8 instances of this register. This register contains * * the information that the II has to remember once it has launched a * * PIO Read operation. The contents are used to form the correct * * Router Network packet and direct the Crosstalk reply to the * * appropriate processor. * - * * + * * ************************************************************************/ typedef union ii_iprte2a_u { - uint64_t ii_iprte2a_regval; - struct { - uint64_t i_rsvd_1 : 54; - uint64_t i_widget : 4; - uint64_t i_to_cnt : 5; - uint64_t i_vld : 1; + uint64_t ii_iprte2a_regval; + struct { + uint64_t i_rsvd_1:54; + uint64_t i_widget:4; + uint64_t i_to_cnt:5; + uint64_t i_vld:1; } ii_iprte2a_fld_s; } ii_iprte2a_u_t; - /************************************************************************ - * * + * * * There are 8 instances of this register. This register contains * * the information that the II has to remember once it has launched a * * PIO Read operation. The contents are used to form the correct * * Router Network packet and direct the Crosstalk reply to the * * appropriate processor. * - * * + * * ************************************************************************/ typedef union ii_iprte3a_u { - uint64_t ii_iprte3a_regval; - struct { - uint64_t i_rsvd_1 : 54; - uint64_t i_widget : 4; - uint64_t i_to_cnt : 5; - uint64_t i_vld : 1; + uint64_t ii_iprte3a_regval; + struct { + uint64_t i_rsvd_1:54; + uint64_t i_widget:4; + uint64_t i_to_cnt:5; + uint64_t i_vld:1; } ii_iprte3a_fld_s; } ii_iprte3a_u_t; - /************************************************************************ - * * + * * * There are 8 instances of this register. This register contains * * the information that the II has to remember once it has launched a * * PIO Read operation. The contents are used to form the correct * * Router Network packet and direct the Crosstalk reply to the * * appropriate processor. * - * * + * * ************************************************************************/ typedef union ii_iprte4a_u { - uint64_t ii_iprte4a_regval; - struct { - uint64_t i_rsvd_1 : 54; - uint64_t i_widget : 4; - uint64_t i_to_cnt : 5; - uint64_t i_vld : 1; + uint64_t ii_iprte4a_regval; + struct { + uint64_t i_rsvd_1:54; + uint64_t i_widget:4; + uint64_t i_to_cnt:5; + uint64_t i_vld:1; } ii_iprte4a_fld_s; } ii_iprte4a_u_t; - /************************************************************************ - * * + * * * There are 8 instances of this register. This register contains * * the information that the II has to remember once it has launched a * * PIO Read operation. The contents are used to form the correct * * Router Network packet and direct the Crosstalk reply to the * * appropriate processor. * - * * + * * ************************************************************************/ typedef union ii_iprte5a_u { - uint64_t ii_iprte5a_regval; - struct { - uint64_t i_rsvd_1 : 54; - uint64_t i_widget : 4; - uint64_t i_to_cnt : 5; - uint64_t i_vld : 1; + uint64_t ii_iprte5a_regval; + struct { + uint64_t i_rsvd_1:54; + uint64_t i_widget:4; + uint64_t i_to_cnt:5; + uint64_t i_vld:1; } ii_iprte5a_fld_s; } ii_iprte5a_u_t; - /************************************************************************ - * * + * * * There are 8 instances of this register. This register contains * * the information that the II has to remember once it has launched a * * PIO Read operation. The contents are used to form the correct * * Router Network packet and direct the Crosstalk reply to the * * appropriate processor. * - * * + * * ************************************************************************/ typedef union ii_iprte6a_u { - uint64_t ii_iprte6a_regval; - struct { - uint64_t i_rsvd_1 : 54; - uint64_t i_widget : 4; - uint64_t i_to_cnt : 5; - uint64_t i_vld : 1; + uint64_t ii_iprte6a_regval; + struct { + uint64_t i_rsvd_1:54; + uint64_t i_widget:4; + uint64_t i_to_cnt:5; + uint64_t i_vld:1; } ii_iprte6a_fld_s; } ii_iprte6a_u_t; - /************************************************************************ - * * + * * * There are 8 instances of this register. This register contains * * the information that the II has to remember once it has launched a * * PIO Read operation. The contents are used to form the correct * * Router Network packet and direct the Crosstalk reply to the * * appropriate processor. * - * * + * * ************************************************************************/ typedef union ii_iprte7a_u { - uint64_t ii_iprte7a_regval; - struct { - uint64_t i_rsvd_1 : 54; - uint64_t i_widget : 4; - uint64_t i_to_cnt : 5; - uint64_t i_vld : 1; - } ii_iprtea7_fld_s; + uint64_t ii_iprte7a_regval; + struct { + uint64_t i_rsvd_1:54; + uint64_t i_widget:4; + uint64_t i_to_cnt:5; + uint64_t i_vld:1; + } ii_iprtea7_fld_s; } ii_iprte7a_u_t; - - /************************************************************************ - * * + * * * There are 8 instances of this register. This register contains * * the information that the II has to remember once it has launched a * * PIO Read operation. The contents are used to form the correct * * Router Network packet and direct the Crosstalk reply to the * * appropriate processor. * - * * + * * ************************************************************************/ - typedef union ii_iprte0b_u { - uint64_t ii_iprte0b_regval; - struct { - uint64_t i_rsvd_1 : 3; - uint64_t i_address : 47; - uint64_t i_init : 3; - uint64_t i_source : 11; + uint64_t ii_iprte0b_regval; + struct { + uint64_t i_rsvd_1:3; + uint64_t i_address:47; + uint64_t i_init:3; + uint64_t i_source:11; } ii_iprte0b_fld_s; } ii_iprte0b_u_t; - /************************************************************************ - * * + * * * There are 8 instances of this register. This register contains * * the information that the II has to remember once it has launched a * * PIO Read operation. The contents are used to form the correct * * Router Network packet and direct the Crosstalk reply to the * * appropriate processor. * - * * + * * ************************************************************************/ typedef union ii_iprte1b_u { - uint64_t ii_iprte1b_regval; - struct { - uint64_t i_rsvd_1 : 3; - uint64_t i_address : 47; - uint64_t i_init : 3; - uint64_t i_source : 11; + uint64_t ii_iprte1b_regval; + struct { + uint64_t i_rsvd_1:3; + uint64_t i_address:47; + uint64_t i_init:3; + uint64_t i_source:11; } ii_iprte1b_fld_s; } ii_iprte1b_u_t; - /************************************************************************ - * * + * * * There are 8 instances of this register. This register contains * * the information that the II has to remember once it has launched a * * PIO Read operation. The contents are used to form the correct * * Router Network packet and direct the Crosstalk reply to the * * appropriate processor. * - * * + * * ************************************************************************/ typedef union ii_iprte2b_u { - uint64_t ii_iprte2b_regval; - struct { - uint64_t i_rsvd_1 : 3; - uint64_t i_address : 47; - uint64_t i_init : 3; - uint64_t i_source : 11; + uint64_t ii_iprte2b_regval; + struct { + uint64_t i_rsvd_1:3; + uint64_t i_address:47; + uint64_t i_init:3; + uint64_t i_source:11; } ii_iprte2b_fld_s; } ii_iprte2b_u_t; - /************************************************************************ - * * + * * * There are 8 instances of this register. This register contains * * the information that the II has to remember once it has launched a * * PIO Read operation. The contents are used to form the correct * * Router Network packet and direct the Crosstalk reply to the * * appropriate processor. * - * * + * * ************************************************************************/ typedef union ii_iprte3b_u { - uint64_t ii_iprte3b_regval; - struct { - uint64_t i_rsvd_1 : 3; - uint64_t i_address : 47; - uint64_t i_init : 3; - uint64_t i_source : 11; + uint64_t ii_iprte3b_regval; + struct { + uint64_t i_rsvd_1:3; + uint64_t i_address:47; + uint64_t i_init:3; + uint64_t i_source:11; } ii_iprte3b_fld_s; } ii_iprte3b_u_t; - /************************************************************************ - * * + * * * There are 8 instances of this register. This register contains * * the information that the II has to remember once it has launched a * * PIO Read operation. The contents are used to form the correct * * Router Network packet and direct the Crosstalk reply to the * * appropriate processor. * - * * + * * ************************************************************************/ typedef union ii_iprte4b_u { - uint64_t ii_iprte4b_regval; - struct { - uint64_t i_rsvd_1 : 3; - uint64_t i_address : 47; - uint64_t i_init : 3; - uint64_t i_source : 11; + uint64_t ii_iprte4b_regval; + struct { + uint64_t i_rsvd_1:3; + uint64_t i_address:47; + uint64_t i_init:3; + uint64_t i_source:11; } ii_iprte4b_fld_s; } ii_iprte4b_u_t; - /************************************************************************ - * * + * * * There are 8 instances of this register. This register contains * * the information that the II has to remember once it has launched a * * PIO Read operation. The contents are used to form the correct * * Router Network packet and direct the Crosstalk reply to the * * appropriate processor. * - * * + * * ************************************************************************/ typedef union ii_iprte5b_u { - uint64_t ii_iprte5b_regval; - struct { - uint64_t i_rsvd_1 : 3; - uint64_t i_address : 47; - uint64_t i_init : 3; - uint64_t i_source : 11; + uint64_t ii_iprte5b_regval; + struct { + uint64_t i_rsvd_1:3; + uint64_t i_address:47; + uint64_t i_init:3; + uint64_t i_source:11; } ii_iprte5b_fld_s; } ii_iprte5b_u_t; - /************************************************************************ - * * + * * * There are 8 instances of this register. This register contains * * the information that the II has to remember once it has launched a * * PIO Read operation. The contents are used to form the correct * * Router Network packet and direct the Crosstalk reply to the * * appropriate processor. * - * * + * * ************************************************************************/ typedef union ii_iprte6b_u { - uint64_t ii_iprte6b_regval; - struct { - uint64_t i_rsvd_1 : 3; - uint64_t i_address : 47; - uint64_t i_init : 3; - uint64_t i_source : 11; + uint64_t ii_iprte6b_regval; + struct { + uint64_t i_rsvd_1:3; + uint64_t i_address:47; + uint64_t i_init:3; + uint64_t i_source:11; } ii_iprte6b_fld_s; } ii_iprte6b_u_t; - /************************************************************************ - * * + * * * There are 8 instances of this register. This register contains * * the information that the II has to remember once it has launched a * * PIO Read operation. The contents are used to form the correct * * Router Network packet and direct the Crosstalk reply to the * * appropriate processor. * - * * + * * ************************************************************************/ typedef union ii_iprte7b_u { - uint64_t ii_iprte7b_regval; - struct { - uint64_t i_rsvd_1 : 3; - uint64_t i_address : 47; - uint64_t i_init : 3; - uint64_t i_source : 11; - } ii_iprte7b_fld_s; + uint64_t ii_iprte7b_regval; + struct { + uint64_t i_rsvd_1:3; + uint64_t i_address:47; + uint64_t i_init:3; + uint64_t i_source:11; + } ii_iprte7b_fld_s; } ii_iprte7b_u_t; - /************************************************************************ - * * + * * * Description: SHub II contains a feature which did not exist in * * the Hub which automatically cleans up after a Read Response * * timeout, including deallocation of the IPRTE and recovery of IBuf * @@ -2108,23 +2034,22 @@ typedef union ii_iprte7b_u { * Note that this register does not affect the contents of the IPRTE * * registers. The Valid bits in those registers have to be * * specifically turned off by software. * - * * + * * ************************************************************************/ typedef union ii_ipdr_u { - uint64_t ii_ipdr_regval; - struct { - uint64_t i_te : 3; - uint64_t i_rsvd_1 : 1; - uint64_t i_pnd : 1; - uint64_t i_init_rpcnt : 1; - uint64_t i_rsvd : 58; + uint64_t ii_ipdr_regval; + struct { + uint64_t i_te:3; + uint64_t i_rsvd_1:1; + uint64_t i_pnd:1; + uint64_t i_init_rpcnt:1; + uint64_t i_rsvd:58; } ii_ipdr_fld_s; } ii_ipdr_u_t; - /************************************************************************ - * * + * * * A write to this register causes a CRB entry to be returned to the * * queue of free CRBs. The entry should have previously been cleared * * (mark bit) via backdoor access to the pertinent CRB entry. This * @@ -2137,21 +2062,20 @@ typedef union ii_ipdr_u { * software clears the mark bit, and finally 4) software writes to * * the ICDR register to return the CRB entry to the list of free CRB * * entries. * - * * + * * ************************************************************************/ typedef union ii_icdr_u { - uint64_t ii_icdr_regval; - struct { - uint64_t i_crb_num : 4; - uint64_t i_pnd : 1; - uint64_t i_rsvd : 59; + uint64_t ii_icdr_regval; + struct { + uint64_t i_crb_num:4; + uint64_t i_pnd:1; + uint64_t i_rsvd:59; } ii_icdr_fld_s; } ii_icdr_u_t; - /************************************************************************ - * * + * * * This register provides debug access to two FIFOs inside of II. * * Both IOQ_MAX* fields of this register contain the instantaneous * * depth (in units of the number of available entries) of the * @@ -2164,130 +2088,124 @@ typedef union ii_icdr_u { * this register is written. If there are any active entries in any * * of these FIFOs when this register is written, the results are * * undefined. * - * * + * * ************************************************************************/ typedef union ii_ifdr_u { - uint64_t ii_ifdr_regval; - struct { - uint64_t i_ioq_max_rq : 7; - uint64_t i_set_ioq_rq : 1; - uint64_t i_ioq_max_rp : 7; - uint64_t i_set_ioq_rp : 1; - uint64_t i_rsvd : 48; + uint64_t ii_ifdr_regval; + struct { + uint64_t i_ioq_max_rq:7; + uint64_t i_set_ioq_rq:1; + uint64_t i_ioq_max_rp:7; + uint64_t i_set_ioq_rp:1; + uint64_t i_rsvd:48; } ii_ifdr_fld_s; } ii_ifdr_u_t; - /************************************************************************ - * * + * * * This register allows the II to become sluggish in removing * * messages from its inbound queue (IIQ). This will cause messages to * * back up in either virtual channel. Disabling the "molasses" mode * * subsequently allows the II to be tested under stress. In the * * sluggish ("Molasses") mode, the localized effects of congestion * * can be observed. * - * * + * * ************************************************************************/ typedef union ii_iiap_u { - uint64_t ii_iiap_regval; - struct { - uint64_t i_rq_mls : 6; - uint64_t i_rsvd_1 : 2; - uint64_t i_rp_mls : 6; - uint64_t i_rsvd : 50; - } ii_iiap_fld_s; + uint64_t ii_iiap_regval; + struct { + uint64_t i_rq_mls:6; + uint64_t i_rsvd_1:2; + uint64_t i_rp_mls:6; + uint64_t i_rsvd:50; + } ii_iiap_fld_s; } ii_iiap_u_t; - /************************************************************************ - * * + * * * This register allows several parameters of CRB operation to be * * set. Note that writing to this register can have catastrophic side * * effects, if the CRB is not quiescent, i.e. if the CRB is * * processing protocol messages when the write occurs. * - * * + * * ************************************************************************/ typedef union ii_icmr_u { - uint64_t ii_icmr_regval; - struct { - uint64_t i_sp_msg : 1; - uint64_t i_rd_hdr : 1; - uint64_t i_rsvd_4 : 2; - uint64_t i_c_cnt : 4; - uint64_t i_rsvd_3 : 4; - uint64_t i_clr_rqpd : 1; - uint64_t i_clr_rppd : 1; - uint64_t i_rsvd_2 : 2; - uint64_t i_fc_cnt : 4; - uint64_t i_crb_vld : 15; - uint64_t i_crb_mark : 15; - uint64_t i_rsvd_1 : 2; - uint64_t i_precise : 1; - uint64_t i_rsvd : 11; + uint64_t ii_icmr_regval; + struct { + uint64_t i_sp_msg:1; + uint64_t i_rd_hdr:1; + uint64_t i_rsvd_4:2; + uint64_t i_c_cnt:4; + uint64_t i_rsvd_3:4; + uint64_t i_clr_rqpd:1; + uint64_t i_clr_rppd:1; + uint64_t i_rsvd_2:2; + uint64_t i_fc_cnt:4; + uint64_t i_crb_vld:15; + uint64_t i_crb_mark:15; + uint64_t i_rsvd_1:2; + uint64_t i_precise:1; + uint64_t i_rsvd:11; } ii_icmr_fld_s; } ii_icmr_u_t; - /************************************************************************ - * * + * * * This register allows control of the table portion of the CRB * * logic via software. Control operations from this register have * * priority over all incoming Crosstalk or BTE requests. * - * * + * * ************************************************************************/ typedef union ii_iccr_u { - uint64_t ii_iccr_regval; - struct { - uint64_t i_crb_num : 4; - uint64_t i_rsvd_1 : 4; - uint64_t i_cmd : 8; - uint64_t i_pending : 1; - uint64_t i_rsvd : 47; + uint64_t ii_iccr_regval; + struct { + uint64_t i_crb_num:4; + uint64_t i_rsvd_1:4; + uint64_t i_cmd:8; + uint64_t i_pending:1; + uint64_t i_rsvd:47; } ii_iccr_fld_s; } ii_iccr_u_t; - /************************************************************************ - * * + * * * This register allows the maximum timeout value to be programmed. * - * * + * * ************************************************************************/ typedef union ii_icto_u { - uint64_t ii_icto_regval; - struct { - uint64_t i_timeout : 8; - uint64_t i_rsvd : 56; + uint64_t ii_icto_regval; + struct { + uint64_t i_timeout:8; + uint64_t i_rsvd:56; } ii_icto_fld_s; } ii_icto_u_t; - /************************************************************************ - * * + * * * This register allows the timeout prescalar to be programmed. An * * internal counter is associated with this register. When the * * internal counter reaches the value of the PRESCALE field, the * * timer registers in all valid CRBs are incremented (CRBx_D[TIMEOUT] * * field). The internal counter resets to zero, and then continues * * counting. * - * * + * * ************************************************************************/ typedef union ii_ictp_u { - uint64_t ii_ictp_regval; - struct { - uint64_t i_prescale : 24; - uint64_t i_rsvd : 40; + uint64_t ii_ictp_regval; + struct { + uint64_t i_prescale:24; + uint64_t i_rsvd:40; } ii_ictp_fld_s; } ii_ictp_u_t; - /************************************************************************ - * * + * * * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are * * used for Crosstalk operations (both cacheline and partial * * operations) or BTE/IO. Because the CRB entries are very wide, five * @@ -2306,243 +2224,234 @@ typedef union ii_ictp_u { * recovering any potential error state from before the reset). * * The following four tables summarize the format for the four * * registers that are used for each ICRB# Entry. * - * * + * * ************************************************************************/ typedef union ii_icrb0_a_u { - uint64_t ii_icrb0_a_regval; - struct { - uint64_t ia_iow : 1; - uint64_t ia_vld : 1; - uint64_t ia_addr : 47; - uint64_t ia_tnum : 5; - uint64_t ia_sidn : 4; - uint64_t ia_rsvd : 6; + uint64_t ii_icrb0_a_regval; + struct { + uint64_t ia_iow:1; + uint64_t ia_vld:1; + uint64_t ia_addr:47; + uint64_t ia_tnum:5; + uint64_t ia_sidn:4; + uint64_t ia_rsvd:6; } ii_icrb0_a_fld_s; } ii_icrb0_a_u_t; - /************************************************************************ - * * + * * * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are * * used for Crosstalk operations (both cacheline and partial * * operations) or BTE/IO. Because the CRB entries are very wide, five * * registers (_A to _E) are required to read and write each entry. * - * * + * * ************************************************************************/ typedef union ii_icrb0_b_u { - uint64_t ii_icrb0_b_regval; - struct { - uint64_t ib_xt_err : 1; - uint64_t ib_mark : 1; - uint64_t ib_ln_uce : 1; - uint64_t ib_errcode : 3; - uint64_t ib_error : 1; - uint64_t ib_stall__bte_1 : 1; - uint64_t ib_stall__bte_0 : 1; - uint64_t ib_stall__intr : 1; - uint64_t ib_stall_ib : 1; - uint64_t ib_intvn : 1; - uint64_t ib_wb : 1; - uint64_t ib_hold : 1; - uint64_t ib_ack : 1; - uint64_t ib_resp : 1; - uint64_t ib_ack_cnt : 11; - uint64_t ib_rsvd : 7; - uint64_t ib_exc : 5; - uint64_t ib_init : 3; - uint64_t ib_imsg : 8; - uint64_t ib_imsgtype : 2; - uint64_t ib_use_old : 1; - uint64_t ib_rsvd_1 : 11; + uint64_t ii_icrb0_b_regval; + struct { + uint64_t ib_xt_err:1; + uint64_t ib_mark:1; + uint64_t ib_ln_uce:1; + uint64_t ib_errcode:3; + uint64_t ib_error:1; + uint64_t ib_stall__bte_1:1; + uint64_t ib_stall__bte_0:1; + uint64_t ib_stall__intr:1; + uint64_t ib_stall_ib:1; + uint64_t ib_intvn:1; + uint64_t ib_wb:1; + uint64_t ib_hold:1; + uint64_t ib_ack:1; + uint64_t ib_resp:1; + uint64_t ib_ack_cnt:11; + uint64_t ib_rsvd:7; + uint64_t ib_exc:5; + uint64_t ib_init:3; + uint64_t ib_imsg:8; + uint64_t ib_imsgtype:2; + uint64_t ib_use_old:1; + uint64_t ib_rsvd_1:11; } ii_icrb0_b_fld_s; } ii_icrb0_b_u_t; - /************************************************************************ - * * + * * * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are * * used for Crosstalk operations (both cacheline and partial * * operations) or BTE/IO. Because the CRB entries are very wide, five * * registers (_A to _E) are required to read and write each entry. * - * * + * * ************************************************************************/ typedef union ii_icrb0_c_u { - uint64_t ii_icrb0_c_regval; - struct { - uint64_t ic_source : 15; - uint64_t ic_size : 2; - uint64_t ic_ct : 1; - uint64_t ic_bte_num : 1; - uint64_t ic_gbr : 1; - uint64_t ic_resprqd : 1; - uint64_t ic_bo : 1; - uint64_t ic_suppl : 15; - uint64_t ic_rsvd : 27; + uint64_t ii_icrb0_c_regval; + struct { + uint64_t ic_source:15; + uint64_t ic_size:2; + uint64_t ic_ct:1; + uint64_t ic_bte_num:1; + uint64_t ic_gbr:1; + uint64_t ic_resprqd:1; + uint64_t ic_bo:1; + uint64_t ic_suppl:15; + uint64_t ic_rsvd:27; } ii_icrb0_c_fld_s; } ii_icrb0_c_u_t; - /************************************************************************ - * * + * * * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are * * used for Crosstalk operations (both cacheline and partial * * operations) or BTE/IO. Because the CRB entries are very wide, five * * registers (_A to _E) are required to read and write each entry. * - * * + * * ************************************************************************/ typedef union ii_icrb0_d_u { - uint64_t ii_icrb0_d_regval; - struct { - uint64_t id_pa_be : 43; - uint64_t id_bte_op : 1; - uint64_t id_pr_psc : 4; - uint64_t id_pr_cnt : 4; - uint64_t id_sleep : 1; - uint64_t id_rsvd : 11; + uint64_t ii_icrb0_d_regval; + struct { + uint64_t id_pa_be:43; + uint64_t id_bte_op:1; + uint64_t id_pr_psc:4; + uint64_t id_pr_cnt:4; + uint64_t id_sleep:1; + uint64_t id_rsvd:11; } ii_icrb0_d_fld_s; } ii_icrb0_d_u_t; - /************************************************************************ - * * + * * * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are * * used for Crosstalk operations (both cacheline and partial * * operations) or BTE/IO. Because the CRB entries are very wide, five * * registers (_A to _E) are required to read and write each entry. * - * * + * * ************************************************************************/ typedef union ii_icrb0_e_u { - uint64_t ii_icrb0_e_regval; - struct { - uint64_t ie_timeout : 8; - uint64_t ie_context : 15; - uint64_t ie_rsvd : 1; - uint64_t ie_tvld : 1; - uint64_t ie_cvld : 1; - uint64_t ie_rsvd_0 : 38; + uint64_t ii_icrb0_e_regval; + struct { + uint64_t ie_timeout:8; + uint64_t ie_context:15; + uint64_t ie_rsvd:1; + uint64_t ie_tvld:1; + uint64_t ie_cvld:1; + uint64_t ie_rsvd_0:38; } ii_icrb0_e_fld_s; } ii_icrb0_e_u_t; - /************************************************************************ - * * + * * * This register contains the lower 64 bits of the header of the * * spurious message captured by II. Valid when the SP_MSG bit in ICMR * * register is set. * - * * + * * ************************************************************************/ typedef union ii_icsml_u { - uint64_t ii_icsml_regval; - struct { - uint64_t i_tt_addr : 47; - uint64_t i_newsuppl_ex : 14; - uint64_t i_reserved : 2; - uint64_t i_overflow : 1; + uint64_t ii_icsml_regval; + struct { + uint64_t i_tt_addr:47; + uint64_t i_newsuppl_ex:14; + uint64_t i_reserved:2; + uint64_t i_overflow:1; } ii_icsml_fld_s; } ii_icsml_u_t; - /************************************************************************ - * * + * * * This register contains the middle 64 bits of the header of the * * spurious message captured by II. Valid when the SP_MSG bit in ICMR * * register is set. * - * * + * * ************************************************************************/ typedef union ii_icsmm_u { - uint64_t ii_icsmm_regval; - struct { - uint64_t i_tt_ack_cnt : 11; - uint64_t i_reserved : 53; + uint64_t ii_icsmm_regval; + struct { + uint64_t i_tt_ack_cnt:11; + uint64_t i_reserved:53; } ii_icsmm_fld_s; } ii_icsmm_u_t; - /************************************************************************ - * * + * * * This register contains the microscopic state, all the inputs to * * the protocol table, captured with the spurious message. Valid when * * the SP_MSG bit in the ICMR register is set. * - * * + * * ************************************************************************/ typedef union ii_icsmh_u { - uint64_t ii_icsmh_regval; - struct { - uint64_t i_tt_vld : 1; - uint64_t i_xerr : 1; - uint64_t i_ft_cwact_o : 1; - uint64_t i_ft_wact_o : 1; - uint64_t i_ft_active_o : 1; - uint64_t i_sync : 1; - uint64_t i_mnusg : 1; - uint64_t i_mnusz : 1; - uint64_t i_plusz : 1; - uint64_t i_plusg : 1; - uint64_t i_tt_exc : 5; - uint64_t i_tt_wb : 1; - uint64_t i_tt_hold : 1; - uint64_t i_tt_ack : 1; - uint64_t i_tt_resp : 1; - uint64_t i_tt_intvn : 1; - uint64_t i_g_stall_bte1 : 1; - uint64_t i_g_stall_bte0 : 1; - uint64_t i_g_stall_il : 1; - uint64_t i_g_stall_ib : 1; - uint64_t i_tt_imsg : 8; - uint64_t i_tt_imsgtype : 2; - uint64_t i_tt_use_old : 1; - uint64_t i_tt_respreqd : 1; - uint64_t i_tt_bte_num : 1; - uint64_t i_cbn : 1; - uint64_t i_match : 1; - uint64_t i_rpcnt_lt_34 : 1; - uint64_t i_rpcnt_ge_34 : 1; - uint64_t i_rpcnt_lt_18 : 1; - uint64_t i_rpcnt_ge_18 : 1; - uint64_t i_rpcnt_lt_2 : 1; - uint64_t i_rpcnt_ge_2 : 1; - uint64_t i_rqcnt_lt_18 : 1; - uint64_t i_rqcnt_ge_18 : 1; - uint64_t i_rqcnt_lt_2 : 1; - uint64_t i_rqcnt_ge_2 : 1; - uint64_t i_tt_device : 7; - uint64_t i_tt_init : 3; - uint64_t i_reserved : 5; + uint64_t ii_icsmh_regval; + struct { + uint64_t i_tt_vld:1; + uint64_t i_xerr:1; + uint64_t i_ft_cwact_o:1; + uint64_t i_ft_wact_o:1; + uint64_t i_ft_active_o:1; + uint64_t i_sync:1; + uint64_t i_mnusg:1; + uint64_t i_mnusz:1; + uint64_t i_plusz:1; + uint64_t i_plusg:1; + uint64_t i_tt_exc:5; + uint64_t i_tt_wb:1; + uint64_t i_tt_hold:1; + uint64_t i_tt_ack:1; + uint64_t i_tt_resp:1; + uint64_t i_tt_intvn:1; + uint64_t i_g_stall_bte1:1; + uint64_t i_g_stall_bte0:1; + uint64_t i_g_stall_il:1; + uint64_t i_g_stall_ib:1; + uint64_t i_tt_imsg:8; + uint64_t i_tt_imsgtype:2; + uint64_t i_tt_use_old:1; + uint64_t i_tt_respreqd:1; + uint64_t i_tt_bte_num:1; + uint64_t i_cbn:1; + uint64_t i_match:1; + uint64_t i_rpcnt_lt_34:1; + uint64_t i_rpcnt_ge_34:1; + uint64_t i_rpcnt_lt_18:1; + uint64_t i_rpcnt_ge_18:1; + uint64_t i_rpcnt_lt_2:1; + uint64_t i_rpcnt_ge_2:1; + uint64_t i_rqcnt_lt_18:1; + uint64_t i_rqcnt_ge_18:1; + uint64_t i_rqcnt_lt_2:1; + uint64_t i_rqcnt_ge_2:1; + uint64_t i_tt_device:7; + uint64_t i_tt_init:3; + uint64_t i_reserved:5; } ii_icsmh_fld_s; } ii_icsmh_u_t; - /************************************************************************ - * * + * * * The Shub DEBUG unit provides a 3-bit selection signal to the * * II core and a 3-bit selection signal to the fsbclk domain in the II * * wrapper. * - * * + * * ************************************************************************/ typedef union ii_idbss_u { - uint64_t ii_idbss_regval; - struct { - uint64_t i_iioclk_core_submenu : 3; - uint64_t i_rsvd : 5; - uint64_t i_fsbclk_wrapper_submenu : 3; - uint64_t i_rsvd_1 : 5; - uint64_t i_iioclk_menu : 5; - uint64_t i_rsvd_2 : 43; + uint64_t ii_idbss_regval; + struct { + uint64_t i_iioclk_core_submenu:3; + uint64_t i_rsvd:5; + uint64_t i_fsbclk_wrapper_submenu:3; + uint64_t i_rsvd_1:5; + uint64_t i_iioclk_menu:5; + uint64_t i_rsvd_2:43; } ii_idbss_fld_s; } ii_idbss_u_t; - /************************************************************************ - * * + * * * Description: This register is used to set up the length for a * * transfer and then to monitor the progress of that transfer. This * * register needs to be initialized before a transfer is started. A * @@ -2553,63 +2462,60 @@ typedef union ii_idbss_u { * transfer completes, hardware will clear the Busy bit. The length * * field will also contain the number of cache lines left to be * * transferred. * - * * + * * ************************************************************************/ typedef union ii_ibls0_u { - uint64_t ii_ibls0_regval; - struct { - uint64_t i_length : 16; - uint64_t i_error : 1; - uint64_t i_rsvd_1 : 3; - uint64_t i_busy : 1; - uint64_t i_rsvd : 43; + uint64_t ii_ibls0_regval; + struct { + uint64_t i_length:16; + uint64_t i_error:1; + uint64_t i_rsvd_1:3; + uint64_t i_busy:1; + uint64_t i_rsvd:43; } ii_ibls0_fld_s; } ii_ibls0_u_t; - /************************************************************************ - * * + * * * This register should be loaded before a transfer is started. The * * address to be loaded in bits 39:0 is the 40-bit TRex+ physical * * address as described in Section 1.3, Figure2 and Figure3. Since * * the bottom 7 bits of the address are always taken to be zero, BTE * * transfers are always cacheline-aligned. * - * * + * * ************************************************************************/ typedef union ii_ibsa0_u { - uint64_t ii_ibsa0_regval; - struct { - uint64_t i_rsvd_1 : 7; - uint64_t i_addr : 42; - uint64_t i_rsvd : 15; + uint64_t ii_ibsa0_regval; + struct { + uint64_t i_rsvd_1:7; + uint64_t i_addr:42; + uint64_t i_rsvd:15; } ii_ibsa0_fld_s; } ii_ibsa0_u_t; - /************************************************************************ - * * + * * * This register should be loaded before a transfer is started. The * * address to be loaded in bits 39:0 is the 40-bit TRex+ physical * * address as described in Section 1.3, Figure2 and Figure3. Since * * the bottom 7 bits of the address are always taken to be zero, BTE * * transfers are always cacheline-aligned. * - * * + * * ************************************************************************/ typedef union ii_ibda0_u { - uint64_t ii_ibda0_regval; - struct { - uint64_t i_rsvd_1 : 7; - uint64_t i_addr : 42; - uint64_t i_rsvd : 15; + uint64_t ii_ibda0_regval; + struct { + uint64_t i_rsvd_1:7; + uint64_t i_addr:42; + uint64_t i_rsvd:15; } ii_ibda0_fld_s; } ii_ibda0_u_t; - /************************************************************************ - * * + * * * Writing to this register sets up the attributes of the transfer * * and initiates the transfer operation. Reading this register has * * the side effect of terminating any transfer in progress. Note: * @@ -2617,61 +2523,58 @@ typedef union ii_ibda0_u { * other BTE. If a BTE stream has to be stopped (due to error * * handling for example), both BTE streams should be stopped and * * their transfers discarded. * - * * + * * ************************************************************************/ typedef union ii_ibct0_u { - uint64_t ii_ibct0_regval; - struct { - uint64_t i_zerofill : 1; - uint64_t i_rsvd_2 : 3; - uint64_t i_notify : 1; - uint64_t i_rsvd_1 : 3; - uint64_t i_poison : 1; - uint64_t i_rsvd : 55; + uint64_t ii_ibct0_regval; + struct { + uint64_t i_zerofill:1; + uint64_t i_rsvd_2:3; + uint64_t i_notify:1; + uint64_t i_rsvd_1:3; + uint64_t i_poison:1; + uint64_t i_rsvd:55; } ii_ibct0_fld_s; } ii_ibct0_u_t; - /************************************************************************ - * * + * * * This register contains the address to which the WINV is sent. * * This address has to be cache line aligned. * - * * + * * ************************************************************************/ typedef union ii_ibna0_u { - uint64_t ii_ibna0_regval; - struct { - uint64_t i_rsvd_1 : 7; - uint64_t i_addr : 42; - uint64_t i_rsvd : 15; + uint64_t ii_ibna0_regval; + struct { + uint64_t i_rsvd_1:7; + uint64_t i_addr:42; + uint64_t i_rsvd:15; } ii_ibna0_fld_s; } ii_ibna0_u_t; - /************************************************************************ - * * + * * * This register contains the programmable level as well as the node * * ID and PI unit of the processor to which the interrupt will be * - * sent. * - * * + * sent. * + * * ************************************************************************/ typedef union ii_ibia0_u { - uint64_t ii_ibia0_regval; - struct { - uint64_t i_rsvd_2 : 1; - uint64_t i_node_id : 11; - uint64_t i_rsvd_1 : 4; - uint64_t i_level : 7; - uint64_t i_rsvd : 41; + uint64_t ii_ibia0_regval; + struct { + uint64_t i_rsvd_2:1; + uint64_t i_node_id:11; + uint64_t i_rsvd_1:4; + uint64_t i_level:7; + uint64_t i_rsvd:41; } ii_ibia0_fld_s; } ii_ibia0_u_t; - /************************************************************************ - * * + * * * Description: This register is used to set up the length for a * * transfer and then to monitor the progress of that transfer. This * * register needs to be initialized before a transfer is started. A * @@ -2682,63 +2585,60 @@ typedef union ii_ibia0_u { * transfer completes, hardware will clear the Busy bit. The length * * field will also contain the number of cache lines left to be * * transferred. * - * * + * * ************************************************************************/ typedef union ii_ibls1_u { - uint64_t ii_ibls1_regval; - struct { - uint64_t i_length : 16; - uint64_t i_error : 1; - uint64_t i_rsvd_1 : 3; - uint64_t i_busy : 1; - uint64_t i_rsvd : 43; + uint64_t ii_ibls1_regval; + struct { + uint64_t i_length:16; + uint64_t i_error:1; + uint64_t i_rsvd_1:3; + uint64_t i_busy:1; + uint64_t i_rsvd:43; } ii_ibls1_fld_s; } ii_ibls1_u_t; - /************************************************************************ - * * + * * * This register should be loaded before a transfer is started. The * * address to be loaded in bits 39:0 is the 40-bit TRex+ physical * * address as described in Section 1.3, Figure2 and Figure3. Since * * the bottom 7 bits of the address are always taken to be zero, BTE * * transfers are always cacheline-aligned. * - * * + * * ************************************************************************/ typedef union ii_ibsa1_u { - uint64_t ii_ibsa1_regval; - struct { - uint64_t i_rsvd_1 : 7; - uint64_t i_addr : 33; - uint64_t i_rsvd : 24; + uint64_t ii_ibsa1_regval; + struct { + uint64_t i_rsvd_1:7; + uint64_t i_addr:33; + uint64_t i_rsvd:24; } ii_ibsa1_fld_s; } ii_ibsa1_u_t; - /************************************************************************ - * * + * * * This register should be loaded before a transfer is started. The * * address to be loaded in bits 39:0 is the 40-bit TRex+ physical * * address as described in Section 1.3, Figure2 and Figure3. Since * * the bottom 7 bits of the address are always taken to be zero, BTE * * transfers are always cacheline-aligned. * - * * + * * ************************************************************************/ typedef union ii_ibda1_u { - uint64_t ii_ibda1_regval; - struct { - uint64_t i_rsvd_1 : 7; - uint64_t i_addr : 33; - uint64_t i_rsvd : 24; + uint64_t ii_ibda1_regval; + struct { + uint64_t i_rsvd_1:7; + uint64_t i_addr:33; + uint64_t i_rsvd:24; } ii_ibda1_fld_s; } ii_ibda1_u_t; - /************************************************************************ - * * + * * * Writing to this register sets up the attributes of the transfer * * and initiates the transfer operation. Reading this register has * * the side effect of terminating any transfer in progress. Note: * @@ -2746,61 +2646,58 @@ typedef union ii_ibda1_u { * other BTE. If a BTE stream has to be stopped (due to error * * handling for example), both BTE streams should be stopped and * * their transfers discarded. * - * * + * * ************************************************************************/ typedef union ii_ibct1_u { - uint64_t ii_ibct1_regval; - struct { - uint64_t i_zerofill : 1; - uint64_t i_rsvd_2 : 3; - uint64_t i_notify : 1; - uint64_t i_rsvd_1 : 3; - uint64_t i_poison : 1; - uint64_t i_rsvd : 55; + uint64_t ii_ibct1_regval; + struct { + uint64_t i_zerofill:1; + uint64_t i_rsvd_2:3; + uint64_t i_notify:1; + uint64_t i_rsvd_1:3; + uint64_t i_poison:1; + uint64_t i_rsvd:55; } ii_ibct1_fld_s; } ii_ibct1_u_t; - /************************************************************************ - * * + * * * This register contains the address to which the WINV is sent. * * This address has to be cache line aligned. * - * * + * * ************************************************************************/ typedef union ii_ibna1_u { - uint64_t ii_ibna1_regval; - struct { - uint64_t i_rsvd_1 : 7; - uint64_t i_addr : 33; - uint64_t i_rsvd : 24; + uint64_t ii_ibna1_regval; + struct { + uint64_t i_rsvd_1:7; + uint64_t i_addr:33; + uint64_t i_rsvd:24; } ii_ibna1_fld_s; } ii_ibna1_u_t; - /************************************************************************ - * * + * * * This register contains the programmable level as well as the node * * ID and PI unit of the processor to which the interrupt will be * - * sent. * - * * + * sent. * + * * ************************************************************************/ typedef union ii_ibia1_u { - uint64_t ii_ibia1_regval; - struct { - uint64_t i_pi_id : 1; - uint64_t i_node_id : 8; - uint64_t i_rsvd_1 : 7; - uint64_t i_level : 7; - uint64_t i_rsvd : 41; + uint64_t ii_ibia1_regval; + struct { + uint64_t i_pi_id:1; + uint64_t i_node_id:8; + uint64_t i_rsvd_1:7; + uint64_t i_level:7; + uint64_t i_rsvd:41; } ii_ibia1_fld_s; } ii_ibia1_u_t; - /************************************************************************ - * * + * * * This register defines the resources that feed information into * * the two performance counters located in the IO Performance * * Profiling Register. There are 17 different quantities that can be * @@ -2811,133 +2708,129 @@ typedef union ii_ibia1_u { * other is available from the other performance counter. Hence, the * * II supports all 17*16=272 possible combinations of quantities to * * measure. * - * * + * * ************************************************************************/ typedef union ii_ipcr_u { - uint64_t ii_ipcr_regval; - struct { - uint64_t i_ippr0_c : 4; - uint64_t i_ippr1_c : 4; - uint64_t i_icct : 8; - uint64_t i_rsvd : 48; + uint64_t ii_ipcr_regval; + struct { + uint64_t i_ippr0_c:4; + uint64_t i_ippr1_c:4; + uint64_t i_icct:8; + uint64_t i_rsvd:48; } ii_ipcr_fld_s; } ii_ipcr_u_t; - /************************************************************************ - * * - * * - * * + * * + * * + * * ************************************************************************/ typedef union ii_ippr_u { - uint64_t ii_ippr_regval; - struct { - uint64_t i_ippr0 : 32; - uint64_t i_ippr1 : 32; + uint64_t ii_ippr_regval; + struct { + uint64_t i_ippr0:32; + uint64_t i_ippr1:32; } ii_ippr_fld_s; } ii_ippr_u_t; - - -/************************************************************************** - * * - * The following defines which were not formed into structures are * - * probably indentical to another register, and the name of the * - * register is provided against each of these registers. This * - * information needs to be checked carefully * - * * - * IIO_ICRB1_A IIO_ICRB0_A * - * IIO_ICRB1_B IIO_ICRB0_B * - * IIO_ICRB1_C IIO_ICRB0_C * - * IIO_ICRB1_D IIO_ICRB0_D * - * IIO_ICRB1_E IIO_ICRB0_E * - * IIO_ICRB2_A IIO_ICRB0_A * - * IIO_ICRB2_B IIO_ICRB0_B * - * IIO_ICRB2_C IIO_ICRB0_C * - * IIO_ICRB2_D IIO_ICRB0_D * - * IIO_ICRB2_E IIO_ICRB0_E * - * IIO_ICRB3_A IIO_ICRB0_A * - * IIO_ICRB3_B IIO_ICRB0_B * - * IIO_ICRB3_C IIO_ICRB0_C * - * IIO_ICRB3_D IIO_ICRB0_D * - * IIO_ICRB3_E IIO_ICRB0_E * - * IIO_ICRB4_A IIO_ICRB0_A * - * IIO_ICRB4_B IIO_ICRB0_B * - * IIO_ICRB4_C IIO_ICRB0_C * - * IIO_ICRB4_D IIO_ICRB0_D * - * IIO_ICRB4_E IIO_ICRB0_E * - * IIO_ICRB5_A IIO_ICRB0_A * - * IIO_ICRB5_B IIO_ICRB0_B * - * IIO_ICRB5_C IIO_ICRB0_C * - * IIO_ICRB5_D IIO_ICRB0_D * - * IIO_ICRB5_E IIO_ICRB0_E * - * IIO_ICRB6_A IIO_ICRB0_A * - * IIO_ICRB6_B IIO_ICRB0_B * - * IIO_ICRB6_C IIO_ICRB0_C * - * IIO_ICRB6_D IIO_ICRB0_D * - * IIO_ICRB6_E IIO_ICRB0_E * - * IIO_ICRB7_A IIO_ICRB0_A * - * IIO_ICRB7_B IIO_ICRB0_B * - * IIO_ICRB7_C IIO_ICRB0_C * - * IIO_ICRB7_D IIO_ICRB0_D * - * IIO_ICRB7_E IIO_ICRB0_E * - * IIO_ICRB8_A IIO_ICRB0_A * - * IIO_ICRB8_B IIO_ICRB0_B * - * IIO_ICRB8_C IIO_ICRB0_C * - * IIO_ICRB8_D IIO_ICRB0_D * - * IIO_ICRB8_E IIO_ICRB0_E * - * IIO_ICRB9_A IIO_ICRB0_A * - * IIO_ICRB9_B IIO_ICRB0_B * - * IIO_ICRB9_C IIO_ICRB0_C * - * IIO_ICRB9_D IIO_ICRB0_D * - * IIO_ICRB9_E IIO_ICRB0_E * - * IIO_ICRBA_A IIO_ICRB0_A * - * IIO_ICRBA_B IIO_ICRB0_B * - * IIO_ICRBA_C IIO_ICRB0_C * - * IIO_ICRBA_D IIO_ICRB0_D * - * IIO_ICRBA_E IIO_ICRB0_E * - * IIO_ICRBB_A IIO_ICRB0_A * - * IIO_ICRBB_B IIO_ICRB0_B * - * IIO_ICRBB_C IIO_ICRB0_C * - * IIO_ICRBB_D IIO_ICRB0_D * - * IIO_ICRBB_E IIO_ICRB0_E * - * IIO_ICRBC_A IIO_ICRB0_A * - * IIO_ICRBC_B IIO_ICRB0_B * - * IIO_ICRBC_C IIO_ICRB0_C * - * IIO_ICRBC_D IIO_ICRB0_D * - * IIO_ICRBC_E IIO_ICRB0_E * - * IIO_ICRBD_A IIO_ICRB0_A * - * IIO_ICRBD_B IIO_ICRB0_B * - * IIO_ICRBD_C IIO_ICRB0_C * - * IIO_ICRBD_D IIO_ICRB0_D * - * IIO_ICRBD_E IIO_ICRB0_E * - * IIO_ICRBE_A IIO_ICRB0_A * - * IIO_ICRBE_B IIO_ICRB0_B * - * IIO_ICRBE_C IIO_ICRB0_C * - * IIO_ICRBE_D IIO_ICRB0_D * - * IIO_ICRBE_E IIO_ICRB0_E * - * * - **************************************************************************/ - +/************************************************************************ + * * + * The following defines which were not formed into structures are * + * probably indentical to another register, and the name of the * + * register is provided against each of these registers. This * + * information needs to be checked carefully * + * * + * IIO_ICRB1_A IIO_ICRB0_A * + * IIO_ICRB1_B IIO_ICRB0_B * + * IIO_ICRB1_C IIO_ICRB0_C * + * IIO_ICRB1_D IIO_ICRB0_D * + * IIO_ICRB1_E IIO_ICRB0_E * + * IIO_ICRB2_A IIO_ICRB0_A * + * IIO_ICRB2_B IIO_ICRB0_B * + * IIO_ICRB2_C IIO_ICRB0_C * + * IIO_ICRB2_D IIO_ICRB0_D * + * IIO_ICRB2_E IIO_ICRB0_E * + * IIO_ICRB3_A IIO_ICRB0_A * + * IIO_ICRB3_B IIO_ICRB0_B * + * IIO_ICRB3_C IIO_ICRB0_C * + * IIO_ICRB3_D IIO_ICRB0_D * + * IIO_ICRB3_E IIO_ICRB0_E * + * IIO_ICRB4_A IIO_ICRB0_A * + * IIO_ICRB4_B IIO_ICRB0_B * + * IIO_ICRB4_C IIO_ICRB0_C * + * IIO_ICRB4_D IIO_ICRB0_D * + * IIO_ICRB4_E IIO_ICRB0_E * + * IIO_ICRB5_A IIO_ICRB0_A * + * IIO_ICRB5_B IIO_ICRB0_B * + * IIO_ICRB5_C IIO_ICRB0_C * + * IIO_ICRB5_D IIO_ICRB0_D * + * IIO_ICRB5_E IIO_ICRB0_E * + * IIO_ICRB6_A IIO_ICRB0_A * + * IIO_ICRB6_B IIO_ICRB0_B * + * IIO_ICRB6_C IIO_ICRB0_C * + * IIO_ICRB6_D IIO_ICRB0_D * + * IIO_ICRB6_E IIO_ICRB0_E * + * IIO_ICRB7_A IIO_ICRB0_A * + * IIO_ICRB7_B IIO_ICRB0_B * + * IIO_ICRB7_C IIO_ICRB0_C * + * IIO_ICRB7_D IIO_ICRB0_D * + * IIO_ICRB7_E IIO_ICRB0_E * + * IIO_ICRB8_A IIO_ICRB0_A * + * IIO_ICRB8_B IIO_ICRB0_B * + * IIO_ICRB8_C IIO_ICRB0_C * + * IIO_ICRB8_D IIO_ICRB0_D * + * IIO_ICRB8_E IIO_ICRB0_E * + * IIO_ICRB9_A IIO_ICRB0_A * + * IIO_ICRB9_B IIO_ICRB0_B * + * IIO_ICRB9_C IIO_ICRB0_C * + * IIO_ICRB9_D IIO_ICRB0_D * + * IIO_ICRB9_E IIO_ICRB0_E * + * IIO_ICRBA_A IIO_ICRB0_A * + * IIO_ICRBA_B IIO_ICRB0_B * + * IIO_ICRBA_C IIO_ICRB0_C * + * IIO_ICRBA_D IIO_ICRB0_D * + * IIO_ICRBA_E IIO_ICRB0_E * + * IIO_ICRBB_A IIO_ICRB0_A * + * IIO_ICRBB_B IIO_ICRB0_B * + * IIO_ICRBB_C IIO_ICRB0_C * + * IIO_ICRBB_D IIO_ICRB0_D * + * IIO_ICRBB_E IIO_ICRB0_E * + * IIO_ICRBC_A IIO_ICRB0_A * + * IIO_ICRBC_B IIO_ICRB0_B * + * IIO_ICRBC_C IIO_ICRB0_C * + * IIO_ICRBC_D IIO_ICRB0_D * + * IIO_ICRBC_E IIO_ICRB0_E * + * IIO_ICRBD_A IIO_ICRB0_A * + * IIO_ICRBD_B IIO_ICRB0_B * + * IIO_ICRBD_C IIO_ICRB0_C * + * IIO_ICRBD_D IIO_ICRB0_D * + * IIO_ICRBD_E IIO_ICRB0_E * + * IIO_ICRBE_A IIO_ICRB0_A * + * IIO_ICRBE_B IIO_ICRB0_B * + * IIO_ICRBE_C IIO_ICRB0_C * + * IIO_ICRBE_D IIO_ICRB0_D * + * IIO_ICRBE_E IIO_ICRB0_E * + * * + ************************************************************************/ /* * Slightly friendlier names for some common registers. */ -#define IIO_WIDGET IIO_WID /* Widget identification */ -#define IIO_WIDGET_STAT IIO_WSTAT /* Widget status register */ -#define IIO_WIDGET_CTRL IIO_WCR /* Widget control register */ -#define IIO_PROTECT IIO_ILAPR /* IO interface protection */ -#define IIO_PROTECT_OVRRD IIO_ILAPO /* IO protect override */ -#define IIO_OUTWIDGET_ACCESS IIO_IOWA /* Outbound widget access */ -#define IIO_INWIDGET_ACCESS IIO_IIWA /* Inbound widget access */ -#define IIO_INDEV_ERR_MASK IIO_IIDEM /* Inbound device error mask */ -#define IIO_LLP_CSR IIO_ILCSR /* LLP control and status */ -#define IIO_LLP_LOG IIO_ILLR /* LLP log */ -#define IIO_XTALKCC_TOUT IIO_IXCC /* Xtalk credit count timeout*/ -#define IIO_XTALKTT_TOUT IIO_IXTT /* Xtalk tail timeout */ -#define IIO_IO_ERR_CLR IIO_IECLR /* IO error clear */ +#define IIO_WIDGET IIO_WID /* Widget identification */ +#define IIO_WIDGET_STAT IIO_WSTAT /* Widget status register */ +#define IIO_WIDGET_CTRL IIO_WCR /* Widget control register */ +#define IIO_PROTECT IIO_ILAPR /* IO interface protection */ +#define IIO_PROTECT_OVRRD IIO_ILAPO /* IO protect override */ +#define IIO_OUTWIDGET_ACCESS IIO_IOWA /* Outbound widget access */ +#define IIO_INWIDGET_ACCESS IIO_IIWA /* Inbound widget access */ +#define IIO_INDEV_ERR_MASK IIO_IIDEM /* Inbound device error mask */ +#define IIO_LLP_CSR IIO_ILCSR /* LLP control and status */ +#define IIO_LLP_LOG IIO_ILLR /* LLP log */ +#define IIO_XTALKCC_TOUT IIO_IXCC /* Xtalk credit count timeout */ +#define IIO_XTALKTT_TOUT IIO_IXTT /* Xtalk tail timeout */ +#define IIO_IO_ERR_CLR IIO_IECLR /* IO error clear */ #define IIO_IGFX_0 IIO_IGFX0 #define IIO_IGFX_1 IIO_IGFX1 #define IIO_IBCT_0 IIO_IBCT0 @@ -2957,12 +2850,12 @@ typedef union ii_ippr_u { #define IIO_PRTE_A(_x) (IIO_IPRTE0_A + (8 * (_x))) #define IIO_PRTE_B(_x) (IIO_IPRTE0_B + (8 * (_x))) #define IIO_NUM_PRTES 8 /* Total number of PRB table entries */ -#define IIO_WIDPRTE_A(x) IIO_PRTE_A(((x) - 8)) /* widget ID to its PRTE num */ -#define IIO_WIDPRTE_B(x) IIO_PRTE_B(((x) - 8)) /* widget ID to its PRTE num */ +#define IIO_WIDPRTE_A(x) IIO_PRTE_A(((x) - 8)) /* widget ID to its PRTE num */ +#define IIO_WIDPRTE_B(x) IIO_PRTE_B(((x) - 8)) /* widget ID to its PRTE num */ -#define IIO_NUM_IPRBS (9) +#define IIO_NUM_IPRBS 9 -#define IIO_LLP_CSR_IS_UP 0x00002000 +#define IIO_LLP_CSR_IS_UP 0x00002000 #define IIO_LLP_CSR_LLP_STAT_MASK 0x00003000 #define IIO_LLP_CSR_LLP_STAT_SHFT 12 @@ -2970,30 +2863,29 @@ typedef union ii_ippr_u { #define IIO_LLP_SN_MAX 0xffff /* in ILLR SN_CNT, Max Sequence Number errors */ /* key to IIO_PROTECT_OVRRD */ -#define IIO_PROTECT_OVRRD_KEY 0x53474972756c6573ull /* "SGIrules" */ +#define IIO_PROTECT_OVRRD_KEY 0x53474972756c6573ull /* "SGIrules" */ /* BTE register names */ -#define IIO_BTE_STAT_0 IIO_IBLS_0 /* Also BTE length/status 0 */ -#define IIO_BTE_SRC_0 IIO_IBSA_0 /* Also BTE source address 0 */ -#define IIO_BTE_DEST_0 IIO_IBDA_0 /* Also BTE dest. address 0 */ -#define IIO_BTE_CTRL_0 IIO_IBCT_0 /* Also BTE control/terminate 0 */ -#define IIO_BTE_NOTIFY_0 IIO_IBNA_0 /* Also BTE notification 0 */ -#define IIO_BTE_INT_0 IIO_IBIA_0 /* Also BTE interrupt 0 */ -#define IIO_BTE_OFF_0 0 /* Base offset from BTE 0 regs. */ -#define IIO_BTE_OFF_1 (IIO_IBLS_1 - IIO_IBLS_0) /* Offset from base to BTE 1 */ +#define IIO_BTE_STAT_0 IIO_IBLS_0 /* Also BTE length/status 0 */ +#define IIO_BTE_SRC_0 IIO_IBSA_0 /* Also BTE source address 0 */ +#define IIO_BTE_DEST_0 IIO_IBDA_0 /* Also BTE dest. address 0 */ +#define IIO_BTE_CTRL_0 IIO_IBCT_0 /* Also BTE control/terminate 0 */ +#define IIO_BTE_NOTIFY_0 IIO_IBNA_0 /* Also BTE notification 0 */ +#define IIO_BTE_INT_0 IIO_IBIA_0 /* Also BTE interrupt 0 */ +#define IIO_BTE_OFF_0 0 /* Base offset from BTE 0 regs. */ +#define IIO_BTE_OFF_1 (IIO_IBLS_1 - IIO_IBLS_0) /* Offset from base to BTE 1 */ /* BTE register offsets from base */ #define BTEOFF_STAT 0 -#define BTEOFF_SRC (IIO_BTE_SRC_0 - IIO_BTE_STAT_0) -#define BTEOFF_DEST (IIO_BTE_DEST_0 - IIO_BTE_STAT_0) -#define BTEOFF_CTRL (IIO_BTE_CTRL_0 - IIO_BTE_STAT_0) -#define BTEOFF_NOTIFY (IIO_BTE_NOTIFY_0 - IIO_BTE_STAT_0) -#define BTEOFF_INT (IIO_BTE_INT_0 - IIO_BTE_STAT_0) - +#define BTEOFF_SRC (IIO_BTE_SRC_0 - IIO_BTE_STAT_0) +#define BTEOFF_DEST (IIO_BTE_DEST_0 - IIO_BTE_STAT_0) +#define BTEOFF_CTRL (IIO_BTE_CTRL_0 - IIO_BTE_STAT_0) +#define BTEOFF_NOTIFY (IIO_BTE_NOTIFY_0 - IIO_BTE_STAT_0) +#define BTEOFF_INT (IIO_BTE_INT_0 - IIO_BTE_STAT_0) /* names used in shub diags */ -#define IIO_BASE_BTE0 IIO_IBLS_0 -#define IIO_BASE_BTE1 IIO_IBLS_1 +#define IIO_BASE_BTE0 IIO_IBLS_0 +#define IIO_BASE_BTE1 IIO_IBLS_1 /* * Macro which takes the widget number, and returns the @@ -3001,10 +2893,9 @@ typedef union ii_ippr_u { * value _x is expected to be a widget number in the range * 0, 8 - 0xF */ -#define IIO_IOPRB(_x) (IIO_IOPRB_0 + ( ( (_x) < HUB_WIDGET_ID_MIN ? \ - (_x) : \ - (_x) - (HUB_WIDGET_ID_MIN-1)) << 3) ) - +#define IIO_IOPRB(_x) (IIO_IOPRB_0 + ( ( (_x) < HUB_WIDGET_ID_MIN ? \ + (_x) : \ + (_x) - (HUB_WIDGET_ID_MIN-1)) << 3) ) /* GFX Flow Control Node/Widget Register */ #define IIO_IGFX_W_NUM_BITS 4 /* size of widget num field */ @@ -3025,7 +2916,6 @@ typedef union ii_ippr_u { (((node) & IIO_IGFX_N_NUM_MASK) << IIO_IGFX_N_NUM_SHIFT) | \ (((cpu) & IIO_IGFX_P_NUM_MASK) << IIO_IGFX_P_NUM_SHIFT)) - /* Scratch registers (all bits available) */ #define IIO_SCRATCH_REG0 IIO_ISCR0 #define IIO_SCRATCH_REG1 IIO_ISCR1 @@ -3046,21 +2936,21 @@ typedef union ii_ippr_u { #define IIO_SCRATCH_BIT1_0 0x0000000000000001UL #define IIO_SCRATCH_BIT1_1 0x0000000000000002UL /* IO Translation Table Entries */ -#define IIO_NUM_ITTES 7 /* ITTEs numbered 0..6 */ - /* Hw manuals number them 1..7! */ +#define IIO_NUM_ITTES 7 /* ITTEs numbered 0..6 */ + /* Hw manuals number them 1..7! */ /* * IIO_IMEM Register fields. */ -#define IIO_IMEM_W0ESD 0x1UL /* Widget 0 shut down due to error */ -#define IIO_IMEM_B0ESD (1UL << 4) /* BTE 0 shut down due to error */ -#define IIO_IMEM_B1ESD (1UL << 8) /* BTE 1 Shut down due to error */ +#define IIO_IMEM_W0ESD 0x1UL /* Widget 0 shut down due to error */ +#define IIO_IMEM_B0ESD (1UL << 4) /* BTE 0 shut down due to error */ +#define IIO_IMEM_B1ESD (1UL << 8) /* BTE 1 Shut down due to error */ /* * As a permanent workaround for a bug in the PI side of the shub, we've * redefined big window 7 as small window 0. XXX does this still apply for SN1?? */ -#define HUB_NUM_BIG_WINDOW (IIO_NUM_ITTES - 1) +#define HUB_NUM_BIG_WINDOW (IIO_NUM_ITTES - 1) /* * Use the top big window as a surrogate for the first small window @@ -3071,11 +2961,11 @@ typedef union ii_ippr_u { /* * CRB manipulation macros - * The CRB macros are slightly complicated, since there are up to - * four registers associated with each CRB entry. + * The CRB macros are slightly complicated, since there are up to + * four registers associated with each CRB entry. */ -#define IIO_NUM_CRBS 15 /* Number of CRBs */ -#define IIO_NUM_PC_CRBS 4 /* Number of partial cache CRBs */ +#define IIO_NUM_CRBS 15 /* Number of CRBs */ +#define IIO_NUM_PC_CRBS 4 /* Number of partial cache CRBs */ #define IIO_ICRB_OFFSET 8 #define IIO_ICRB_0 IIO_ICRB0_A #define IIO_ICRB_ADDR_SHFT 2 /* Shift to get proper address */ @@ -3083,43 +2973,43 @@ typedef union ii_ippr_u { #define IIO_FIRST_PC_ENTRY 12 */ -#define IIO_ICRB_A(_x) ((u64)(IIO_ICRB_0 + (6 * IIO_ICRB_OFFSET * (_x)))) -#define IIO_ICRB_B(_x) ((u64)((char *)IIO_ICRB_A(_x) + 1*IIO_ICRB_OFFSET)) -#define IIO_ICRB_C(_x) ((u64)((char *)IIO_ICRB_A(_x) + 2*IIO_ICRB_OFFSET)) -#define IIO_ICRB_D(_x) ((u64)((char *)IIO_ICRB_A(_x) + 3*IIO_ICRB_OFFSET)) -#define IIO_ICRB_E(_x) ((u64)((char *)IIO_ICRB_A(_x) + 4*IIO_ICRB_OFFSET)) +#define IIO_ICRB_A(_x) ((u64)(IIO_ICRB_0 + (6 * IIO_ICRB_OFFSET * (_x)))) +#define IIO_ICRB_B(_x) ((u64)((char *)IIO_ICRB_A(_x) + 1*IIO_ICRB_OFFSET)) +#define IIO_ICRB_C(_x) ((u64)((char *)IIO_ICRB_A(_x) + 2*IIO_ICRB_OFFSET)) +#define IIO_ICRB_D(_x) ((u64)((char *)IIO_ICRB_A(_x) + 3*IIO_ICRB_OFFSET)) +#define IIO_ICRB_E(_x) ((u64)((char *)IIO_ICRB_A(_x) + 4*IIO_ICRB_OFFSET)) #define TNUM_TO_WIDGET_DEV(_tnum) (_tnum & 0x7) /* * values for "ecode" field */ -#define IIO_ICRB_ECODE_DERR 0 /* Directory error due to IIO access */ -#define IIO_ICRB_ECODE_PERR 1 /* Poison error on IO access */ -#define IIO_ICRB_ECODE_WERR 2 /* Write error by IIO access - * e.g. WINV to a Read only line. */ -#define IIO_ICRB_ECODE_AERR 3 /* Access error caused by IIO access */ -#define IIO_ICRB_ECODE_PWERR 4 /* Error on partial write */ -#define IIO_ICRB_ECODE_PRERR 5 /* Error on partial read */ -#define IIO_ICRB_ECODE_TOUT 6 /* CRB timeout before deallocating */ -#define IIO_ICRB_ECODE_XTERR 7 /* Incoming xtalk pkt had error bit */ +#define IIO_ICRB_ECODE_DERR 0 /* Directory error due to IIO access */ +#define IIO_ICRB_ECODE_PERR 1 /* Poison error on IO access */ +#define IIO_ICRB_ECODE_WERR 2 /* Write error by IIO access + * e.g. WINV to a Read only line. */ +#define IIO_ICRB_ECODE_AERR 3 /* Access error caused by IIO access */ +#define IIO_ICRB_ECODE_PWERR 4 /* Error on partial write */ +#define IIO_ICRB_ECODE_PRERR 5 /* Error on partial read */ +#define IIO_ICRB_ECODE_TOUT 6 /* CRB timeout before deallocating */ +#define IIO_ICRB_ECODE_XTERR 7 /* Incoming xtalk pkt had error bit */ /* * Values for field imsgtype */ -#define IIO_ICRB_IMSGT_XTALK 0 /* Incoming Meessage from Xtalk */ -#define IIO_ICRB_IMSGT_BTE 1 /* Incoming message from BTE */ -#define IIO_ICRB_IMSGT_SN1NET 2 /* Incoming message from SN1 net */ -#define IIO_ICRB_IMSGT_CRB 3 /* Incoming message from CRB ??? */ +#define IIO_ICRB_IMSGT_XTALK 0 /* Incoming Meessage from Xtalk */ +#define IIO_ICRB_IMSGT_BTE 1 /* Incoming message from BTE */ +#define IIO_ICRB_IMSGT_SN1NET 2 /* Incoming message from SN1 net */ +#define IIO_ICRB_IMSGT_CRB 3 /* Incoming message from CRB ??? */ /* * values for field initiator. */ -#define IIO_ICRB_INIT_XTALK 0 /* Message originated in xtalk */ -#define IIO_ICRB_INIT_BTE0 0x1 /* Message originated in BTE 0 */ -#define IIO_ICRB_INIT_SN1NET 0x2 /* Message originated in SN1net */ -#define IIO_ICRB_INIT_CRB 0x3 /* Message originated in CRB ? */ -#define IIO_ICRB_INIT_BTE1 0x5 /* MEssage originated in BTE 1 */ +#define IIO_ICRB_INIT_XTALK 0 /* Message originated in xtalk */ +#define IIO_ICRB_INIT_BTE0 0x1 /* Message originated in BTE 0 */ +#define IIO_ICRB_INIT_SN1NET 0x2 /* Message originated in SN1net */ +#define IIO_ICRB_INIT_CRB 0x3 /* Message originated in CRB ? */ +#define IIO_ICRB_INIT_BTE1 0x5 /* MEssage originated in BTE 1 */ /* * Number of credits Hub widget has while sending req/response to @@ -3127,8 +3017,8 @@ typedef union ii_ippr_u { * Value of 3 is required by Xbow 1.1 * We may be able to increase this to 4 with Xbow 1.2. */ -#define HUBII_XBOW_CREDIT 3 -#define HUBII_XBOW_REV2_CREDIT 4 +#define HUBII_XBOW_CREDIT 3 +#define HUBII_XBOW_REV2_CREDIT 4 /* * Number of credits that xtalk devices should use when communicating @@ -3159,28 +3049,28 @@ typedef union ii_ippr_u { */ #define IIO_ICMR_CRB_VLD_SHFT 20 -#define IIO_ICMR_CRB_VLD_MASK (0x7fffUL << IIO_ICMR_CRB_VLD_SHFT) +#define IIO_ICMR_CRB_VLD_MASK (0x7fffUL << IIO_ICMR_CRB_VLD_SHFT) #define IIO_ICMR_FC_CNT_SHFT 16 -#define IIO_ICMR_FC_CNT_MASK (0xf << IIO_ICMR_FC_CNT_SHFT) +#define IIO_ICMR_FC_CNT_MASK (0xf << IIO_ICMR_FC_CNT_SHFT) #define IIO_ICMR_C_CNT_SHFT 4 -#define IIO_ICMR_C_CNT_MASK (0xf << IIO_ICMR_C_CNT_SHFT) +#define IIO_ICMR_C_CNT_MASK (0xf << IIO_ICMR_C_CNT_SHFT) -#define IIO_ICMR_PRECISE (1UL << 52) -#define IIO_ICMR_CLR_RPPD (1UL << 13) -#define IIO_ICMR_CLR_RQPD (1UL << 12) +#define IIO_ICMR_PRECISE (1UL << 52) +#define IIO_ICMR_CLR_RPPD (1UL << 13) +#define IIO_ICMR_CLR_RQPD (1UL << 12) /* * IIO PIO Deallocation register field masks : (IIO_IPDR) XXX present but not needed in bedrock? See the manual. */ -#define IIO_IPDR_PND (1 << 4) +#define IIO_IPDR_PND (1 << 4) /* * IIO CRB deallocation register field masks: (IIO_ICDR) */ -#define IIO_ICDR_PND (1 << 4) +#define IIO_ICDR_PND (1 << 4) /* * IO BTE Length/Status (IIO_IBLS) register bit field definitions @@ -3223,35 +3113,35 @@ typedef union ii_ippr_u { /* * IO Error Clear register bit field definitions */ -#define IECLR_PI1_FWD_INT (1UL << 31) /* clear PI1_FORWARD_INT in iidsr */ -#define IECLR_PI0_FWD_INT (1UL << 30) /* clear PI0_FORWARD_INT in iidsr */ -#define IECLR_SPUR_RD_HDR (1UL << 29) /* clear valid bit in ixss reg */ -#define IECLR_BTE1 (1UL << 18) /* clear bte error 1 */ -#define IECLR_BTE0 (1UL << 17) /* clear bte error 0 */ -#define IECLR_CRAZY (1UL << 16) /* clear crazy bit in wstat reg */ -#define IECLR_PRB_F (1UL << 15) /* clear err bit in PRB_F reg */ -#define IECLR_PRB_E (1UL << 14) /* clear err bit in PRB_E reg */ -#define IECLR_PRB_D (1UL << 13) /* clear err bit in PRB_D reg */ -#define IECLR_PRB_C (1UL << 12) /* clear err bit in PRB_C reg */ -#define IECLR_PRB_B (1UL << 11) /* clear err bit in PRB_B reg */ -#define IECLR_PRB_A (1UL << 10) /* clear err bit in PRB_A reg */ -#define IECLR_PRB_9 (1UL << 9) /* clear err bit in PRB_9 reg */ -#define IECLR_PRB_8 (1UL << 8) /* clear err bit in PRB_8 reg */ -#define IECLR_PRB_0 (1UL << 0) /* clear err bit in PRB_0 reg */ +#define IECLR_PI1_FWD_INT (1UL << 31) /* clear PI1_FORWARD_INT in iidsr */ +#define IECLR_PI0_FWD_INT (1UL << 30) /* clear PI0_FORWARD_INT in iidsr */ +#define IECLR_SPUR_RD_HDR (1UL << 29) /* clear valid bit in ixss reg */ +#define IECLR_BTE1 (1UL << 18) /* clear bte error 1 */ +#define IECLR_BTE0 (1UL << 17) /* clear bte error 0 */ +#define IECLR_CRAZY (1UL << 16) /* clear crazy bit in wstat reg */ +#define IECLR_PRB_F (1UL << 15) /* clear err bit in PRB_F reg */ +#define IECLR_PRB_E (1UL << 14) /* clear err bit in PRB_E reg */ +#define IECLR_PRB_D (1UL << 13) /* clear err bit in PRB_D reg */ +#define IECLR_PRB_C (1UL << 12) /* clear err bit in PRB_C reg */ +#define IECLR_PRB_B (1UL << 11) /* clear err bit in PRB_B reg */ +#define IECLR_PRB_A (1UL << 10) /* clear err bit in PRB_A reg */ +#define IECLR_PRB_9 (1UL << 9) /* clear err bit in PRB_9 reg */ +#define IECLR_PRB_8 (1UL << 8) /* clear err bit in PRB_8 reg */ +#define IECLR_PRB_0 (1UL << 0) /* clear err bit in PRB_0 reg */ /* * IIO CRB control register Fields: IIO_ICCR */ -#define IIO_ICCR_PENDING (0x10000) -#define IIO_ICCR_CMD_MASK (0xFF) -#define IIO_ICCR_CMD_SHFT (7) -#define IIO_ICCR_CMD_NOP (0x0) /* No Op */ -#define IIO_ICCR_CMD_WAKE (0x100) /* Reactivate CRB entry and process */ -#define IIO_ICCR_CMD_TIMEOUT (0x200) /* Make CRB timeout & mark invalid */ -#define IIO_ICCR_CMD_EJECT (0x400) /* Contents of entry written to memory +#define IIO_ICCR_PENDING 0x10000 +#define IIO_ICCR_CMD_MASK 0xFF +#define IIO_ICCR_CMD_SHFT 7 +#define IIO_ICCR_CMD_NOP 0x0 /* No Op */ +#define IIO_ICCR_CMD_WAKE 0x100 /* Reactivate CRB entry and process */ +#define IIO_ICCR_CMD_TIMEOUT 0x200 /* Make CRB timeout & mark invalid */ +#define IIO_ICCR_CMD_EJECT 0x400 /* Contents of entry written to memory * via a WB */ -#define IIO_ICCR_CMD_FLUSH (0x800) +#define IIO_ICCR_CMD_FLUSH 0x800 /* * @@ -3283,8 +3173,8 @@ typedef union ii_ippr_u { * Easy access macros for CRBs, all 5 registers (A-E) */ typedef ii_icrb0_a_u_t icrba_t; -#define a_sidn ii_icrb0_a_fld_s.ia_sidn -#define a_tnum ii_icrb0_a_fld_s.ia_tnum +#define a_sidn ii_icrb0_a_fld_s.ia_sidn +#define a_tnum ii_icrb0_a_fld_s.ia_tnum #define a_addr ii_icrb0_a_fld_s.ia_addr #define a_valid ii_icrb0_a_fld_s.ia_vld #define a_iow ii_icrb0_a_fld_s.ia_iow @@ -3324,14 +3214,13 @@ typedef ii_icrb0_c_u_t icrbc_t; #define c_source ii_icrb0_c_fld_s.ic_source #define c_regvalue ii_icrb0_c_regval - typedef ii_icrb0_d_u_t icrbd_t; #define d_sleep ii_icrb0_d_fld_s.id_sleep #define d_pricnt ii_icrb0_d_fld_s.id_pr_cnt #define d_pripsc ii_icrb0_d_fld_s.id_pr_psc #define d_bteop ii_icrb0_d_fld_s.id_bte_op -#define d_bteaddr ii_icrb0_d_fld_s.id_pa_be /* ic_pa_be fld has 2 names*/ -#define d_benable ii_icrb0_d_fld_s.id_pa_be /* ic_pa_be fld has 2 names*/ +#define d_bteaddr ii_icrb0_d_fld_s.id_pa_be /* ic_pa_be fld has 2 names */ +#define d_benable ii_icrb0_d_fld_s.id_pa_be /* ic_pa_be fld has 2 names */ #define d_regvalue ii_icrb0_d_regval typedef ii_icrb0_e_u_t icrbe_t; @@ -3341,7 +3230,6 @@ typedef ii_icrb0_e_u_t icrbe_t; #define icrbe_timeout ii_icrb0_e_fld_s.ie_timeout #define e_regvalue ii_icrb0_e_regval - /* Number of widgets supported by shub */ #define HUB_NUM_WIDGET 9 #define HUB_WIDGET_ID_MIN 0x8 @@ -3367,27 +3255,27 @@ typedef ii_icrb0_e_u_t icrbe_t; #define LNK_STAT_WORKING 0x2 /* LLP is working */ -#define IIO_WSTAT_ECRAZY (1ULL << 32) /* Hub gone crazy */ -#define IIO_WSTAT_TXRETRY (1ULL << 9) /* Hub Tx Retry timeout */ -#define IIO_WSTAT_TXRETRY_MASK (0x7F) /* should be 0xFF?? */ -#define IIO_WSTAT_TXRETRY_SHFT (16) -#define IIO_WSTAT_TXRETRY_CNT(w) (((w) >> IIO_WSTAT_TXRETRY_SHFT) & \ - IIO_WSTAT_TXRETRY_MASK) +#define IIO_WSTAT_ECRAZY (1ULL << 32) /* Hub gone crazy */ +#define IIO_WSTAT_TXRETRY (1ULL << 9) /* Hub Tx Retry timeout */ +#define IIO_WSTAT_TXRETRY_MASK 0x7F /* should be 0xFF?? */ +#define IIO_WSTAT_TXRETRY_SHFT 16 +#define IIO_WSTAT_TXRETRY_CNT(w) (((w) >> IIO_WSTAT_TXRETRY_SHFT) & \ + IIO_WSTAT_TXRETRY_MASK) /* Number of II perf. counters we can multiplex at once */ #define IO_PERF_SETS 32 /* Bit for the widget in inbound access register */ -#define IIO_IIWA_WIDGET(_w) ((uint64_t)(1ULL << _w)) +#define IIO_IIWA_WIDGET(_w) ((uint64_t)(1ULL << _w)) /* Bit for the widget in outbound access register */ -#define IIO_IOWA_WIDGET(_w) ((uint64_t)(1ULL << _w)) +#define IIO_IOWA_WIDGET(_w) ((uint64_t)(1ULL << _w)) /* NOTE: The following define assumes that we are going to get * widget numbers from 8 thru F and the device numbers within * widget from 0 thru 7. */ -#define IIO_IIDEM_WIDGETDEV_MASK(w, d) ((uint64_t)(1ULL << (8 * ((w) - 8) + (d)))) +#define IIO_IIDEM_WIDGETDEV_MASK(w, d) ((uint64_t)(1ULL << (8 * ((w) - 8) + (d)))) /* IO Interrupt Destination Register */ #define IIO_IIDSR_SENT_SHIFT 28 @@ -3402,11 +3290,11 @@ typedef ii_icrb0_e_u_t icrbe_t; #define IIO_IIDSR_LVL_MASK 0x000000ff /* Xtalk timeout threshhold register (IIO_IXTT) */ -#define IXTT_RRSP_TO_SHFT 55 /* read response timeout */ +#define IXTT_RRSP_TO_SHFT 55 /* read response timeout */ #define IXTT_RRSP_TO_MASK (0x1FULL << IXTT_RRSP_TO_SHFT) -#define IXTT_RRSP_PS_SHFT 32 /* read responsed TO prescalar */ +#define IXTT_RRSP_PS_SHFT 32 /* read responsed TO prescalar */ #define IXTT_RRSP_PS_MASK (0x7FFFFFULL << IXTT_RRSP_PS_SHFT) -#define IXTT_TAIL_TO_SHFT 0 /* tail timeout counter threshold */ +#define IXTT_TAIL_TO_SHFT 0 /* tail timeout counter threshold */ #define IXTT_TAIL_TO_MASK (0x3FFFFFFULL << IXTT_TAIL_TO_SHFT) /* @@ -3414,17 +3302,17 @@ typedef ii_icrb0_e_u_t icrbe_t; */ typedef union hubii_wcr_u { - uint64_t wcr_reg_value; - struct { - uint64_t wcr_widget_id: 4, /* LLP crossbar credit */ - wcr_tag_mode: 1, /* Tag mode */ - wcr_rsvd1: 8, /* Reserved */ - wcr_xbar_crd: 3, /* LLP crossbar credit */ - wcr_f_bad_pkt: 1, /* Force bad llp pkt enable */ - wcr_dir_con: 1, /* widget direct connect */ - wcr_e_thresh: 5, /* elasticity threshold */ - wcr_rsvd: 41; /* unused */ - } wcr_fields_s; + uint64_t wcr_reg_value; + struct { + uint64_t wcr_widget_id:4, /* LLP crossbar credit */ + wcr_tag_mode:1, /* Tag mode */ + wcr_rsvd1:8, /* Reserved */ + wcr_xbar_crd:3, /* LLP crossbar credit */ + wcr_f_bad_pkt:1, /* Force bad llp pkt enable */ + wcr_dir_con:1, /* widget direct connect */ + wcr_e_thresh:5, /* elasticity threshold */ + wcr_rsvd:41; /* unused */ + } wcr_fields_s; } hubii_wcr_t; #define iwcr_dir_con wcr_fields_s.wcr_dir_con @@ -3436,41 +3324,35 @@ performance registers */ performed */ typedef union io_perf_sel { - uint64_t perf_sel_reg; - struct { - uint64_t perf_ippr0 : 4, - perf_ippr1 : 4, - perf_icct : 8, - perf_rsvd : 48; - } perf_sel_bits; + uint64_t perf_sel_reg; + struct { + uint64_t perf_ippr0:4, perf_ippr1:4, perf_icct:8, perf_rsvd:48; + } perf_sel_bits; } io_perf_sel_t; /* io_perf_cnt is to extract the count from the shub registers. Due to hardware problems there is only one counter, not two. */ typedef union io_perf_cnt { - uint64_t perf_cnt; - struct { - uint64_t perf_cnt : 20, - perf_rsvd2 : 12, - perf_rsvd1 : 32; - } perf_cnt_bits; + uint64_t perf_cnt; + struct { + uint64_t perf_cnt:20, perf_rsvd2:12, perf_rsvd1:32; + } perf_cnt_bits; } io_perf_cnt_t; typedef union iprte_a { - uint64_t entry; - struct { - uint64_t i_rsvd_1 : 3; - uint64_t i_addr : 38; - uint64_t i_init : 3; - uint64_t i_source : 8; - uint64_t i_rsvd : 2; - uint64_t i_widget : 4; - uint64_t i_to_cnt : 5; - uint64_t i_vld : 1; + uint64_t entry; + struct { + uint64_t i_rsvd_1:3; + uint64_t i_addr:38; + uint64_t i_init:3; + uint64_t i_source:8; + uint64_t i_rsvd:2; + uint64_t i_widget:4; + uint64_t i_to_cnt:5; + uint64_t i_vld:1; } iprte_fields; } iprte_a_t; -#endif /* _ASM_IA64_SN_SHUBIO_H */ - +#endif /* _ASM_IA64_SN_SHUBIO_H */ diff --git a/include/asm-ia64/sn/sn_cpuid.h b/include/asm-ia64/sn/sn_cpuid.h index 685435af170d..20b300187669 100644 --- a/include/asm-ia64/sn/sn_cpuid.h +++ b/include/asm-ia64/sn/sn_cpuid.h @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 2000-2005 Silicon Graphics, Inc. All rights reserved. */ @@ -92,24 +92,24 @@ * NOTE: on non-MP systems, only cpuid 0 exists */ -extern short physical_node_map[]; /* indexed by nasid to get cnode */ +extern short physical_node_map[]; /* indexed by nasid to get cnode */ /* * Macros for retrieving info about current cpu */ -#define get_nasid() (nodepda->phys_cpuid[smp_processor_id()].nasid) -#define get_subnode() (nodepda->phys_cpuid[smp_processor_id()].subnode) -#define get_slice() (nodepda->phys_cpuid[smp_processor_id()].slice) -#define get_cnode() (nodepda->phys_cpuid[smp_processor_id()].cnode) -#define get_sapicid() ((ia64_getreg(_IA64_REG_CR_LID) >> 16) & 0xffff) +#define get_nasid() (sn_nodepda->phys_cpuid[smp_processor_id()].nasid) +#define get_subnode() (sn_nodepda->phys_cpuid[smp_processor_id()].subnode) +#define get_slice() (sn_nodepda->phys_cpuid[smp_processor_id()].slice) +#define get_cnode() (sn_nodepda->phys_cpuid[smp_processor_id()].cnode) +#define get_sapicid() ((ia64_getreg(_IA64_REG_CR_LID) >> 16) & 0xffff) /* * Macros for retrieving info about an arbitrary cpu * cpuid - logical cpu id */ -#define cpuid_to_nasid(cpuid) (nodepda->phys_cpuid[cpuid].nasid) -#define cpuid_to_subnode(cpuid) (nodepda->phys_cpuid[cpuid].subnode) -#define cpuid_to_slice(cpuid) (nodepda->phys_cpuid[cpuid].slice) +#define cpuid_to_nasid(cpuid) (sn_nodepda->phys_cpuid[cpuid].nasid) +#define cpuid_to_subnode(cpuid) (sn_nodepda->phys_cpuid[cpuid].subnode) +#define cpuid_to_slice(cpuid) (sn_nodepda->phys_cpuid[cpuid].slice) #define cpuid_to_cnodeid(cpuid) (physical_node_map[cpuid_to_nasid(cpuid)]) @@ -123,11 +123,8 @@ extern int nasid_slice_to_cpuid(int, int); /* * cnodeid_to_nasid - convert a cnodeid to a NASID - * Macro relies on pg_data for a node being on the node itself. - * Just extract the NASID from the pointer. - * */ -#define cnodeid_to_nasid(cnodeid) pda->cnodeid_to_nasid_table[cnodeid] +#define cnodeid_to_nasid(cnodeid) (sn_cnodeid_to_nasid[cnodeid]) /* * nasid_to_cnodeid - convert a NASID to a cnodeid diff --git a/include/asm-ia64/sn/sn_fru.h b/include/asm-ia64/sn/sn_fru.h deleted file mode 100644 index 8c21ac3f0156..000000000000 --- a/include/asm-ia64/sn/sn_fru.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992-1997,1999-2004 Silicon Graphics, Inc. All rights reserved. - */ -#ifndef _ASM_IA64_SN_SN_FRU_H -#define _ASM_IA64_SN_SN_FRU_H - -#define MAX_DIMMS 8 /* max # of dimm banks */ -#define MAX_PCIDEV 8 /* max # of pci devices on a pci bus */ - -typedef unsigned char confidence_t; - -typedef struct kf_mem_s { - confidence_t km_confidence; /* confidence level that the memory is bad - * is this necessary ? - */ - confidence_t km_dimm[MAX_DIMMS]; - /* confidence level that dimm[i] is bad - *I think this is the right number - */ - -} kf_mem_t; - -typedef struct kf_cpu_s { - confidence_t kc_confidence; /* confidence level that cpu is bad */ - confidence_t kc_icache; /* confidence level that instr. cache is bad */ - confidence_t kc_dcache; /* confidence level that data cache is bad */ - confidence_t kc_scache; /* confidence level that sec. cache is bad */ - confidence_t kc_sysbus; /* confidence level that sysad/cmd/state bus is bad */ -} kf_cpu_t; - - -typedef struct kf_pci_bus_s { - confidence_t kpb_belief; /* confidence level that the pci bus is bad */ - confidence_t kpb_pcidev_belief[MAX_PCIDEV]; - /* confidence level that the pci dev is bad */ -} kf_pci_bus_t; - - -#endif /* _ASM_IA64_SN_SN_FRU_H */ - diff --git a/include/asm-ia64/sn/sn_sal.h b/include/asm-ia64/sn/sn_sal.h index 88c31b53dc09..56d74ca76b5d 100644 --- a/include/asm-ia64/sn/sn_sal.h +++ b/include/asm-ia64/sn/sn_sal.h @@ -8,7 +8,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (c) 2000-2004 Silicon Graphics, Inc. All rights reserved. + * Copyright (c) 2000-2005 Silicon Graphics, Inc. All rights reserved. */ @@ -35,8 +35,8 @@ #define SN_SAL_PRINT_ERROR 0x02000012 #define SN_SAL_SET_ERROR_HANDLING_FEATURES 0x0200001a // reentrant #define SN_SAL_GET_FIT_COMPT 0x0200001b // reentrant -#define SN_SAL_GET_SN_INFO 0x0200001c #define SN_SAL_GET_SAPIC_INFO 0x0200001d +#define SN_SAL_GET_SN_INFO 0x0200001e #define SN_SAL_CONSOLE_PUTC 0x02000021 #define SN_SAL_CONSOLE_GETC 0x02000022 #define SN_SAL_CONSOLE_PUTS 0x02000023 @@ -64,6 +64,7 @@ #define SN_SAL_SYSCTL_IOBRICK_PCI_OP 0x02000042 // reentrant #define SN_SAL_IROUTER_OP 0x02000043 +#define SN_SAL_SYSCTL_EVENT 0x02000044 #define SN_SAL_IOIF_INTERRUPT 0x0200004a #define SN_SAL_HWPERF_OP 0x02000050 // lock #define SN_SAL_IOIF_ERROR_INTERRUPT 0x02000051 @@ -76,7 +77,8 @@ #define SN_SAL_IOIF_GET_WIDGET_DMAFLUSH_LIST 0x02000058 #define SN_SAL_HUB_ERROR_INTERRUPT 0x02000060 - +#define SN_SAL_BTE_RECOVER 0x02000061 +#define SN_SAL_IOIF_GET_PCI_TOPOLOGY 0x02000062 /* * Service-specific constants @@ -555,7 +557,8 @@ static inline u64 ia64_sn_partition_serial_get(void) { struct ia64_sal_retval ret_stuff; - SAL_CALL(ret_stuff, SN_SAL_PARTITION_SERIAL_GET, 0, 0, 0, 0, 0, 0, 0); + ia64_sal_oemcall_reentrant(&ret_stuff, SN_SAL_PARTITION_SERIAL_GET, 0, + 0, 0, 0, 0, 0, 0); if (ret_stuff.status != 0) return 0; return ret_stuff.v0; @@ -563,11 +566,10 @@ ia64_sn_partition_serial_get(void) static inline u64 sn_partition_serial_number_val(void) { - if (sn_partition_serial_number) { - return(sn_partition_serial_number); - } else { - return(sn_partition_serial_number = ia64_sn_partition_serial_get()); + if (unlikely(sn_partition_serial_number == 0)) { + sn_partition_serial_number = ia64_sn_partition_serial_get(); } + return sn_partition_serial_number; } /* @@ -578,8 +580,8 @@ static inline partid_t ia64_sn_sysctl_partition_get(nasid_t nasid) { struct ia64_sal_retval ret_stuff; - SAL_CALL(ret_stuff, SN_SAL_SYSCTL_PARTITION_GET, nasid, - 0, 0, 0, 0, 0, 0); + ia64_sal_oemcall_nolock(&ret_stuff, SN_SAL_SYSCTL_PARTITION_GET, nasid, + 0, 0, 0, 0, 0, 0); if (ret_stuff.status != 0) return INVALID_PARTID; return ((partid_t)ret_stuff.v0); @@ -593,11 +595,38 @@ extern partid_t sn_partid; static inline partid_t sn_local_partid(void) { - if (sn_partid < 0) { - return (sn_partid = ia64_sn_sysctl_partition_get(cpuid_to_nasid(smp_processor_id()))); - } else { - return sn_partid; + if (unlikely(sn_partid < 0)) { + sn_partid = ia64_sn_sysctl_partition_get(cpuid_to_nasid(smp_processor_id())); } + return sn_partid; +} + +/* + * Returns the physical address of the partition's reserved page through + * an iterative number of calls. + * + * On first call, 'cookie' and 'len' should be set to 0, and 'addr' + * set to the nasid of the partition whose reserved page's address is + * being sought. + * On subsequent calls, pass the values, that were passed back on the + * previous call. + * + * While the return status equals SALRET_MORE_PASSES, keep calling + * this function after first copying 'len' bytes starting at 'addr' + * into 'buf'. Once the return status equals SALRET_OK, 'addr' will + * be the physical address of the partition's reserved page. If the + * return status equals neither of these, an error as occurred. + */ +static inline s64 +sn_partition_reserved_page_pa(u64 buf, u64 *cookie, u64 *addr, u64 *len) +{ + struct ia64_sal_retval rv; + ia64_sal_oemcall_reentrant(&rv, SN_SAL_GET_PARTITION_ADDR, *cookie, + *addr, buf, *len, 0, 0, 0); + *cookie = rv.v0; + *addr = rv.v1; + *len = rv.v2; + return rv.status; } /* @@ -619,8 +648,8 @@ static inline int sn_register_xp_addr_region(u64 paddr, u64 len, int operation) { struct ia64_sal_retval ret_stuff; - SAL_CALL(ret_stuff, SN_SAL_XP_ADDR_REGION, paddr, len, (u64)operation, - 0, 0, 0, 0); + ia64_sal_oemcall(&ret_stuff, SN_SAL_XP_ADDR_REGION, paddr, len, + (u64)operation, 0, 0, 0, 0); return ret_stuff.status; } @@ -644,8 +673,8 @@ sn_register_nofault_code(u64 start_addr, u64 end_addr, u64 return_addr, } else { call = SN_SAL_NO_FAULT_ZONE_PHYSICAL; } - SAL_CALL(ret_stuff, call, start_addr, end_addr, return_addr, (u64)1, - 0, 0, 0); + ia64_sal_oemcall(&ret_stuff, call, start_addr, end_addr, return_addr, + (u64)1, 0, 0, 0); return ret_stuff.status; } @@ -666,8 +695,8 @@ static inline int sn_change_coherence(u64 *new_domain, u64 *old_domain) { struct ia64_sal_retval ret_stuff; - SAL_CALL(ret_stuff, SN_SAL_COHERENCE, new_domain, old_domain, 0, 0, - 0, 0, 0); + ia64_sal_oemcall(&ret_stuff, SN_SAL_COHERENCE, (u64)new_domain, + (u64)old_domain, 0, 0, 0, 0, 0); return ret_stuff.status; } @@ -686,8 +715,8 @@ sn_change_memprotect(u64 paddr, u64 len, u64 perms, u64 *nasid_array) cnodeid = nasid_to_cnodeid(get_node_number(paddr)); // spin_lock(&NODEPDA(cnodeid)->bist_lock); local_irq_save(irq_flags); - SAL_CALL_NOLOCK(ret_stuff, SN_SAL_MEMPROTECT, paddr, len, nasid_array, - perms, 0, 0, 0); + ia64_sal_oemcall_nolock(&ret_stuff, SN_SAL_MEMPROTECT, paddr, len, + (u64)nasid_array, perms, 0, 0, 0); local_irq_restore(irq_flags); // spin_unlock(&NODEPDA(cnodeid)->bist_lock); return ret_stuff.status; @@ -849,6 +878,19 @@ ia64_sn_irtr_intr_disable(nasid_t nasid, int subch, u64 intr) return (int) rv.v0; } +/* + * Set up a node as the point of contact for system controller + * environmental event delivery. + */ +static inline int +ia64_sn_sysctl_event_init(nasid_t nasid) +{ + struct ia64_sal_retval rv; + SAL_CALL_REENTRANT(rv, SN_SAL_SYSCTL_EVENT, (u64) nasid, + 0, 0, 0, 0, 0, 0); + return (int) rv.v0; +} + /** * ia64_sn_get_fit_compt - read a FIT entry from the PROM header * @nasid: NASID of node to read @@ -1012,4 +1054,29 @@ ia64_sn_hwperf_op(nasid_t nasid, u64 opcode, u64 a0, u64 a1, u64 a2, return (int) rv.status; } +static inline int +ia64_sn_ioif_get_pci_topology(u64 rack, u64 bay, u64 slot, u64 slab, + u64 buf, u64 len) +{ + struct ia64_sal_retval rv; + SAL_CALL_NOLOCK(rv, SN_SAL_IOIF_GET_PCI_TOPOLOGY, + rack, bay, slot, slab, buf, len, 0); + return (int) rv.status; +} + +/* + * BTE error recovery is implemented in SAL + */ +static inline int +ia64_sn_bte_recovery(nasid_t nasid) +{ + struct ia64_sal_retval rv; + + rv.status = 0; + SAL_CALL_NOLOCK(rv, SN_SAL_BTE_RECOVER, 0, 0, 0, 0, 0, 0, 0); + if (rv.status == SALRET_NOT_IMPLEMENTED) + return 0; + return (int) rv.status; +} + #endif /* _ASM_IA64_SN_SN_SAL_H */ diff --git a/include/asm-ia64/sn/sndrv.h b/include/asm-ia64/sn/sndrv.h deleted file mode 100644 index aa00d42cde32..000000000000 --- a/include/asm-ia64/sn/sndrv.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (c) 2002-2004 Silicon Graphics, Inc. All Rights Reserved. - */ - -#ifndef _ASM_IA64_SN_SNDRV_H -#define _ASM_IA64_SN_SNDRV_H - -/* ioctl commands */ -#define SNDRV_GET_ROUTERINFO 1 -#define SNDRV_GET_INFOSIZE 2 -#define SNDRV_GET_HUBINFO 3 -#define SNDRV_GET_FLASHLOGSIZE 4 -#define SNDRV_SET_FLASHSYNC 5 -#define SNDRV_GET_FLASHLOGDATA 6 -#define SNDRV_GET_FLASHLOGALL 7 - -#define SNDRV_SET_HISTOGRAM_TYPE 14 - -#define SNDRV_ELSC_COMMAND 19 -#define SNDRV_CLEAR_LOG 20 -#define SNDRV_INIT_LOG 21 -#define SNDRV_GET_PIMM_PSC 22 -#define SNDRV_SET_PARTITION 23 -#define SNDRV_GET_PARTITION 24 - -/* see synergy_perf_ioctl() */ -#define SNDRV_GET_SYNERGY_VERSION 30 -#define SNDRV_GET_SYNERGY_STATUS 31 -#define SNDRV_GET_SYNERGYINFO 32 -#define SNDRV_SYNERGY_APPEND 33 -#define SNDRV_SYNERGY_ENABLE 34 -#define SNDRV_SYNERGY_FREQ 35 - -/* Devices */ -#define SNDRV_UKNOWN_DEVICE -1 -#define SNDRV_ROUTER_DEVICE 1 -#define SNDRV_HUB_DEVICE 2 -#define SNDRV_ELSC_NVRAM_DEVICE 3 -#define SNDRV_ELSC_CONTROLLER_DEVICE 4 -#define SNDRV_SYSCTL_SUBCH 5 -#define SNDRV_SYNERGY_DEVICE 6 - -#endif /* _ASM_IA64_SN_SNDRV_H */ diff --git a/include/asm-ia64/sn/tioca.h b/include/asm-ia64/sn/tioca.h new file mode 100644 index 000000000000..bc1aacfb9483 --- /dev/null +++ b/include/asm-ia64/sn/tioca.h @@ -0,0 +1,596 @@ +#ifndef _ASM_IA64_SN_TIO_TIOCA_H +#define _ASM_IA64_SN_TIO_TIOCA_H + +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (c) 2003-2005 Silicon Graphics, Inc. All rights reserved. + */ + + +#define TIOCA_PART_NUM 0xE020 +#define TIOCA_MFGR_NUM 0x24 +#define TIOCA_REV_A 0x1 + +/* + * Register layout for TIO:CA. See below for bitmasks for each register. + */ + +struct tioca { + uint64_t ca_id; /* 0x000000 */ + uint64_t ca_control1; /* 0x000008 */ + uint64_t ca_control2; /* 0x000010 */ + uint64_t ca_status1; /* 0x000018 */ + uint64_t ca_status2; /* 0x000020 */ + uint64_t ca_gart_aperature; /* 0x000028 */ + uint64_t ca_gfx_detach; /* 0x000030 */ + uint64_t ca_inta_dest_addr; /* 0x000038 */ + uint64_t ca_intb_dest_addr; /* 0x000040 */ + uint64_t ca_err_int_dest_addr; /* 0x000048 */ + uint64_t ca_int_status; /* 0x000050 */ + uint64_t ca_int_status_alias; /* 0x000058 */ + uint64_t ca_mult_error; /* 0x000060 */ + uint64_t ca_mult_error_alias; /* 0x000068 */ + uint64_t ca_first_error; /* 0x000070 */ + uint64_t ca_int_mask; /* 0x000078 */ + uint64_t ca_crm_pkterr_type; /* 0x000080 */ + uint64_t ca_crm_pkterr_type_alias; /* 0x000088 */ + uint64_t ca_crm_ct_error_detail_1; /* 0x000090 */ + uint64_t ca_crm_ct_error_detail_2; /* 0x000098 */ + uint64_t ca_crm_tnumto; /* 0x0000A0 */ + uint64_t ca_gart_err; /* 0x0000A8 */ + uint64_t ca_pcierr_type; /* 0x0000B0 */ + uint64_t ca_pcierr_addr; /* 0x0000B8 */ + + uint64_t ca_pad_0000C0[3]; /* 0x0000{C0..D0} */ + + uint64_t ca_pci_rd_buf_flush; /* 0x0000D8 */ + uint64_t ca_pci_dma_addr_extn; /* 0x0000E0 */ + uint64_t ca_agp_dma_addr_extn; /* 0x0000E8 */ + uint64_t ca_force_inta; /* 0x0000F0 */ + uint64_t ca_force_intb; /* 0x0000F8 */ + uint64_t ca_debug_vector_sel; /* 0x000100 */ + uint64_t ca_debug_mux_core_sel; /* 0x000108 */ + uint64_t ca_debug_mux_pci_sel; /* 0x000110 */ + uint64_t ca_debug_domain_sel; /* 0x000118 */ + + uint64_t ca_pad_000120[28]; /* 0x0001{20..F8} */ + + uint64_t ca_gart_ptr_table; /* 0x200 */ + uint64_t ca_gart_tlb_addr[8]; /* 0x2{08..40} */ +}; + +/* + * Mask/shift definitions for TIO:CA registers. The convention here is + * to mainly use the names as they appear in the "TIO AEGIS Programmers' + * Reference" with a CA_ prefix added. Some exceptions were made to fix + * duplicate field names or to generalize fields that are common to + * different registers (ca_debug_mux_core_sel and ca_debug_mux_pci_sel for + * example). + * + * Fields consisting of a single bit have a single #define have a single + * macro declaration to mask the bit. Fields consisting of multiple bits + * have two declarations: one to mask the proper bits in a register, and + * a second with the suffix "_SHFT" to identify how far the mask needs to + * be shifted right to get its base value. + */ + +/* ==== ca_control1 */ +#define CA_SYS_BIG_END (1ull << 0) +#define CA_DMA_AGP_SWAP (1ull << 1) +#define CA_DMA_PCI_SWAP (1ull << 2) +#define CA_PIO_IO_SWAP (1ull << 3) +#define CA_PIO_MEM_SWAP (1ull << 4) +#define CA_GFX_WR_SWAP (1ull << 5) +#define CA_AGP_FW_ENABLE (1ull << 6) +#define CA_AGP_CAL_CYCLE (0x7ull << 7) +#define CA_AGP_CAL_CYCLE_SHFT 7 +#define CA_AGP_CAL_PRSCL_BYP (1ull << 10) +#define CA_AGP_INIT_CAL_ENB (1ull << 11) +#define CA_INJ_ADDR_PERR (1ull << 12) +#define CA_INJ_DATA_PERR (1ull << 13) + /* bits 15:14 unused */ +#define CA_PCIM_IO_NBE_AD (0x7ull << 16) +#define CA_PCIM_IO_NBE_AD_SHFT 16 +#define CA_PCIM_FAST_BTB_ENB (1ull << 19) + /* bits 23:20 unused */ +#define CA_PIO_ADDR_OFFSET (0xffull << 24) +#define CA_PIO_ADDR_OFFSET_SHFT 24 + /* bits 35:32 unused */ +#define CA_AGPDMA_OP_COMBDELAY (0x1full << 36) +#define CA_AGPDMA_OP_COMBDELAY_SHFT 36 + /* bit 41 unused */ +#define CA_AGPDMA_OP_ENB_COMBDELAY (1ull << 42) +#define CA_PCI_INT_LPCNT (0xffull << 44) +#define CA_PCI_INT_LPCNT_SHFT 44 + /* bits 63:52 unused */ + +/* ==== ca_control2 */ +#define CA_AGP_LATENCY_TO (0xffull << 0) +#define CA_AGP_LATENCY_TO_SHFT 0 +#define CA_PCI_LATENCY_TO (0xffull << 8) +#define CA_PCI_LATENCY_TO_SHFT 8 +#define CA_PCI_MAX_RETRY (0x3ffull << 16) +#define CA_PCI_MAX_RETRY_SHFT 16 + /* bits 27:26 unused */ +#define CA_RT_INT_EN (0x3ull << 28) +#define CA_RT_INT_EN_SHFT 28 +#define CA_MSI_INT_ENB (1ull << 30) +#define CA_PCI_ARB_ERR_ENB (1ull << 31) +#define CA_GART_MEM_PARAM (0x3ull << 32) +#define CA_GART_MEM_PARAM_SHFT 32 +#define CA_GART_RD_PREFETCH_ENB (1ull << 34) +#define CA_GART_WR_PREFETCH_ENB (1ull << 35) +#define CA_GART_FLUSH_TLB (1ull << 36) + /* bits 39:37 unused */ +#define CA_CRM_TNUMTO_PERIOD (0x1fffull << 40) +#define CA_CRM_TNUMTO_PERIOD_SHFT 40 + /* bits 55:53 unused */ +#define CA_CRM_TNUMTO_ENB (1ull << 56) +#define CA_CRM_PRESCALER_BYP (1ull << 57) + /* bits 59:58 unused */ +#define CA_CRM_MAX_CREDIT (0x7ull << 60) +#define CA_CRM_MAX_CREDIT_SHFT 60 + /* bit 63 unused */ + +/* ==== ca_status1 */ +#define CA_CORELET_ID (0x3ull << 0) +#define CA_CORELET_ID_SHFT 0 +#define CA_INTA_N (1ull << 2) +#define CA_INTB_N (1ull << 3) +#define CA_CRM_CREDIT_AVAIL (0x7ull << 4) +#define CA_CRM_CREDIT_AVAIL_SHFT 4 + /* bit 7 unused */ +#define CA_CRM_SPACE_AVAIL (0x7full << 8) +#define CA_CRM_SPACE_AVAIL_SHFT 8 + /* bit 15 unused */ +#define CA_GART_TLB_VAL (0xffull << 16) +#define CA_GART_TLB_VAL_SHFT 16 + /* bits 63:24 unused */ + +/* ==== ca_status2 */ +#define CA_GFX_CREDIT_AVAIL (0xffull << 0) +#define CA_GFX_CREDIT_AVAIL_SHFT 0 +#define CA_GFX_OPQ_AVAIL (0xffull << 8) +#define CA_GFX_OPQ_AVAIL_SHFT 8 +#define CA_GFX_WRBUFF_AVAIL (0xffull << 16) +#define CA_GFX_WRBUFF_AVAIL_SHFT 16 +#define CA_ADMA_OPQ_AVAIL (0xffull << 24) +#define CA_ADMA_OPQ_AVAIL_SHFT 24 +#define CA_ADMA_WRBUFF_AVAIL (0xffull << 32) +#define CA_ADMA_WRBUFF_AVAIL_SHFT 32 +#define CA_ADMA_RDBUFF_AVAIL (0x7full << 40) +#define CA_ADMA_RDBUFF_AVAIL_SHFT 40 +#define CA_PCI_PIO_OP_STAT (1ull << 47) +#define CA_PDMA_OPQ_AVAIL (0xfull << 48) +#define CA_PDMA_OPQ_AVAIL_SHFT 48 +#define CA_PDMA_WRBUFF_AVAIL (0xfull << 52) +#define CA_PDMA_WRBUFF_AVAIL_SHFT 52 +#define CA_PDMA_RDBUFF_AVAIL (0x3ull << 56) +#define CA_PDMA_RDBUFF_AVAIL_SHFT 56 + /* bits 63:58 unused */ + +/* ==== ca_gart_aperature */ +#define CA_GART_AP_ENB_AGP (1ull << 0) +#define CA_GART_PAGE_SIZE (1ull << 1) +#define CA_GART_AP_ENB_PCI (1ull << 2) + /* bits 11:3 unused */ +#define CA_GART_AP_SIZE (0x3ffull << 12) +#define CA_GART_AP_SIZE_SHFT 12 +#define CA_GART_AP_BASE (0x3ffffffffffull << 22) +#define CA_GART_AP_BASE_SHFT 22 + +/* ==== ca_inta_dest_addr + ==== ca_intb_dest_addr + ==== ca_err_int_dest_addr */ + /* bits 2:0 unused */ +#define CA_INT_DEST_ADDR (0x7ffffffffffffull << 3) +#define CA_INT_DEST_ADDR_SHFT 3 + /* bits 55:54 unused */ +#define CA_INT_DEST_VECT (0xffull << 56) +#define CA_INT_DEST_VECT_SHFT 56 + +/* ==== ca_int_status */ +/* ==== ca_int_status_alias */ +/* ==== ca_mult_error */ +/* ==== ca_mult_error_alias */ +/* ==== ca_first_error */ +/* ==== ca_int_mask */ +#define CA_PCI_ERR (1ull << 0) + /* bits 3:1 unused */ +#define CA_GART_FETCH_ERR (1ull << 4) +#define CA_GFX_WR_OVFLW (1ull << 5) +#define CA_PIO_REQ_OVFLW (1ull << 6) +#define CA_CRM_PKTERR (1ull << 7) +#define CA_CRM_DVERR (1ull << 8) +#define CA_TNUMTO (1ull << 9) +#define CA_CXM_RSP_CRED_OVFLW (1ull << 10) +#define CA_CXM_REQ_CRED_OVFLW (1ull << 11) +#define CA_PIO_INVALID_ADDR (1ull << 12) +#define CA_PCI_ARB_TO (1ull << 13) +#define CA_AGP_REQ_OFLOW (1ull << 14) +#define CA_SBA_TYPE1_ERR (1ull << 15) + /* bit 16 unused */ +#define CA_INTA (1ull << 17) +#define CA_INTB (1ull << 18) +#define CA_MULT_INTA (1ull << 19) +#define CA_MULT_INTB (1ull << 20) +#define CA_GFX_CREDIT_OVFLW (1ull << 21) + /* bits 63:22 unused */ + +/* ==== ca_crm_pkterr_type */ +/* ==== ca_crm_pkterr_type_alias */ +#define CA_CRM_PKTERR_SBERR_HDR (1ull << 0) +#define CA_CRM_PKTERR_DIDN (1ull << 1) +#define CA_CRM_PKTERR_PACTYPE (1ull << 2) +#define CA_CRM_PKTERR_INV_TNUM (1ull << 3) +#define CA_CRM_PKTERR_ADDR_RNG (1ull << 4) +#define CA_CRM_PKTERR_ADDR_ALGN (1ull << 5) +#define CA_CRM_PKTERR_HDR_PARAM (1ull << 6) +#define CA_CRM_PKTERR_CW_ERR (1ull << 7) +#define CA_CRM_PKTERR_SBERR_NH (1ull << 8) +#define CA_CRM_PKTERR_EARLY_TERM (1ull << 9) +#define CA_CRM_PKTERR_EARLY_TAIL (1ull << 10) +#define CA_CRM_PKTERR_MSSNG_TAIL (1ull << 11) +#define CA_CRM_PKTERR_MSSNG_HDR (1ull << 12) + /* bits 15:13 unused */ +#define CA_FIRST_CRM_PKTERR_SBERR_HDR (1ull << 16) +#define CA_FIRST_CRM_PKTERR_DIDN (1ull << 17) +#define CA_FIRST_CRM_PKTERR_PACTYPE (1ull << 18) +#define CA_FIRST_CRM_PKTERR_INV_TNUM (1ull << 19) +#define CA_FIRST_CRM_PKTERR_ADDR_RNG (1ull << 20) +#define CA_FIRST_CRM_PKTERR_ADDR_ALGN (1ull << 21) +#define CA_FIRST_CRM_PKTERR_HDR_PARAM (1ull << 22) +#define CA_FIRST_CRM_PKTERR_CW_ERR (1ull << 23) +#define CA_FIRST_CRM_PKTERR_SBERR_NH (1ull << 24) +#define CA_FIRST_CRM_PKTERR_EARLY_TERM (1ull << 25) +#define CA_FIRST_CRM_PKTERR_EARLY_TAIL (1ull << 26) +#define CA_FIRST_CRM_PKTERR_MSSNG_TAIL (1ull << 27) +#define CA_FIRST_CRM_PKTERR_MSSNG_HDR (1ull << 28) + /* bits 63:29 unused */ + +/* ==== ca_crm_ct_error_detail_1 */ +#define CA_PKT_TYPE (0xfull << 0) +#define CA_PKT_TYPE_SHFT 0 +#define CA_SRC_ID (0x3ull << 4) +#define CA_SRC_ID_SHFT 4 +#define CA_DATA_SZ (0x3ull << 6) +#define CA_DATA_SZ_SHFT 6 +#define CA_TNUM (0xffull << 8) +#define CA_TNUM_SHFT 8 +#define CA_DW_DATA_EN (0xffull << 16) +#define CA_DW_DATA_EN_SHFT 16 +#define CA_GFX_CRED (0xffull << 24) +#define CA_GFX_CRED_SHFT 24 +#define CA_MEM_RD_PARAM (0x3ull << 32) +#define CA_MEM_RD_PARAM_SHFT 32 +#define CA_PIO_OP (1ull << 34) +#define CA_CW_ERR (1ull << 35) + /* bits 62:36 unused */ +#define CA_VALID (1ull << 63) + +/* ==== ca_crm_ct_error_detail_2 */ + /* bits 2:0 unused */ +#define CA_PKT_ADDR (0x1fffffffffffffull << 3) +#define CA_PKT_ADDR_SHFT 3 + /* bits 63:56 unused */ + +/* ==== ca_crm_tnumto */ +#define CA_CRM_TNUMTO_VAL (0xffull << 0) +#define CA_CRM_TNUMTO_VAL_SHFT 0 +#define CA_CRM_TNUMTO_WR (1ull << 8) + /* bits 63:9 unused */ + +/* ==== ca_gart_err */ +#define CA_GART_ERR_SOURCE (0x3ull << 0) +#define CA_GART_ERR_SOURCE_SHFT 0 + /* bits 3:2 unused */ +#define CA_GART_ERR_ADDR (0xfffffffffull << 4) +#define CA_GART_ERR_ADDR_SHFT 4 + /* bits 63:40 unused */ + +/* ==== ca_pcierr_type */ +#define CA_PCIERR_DATA (0xffffffffull << 0) +#define CA_PCIERR_DATA_SHFT 0 +#define CA_PCIERR_ENB (0xfull << 32) +#define CA_PCIERR_ENB_SHFT 32 +#define CA_PCIERR_CMD (0xfull << 36) +#define CA_PCIERR_CMD_SHFT 36 +#define CA_PCIERR_A64 (1ull << 40) +#define CA_PCIERR_SLV_SERR (1ull << 41) +#define CA_PCIERR_SLV_WR_PERR (1ull << 42) +#define CA_PCIERR_SLV_RD_PERR (1ull << 43) +#define CA_PCIERR_MST_SERR (1ull << 44) +#define CA_PCIERR_MST_WR_PERR (1ull << 45) +#define CA_PCIERR_MST_RD_PERR (1ull << 46) +#define CA_PCIERR_MST_MABT (1ull << 47) +#define CA_PCIERR_MST_TABT (1ull << 48) +#define CA_PCIERR_MST_RETRY_TOUT (1ull << 49) + +#define CA_PCIERR_TYPES \ + (CA_PCIERR_A64|CA_PCIERR_SLV_SERR| \ + CA_PCIERR_SLV_WR_PERR|CA_PCIERR_SLV_RD_PERR| \ + CA_PCIERR_MST_SERR|CA_PCIERR_MST_WR_PERR|CA_PCIERR_MST_RD_PERR| \ + CA_PCIERR_MST_MABT|CA_PCIERR_MST_TABT|CA_PCIERR_MST_RETRY_TOUT) + + /* bits 63:50 unused */ + +/* ==== ca_pci_dma_addr_extn */ +#define CA_UPPER_NODE_OFFSET (0x3full << 0) +#define CA_UPPER_NODE_OFFSET_SHFT 0 + /* bits 7:6 unused */ +#define CA_CHIPLET_ID (0x3ull << 8) +#define CA_CHIPLET_ID_SHFT 8 + /* bits 11:10 unused */ +#define CA_PCI_DMA_NODE_ID (0xffffull << 12) +#define CA_PCI_DMA_NODE_ID_SHFT 12 + /* bits 27:26 unused */ +#define CA_PCI_DMA_PIO_MEM_TYPE (1ull << 28) + /* bits 63:29 unused */ + + +/* ==== ca_agp_dma_addr_extn */ + /* bits 19:0 unused */ +#define CA_AGP_DMA_NODE_ID (0xffffull << 20) +#define CA_AGP_DMA_NODE_ID_SHFT 20 + /* bits 27:26 unused */ +#define CA_AGP_DMA_PIO_MEM_TYPE (1ull << 28) + /* bits 63:29 unused */ + +/* ==== ca_debug_vector_sel */ +#define CA_DEBUG_MN_VSEL (0xfull << 0) +#define CA_DEBUG_MN_VSEL_SHFT 0 +#define CA_DEBUG_PP_VSEL (0xfull << 4) +#define CA_DEBUG_PP_VSEL_SHFT 4 +#define CA_DEBUG_GW_VSEL (0xfull << 8) +#define CA_DEBUG_GW_VSEL_SHFT 8 +#define CA_DEBUG_GT_VSEL (0xfull << 12) +#define CA_DEBUG_GT_VSEL_SHFT 12 +#define CA_DEBUG_PD_VSEL (0xfull << 16) +#define CA_DEBUG_PD_VSEL_SHFT 16 +#define CA_DEBUG_AD_VSEL (0xfull << 20) +#define CA_DEBUG_AD_VSEL_SHFT 20 +#define CA_DEBUG_CX_VSEL (0xfull << 24) +#define CA_DEBUG_CX_VSEL_SHFT 24 +#define CA_DEBUG_CR_VSEL (0xfull << 28) +#define CA_DEBUG_CR_VSEL_SHFT 28 +#define CA_DEBUG_BA_VSEL (0xfull << 32) +#define CA_DEBUG_BA_VSEL_SHFT 32 +#define CA_DEBUG_PE_VSEL (0xfull << 36) +#define CA_DEBUG_PE_VSEL_SHFT 36 +#define CA_DEBUG_BO_VSEL (0xfull << 40) +#define CA_DEBUG_BO_VSEL_SHFT 40 +#define CA_DEBUG_BI_VSEL (0xfull << 44) +#define CA_DEBUG_BI_VSEL_SHFT 44 +#define CA_DEBUG_AS_VSEL (0xfull << 48) +#define CA_DEBUG_AS_VSEL_SHFT 48 +#define CA_DEBUG_PS_VSEL (0xfull << 52) +#define CA_DEBUG_PS_VSEL_SHFT 52 +#define CA_DEBUG_PM_VSEL (0xfull << 56) +#define CA_DEBUG_PM_VSEL_SHFT 56 + /* bits 63:60 unused */ + +/* ==== ca_debug_mux_core_sel */ +/* ==== ca_debug_mux_pci_sel */ +#define CA_DEBUG_MSEL0 (0x7ull << 0) +#define CA_DEBUG_MSEL0_SHFT 0 + /* bit 3 unused */ +#define CA_DEBUG_NSEL0 (0x7ull << 4) +#define CA_DEBUG_NSEL0_SHFT 4 + /* bit 7 unused */ +#define CA_DEBUG_MSEL1 (0x7ull << 8) +#define CA_DEBUG_MSEL1_SHFT 8 + /* bit 11 unused */ +#define CA_DEBUG_NSEL1 (0x7ull << 12) +#define CA_DEBUG_NSEL1_SHFT 12 + /* bit 15 unused */ +#define CA_DEBUG_MSEL2 (0x7ull << 16) +#define CA_DEBUG_MSEL2_SHFT 16 + /* bit 19 unused */ +#define CA_DEBUG_NSEL2 (0x7ull << 20) +#define CA_DEBUG_NSEL2_SHFT 20 + /* bit 23 unused */ +#define CA_DEBUG_MSEL3 (0x7ull << 24) +#define CA_DEBUG_MSEL3_SHFT 24 + /* bit 27 unused */ +#define CA_DEBUG_NSEL3 (0x7ull << 28) +#define CA_DEBUG_NSEL3_SHFT 28 + /* bit 31 unused */ +#define CA_DEBUG_MSEL4 (0x7ull << 32) +#define CA_DEBUG_MSEL4_SHFT 32 + /* bit 35 unused */ +#define CA_DEBUG_NSEL4 (0x7ull << 36) +#define CA_DEBUG_NSEL4_SHFT 36 + /* bit 39 unused */ +#define CA_DEBUG_MSEL5 (0x7ull << 40) +#define CA_DEBUG_MSEL5_SHFT 40 + /* bit 43 unused */ +#define CA_DEBUG_NSEL5 (0x7ull << 44) +#define CA_DEBUG_NSEL5_SHFT 44 + /* bit 47 unused */ +#define CA_DEBUG_MSEL6 (0x7ull << 48) +#define CA_DEBUG_MSEL6_SHFT 48 + /* bit 51 unused */ +#define CA_DEBUG_NSEL6 (0x7ull << 52) +#define CA_DEBUG_NSEL6_SHFT 52 + /* bit 55 unused */ +#define CA_DEBUG_MSEL7 (0x7ull << 56) +#define CA_DEBUG_MSEL7_SHFT 56 + /* bit 59 unused */ +#define CA_DEBUG_NSEL7 (0x7ull << 60) +#define CA_DEBUG_NSEL7_SHFT 60 + /* bit 63 unused */ + + +/* ==== ca_debug_domain_sel */ +#define CA_DEBUG_DOMAIN_L (1ull << 0) +#define CA_DEBUG_DOMAIN_H (1ull << 1) + /* bits 63:2 unused */ + +/* ==== ca_gart_ptr_table */ +#define CA_GART_PTR_VAL (1ull << 0) + /* bits 11:1 unused */ +#define CA_GART_PTR_ADDR (0xfffffffffffull << 12) +#define CA_GART_PTR_ADDR_SHFT 12 + /* bits 63:56 unused */ + +/* ==== ca_gart_tlb_addr[0-7] */ +#define CA_GART_TLB_ADDR (0xffffffffffffffull << 0) +#define CA_GART_TLB_ADDR_SHFT 0 + /* bits 62:56 unused */ +#define CA_GART_TLB_ENTRY_VAL (1ull << 63) + +/* + * PIO address space ranges for TIO:CA + */ + +/* CA internal registers */ +#define CA_PIO_ADMIN 0x00000000 +#define CA_PIO_ADMIN_LEN 0x00010000 + +/* GFX Write Buffer - Diagnostics */ +#define CA_PIO_GFX 0x00010000 +#define CA_PIO_GFX_LEN 0x00010000 + +/* AGP DMA Write Buffer - Diagnostics */ +#define CA_PIO_AGP_DMAWRITE 0x00020000 +#define CA_PIO_AGP_DMAWRITE_LEN 0x00010000 + +/* AGP DMA READ Buffer - Diagnostics */ +#define CA_PIO_AGP_DMAREAD 0x00030000 +#define CA_PIO_AGP_DMAREAD_LEN 0x00010000 + +/* PCI Config Type 0 */ +#define CA_PIO_PCI_TYPE0_CONFIG 0x01000000 +#define CA_PIO_PCI_TYPE0_CONFIG_LEN 0x01000000 + +/* PCI Config Type 1 */ +#define CA_PIO_PCI_TYPE1_CONFIG 0x02000000 +#define CA_PIO_PCI_TYPE1_CONFIG_LEN 0x01000000 + +/* PCI I/O Cycles - mapped to PCI Address 0x00000000-0x04ffffff */ +#define CA_PIO_PCI_IO 0x03000000 +#define CA_PIO_PCI_IO_LEN 0x05000000 + +/* PCI MEM Cycles - mapped to PCI with CA_PIO_ADDR_OFFSET of ca_control1 */ +/* use Fast Write if enabled and coretalk packet type is a GFX request */ +#define CA_PIO_PCI_MEM_OFFSET 0x08000000 +#define CA_PIO_PCI_MEM_OFFSET_LEN 0x08000000 + +/* PCI MEM Cycles - mapped to PCI Address 0x00000000-0xbfffffff */ +/* use Fast Write if enabled and coretalk packet type is a GFX request */ +#define CA_PIO_PCI_MEM 0x40000000 +#define CA_PIO_PCI_MEM_LEN 0xc0000000 + +/* + * DMA space + * + * The CA aperature (ie. bus address range) mapped by the GART is segmented into + * two parts. The lower portion of the aperature is used for mapping 32 bit + * PCI addresses which are managed by the dma interfaces in this file. The + * upper poprtion of the aperature is used for mapping 48 bit AGP addresses. + * The AGP portion of the aperature is managed by the agpgart_be.c driver + * in drivers/linux/agp. There are ca-specific hooks in that driver to + * manipulate the gart, but management of the AGP portion of the aperature + * is the responsibility of that driver. + * + * CA allows three main types of DMA mapping: + * + * PCI 64-bit Managed by this driver + * PCI 32-bit Managed by this driver + * AGP 48-bit Managed by hooks in the /dev/agpgart driver + * + * All of the above can optionally be remapped through the GART. The following + * table lists the combinations of addressing types and GART remapping that + * is currently supported by the driver (h/w supports all, s/w limits this): + * + * PCI64 PCI32 AGP48 + * GART no yes yes + * Direct yes yes no + * + * GART remapping of PCI64 is not done because there is no need to. The + * 64 bit PCI address holds all of the information necessary to target any + * memory in the system. + * + * AGP48 is always mapped through the GART. Management of the AGP48 portion + * of the aperature is the responsibility of code in the agpgart_be driver. + * + * The non-64 bit bus address space will currently be partitioned like this: + * + * 0xffff_ffff_ffff +-------- + * | AGP48 direct + * | Space managed by this driver + * CA_AGP_DIRECT_BASE +-------- + * | AGP GART mapped (gfx aperature) + * | Space managed by /dev/agpgart driver + * | This range is exposed to the agpgart + * | driver as the "graphics aperature" + * CA_AGP_MAPPED_BASE +----- + * | PCI GART mapped + * | Space managed by this driver + * CA_PCI32_MAPPED_BASE +---- + * | PCI32 direct + * | Space managed by this driver + * 0xC000_0000 +-------- + * (CA_PCI32_DIRECT_BASE) + * + * The bus address range CA_PCI32_MAPPED_BASE through CA_AGP_DIRECT_BASE + * is what we call the CA aperature. Addresses falling in this range will + * be remapped using the GART. + * + * The bus address range CA_AGP_MAPPED_BASE through CA_AGP_DIRECT_BASE + * is what we call the graphics aperature. This is a subset of the CA + * aperature and is under the control of the agpgart_be driver. + * + * CA_PCI32_MAPPED_BASE, CA_AGP_MAPPED_BASE, and CA_AGP_DIRECT_BASE are + * somewhat arbitrary values. The known constraints on choosing these is: + * + * 1) CA_AGP_DIRECT_BASE-CA_PCI32_MAPPED_BASE+1 (the CA aperature size) + * must be one of the values supported by the ca_gart_aperature register. + * Currently valid values are: 4MB through 4096MB in powers of 2 increments + * + * 2) CA_AGP_DIRECT_BASE-CA_AGP_MAPPED_BASE+1 (the gfx aperature size) + * must be in MB units since that's what the agpgart driver assumes. + */ + +/* + * Define Bus DMA ranges. These are configurable (see constraints above) + * and will probably need tuning based on experience. + */ + + +/* + * 11/24/03 + * CA has an addressing glitch w.r.t. PCI direct 32 bit DMA that makes it + * generally unusable. The problem is that for PCI direct 32 + * DMA's, all 32 bits of the bus address are used to form the lower 32 bits + * of the coretalk address, and coretalk bits 38:32 come from a register. + * Since only PCI bus addresses 0xC0000000-0xFFFFFFFF (1GB) are available + * for DMA (the rest is allocated to PIO), host node addresses need to be + * such that their lower 32 bits fall in the 0xC0000000-0xffffffff range + * as well. So there can be no PCI32 direct DMA below 3GB!! For this + * reason we set the CA_PCI32_DIRECT_SIZE to 0 which essentially makes + * tioca_dma_direct32() a noop but preserves the code flow should this issue + * be fixed in a respin. + * + * For now, all PCI32 DMA's must be mapped through the GART. + */ + +#define CA_PCI32_DIRECT_BASE 0xC0000000UL /* BASE not configurable */ +#define CA_PCI32_DIRECT_SIZE 0x00000000UL /* 0 MB */ + +#define CA_PCI32_MAPPED_BASE 0xC0000000UL +#define CA_PCI32_MAPPED_SIZE 0x40000000UL /* 2GB */ + +#define CA_AGP_MAPPED_BASE 0x80000000UL +#define CA_AGP_MAPPED_SIZE 0x40000000UL /* 2GB */ + +#define CA_AGP_DIRECT_BASE 0x40000000UL /* 2GB */ +#define CA_AGP_DIRECT_SIZE 0x40000000UL + +#define CA_APERATURE_BASE (CA_AGP_MAPPED_BASE) +#define CA_APERATURE_SIZE (CA_AGP_MAPPED_SIZE+CA_PCI32_MAPPED_SIZE) + +#endif /* _ASM_IA64_SN_TIO_TIOCA_H */ diff --git a/include/asm-ia64/sn/tioca_provider.h b/include/asm-ia64/sn/tioca_provider.h new file mode 100644 index 000000000000..b6acc22ab239 --- /dev/null +++ b/include/asm-ia64/sn/tioca_provider.h @@ -0,0 +1,206 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (c) 2003-2005 Silicon Graphics, Inc. All rights reserved. + */ + +#ifndef _ASM_IA64_SN_TIO_CA_AGP_PROVIDER_H +#define _ASM_IA64_SN_TIO_CA_AGP_PROVIDER_H + +#include <asm/sn/tioca.h> + +/* + * WAR enables + * Defines for individual WARs. Each is a bitmask of applicable + * part revision numbers. (1 << 1) == rev A, (1 << 2) == rev B, + * (3 << 1) == (rev A or rev B), etc + */ + +#define TIOCA_WAR_ENABLED(pv, tioca_common) \ + ((1 << tioca_common->ca_rev) & pv) + + /* TIO:ICE:FRZ:Freezer loses a PIO data ucred on PIO RD RSP with CW error */ +#define PV907908 (1 << 1) + /* ATI config space problems after BIOS execution starts */ +#define PV908234 (1 << 1) + /* CA:AGPDMA write request data mismatch with ABC1CL merge */ +#define PV895469 (1 << 1) + /* TIO:CA TLB invalidate of written GART entries possibly not occuring in CA*/ +#define PV910244 (1 << 1) + +struct tioca_dmamap{ + struct list_head cad_list; /* headed by ca_list */ + + dma_addr_t cad_dma_addr; /* Linux dma handle */ + uint cad_gart_entry; /* start entry in ca_gart_pagemap */ + uint cad_gart_size; /* #entries for this map */ +}; + +/* + * Kernel only fields. Prom may look at this stuff for debugging only. + * Access this structure through the ca_kernel_private ptr. + */ + +struct tioca_common ; + +struct tioca_kernel { + struct tioca_common *ca_common; /* tioca this belongs to */ + struct list_head ca_list; /* list of all ca's */ + struct list_head ca_dmamaps; + spinlock_t ca_lock; /* Kernel lock */ + cnodeid_t ca_closest_node; + struct list_head *ca_devices; /* bus->devices */ + + /* + * General GART stuff + */ + uint64_t ca_ap_size; /* size of aperature in bytes */ + uint32_t ca_gart_entries; /* # uint64_t entries in gart */ + uint32_t ca_ap_pagesize; /* aperature page size in bytes */ + uint64_t ca_ap_bus_base; /* bus address of CA aperature */ + uint64_t ca_gart_size; /* gart size in bytes */ + uint64_t *ca_gart; /* gart table vaddr */ + uint64_t ca_gart_coretalk_addr; /* gart coretalk addr */ + uint8_t ca_gart_iscoherent; /* used in tioca_tlbflush */ + + /* PCI GART convenience values */ + uint64_t ca_pciap_base; /* pci aperature bus base address */ + uint64_t ca_pciap_size; /* pci aperature size (bytes) */ + uint64_t ca_pcigart_base; /* gfx GART bus base address */ + uint64_t *ca_pcigart; /* gfx GART vm address */ + uint32_t ca_pcigart_entries; + uint32_t ca_pcigart_start; /* PCI start index in ca_gart */ + void *ca_pcigart_pagemap; + + /* AGP GART convenience values */ + uint64_t ca_gfxap_base; /* gfx aperature bus base address */ + uint64_t ca_gfxap_size; /* gfx aperature size (bytes) */ + uint64_t ca_gfxgart_base; /* gfx GART bus base address */ + uint64_t *ca_gfxgart; /* gfx GART vm address */ + uint32_t ca_gfxgart_entries; + uint32_t ca_gfxgart_start; /* agpgart start index in ca_gart */ +}; + +/* + * Common tioca info shared between kernel and prom + * + * DO NOT CHANGE THIS STRUCT WITHOUT MAKING CORRESPONDING CHANGES + * TO THE PROM VERSION. + */ + +struct tioca_common { + struct pcibus_bussoft ca_common; /* common pciio header */ + + uint32_t ca_rev; + uint32_t ca_closest_nasid; + + uint64_t ca_prom_private; + uint64_t ca_kernel_private; +}; + +/** + * tioca_paddr_to_gart - Convert an SGI coretalk address to a CA GART entry + * @paddr: page address to convert + * + * Convert a system [coretalk] address to a GART entry. GART entries are + * formed using the following: + * + * data = ( (1<<63) | ( (REMAP_NODE_ID << 40) | (MD_CHIPLET_ID << 38) | + * (REMAP_SYS_ADDR) ) >> 12 ) + * + * DATA written to 1 GART TABLE Entry in system memory is remapped system + * addr for 1 page + * + * The data is for coretalk address format right shifted 12 bits with a + * valid bit. + * + * GART_TABLE_ENTRY [ 25:0 ] -- REMAP_SYS_ADDRESS[37:12]. + * GART_TABLE_ENTRY [ 27:26 ] -- SHUB MD chiplet id. + * GART_TABLE_ENTRY [ 41:28 ] -- REMAP_NODE_ID. + * GART_TABLE_ENTRY [ 63 ] -- Valid Bit + */ +static inline u64 +tioca_paddr_to_gart(unsigned long paddr) +{ + /* + * We are assuming right now that paddr already has the correct + * format since the address from xtalk_dmaXXX should already have + * NODE_ID, CHIPLET_ID, and SYS_ADDR in the correct locations. + */ + + return ((paddr) >> 12) | (1UL << 63); +} + +/** + * tioca_physpage_to_gart - Map a host physical page for SGI CA based DMA + * @page_addr: system page address to map + */ + +static inline unsigned long +tioca_physpage_to_gart(uint64_t page_addr) +{ + uint64_t coretalk_addr; + + coretalk_addr = PHYS_TO_TIODMA(page_addr); + if (!coretalk_addr) { + return 0; + } + + return tioca_paddr_to_gart(coretalk_addr); +} + +/** + * tioca_tlbflush - invalidate cached SGI CA GART TLB entries + * @tioca_kernel: CA context + * + * Invalidate tlb entries for a given CA GART. Main complexity is to account + * for revA bug. + */ +static inline void +tioca_tlbflush(struct tioca_kernel *tioca_kernel) +{ + volatile uint64_t tmp; + volatile struct tioca *ca_base; + struct tioca_common *tioca_common; + + tioca_common = tioca_kernel->ca_common; + ca_base = (struct tioca *)tioca_common->ca_common.bs_base; + + /* + * Explicit flushes not needed if GART is in cached mode + */ + if (tioca_kernel->ca_gart_iscoherent) { + if (TIOCA_WAR_ENABLED(PV910244, tioca_common)) { + /* + * PV910244: RevA CA needs explicit flushes. + * Need to put GART into uncached mode before + * flushing otherwise the explicit flush is ignored. + * + * Alternate WAR would be to leave GART cached and + * touch every CL aligned GART entry. + */ + + ca_base->ca_control2 &= ~(CA_GART_MEM_PARAM); + ca_base->ca_control2 |= CA_GART_FLUSH_TLB; + ca_base->ca_control2 |= + (0x2ull << CA_GART_MEM_PARAM_SHFT); + tmp = ca_base->ca_control2; + } + + return; + } + + /* + * Gart in uncached mode ... need an explicit flush. + */ + + ca_base->ca_control2 |= CA_GART_FLUSH_TLB; + tmp = ca_base->ca_control2; +} + +extern uint32_t tioca_gart_found; +extern int tioca_init_provider(void); +extern void tioca_fastwrite_enable(struct tioca_kernel *tioca_kern); +#endif /* _ASM_IA64_SN_TIO_CA_AGP_PROVIDER_H */ diff --git a/include/asm-ia64/sn/tiocx.h b/include/asm-ia64/sn/tiocx.h new file mode 100644 index 000000000000..c5447a504509 --- /dev/null +++ b/include/asm-ia64/sn/tiocx.h @@ -0,0 +1,71 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (c) 2005 Silicon Graphics, Inc. All rights reserved. + */ + +#ifndef _ASM_IA64_SN_TIO_TIOCX_H +#define _ASM_IA64_SN_TIO_TIOCX_H + +#ifdef __KERNEL__ + +struct cx_id_s { + unsigned int part_num; + unsigned int mfg_num; + int nasid; +}; + +struct cx_dev { + struct cx_id_s cx_id; + void *soft; /* driver specific */ + struct hubdev_info *hubdev; + struct device dev; + struct cx_drv *driver; +}; + +struct cx_device_id { + unsigned int part_num; + unsigned int mfg_num; +}; + +struct cx_drv { + char *name; + const struct cx_device_id *id_table; + struct device_driver driver; + int (*probe) (struct cx_dev * dev, const struct cx_device_id * id); + int (*remove) (struct cx_dev * dev); +}; + +/* create DMA address by stripping AS bits */ +#define TIOCX_DMA_ADDR(a) (uint64_t)((uint64_t)(a) & 0xffffcfffffffffUL) + +#define TIOCX_TO_TIOCX_DMA_ADDR(a) (uint64_t)(((uint64_t)(a) & 0xfffffffff) | \ + ((((uint64_t)(a)) & 0xffffc000000000UL) <<2)) + +#define TIO_CE_ASIC_PARTNUM 0xce00 +#define TIOCX_CORELET 3 + +/* These are taken from tio_mmr_as.h */ +#define TIO_ICE_FRZ_CFG TIO_MMR_ADDR_MOD(0x00000000b0008100UL) +#define TIO_ICE_PMI_TX_CFG TIO_MMR_ADDR_MOD(0x00000000b000b100UL) +#define TIO_ICE_PMI_TX_DYN_CREDIT_STAT_CB3 TIO_MMR_ADDR_MOD(0x00000000b000be18UL) +#define TIO_ICE_PMI_TX_DYN_CREDIT_STAT_CB3_CREDIT_CNT_MASK 0x000000000000000fUL + +#define to_cx_dev(n) container_of(n, struct cx_dev, dev) +#define to_cx_driver(drv) container_of(drv, struct cx_drv, driver) + +extern struct sn_irq_info *tiocx_irq_alloc(nasid_t, int, int, nasid_t, int); +extern void tiocx_irq_free(struct sn_irq_info *); +extern int cx_device_unregister(struct cx_dev *); +extern int cx_device_register(nasid_t, int, int, struct hubdev_info *); +extern int cx_driver_unregister(struct cx_drv *); +extern int cx_driver_register(struct cx_drv *); +extern uint64_t tiocx_dma_addr(uint64_t addr); +extern uint64_t tiocx_swin_base(int nasid); +extern void tiocx_mmr_store(int nasid, uint64_t offset, uint64_t value); +extern uint64_t tiocx_mmr_load(int nasid, uint64_t offset); + +#endif // __KERNEL__ +#endif // _ASM_IA64_SN_TIO_TIOCX__ diff --git a/include/asm-ia64/sn/types.h b/include/asm-ia64/sn/types.h index 586ed47cae9c..8e04ee211e59 100644 --- a/include/asm-ia64/sn/types.h +++ b/include/asm-ia64/sn/types.h @@ -16,7 +16,8 @@ typedef signed short nasid_t; /* node id in numa-as-id space */ typedef signed char partid_t; /* partition ID type */ typedef unsigned int moduleid_t; /* user-visible module number type */ typedef unsigned int cmoduleid_t; /* kernel compact module id type */ -typedef signed char slabid_t; +typedef unsigned char slotid_t; /* slot (blade) within module */ +typedef unsigned char slabid_t; /* slab (asic) within slot */ typedef u64 nic_t; typedef unsigned long iopaddr_t; typedef unsigned long paddr_t; diff --git a/include/asm-ia64/sn/xp.h b/include/asm-ia64/sn/xp.h new file mode 100644 index 000000000000..9902185c0288 --- /dev/null +++ b/include/asm-ia64/sn/xp.h @@ -0,0 +1,436 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2004-2005 Silicon Graphics, Inc. All rights reserved. + */ + + +/* + * External Cross Partition (XP) structures and defines. + */ + + +#ifndef _ASM_IA64_SN_XP_H +#define _ASM_IA64_SN_XP_H + + +#include <linux/version.h> +#include <linux/cache.h> +#include <linux/hardirq.h> +#include <asm/sn/types.h> +#include <asm/sn/bte.h> + + +#ifdef USE_DBUG_ON +#define DBUG_ON(condition) BUG_ON(condition) +#else +#define DBUG_ON(condition) +#endif + + +/* + * Define the maximum number of logically defined partitions the system + * can support. It is constrained by the maximum number of hardware + * partitionable regions. The term 'region' in this context refers to the + * minimum number of nodes that can comprise an access protection grouping. + * The access protection is in regards to memory, IPI and IOI. + * + * The maximum number of hardware partitionable regions is equal to the + * maximum number of nodes in the entire system divided by the minimum number + * of nodes that comprise an access protection grouping. + */ +#define XP_MAX_PARTITIONS 64 + + +/* + * Define the number of u64s required to represent all the C-brick nasids + * as a bitmap. The cross-partition kernel modules deal only with + * C-brick nasids, thus the need for bitmaps which don't account for + * odd-numbered (non C-brick) nasids. + */ +#define XP_MAX_PHYSNODE_ID (MAX_PHYSNODE_ID / 2) +#define XP_NASID_MASK_BYTES ((XP_MAX_PHYSNODE_ID + 7) / 8) +#define XP_NASID_MASK_WORDS ((XP_MAX_PHYSNODE_ID + 63) / 64) + + +/* + * Wrapper for bte_copy() that should it return a failure status will retry + * the bte_copy() once in the hope that the failure was due to a temporary + * aberration (i.e., the link going down temporarily). + * + * See bte_copy for definition of the input parameters. + * + * Note: xp_bte_copy() should never be called while holding a spinlock. + */ +static inline bte_result_t +xp_bte_copy(u64 src, u64 dest, u64 len, u64 mode, void *notification) +{ + bte_result_t ret; + + + ret = bte_copy(src, dest, len, mode, notification); + + if (ret != BTE_SUCCESS) { + if (!in_interrupt()) { + cond_resched(); + } + ret = bte_copy(src, dest, len, mode, notification); + } + + return ret; +} + + +/* + * XPC establishes channel connections between the local partition and any + * other partition that is currently up. Over these channels, kernel-level + * `users' can communicate with their counterparts on the other partitions. + * + * The maxinum number of channels is limited to eight. For performance reasons, + * the internal cross partition structures require sixteen bytes per channel, + * and eight allows all of this interface-shared info to fit in one cache line. + * + * XPC_NCHANNELS reflects the total number of channels currently defined. + * If the need for additional channels arises, one can simply increase + * XPC_NCHANNELS accordingly. If the day should come where that number + * exceeds the MAXIMUM number of channels allowed (eight), then one will need + * to make changes to the XPC code to allow for this. + */ +#define XPC_MEM_CHANNEL 0 /* memory channel number */ +#define XPC_NET_CHANNEL 1 /* network channel number */ + +#define XPC_NCHANNELS 2 /* #of defined channels */ +#define XPC_MAX_NCHANNELS 8 /* max #of channels allowed */ + +#if XPC_NCHANNELS > XPC_MAX_NCHANNELS +#error XPC_NCHANNELS exceeds MAXIMUM allowed. +#endif + + +/* + * The format of an XPC message is as follows: + * + * +-------+--------------------------------+ + * | flags |////////////////////////////////| + * +-------+--------------------------------+ + * | message # | + * +----------------------------------------+ + * | payload (user-defined message) | + * | | + * : + * | | + * +----------------------------------------+ + * + * The size of the payload is defined by the user via xpc_connect(). A user- + * defined message resides in the payload area. + * + * The user should have no dealings with the message header, but only the + * message's payload. When a message entry is allocated (via xpc_allocate()) + * a pointer to the payload area is returned and not the actual beginning of + * the XPC message. The user then constructs a message in the payload area + * and passes that pointer as an argument on xpc_send() or xpc_send_notify(). + * + * The size of a message entry (within a message queue) must be a cacheline + * sized multiple in order to facilitate the BTE transfer of messages from one + * message queue to another. A macro, XPC_MSG_SIZE(), is provided for the user + * that wants to fit as many msg entries as possible in a given memory size + * (e.g. a memory page). + */ +struct xpc_msg { + u8 flags; /* FOR XPC INTERNAL USE ONLY */ + u8 reserved[7]; /* FOR XPC INTERNAL USE ONLY */ + s64 number; /* FOR XPC INTERNAL USE ONLY */ + + u64 payload; /* user defined portion of message */ +}; + + +#define XPC_MSG_PAYLOAD_OFFSET (u64) (&((struct xpc_msg *)0)->payload) +#define XPC_MSG_SIZE(_payload_size) \ + L1_CACHE_ALIGN(XPC_MSG_PAYLOAD_OFFSET + (_payload_size)) + + +/* + * Define the return values and values passed to user's callout functions. + * (It is important to add new value codes at the end just preceding + * xpcUnknownReason, which must have the highest numerical value.) + */ +enum xpc_retval { + xpcSuccess = 0, + + xpcNotConnected, /* 1: channel is not connected */ + xpcConnected, /* 2: channel connected (opened) */ + xpcRETIRED1, /* 3: (formerly xpcDisconnected) */ + + xpcMsgReceived, /* 4: message received */ + xpcMsgDelivered, /* 5: message delivered and acknowledged */ + + xpcRETIRED2, /* 6: (formerly xpcTransferFailed) */ + + xpcNoWait, /* 7: operation would require wait */ + xpcRetry, /* 8: retry operation */ + xpcTimeout, /* 9: timeout in xpc_allocate_msg_wait() */ + xpcInterrupted, /* 10: interrupted wait */ + + xpcUnequalMsgSizes, /* 11: message size disparity between sides */ + xpcInvalidAddress, /* 12: invalid address */ + + xpcNoMemory, /* 13: no memory available for XPC structures */ + xpcLackOfResources, /* 14: insufficient resources for operation */ + xpcUnregistered, /* 15: channel is not registered */ + xpcAlreadyRegistered, /* 16: channel is already registered */ + + xpcPartitionDown, /* 17: remote partition is down */ + xpcNotLoaded, /* 18: XPC module is not loaded */ + xpcUnloading, /* 19: this side is unloading XPC module */ + + xpcBadMagic, /* 20: XPC MAGIC string not found */ + + xpcReactivating, /* 21: remote partition was reactivated */ + + xpcUnregistering, /* 22: this side is unregistering channel */ + xpcOtherUnregistering, /* 23: other side is unregistering channel */ + + xpcCloneKThread, /* 24: cloning kernel thread */ + xpcCloneKThreadFailed, /* 25: cloning kernel thread failed */ + + xpcNoHeartbeat, /* 26: remote partition has no heartbeat */ + + xpcPioReadError, /* 27: PIO read error */ + xpcPhysAddrRegFailed, /* 28: registration of phys addr range failed */ + + xpcBteDirectoryError, /* 29: maps to BTEFAIL_DIR */ + xpcBtePoisonError, /* 30: maps to BTEFAIL_POISON */ + xpcBteWriteError, /* 31: maps to BTEFAIL_WERR */ + xpcBteAccessError, /* 32: maps to BTEFAIL_ACCESS */ + xpcBtePWriteError, /* 33: maps to BTEFAIL_PWERR */ + xpcBtePReadError, /* 34: maps to BTEFAIL_PRERR */ + xpcBteTimeOutError, /* 35: maps to BTEFAIL_TOUT */ + xpcBteXtalkError, /* 36: maps to BTEFAIL_XTERR */ + xpcBteNotAvailable, /* 37: maps to BTEFAIL_NOTAVAIL */ + xpcBteUnmappedError, /* 38: unmapped BTEFAIL_ error */ + + xpcBadVersion, /* 39: bad version number */ + xpcVarsNotSet, /* 40: the XPC variables are not set up */ + xpcNoRsvdPageAddr, /* 41: unable to get rsvd page's phys addr */ + xpcInvalidPartid, /* 42: invalid partition ID */ + xpcLocalPartid, /* 43: local partition ID */ + + xpcUnknownReason /* 44: unknown reason -- must be last in list */ +}; + + +/* + * Define the callout function types used by XPC to update the user on + * connection activity and state changes (via the user function registered by + * xpc_connect()) and to notify them of messages received and delivered (via + * the user function registered by xpc_send_notify()). + * + * The two function types are xpc_channel_func and xpc_notify_func and + * both share the following arguments, with the exception of "data", which + * only xpc_channel_func has. + * + * Arguments: + * + * reason - reason code. (See following table.) + * partid - partition ID associated with condition. + * ch_number - channel # associated with condition. + * data - pointer to optional data. (See following table.) + * key - pointer to optional user-defined value provided as the "key" + * argument to xpc_connect() or xpc_send_notify(). + * + * In the following table the "Optional Data" column applies to callouts made + * to functions registered by xpc_connect(). A "NA" in that column indicates + * that this reason code can be passed to functions registered by + * xpc_send_notify() (i.e. they don't have data arguments). + * + * Also, the first three reason codes in the following table indicate + * success, whereas the others indicate failure. When a failure reason code + * is received, one can assume that the channel is not connected. + * + * + * Reason Code | Cause | Optional Data + * =====================+================================+===================== + * xpcConnected | connection has been established| max #of entries + * | to the specified partition on | allowed in message + * | the specified channel | queue + * ---------------------+--------------------------------+--------------------- + * xpcMsgReceived | an XPC message arrived from | address of payload + * | the specified partition on the | + * | specified channel | [the user must call + * | | xpc_received() when + * | | finished with the + * | | payload] + * ---------------------+--------------------------------+--------------------- + * xpcMsgDelivered | notification that the message | NA + * | was delivered to the intended | + * | recipient and that they have | + * | acknowledged its receipt by | + * | calling xpc_received() | + * =====================+================================+===================== + * xpcUnequalMsgSizes | can't connect to the specified | NULL + * | partition on the specified | + * | channel because of mismatched | + * | message sizes | + * ---------------------+--------------------------------+--------------------- + * xpcNoMemory | insufficient memory avaiable | NULL + * | to allocate message queue | + * ---------------------+--------------------------------+--------------------- + * xpcLackOfResources | lack of resources to create | NULL + * | the necessary kthreads to | + * | support the channel | + * ---------------------+--------------------------------+--------------------- + * xpcUnregistering | this side's user has | NULL or NA + * | unregistered by calling | + * | xpc_disconnect() | + * ---------------------+--------------------------------+--------------------- + * xpcOtherUnregistering| the other side's user has | NULL or NA + * | unregistered by calling | + * | xpc_disconnect() | + * ---------------------+--------------------------------+--------------------- + * xpcNoHeartbeat | the other side's XPC is no | NULL or NA + * | longer heartbeating | + * | | + * ---------------------+--------------------------------+--------------------- + * xpcUnloading | this side's XPC module is | NULL or NA + * | being unloaded | + * | | + * ---------------------+--------------------------------+--------------------- + * xpcOtherUnloading | the other side's XPC module is | NULL or NA + * | is being unloaded | + * | | + * ---------------------+--------------------------------+--------------------- + * xpcPioReadError | xp_nofault_PIOR() returned an | NULL or NA + * | error while sending an IPI | + * | | + * ---------------------+--------------------------------+--------------------- + * xpcInvalidAddress | the address either received or | NULL or NA + * | sent by the specified partition| + * | is invalid | + * ---------------------+--------------------------------+--------------------- + * xpcBteNotAvailable | attempt to pull data from the | NULL or NA + * xpcBtePoisonError | specified partition over the | + * xpcBteWriteError | specified channel via a | + * xpcBteAccessError | bte_copy() failed | + * xpcBteTimeOutError | | + * xpcBteXtalkError | | + * xpcBteDirectoryError | | + * xpcBteGenericError | | + * xpcBteUnmappedError | | + * ---------------------+--------------------------------+--------------------- + * xpcUnknownReason | the specified channel to the | NULL or NA + * | specified partition was | + * | unavailable for unknown reasons| + * =====================+================================+===================== + */ + +typedef void (*xpc_channel_func)(enum xpc_retval reason, partid_t partid, + int ch_number, void *data, void *key); + +typedef void (*xpc_notify_func)(enum xpc_retval reason, partid_t partid, + int ch_number, void *key); + + +/* + * The following is a registration entry. There is a global array of these, + * one per channel. It is used to record the connection registration made + * by the users of XPC. As long as a registration entry exists, for any + * partition that comes up, XPC will attempt to establish a connection on + * that channel. Notification that a connection has been made will occur via + * the xpc_channel_func function. + * + * The 'func' field points to the function to call when aynchronous + * notification is required for such events as: a connection established/lost, + * or an incomming message received, or an error condition encountered. A + * non-NULL 'func' field indicates that there is an active registration for + * the channel. + */ +struct xpc_registration { + struct semaphore sema; + xpc_channel_func func; /* function to call */ + void *key; /* pointer to user's key */ + u16 nentries; /* #of msg entries in local msg queue */ + u16 msg_size; /* message queue's message size */ + u32 assigned_limit; /* limit on #of assigned kthreads */ + u32 idle_limit; /* limit on #of idle kthreads */ +} ____cacheline_aligned; + + +#define XPC_CHANNEL_REGISTERED(_c) (xpc_registrations[_c].func != NULL) + + +/* the following are valid xpc_allocate() flags */ +#define XPC_WAIT 0 /* wait flag */ +#define XPC_NOWAIT 1 /* no wait flag */ + + +struct xpc_interface { + void (*connect)(int); + void (*disconnect)(int); + enum xpc_retval (*allocate)(partid_t, int, u32, void **); + enum xpc_retval (*send)(partid_t, int, void *); + enum xpc_retval (*send_notify)(partid_t, int, void *, + xpc_notify_func, void *); + void (*received)(partid_t, int, void *); + enum xpc_retval (*partid_to_nasids)(partid_t, void *); +}; + + +extern struct xpc_interface xpc_interface; + +extern void xpc_set_interface(void (*)(int), + void (*)(int), + enum xpc_retval (*)(partid_t, int, u32, void **), + enum xpc_retval (*)(partid_t, int, void *), + enum xpc_retval (*)(partid_t, int, void *, xpc_notify_func, + void *), + void (*)(partid_t, int, void *), + enum xpc_retval (*)(partid_t, void *)); +extern void xpc_clear_interface(void); + + +extern enum xpc_retval xpc_connect(int, xpc_channel_func, void *, u16, + u16, u32, u32); +extern void xpc_disconnect(int); + +static inline enum xpc_retval +xpc_allocate(partid_t partid, int ch_number, u32 flags, void **payload) +{ + return xpc_interface.allocate(partid, ch_number, flags, payload); +} + +static inline enum xpc_retval +xpc_send(partid_t partid, int ch_number, void *payload) +{ + return xpc_interface.send(partid, ch_number, payload); +} + +static inline enum xpc_retval +xpc_send_notify(partid_t partid, int ch_number, void *payload, + xpc_notify_func func, void *key) +{ + return xpc_interface.send_notify(partid, ch_number, payload, func, key); +} + +static inline void +xpc_received(partid_t partid, int ch_number, void *payload) +{ + return xpc_interface.received(partid, ch_number, payload); +} + +static inline enum xpc_retval +xpc_partid_to_nasids(partid_t partid, void *nasids) +{ + return xpc_interface.partid_to_nasids(partid, nasids); +} + + +extern u64 xp_nofault_PIOR_target; +extern int xp_nofault_PIOR(void *); +extern int xp_error_PIOR(void); + + +#endif /* _ASM_IA64_SN_XP_H */ + diff --git a/include/asm-m32r/signal.h b/include/asm-m32r/signal.h index ce46eaea4494..95f69b191953 100644 --- a/include/asm-m32r/signal.h +++ b/include/asm-m32r/signal.h @@ -114,34 +114,7 @@ typedef unsigned long sigset_t; #define MINSIGSTKSZ 2048 #define SIGSTKSZ 8192 -#ifdef __KERNEL__ - -/* - * These values of sa_flags are used only by the kernel as part of the - * irq handling routines. - * - * SA_INTERRUPT is also used by the irq handling routines. - * SA_SHIRQ is for shared interrupt support on PCI and EISA. - */ -#define SA_PROBE SA_ONESHOT -#define SA_SAMPLE_RANDOM SA_RESTART -#define SA_SHIRQ 0x04000000 -#endif - -#define SIG_BLOCK 0 /* for blocking signals */ -#define SIG_UNBLOCK 1 /* for unblocking signals */ -#define SIG_SETMASK 2 /* for setting the signal mask */ - -/* Type of a signal handler. */ -typedef void __signalfn_t(int); -typedef __signalfn_t __user *__sighandler_t; - -typedef void __restorefn_t(void); -typedef __restorefn_t __user *__sigrestore_t; - -#define SIG_DFL ((__sighandler_t)0) /* default signal handling */ -#define SIG_IGN ((__sighandler_t)1) /* ignore signal */ -#define SIG_ERR ((__sighandler_t)-1) /* error return from signal */ +#include <asm-generic/signal.h> #ifdef __KERNEL__ struct old_sigaction { diff --git a/include/asm-m68k/bug.h b/include/asm-m68k/bug.h index 3e1d2266fa69..072ce274d537 100644 --- a/include/asm-m68k/bug.h +++ b/include/asm-m68k/bug.h @@ -3,6 +3,7 @@ #include <linux/config.h> +#ifdef CONFIG_BUG #ifdef CONFIG_DEBUG_BUGVERBOSE #ifndef CONFIG_SUN3 #define BUG() do { \ @@ -22,6 +23,8 @@ #endif #define HAVE_ARCH_BUG +#endif + #include <asm-generic/bug.h> #endif diff --git a/include/asm-m68k/signal.h b/include/asm-m68k/signal.h index 6681bb6a5523..a0cdf9082372 100644 --- a/include/asm-m68k/signal.h +++ b/include/asm-m68k/signal.h @@ -105,42 +105,20 @@ typedef unsigned long sigset_t; #define MINSIGSTKSZ 2048 #define SIGSTKSZ 8192 -#ifdef __KERNEL__ -/* - * These values of sa_flags are used only by the kernel as part of the - * irq handling routines. - * - * SA_INTERRUPT is also used by the irq handling routines. - * SA_SHIRQ is for shared interrupt support on PCI and EISA. - */ -#define SA_PROBE SA_ONESHOT -#define SA_SAMPLE_RANDOM SA_RESTART -#define SA_SHIRQ 0x04000000 -#endif - -#define SIG_BLOCK 0 /* for blocking signals */ -#define SIG_UNBLOCK 1 /* for unblocking signals */ -#define SIG_SETMASK 2 /* for setting the signal mask */ - -/* Type of a signal handler. */ -typedef void (*__sighandler_t)(int); - -#define SIG_DFL ((__sighandler_t)0) /* default signal handling */ -#define SIG_IGN ((__sighandler_t)1) /* ignore signal */ -#define SIG_ERR ((__sighandler_t)-1) /* error return from signal */ +#include <asm-generic/signal.h> #ifdef __KERNEL__ struct old_sigaction { __sighandler_t sa_handler; old_sigset_t sa_mask; unsigned long sa_flags; - void (*sa_restorer)(void); + __sigrestore_t sa_restorer; }; struct sigaction { __sighandler_t sa_handler; unsigned long sa_flags; - void (*sa_restorer)(void); + __sigrestore_t sa_restorer; sigset_t sa_mask; /* mask last for extensibility */ }; diff --git a/include/asm-m68knommu/MC68328.h b/include/asm-m68knommu/MC68328.h index 4f5a9845f5be..a337e56d09bf 100644 --- a/include/asm-m68knommu/MC68328.h +++ b/include/asm-m68knommu/MC68328.h @@ -993,7 +993,7 @@ typedef volatile struct { volatile unsigned short int pad1; volatile unsigned short int pad2; volatile unsigned short int pad3; -} m68328_uart __attribute__((packed)); +} __attribute__((packed)) m68328_uart; /********** diff --git a/include/asm-m68knommu/MC68EZ328.h b/include/asm-m68knommu/MC68EZ328.h index 801933da4c70..69b7f9139e5e 100644 --- a/include/asm-m68knommu/MC68EZ328.h +++ b/include/asm-m68knommu/MC68EZ328.h @@ -815,7 +815,7 @@ typedef volatile struct { volatile unsigned short int nipr; volatile unsigned short int pad1; volatile unsigned short int pad2; -} m68328_uart __attribute__((packed)); +} __attribute__((packed)) m68328_uart; /********** diff --git a/include/asm-m68knommu/MC68VZ328.h b/include/asm-m68knommu/MC68VZ328.h index df74322f37ed..2b9bf626a0a5 100644 --- a/include/asm-m68knommu/MC68VZ328.h +++ b/include/asm-m68knommu/MC68VZ328.h @@ -909,7 +909,7 @@ typedef struct { volatile unsigned short int nipr; volatile unsigned short int hmark; volatile unsigned short int unused; -} m68328_uart __attribute__((packed)); +} __attribute__((packed)) m68328_uart; diff --git a/include/asm-m68knommu/signal.h b/include/asm-m68knommu/signal.h index 486cbb0dc088..1d13187f6062 100644 --- a/include/asm-m68knommu/signal.h +++ b/include/asm-m68knommu/signal.h @@ -105,29 +105,7 @@ typedef unsigned long sigset_t; #define MINSIGSTKSZ 2048 #define SIGSTKSZ 8192 -#ifdef __KERNEL__ -/* - * These values of sa_flags are used only by the kernel as part of the - * irq handling routines. - * - * SA_INTERRUPT is also used by the irq handling routines. - * SA_SHIRQ is for shared interrupt support on PCI and EISA. - */ -#define SA_PROBE SA_ONESHOT -#define SA_SAMPLE_RANDOM SA_RESTART -#define SA_SHIRQ 0x04000000 -#endif - -#define SIG_BLOCK 0 /* for blocking signals */ -#define SIG_UNBLOCK 1 /* for unblocking signals */ -#define SIG_SETMASK 2 /* for setting the signal mask */ - -/* Type of a signal handler. */ -typedef void (*__sighandler_t)(int); - -#define SIG_DFL ((__sighandler_t)0) /* default signal handling */ -#define SIG_IGN ((__sighandler_t)1) /* ignore signal */ -#define SIG_ERR ((__sighandler_t)-1) /* error return from signal */ +#include <asm-generic/signal.h> #ifdef __KERNEL__ struct old_sigaction { diff --git a/include/asm-mips/bug.h b/include/asm-mips/bug.h index eb94bb96cfbc..3f594b440abc 100644 --- a/include/asm-mips/bug.h +++ b/include/asm-mips/bug.h @@ -3,12 +3,14 @@ #include <asm/break.h> +#ifdef CONFIG_BUG +#define HAVE_ARCH_BUG #define BUG() \ do { \ __asm__ __volatile__("break %0" : : "i" (BRK_BUG)); \ } while (0) +#endif -#define HAVE_ARCH_BUG #include <asm-generic/bug.h> #endif diff --git a/include/asm-mips/errno.h b/include/asm-mips/errno.h index 2b458f9538cd..3c0d840e4577 100644 --- a/include/asm-mips/errno.h +++ b/include/asm-mips/errno.h @@ -115,6 +115,10 @@ #define EKEYREVOKED 163 /* Key has been revoked */ #define EKEYREJECTED 164 /* Key was rejected by service */ +/* for robust mutexes */ +#define EOWNERDEAD 165 /* Owner died */ +#define ENOTRECOVERABLE 166 /* State not recoverable */ + #define EDQUOT 1133 /* Quota exceeded */ #ifdef __KERNEL__ diff --git a/include/asm-mips/siginfo.h b/include/asm-mips/siginfo.h index 8ddd3c99bcf7..a0e26e6c994d 100644 --- a/include/asm-mips/siginfo.h +++ b/include/asm-mips/siginfo.h @@ -11,8 +11,6 @@ #include <linux/config.h> -#define SIGEV_HEAD_SIZE (sizeof(long) + 2*sizeof(int)) -#define SIGEV_PAD_SIZE ((SIGEV_MAX_SIZE-SIGEV_HEAD_SIZE) / sizeof(int)) #undef __ARCH_SI_TRAPNO /* exception code needs to fill this ... */ #define HAVE_ARCH_SIGINFO_T diff --git a/include/asm-mips/signal.h b/include/asm-mips/signal.h index 994987db61be..f2c470f1d369 100644 --- a/include/asm-mips/signal.h +++ b/include/asm-mips/signal.h @@ -98,34 +98,12 @@ typedef unsigned long old_sigset_t; /* at least 32 bits */ #define MINSIGSTKSZ 2048 #define SIGSTKSZ 8192 -#ifdef __KERNEL__ - -/* - * These values of sa_flags are used only by the kernel as part of the - * irq handling routines. - * - * SA_INTERRUPT is also used by the irq handling routines. - * SA_SHIRQ flag is for shared interrupt support on PCI and EISA. - */ -#define SA_PROBE SA_ONESHOT -#define SA_SAMPLE_RANDOM SA_RESTART -#define SA_SHIRQ 0x02000000 - -#endif /* __KERNEL__ */ - #define SIG_BLOCK 1 /* for blocking signals */ #define SIG_UNBLOCK 2 /* for unblocking signals */ #define SIG_SETMASK 3 /* for setting the signal mask */ #define SIG_SETMASK32 256 /* Goodie from SGI for BSD compatibility: set only the low 32 bit of the sigset. */ - -/* Type of a signal handler. */ -typedef void (*__sighandler_t)(int); - -/* Fake signal functions */ -#define SIG_DFL ((__sighandler_t)0) /* default signal handling */ -#define SIG_IGN ((__sighandler_t)1) /* ignore signal */ -#define SIG_ERR ((__sighandler_t)-1) /* error return from signal */ +#include <asm-generic/signal.h> struct sigaction { unsigned int sa_flags; diff --git a/include/asm-parisc/bug.h b/include/asm-parisc/bug.h index e72f6e2b4b9f..695588da41f8 100644 --- a/include/asm-parisc/bug.h +++ b/include/asm-parisc/bug.h @@ -1,12 +1,14 @@ #ifndef _PARISC_BUG_H #define _PARISC_BUG_H +#ifdef CONFIG_BUG #define HAVE_ARCH_BUG #define BUG() do { \ printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__); \ dump_stack(); \ panic("BUG!"); \ } while (0) +#endif #include <asm-generic/bug.h> #endif diff --git a/include/asm-parisc/errno.h b/include/asm-parisc/errno.h index a10f109770f1..08464c405471 100644 --- a/include/asm-parisc/errno.h +++ b/include/asm-parisc/errno.h @@ -115,5 +115,9 @@ #define ENOTSUP 252 /* Function not implemented (POSIX.4 / HPUX) */ #define ECANCELLED 253 /* aio request was canceled before complete (POSIX.4 / HPUX) */ +/* for robust mutexes */ +#define EOWNERDEAD 254 /* Owner died */ +#define ENOTRECOVERABLE 255 /* State not recoverable */ + #endif diff --git a/include/asm-parisc/floppy.h b/include/asm-parisc/floppy.h index 47f53df2cef5..ca3aed768cdc 100644 --- a/include/asm-parisc/floppy.h +++ b/include/asm-parisc/floppy.h @@ -235,7 +235,7 @@ static int hard_dma_setup(char *addr, unsigned long size, int mode, int io) return 0; } -struct fd_routine_l { +static struct fd_routine_l { int (*_request_dma)(unsigned int dmanr, const char * device_id); void (*_free_dma)(unsigned int dmanr); int (*_get_dma_residue)(unsigned int dummy); diff --git a/include/asm-parisc/signal.h b/include/asm-parisc/signal.h index 358f577c8eb8..25cb23ef7dd1 100644 --- a/include/asm-parisc/signal.h +++ b/include/asm-parisc/signal.h @@ -89,17 +89,6 @@ #define _NSIG_BPW BITS_PER_LONG #define _NSIG_WORDS (_NSIG / _NSIG_BPW) -/* - * These values of sa_flags are used only by the kernel as part of the - * irq handling routines. - * - * SA_INTERRUPT is also used by the irq handling routines. - * SA_SHIRQ is for shared interrupt support on PCI and EISA. - */ -#define SA_PROBE SA_ONESHOT -#define SA_SAMPLE_RANDOM SA_RESTART -#define SA_SHIRQ 0x04000000 - #endif /* __KERNEL__ */ #define SIG_BLOCK 0 /* for blocking signals */ diff --git a/include/asm-parisc/uaccess.h b/include/asm-parisc/uaccess.h index 8a08423b7570..c1b5bdea53ee 100644 --- a/include/asm-parisc/uaccess.h +++ b/include/asm-parisc/uaccess.h @@ -24,7 +24,7 @@ /* * Note that since kernel addresses are in a separate address space on - * parisc, we don't need to do anything for access_ok() or verify_area(). + * parisc, we don't need to do anything for access_ok(). * We just let the page fault handler do the right thing. This also means * that put_user is the same as __put_user, etc. */ diff --git a/include/asm-ppc/bug.h b/include/asm-ppc/bug.h index e99c6cb9d618..8b34fd682b0d 100644 --- a/include/asm-ppc/bug.h +++ b/include/asm-ppc/bug.h @@ -14,6 +14,7 @@ struct bug_entry { */ #define BUG_WARNING_TRAP 0x1000000 +#ifdef CONFIG_BUG #define BUG() do { \ __asm__ __volatile__( \ "1: twi 31,0,0\n" \ @@ -50,6 +51,8 @@ struct bug_entry { #define HAVE_ARCH_BUG #define HAVE_ARCH_BUG_ON #define HAVE_ARCH_WARN_ON +#endif + #include <asm-generic/bug.h> #endif diff --git a/include/asm-ppc/hydra.h b/include/asm-ppc/hydra.h index 1134431431da..833a8aff2a80 100644 --- a/include/asm-ppc/hydra.h +++ b/include/asm-ppc/hydra.h @@ -51,7 +51,7 @@ struct Hydra { char OpenPIC[0x40000]; }; -extern volatile struct Hydra *Hydra; +extern volatile struct Hydra __iomem *Hydra; /* diff --git a/include/asm-ppc/pci-bridge.h b/include/asm-ppc/pci-bridge.h index 78e9be619f14..ffa423456c2b 100644 --- a/include/asm-ppc/pci-bridge.h +++ b/include/asm-ppc/pci-bridge.h @@ -12,7 +12,7 @@ struct pci_controller; * pci_io_base returns the memory address at which you can access * the I/O space for PCI bus number `bus' (or NULL on error). */ -extern void *pci_bus_io_base(unsigned int bus); +extern void __iomem *pci_bus_io_base(unsigned int bus); extern unsigned long pci_bus_io_base_phys(unsigned int bus); extern unsigned long pci_bus_mem_base_phys(unsigned int bus); @@ -48,7 +48,7 @@ struct pci_controller { int last_busno; int bus_offset; - void *io_base_virt; + void __iomem *io_base_virt; unsigned long io_base_phys; /* Some machines (PReP) have a non 1:1 mapping of diff --git a/include/asm-ppc/pmac_feature.h b/include/asm-ppc/pmac_feature.h index 639b690ce6f7..8beb162873f4 100644 --- a/include/asm-ppc/pmac_feature.h +++ b/include/asm-ppc/pmac_feature.h @@ -316,6 +316,9 @@ extern void pmac_register_agp_pm(struct pci_dev *bridge, extern void pmac_suspend_agp_for_card(struct pci_dev *dev); extern void pmac_resume_agp_for_card(struct pci_dev *dev); +/* Used by the via-pmu driver for suspend/resume + */ +extern void pmac_tweak_clock_spreading(int enable); /* * The part below is for use by macio_asic.c only, do not rely diff --git a/include/asm-ppc/reg_booke.h b/include/asm-ppc/reg_booke.h index e70c25f3c339..45c5e6f2b7ab 100644 --- a/include/asm-ppc/reg_booke.h +++ b/include/asm-ppc/reg_booke.h @@ -305,6 +305,7 @@ do { \ #define ESR_PIL 0x08000000 /* Program Exception - Illegal */ #define ESR_PPR 0x04000000 /* Program Exception - Priveleged */ #define ESR_PTR 0x02000000 /* Program Exception - Trap */ +#define ESR_FP 0x01000000 /* Floating Point Operation */ #define ESR_DST 0x00800000 /* Storage Exception - Data miss */ #define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */ #define ESR_ST 0x00800000 /* Store Operation */ diff --git a/include/asm-ppc/sigcontext.h b/include/asm-ppc/sigcontext.h index fc5e358c65f1..f82dcccdee1e 100644 --- a/include/asm-ppc/sigcontext.h +++ b/include/asm-ppc/sigcontext.h @@ -9,7 +9,7 @@ struct sigcontext { int signal; unsigned long handler; unsigned long oldmask; - struct pt_regs *regs; + struct pt_regs __user *regs; }; #endif diff --git a/include/asm-ppc/signal.h b/include/asm-ppc/signal.h index 8cc8b88d4edd..caf6ede3710f 100644 --- a/include/asm-ppc/signal.h +++ b/include/asm-ppc/signal.h @@ -99,34 +99,8 @@ typedef struct { #define MINSIGSTKSZ 2048 #define SIGSTKSZ 8192 -#ifdef __KERNEL__ - -/* - * These values of sa_flags are used only by the kernel as part of the - * irq handling routines. - * - * SA_INTERRUPT is also used by the irq handling routines. - * SA_SHIRQ is for shared interrupt support on PCI and EISA. - */ -#define SA_PROBE SA_ONESHOT -#define SA_SAMPLE_RANDOM SA_RESTART -#define SA_SHIRQ 0x04000000 -#endif /* __KERNEL__ */ - -#define SIG_BLOCK 0 /* for blocking signals */ -#define SIG_UNBLOCK 1 /* for unblocking signals */ -#define SIG_SETMASK 2 /* for setting the signal mask */ - -/* Type of a signal handler. */ -typedef void __signalfn_t(int); -typedef __signalfn_t __user *__sighandler_t; - -typedef void __restorefn_t(void); -typedef __restorefn_t __user *__sigrestore_t; -#define SIG_DFL ((__sighandler_t)0) /* default signal handling */ -#define SIG_IGN ((__sighandler_t)1) /* ignore signal */ -#define SIG_ERR ((__sighandler_t)-1) /* error return from signal */ +#include <asm-generic/signal.h> struct old_sigaction { __sighandler_t sa_handler; diff --git a/include/asm-ppc64/a.out.h b/include/asm-ppc64/a.out.h index 802338efcb19..3871e252a6f1 100644 --- a/include/asm-ppc64/a.out.h +++ b/include/asm-ppc64/a.out.h @@ -1,8 +1,6 @@ #ifndef __PPC64_A_OUT_H__ #define __PPC64_A_OUT_H__ -#include <asm/ppcdebug.h> - /* * c 2001 PPC 64 Team, IBM Corp * diff --git a/include/asm-ppc64/bug.h b/include/asm-ppc64/bug.h index db31dd22233c..169868fa307d 100644 --- a/include/asm-ppc64/bug.h +++ b/include/asm-ppc64/bug.h @@ -26,6 +26,8 @@ struct bug_entry *find_bug(unsigned long bugaddr); */ #define BUG_WARNING_TRAP 0x1000000 +#ifdef CONFIG_BUG + #define BUG() do { \ __asm__ __volatile__( \ "1: twi 31,0,0\n" \ @@ -55,11 +57,12 @@ struct bug_entry *find_bug(unsigned long bugaddr); "i" (__FILE__), "i" (__FUNCTION__)); \ } while (0) -#endif - #define HAVE_ARCH_BUG #define HAVE_ARCH_BUG_ON #define HAVE_ARCH_WARN_ON +#endif +#endif + #include <asm-generic/bug.h> #endif diff --git a/include/asm-ppc64/elf.h b/include/asm-ppc64/elf.h index 8457d90244fb..6c42d61bedd1 100644 --- a/include/asm-ppc64/elf.h +++ b/include/asm-ppc64/elf.h @@ -229,9 +229,13 @@ do { \ /* * An executable for which elf_read_implies_exec() returns TRUE will - * have the READ_IMPLIES_EXEC personality flag set automatically. + * have the READ_IMPLIES_EXEC personality flag set automatically. This + * is only required to work around bugs in old 32bit toolchains. Since + * the 64bit ABI has never had these issues dont enable the workaround + * even if we have an executable stack. */ -#define elf_read_implies_exec(ex, exec_stk) (exec_stk != EXSTACK_DISABLE_X) +#define elf_read_implies_exec(ex, exec_stk) (test_thread_flag(TIF_32BIT) ? \ + (exec_stk != EXSTACK_DISABLE_X) : 0) #endif diff --git a/include/asm-ppc64/imalloc.h b/include/asm-ppc64/imalloc.h new file mode 100644 index 000000000000..3a45e918bf16 --- /dev/null +++ b/include/asm-ppc64/imalloc.h @@ -0,0 +1,24 @@ +#ifndef _PPC64_IMALLOC_H +#define _PPC64_IMALLOC_H + +/* + * Define the address range of the imalloc VM area. + */ +#define PHBS_IO_BASE IOREGIONBASE +#define IMALLOC_BASE (IOREGIONBASE + 0x80000000ul) /* Reserve 2 gigs for PHBs */ +#define IMALLOC_END (IOREGIONBASE + EADDR_MASK) + + +/* imalloc region types */ +#define IM_REGION_UNUSED 0x1 +#define IM_REGION_SUBSET 0x2 +#define IM_REGION_EXISTS 0x4 +#define IM_REGION_OVERLAP 0x8 +#define IM_REGION_SUPERSET 0x10 + +extern struct vm_struct * im_get_free_area(unsigned long size); +extern struct vm_struct * im_get_area(unsigned long v_addr, unsigned long size, + int region_type); +unsigned long im_free(void *addr); + +#endif /* _PPC64_IMALLOC_H */ diff --git a/include/asm-ppc64/mmu.h b/include/asm-ppc64/mmu.h index 188987e9d9d4..c78282a67d8e 100644 --- a/include/asm-ppc64/mmu.h +++ b/include/asm-ppc64/mmu.h @@ -15,19 +15,10 @@ #include <linux/config.h> #include <asm/page.h> -#include <linux/stringify.h> -#ifndef __ASSEMBLY__ - -/* Time to allow for more things here */ -typedef unsigned long mm_context_id_t; -typedef struct { - mm_context_id_t id; -#ifdef CONFIG_HUGETLB_PAGE - pgd_t *huge_pgdir; - u16 htlb_segs; /* bitmask */ -#endif -} mm_context_t; +/* + * Segment table + */ #define STE_ESID_V 0x80 #define STE_ESID_KS 0x20 @@ -36,15 +27,48 @@ typedef struct { #define STE_VSID_SHIFT 12 -struct stab_entry { - unsigned long esid_data; - unsigned long vsid_data; -}; +/* Location of cpu0's segment table */ +#define STAB0_PAGE 0x9 +#define STAB0_PHYS_ADDR (STAB0_PAGE<<PAGE_SHIFT) +#define STAB0_VIRT_ADDR (KERNELBASE+STAB0_PHYS_ADDR) + +/* + * SLB + */ -/* Hardware Page Table Entry */ +#define SLB_NUM_BOLTED 3 +#define SLB_CACHE_ENTRIES 8 + +/* Bits in the SLB ESID word */ +#define SLB_ESID_V ASM_CONST(0x0000000008000000) /* valid */ + +/* Bits in the SLB VSID word */ +#define SLB_VSID_SHIFT 12 +#define SLB_VSID_KS ASM_CONST(0x0000000000000800) +#define SLB_VSID_KP ASM_CONST(0x0000000000000400) +#define SLB_VSID_N ASM_CONST(0x0000000000000200) /* no-execute */ +#define SLB_VSID_L ASM_CONST(0x0000000000000100) /* largepage 16M */ +#define SLB_VSID_C ASM_CONST(0x0000000000000080) /* class */ + +#define SLB_VSID_KERNEL (SLB_VSID_KP|SLB_VSID_C) +#define SLB_VSID_USER (SLB_VSID_KP|SLB_VSID_KS) + +/* + * Hash table + */ #define HPTES_PER_GROUP 8 +/* Values for PP (assumes Ks=0, Kp=1) */ +/* pp0 will always be 0 for linux */ +#define PP_RWXX 0 /* Supervisor read/write, User none */ +#define PP_RWRX 1 /* Supervisor read/write, User read */ +#define PP_RWRW 2 /* Supervisor read/write, User read/write */ +#define PP_RXRX 3 /* Supervisor read, User read */ + +#ifndef __ASSEMBLY__ + +/* Hardware Page Table Entry */ typedef struct { unsigned long avpn:57; /* vsid | api == avpn */ unsigned long : 2; /* Software use */ @@ -90,14 +114,6 @@ typedef struct { } dw1; } HPTE; -/* Values for PP (assumes Ks=0, Kp=1) */ -/* pp0 will always be 0 for linux */ -#define PP_RWXX 0 /* Supervisor read/write, User none */ -#define PP_RWRX 1 /* Supervisor read/write, User read */ -#define PP_RWRW 2 /* Supervisor read/write, User read/write */ -#define PP_RXRX 3 /* Supervisor read, User read */ - - extern HPTE * htab_address; extern unsigned long htab_hash_mask; @@ -174,31 +190,70 @@ extern int __hash_page(unsigned long ea, unsigned long access, extern void htab_finish_init(void); +extern void hpte_init_native(void); +extern void hpte_init_lpar(void); +extern void hpte_init_iSeries(void); + +extern long pSeries_lpar_hpte_insert(unsigned long hpte_group, + unsigned long va, unsigned long prpn, + int secondary, unsigned long hpteflags, + int bolted, int large); +extern long native_hpte_insert(unsigned long hpte_group, unsigned long va, + unsigned long prpn, int secondary, + unsigned long hpteflags, int bolted, int large); + #endif /* __ASSEMBLY__ */ /* - * Location of cpu0's segment table + * VSID allocation + * + * We first generate a 36-bit "proto-VSID". For kernel addresses this + * is equal to the ESID, for user addresses it is: + * (context << 15) | (esid & 0x7fff) + * + * The two forms are distinguishable because the top bit is 0 for user + * addresses, whereas the top two bits are 1 for kernel addresses. + * Proto-VSIDs with the top two bits equal to 0b10 are reserved for + * now. + * + * The proto-VSIDs are then scrambled into real VSIDs with the + * multiplicative hash: + * + * VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS + * where VSID_MULTIPLIER = 268435399 = 0xFFFFFC7 + * VSID_MODULUS = 2^36-1 = 0xFFFFFFFFF + * + * This scramble is only well defined for proto-VSIDs below + * 0xFFFFFFFFF, so both proto-VSID and actual VSID 0xFFFFFFFFF are + * reserved. VSID_MULTIPLIER is prime, so in particular it is + * co-prime to VSID_MODULUS, making this a 1:1 scrambling function. + * Because the modulus is 2^n-1 we can compute it efficiently without + * a divide or extra multiply (see below). + * + * This scheme has several advantages over older methods: + * + * - We have VSIDs allocated for every kernel address + * (i.e. everything above 0xC000000000000000), except the very top + * segment, which simplifies several things. + * + * - We allow for 15 significant bits of ESID and 20 bits of + * context for user addresses. i.e. 8T (43 bits) of address space for + * up to 1M contexts (although the page table structure and context + * allocation will need changes to take advantage of this). + * + * - The scramble function gives robust scattering in the hash + * table (at least based on some initial results). The previous + * method was more susceptible to pathological cases giving excessive + * hash collisions. + */ +/* + * WARNING - If you change these you must make sure the asm + * implementations in slb_allocate (slb_low.S), do_stab_bolted + * (head.S) and ASM_VSID_SCRAMBLE (below) are changed accordingly. + * + * You'll also need to change the precomputed VSID values in head.S + * which are used by the iSeries firmware. */ -#define STAB0_PAGE 0x9 -#define STAB0_PHYS_ADDR (STAB0_PAGE<<PAGE_SHIFT) -#define STAB0_VIRT_ADDR (KERNELBASE+STAB0_PHYS_ADDR) - -#define SLB_NUM_BOLTED 3 -#define SLB_CACHE_ENTRIES 8 - -/* Bits in the SLB ESID word */ -#define SLB_ESID_V 0x0000000008000000 /* entry is valid */ - -/* Bits in the SLB VSID word */ -#define SLB_VSID_SHIFT 12 -#define SLB_VSID_KS 0x0000000000000800 -#define SLB_VSID_KP 0x0000000000000400 -#define SLB_VSID_N 0x0000000000000200 /* no-execute */ -#define SLB_VSID_L 0x0000000000000100 /* largepage (4M) */ -#define SLB_VSID_C 0x0000000000000080 /* class */ - -#define SLB_VSID_KERNEL (SLB_VSID_KP|SLB_VSID_C) -#define SLB_VSID_USER (SLB_VSID_KP|SLB_VSID_KS) #define VSID_MULTIPLIER ASM_CONST(200730139) /* 28-bit prime */ #define VSID_BITS 36 @@ -239,4 +294,50 @@ extern void htab_finish_init(void); srdi rx,rx,VSID_BITS; /* extract 2^36 bit */ \ add rt,rt,rx + +#ifndef __ASSEMBLY__ + +typedef unsigned long mm_context_id_t; + +typedef struct { + mm_context_id_t id; +#ifdef CONFIG_HUGETLB_PAGE + pgd_t *huge_pgdir; + u16 htlb_segs; /* bitmask */ +#endif +} mm_context_t; + + +static inline unsigned long vsid_scramble(unsigned long protovsid) +{ +#if 0 + /* The code below is equivalent to this function for arguments + * < 2^VSID_BITS, which is all this should ever be called + * with. However gcc is not clever enough to compute the + * modulus (2^n-1) without a second multiply. */ + return ((protovsid * VSID_MULTIPLIER) % VSID_MODULUS); +#else /* 1 */ + unsigned long x; + + x = protovsid * VSID_MULTIPLIER; + x = (x >> VSID_BITS) + (x & VSID_MODULUS); + return (x + ((x+1) >> VSID_BITS)) & VSID_MODULUS; +#endif /* 1 */ +} + +/* This is only valid for addresses >= KERNELBASE */ +static inline unsigned long get_kernel_vsid(unsigned long ea) +{ + return vsid_scramble(ea >> SID_SHIFT); +} + +/* This is only valid for user addresses (which are below 2^41) */ +static inline unsigned long get_vsid(unsigned long context, unsigned long ea) +{ + return vsid_scramble((context << USER_ESID_BITS) + | (ea >> SID_SHIFT)); +} + +#endif /* __ASSEMBLY */ + #endif /* _PPC64_MMU_H_ */ diff --git a/include/asm-ppc64/mmu_context.h b/include/asm-ppc64/mmu_context.h index c2e8e0466383..77a743402db4 100644 --- a/include/asm-ppc64/mmu_context.h +++ b/include/asm-ppc64/mmu_context.h @@ -84,86 +84,4 @@ static inline void activate_mm(struct mm_struct *prev, struct mm_struct *next) local_irq_restore(flags); } -/* VSID allocation - * =============== - * - * We first generate a 36-bit "proto-VSID". For kernel addresses this - * is equal to the ESID, for user addresses it is: - * (context << 15) | (esid & 0x7fff) - * - * The two forms are distinguishable because the top bit is 0 for user - * addresses, whereas the top two bits are 1 for kernel addresses. - * Proto-VSIDs with the top two bits equal to 0b10 are reserved for - * now. - * - * The proto-VSIDs are then scrambled into real VSIDs with the - * multiplicative hash: - * - * VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS - * where VSID_MULTIPLIER = 268435399 = 0xFFFFFC7 - * VSID_MODULUS = 2^36-1 = 0xFFFFFFFFF - * - * This scramble is only well defined for proto-VSIDs below - * 0xFFFFFFFFF, so both proto-VSID and actual VSID 0xFFFFFFFFF are - * reserved. VSID_MULTIPLIER is prime, so in particular it is - * co-prime to VSID_MODULUS, making this a 1:1 scrambling function. - * Because the modulus is 2^n-1 we can compute it efficiently without - * a divide or extra multiply (see below). - * - * This scheme has several advantages over older methods: - * - * - We have VSIDs allocated for every kernel address - * (i.e. everything above 0xC000000000000000), except the very top - * segment, which simplifies several things. - * - * - We allow for 15 significant bits of ESID and 20 bits of - * context for user addresses. i.e. 8T (43 bits) of address space for - * up to 1M contexts (although the page table structure and context - * allocation will need changes to take advantage of this). - * - * - The scramble function gives robust scattering in the hash - * table (at least based on some initial results). The previous - * method was more susceptible to pathological cases giving excessive - * hash collisions. - */ - -/* - * WARNING - If you change these you must make sure the asm - * implementations in slb_allocate(), do_stab_bolted and mmu.h - * (ASM_VSID_SCRAMBLE macro) are changed accordingly. - * - * You'll also need to change the precomputed VSID values in head.S - * which are used by the iSeries firmware. - */ - -static inline unsigned long vsid_scramble(unsigned long protovsid) -{ -#if 0 - /* The code below is equivalent to this function for arguments - * < 2^VSID_BITS, which is all this should ever be called - * with. However gcc is not clever enough to compute the - * modulus (2^n-1) without a second multiply. */ - return ((protovsid * VSID_MULTIPLIER) % VSID_MODULUS); -#else /* 1 */ - unsigned long x; - - x = protovsid * VSID_MULTIPLIER; - x = (x >> VSID_BITS) + (x & VSID_MODULUS); - return (x + ((x+1) >> VSID_BITS)) & VSID_MODULUS; -#endif /* 1 */ -} - -/* This is only valid for addresses >= KERNELBASE */ -static inline unsigned long get_kernel_vsid(unsigned long ea) -{ - return vsid_scramble(ea >> SID_SHIFT); -} - -/* This is only valid for user addresses (which are below 2^41) */ -static inline unsigned long get_vsid(unsigned long context, unsigned long ea) -{ - return vsid_scramble((context << USER_ESID_BITS) - | (ea >> SID_SHIFT)); -} - #endif /* __PPC64_MMU_CONTEXT_H */ diff --git a/include/asm-ppc64/page.h b/include/asm-ppc64/page.h index 20e0f19324e8..bcd21789d3b7 100644 --- a/include/asm-ppc64/page.h +++ b/include/asm-ppc64/page.h @@ -23,7 +23,6 @@ #define PAGE_SHIFT 12 #define PAGE_SIZE (ASM_CONST(1) << PAGE_SHIFT) #define PAGE_MASK (~(PAGE_SIZE-1)) -#define PAGE_OFFSET_MASK (PAGE_SIZE-1) #define SID_SHIFT 28 #define SID_MASK 0xfffffffffUL @@ -85,9 +84,6 @@ /* align addr on a size boundary - adjust address up if needed */ #define _ALIGN(addr,size) _ALIGN_UP(addr,size) -/* to align the pointer to the (next) double word boundary */ -#define DOUBLEWORD_ALIGN(addr) _ALIGN(addr,sizeof(unsigned long)) - /* to align the pointer to the (next) page boundary */ #define PAGE_ALIGN(addr) _ALIGN(addr, PAGE_SIZE) @@ -100,7 +96,6 @@ #define REGION_SIZE 4UL #define REGION_SHIFT 60UL #define REGION_MASK (((1UL<<REGION_SIZE)-1UL)<<REGION_SHIFT) -#define REGION_STRIDE (1UL << REGION_SHIFT) static __inline__ void clear_page(void *addr) { @@ -209,13 +204,13 @@ extern u64 ppc64_pft_size; /* Log 2 of page table size */ #define VMALLOCBASE ASM_CONST(0xD000000000000000) #define IOREGIONBASE ASM_CONST(0xE000000000000000) -#define IO_REGION_ID (IOREGIONBASE>>REGION_SHIFT) -#define VMALLOC_REGION_ID (VMALLOCBASE>>REGION_SHIFT) -#define KERNEL_REGION_ID (KERNELBASE>>REGION_SHIFT) +#define IO_REGION_ID (IOREGIONBASE >> REGION_SHIFT) +#define VMALLOC_REGION_ID (VMALLOCBASE >> REGION_SHIFT) +#define KERNEL_REGION_ID (KERNELBASE >> REGION_SHIFT) #define USER_REGION_ID (0UL) -#define REGION_ID(X) (((unsigned long)(X))>>REGION_SHIFT) +#define REGION_ID(ea) (((unsigned long)(ea)) >> REGION_SHIFT) -#define __bpn_to_ba(x) ((((unsigned long)(x))<<PAGE_SHIFT) + KERNELBASE) +#define __bpn_to_ba(x) ((((unsigned long)(x)) << PAGE_SHIFT) + KERNELBASE) #define __ba_to_bpn(x) ((((unsigned long)(x)) & ~REGION_MASK) >> PAGE_SHIFT) #define __va(x) ((void *)((unsigned long)(x) + KERNELBASE)) @@ -252,10 +247,19 @@ extern u64 ppc64_pft_size; /* Log 2 of page table size */ /* * This is the default if a program doesn't have a PT_GNU_STACK - * program header entry. + * program header entry. The PPC64 ELF ABI has a non executable stack + * stack by default, so in the absense of a PT_GNU_STACK program header + * we turn execute permission off. */ -#define VM_STACK_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ - VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) +#define VM_STACK_DEFAULT_FLAGS32 (VM_READ | VM_WRITE | VM_EXEC | \ + VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) + +#define VM_STACK_DEFAULT_FLAGS64 (VM_READ | VM_WRITE | \ + VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) + +#define VM_STACK_DEFAULT_FLAGS \ + (test_thread_flag(TIF_32BIT) ? \ + VM_STACK_DEFAULT_FLAGS32 : VM_STACK_DEFAULT_FLAGS64) #endif /* __KERNEL__ */ #endif /* _PPC64_PAGE_H */ diff --git a/include/asm-ppc64/pgalloc.h b/include/asm-ppc64/pgalloc.h index 16232d740173..4fc4b739b380 100644 --- a/include/asm-ppc64/pgalloc.h +++ b/include/asm-ppc64/pgalloc.h @@ -27,7 +27,7 @@ pgd_free(pgd_t *pgd) kmem_cache_free(zero_cache, pgd); } -#define pgd_populate(MM, PGD, PMD) pgd_set(PGD, PMD) +#define pud_populate(MM, PUD, PMD) pud_set(PUD, PMD) static inline pmd_t * pmd_alloc_one(struct mm_struct *mm, unsigned long addr) diff --git a/include/asm-ppc64/pgtable.h b/include/asm-ppc64/pgtable.h index a26120517c54..264c4f7993be 100644 --- a/include/asm-ppc64/pgtable.h +++ b/include/asm-ppc64/pgtable.h @@ -1,8 +1,6 @@ #ifndef _PPC64_PGTABLE_H #define _PPC64_PGTABLE_H -#include <asm-generic/4level-fixup.h> - /* * This file contains the functions and defines necessary to modify and use * the ppc64 hashed page table. @@ -17,15 +15,7 @@ #include <asm/tlbflush.h> #endif /* __ASSEMBLY__ */ -/* PMD_SHIFT determines what a second-level page table entry can map */ -#define PMD_SHIFT (PAGE_SHIFT + PAGE_SHIFT - 3) -#define PMD_SIZE (1UL << PMD_SHIFT) -#define PMD_MASK (~(PMD_SIZE-1)) - -/* PGDIR_SHIFT determines what a third-level page table entry can map */ -#define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT - 3) + (PAGE_SHIFT - 2)) -#define PGDIR_SIZE (1UL << PGDIR_SHIFT) -#define PGDIR_MASK (~(PGDIR_SIZE-1)) +#include <asm-generic/pgtable-nopud.h> /* * Entries per page directory level. The PTE level must use a 64b record @@ -40,40 +30,30 @@ #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) -#define USER_PTRS_PER_PGD (1024) -#define FIRST_USER_ADDRESS 0 +/* PMD_SHIFT determines what a second-level page table entry can map */ +#define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) +#define PMD_SIZE (1UL << PMD_SHIFT) +#define PMD_MASK (~(PMD_SIZE-1)) -#define EADDR_SIZE (PTE_INDEX_SIZE + PMD_INDEX_SIZE + \ - PGD_INDEX_SIZE + PAGE_SHIFT) +/* PGDIR_SHIFT determines what a third-level page table entry can map */ +#define PGDIR_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE) +#define PGDIR_SIZE (1UL << PGDIR_SHIFT) +#define PGDIR_MASK (~(PGDIR_SIZE-1)) + +#define FIRST_USER_ADDRESS 0 /* * Size of EA range mapped by our pagetables. */ -#define PGTABLE_EA_BITS 41 -#define PGTABLE_EA_MASK ((1UL<<PGTABLE_EA_BITS)-1) +#define EADDR_SIZE (PTE_INDEX_SIZE + PMD_INDEX_SIZE + \ + PGD_INDEX_SIZE + PAGE_SHIFT) +#define EADDR_MASK ((1UL << EADDR_SIZE) - 1) /* * Define the address range of the vmalloc VM area. */ #define VMALLOC_START (0xD000000000000000ul) -#define VMALLOC_END (VMALLOC_START + PGTABLE_EA_MASK) - -/* - * Define the address range of the imalloc VM area. - * (used for ioremap) - */ -#define IMALLOC_START (ioremap_bot) -#define IMALLOC_VMADDR(x) ((unsigned long)(x)) -#define PHBS_IO_BASE (0xE000000000000000ul) /* Reserve 2 gigs for PHBs */ -#define IMALLOC_BASE (0xE000000080000000ul) -#define IMALLOC_END (IMALLOC_BASE + PGTABLE_EA_MASK) - -/* - * Define the user address range - */ -#define USER_START (0UL) -#define USER_END (USER_START + PGTABLE_EA_MASK) - +#define VMALLOC_END (VMALLOC_START + EADDR_MASK) /* * Bits in a linux-style PTE. These match the bits in the @@ -168,10 +148,6 @@ extern unsigned long empty_zero_page[PAGE_SIZE/sizeof(unsigned long)]; /* shift to put page number into pte */ #define PTE_SHIFT (17) -/* We allow 2^41 bytes of real memory, so we need 29 bits in the PMD - * to give the PTE page number. The bottom two bits are for flags. */ -#define PMD_TO_PTEPAGE_SHIFT (2) - #ifdef CONFIG_HUGETLB_PAGE #ifndef __ASSEMBLY__ @@ -200,13 +176,14 @@ void hugetlb_mm_free_pgd(struct mm_struct *mm); */ #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) -#define pfn_pte(pfn,pgprot) \ -({ \ - pte_t pte; \ - pte_val(pte) = ((unsigned long)(pfn) << PTE_SHIFT) | \ - pgprot_val(pgprot); \ - pte; \ -}) +static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) +{ + pte_t pte; + + + pte_val(pte) = (pfn << PTE_SHIFT) | pgprot_val(pgprot); + return pte; +} #define pte_modify(_pte, newprot) \ (__pte((pte_val(_pte) & _PAGE_CHG_MASK) | pgprot_val(newprot))) @@ -220,20 +197,20 @@ void hugetlb_mm_free_pgd(struct mm_struct *mm); #define pte_page(x) pfn_to_page(pte_pfn(x)) #define pmd_set(pmdp, ptep) \ - (pmd_val(*(pmdp)) = (__ba_to_bpn(ptep) << PMD_TO_PTEPAGE_SHIFT)) + (pmd_val(*(pmdp)) = __ba_to_bpn(ptep)) #define pmd_none(pmd) (!pmd_val(pmd)) #define pmd_bad(pmd) (pmd_val(pmd) == 0) #define pmd_present(pmd) (pmd_val(pmd) != 0) #define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0) -#define pmd_page_kernel(pmd) \ - (__bpn_to_ba(pmd_val(pmd) >> PMD_TO_PTEPAGE_SHIFT)) +#define pmd_page_kernel(pmd) (__bpn_to_ba(pmd_val(pmd))) #define pmd_page(pmd) virt_to_page(pmd_page_kernel(pmd)) -#define pgd_set(pgdp, pmdp) (pgd_val(*(pgdp)) = (__ba_to_bpn(pmdp))) -#define pgd_none(pgd) (!pgd_val(pgd)) -#define pgd_bad(pgd) ((pgd_val(pgd)) == 0) -#define pgd_present(pgd) (pgd_val(pgd) != 0UL) -#define pgd_clear(pgdp) (pgd_val(*(pgdp)) = 0UL) -#define pgd_page(pgd) (__bpn_to_ba(pgd_val(pgd))) + +#define pud_set(pudp, pmdp) (pud_val(*(pudp)) = (__ba_to_bpn(pmdp))) +#define pud_none(pud) (!pud_val(pud)) +#define pud_bad(pud) ((pud_val(pud)) == 0UL) +#define pud_present(pud) (pud_val(pud) != 0UL) +#define pud_clear(pudp) (pud_val(*(pudp)) = 0UL) +#define pud_page(pud) (__bpn_to_ba(pud_val(pud))) /* * Find an entry in a page-table-directory. We combine the address region @@ -245,12 +222,13 @@ void hugetlb_mm_free_pgd(struct mm_struct *mm); #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) /* Find an entry in the second-level page table.. */ -#define pmd_offset(dir,addr) \ - ((pmd_t *) pgd_page(*(dir)) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))) +#define pmd_offset(pudp,addr) \ + ((pmd_t *) pud_page(*(pudp)) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))) /* Find an entry in the third-level page table.. */ #define pte_offset_kernel(dir,addr) \ - ((pte_t *) pmd_page_kernel(*(dir)) + (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))) + ((pte_t *) pmd_page_kernel(*(dir)) \ + + (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))) #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr)) #define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr)) @@ -264,8 +242,6 @@ void hugetlb_mm_free_pgd(struct mm_struct *mm); /* to find an entry in the ioremap page-table-directory */ #define pgd_offset_i(address) (ioremap_pgd + pgd_index(address)) -#define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT)) - /* * The following only work if pte_present() is true. * Undefined behaviour if not.. @@ -440,7 +416,7 @@ static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_clear(mm, addr, ptep); flush_tlb_pending(); } - *ptep = __pte(pte_val(pte)) & ~_PAGE_HPTEFLAGS; + *ptep = __pte(pte_val(pte) & ~_PAGE_HPTEFLAGS); } /* Set the dirty and/or accessed bits atomically in a linux PTE, this @@ -485,18 +461,13 @@ extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long addr, extern unsigned long ioremap_bot, ioremap_base; -#define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT) -#define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS) - -#define pte_ERROR(e) \ - printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e)) #define pmd_ERROR(e) \ printk("%s:%d: bad pmd %08x.\n", __FILE__, __LINE__, pmd_val(e)) #define pgd_ERROR(e) \ printk("%s:%d: bad pgd %08x.\n", __FILE__, __LINE__, pgd_val(e)) -extern pgd_t swapper_pg_dir[1024]; -extern pgd_t ioremap_dir[1024]; +extern pgd_t swapper_pg_dir[]; +extern pgd_t ioremap_dir[]; extern void paging_init(void); @@ -538,43 +509,11 @@ extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t); */ #define kern_addr_valid(addr) (1) -#define io_remap_page_range(vma, vaddr, paddr, size, prot) \ - remap_pfn_range(vma, vaddr, (paddr) >> PAGE_SHIFT, size, prot) - #define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \ remap_pfn_range(vma, vaddr, pfn, size, prot) -#define MK_IOSPACE_PFN(space, pfn) (pfn) -#define GET_IOSPACE(pfn) 0 -#define GET_PFN(pfn) (pfn) - void pgtable_cache_init(void); -extern void hpte_init_native(void); -extern void hpte_init_lpar(void); -extern void hpte_init_iSeries(void); - -/* imalloc region types */ -#define IM_REGION_UNUSED 0x1 -#define IM_REGION_SUBSET 0x2 -#define IM_REGION_EXISTS 0x4 -#define IM_REGION_OVERLAP 0x8 -#define IM_REGION_SUPERSET 0x10 - -extern struct vm_struct * im_get_free_area(unsigned long size); -extern struct vm_struct * im_get_area(unsigned long v_addr, unsigned long size, - int region_type); -unsigned long im_free(void *addr); - -extern long pSeries_lpar_hpte_insert(unsigned long hpte_group, - unsigned long va, unsigned long prpn, - int secondary, unsigned long hpteflags, - int bolted, int large); - -extern long native_hpte_insert(unsigned long hpte_group, unsigned long va, - unsigned long prpn, int secondary, - unsigned long hpteflags, int bolted, int large); - /* * find_linux_pte returns the address of a linux pte for a given * effective address and directory. If not found, it returns zero. @@ -582,19 +521,22 @@ extern long native_hpte_insert(unsigned long hpte_group, unsigned long va, static inline pte_t *find_linux_pte(pgd_t *pgdir, unsigned long ea) { pgd_t *pg; + pud_t *pu; pmd_t *pm; pte_t *pt = NULL; pte_t pte; pg = pgdir + pgd_index(ea); if (!pgd_none(*pg)) { - - pm = pmd_offset(pg, ea); - if (pmd_present(*pm)) { - pt = pte_offset_kernel(pm, ea); - pte = *pt; - if (!pte_present(pte)) - pt = NULL; + pu = pud_offset(pg, ea); + if (!pud_none(*pu)) { + pm = pmd_offset(pu, ea); + if (pmd_present(*pm)) { + pt = pte_offset_kernel(pm, ea); + pte = *pt; + if (!pte_present(pte)) + pt = NULL; + } } } diff --git a/include/asm-ppc64/signal.h b/include/asm-ppc64/signal.h index fe5401adb41b..432df7dd355d 100644 --- a/include/asm-ppc64/signal.h +++ b/include/asm-ppc64/signal.h @@ -96,47 +96,20 @@ typedef struct { #define MINSIGSTKSZ 2048 #define SIGSTKSZ 8192 -#ifdef __KERNEL__ -/* - * These values of sa_flags are used only by the kernel as part of the - * irq handling routines. - * - * SA_INTERRUPT is also used by the irq handling routines. - * SA_SHIRQ is for shared interrupt support on PCI and EISA. - */ -#define SA_PROBE SA_ONESHOT -#define SA_SAMPLE_RANDOM SA_RESTART -#define SA_SHIRQ 0x04000000 -#endif - -#define SIG_BLOCK 0 /* for blocking signals */ -#define SIG_UNBLOCK 1 /* for unblocking signals */ -#define SIG_SETMASK 2 /* for setting the signal mask */ - -/* Type of a signal handler. */ -typedef void __sigfunction(int); -typedef __sigfunction __user * __sighandler_t; - -/* Type of the restorer function */ -typedef void __sigrestorer(void); -typedef __sigrestorer __user * __sigrestorer_t; - -#define SIG_DFL ((__sighandler_t)0) /* default signal handling */ -#define SIG_IGN ((__sighandler_t)1) /* ignore signal */ -#define SIG_ERR ((__sighandler_t)-1) /* error return from signal */ +#include <asm-generic/signal.h> struct old_sigaction { __sighandler_t sa_handler; old_sigset_t sa_mask; unsigned long sa_flags; - __sigrestorer_t sa_restorer; + __sigrestore_t sa_restorer; }; struct sigaction { __sighandler_t sa_handler; unsigned long sa_flags; - __sigrestorer_t sa_restorer; + __sigrestore_t sa_restorer; sigset_t sa_mask; /* mask last for extensibility */ }; diff --git a/include/asm-ppc64/spinlock.h b/include/asm-ppc64/spinlock.h index a9b2a1162cf7..acd11564dd75 100644 --- a/include/asm-ppc64/spinlock.h +++ b/include/asm-ppc64/spinlock.h @@ -110,7 +110,7 @@ static void __inline__ _raw_spin_lock(spinlock_t *lock) HMT_low(); if (SHARED_PROCESSOR) __spin_yield(lock); - } while (likely(lock->lock != 0)); + } while (unlikely(lock->lock != 0)); HMT_medium(); } } @@ -128,7 +128,7 @@ static void __inline__ _raw_spin_lock_flags(spinlock_t *lock, unsigned long flag HMT_low(); if (SHARED_PROCESSOR) __spin_yield(lock); - } while (likely(lock->lock != 0)); + } while (unlikely(lock->lock != 0)); HMT_medium(); local_irq_restore(flags_dis); } @@ -194,7 +194,7 @@ static void __inline__ _raw_read_lock(rwlock_t *rw) HMT_low(); if (SHARED_PROCESSOR) __rw_yield(rw); - } while (likely(rw->lock < 0)); + } while (unlikely(rw->lock < 0)); HMT_medium(); } } @@ -251,7 +251,7 @@ static void __inline__ _raw_write_lock(rwlock_t *rw) HMT_low(); if (SHARED_PROCESSOR) __rw_yield(rw); - } while (likely(rw->lock != 0)); + } while (unlikely(rw->lock != 0)); HMT_medium(); } } diff --git a/include/asm-ppc64/xics.h b/include/asm-ppc64/xics.h index 0027da4364ac..fdec5e7a7af6 100644 --- a/include/asm-ppc64/xics.h +++ b/include/asm-ppc64/xics.h @@ -30,7 +30,4 @@ struct xics_ipi_struct { extern struct xics_ipi_struct xics_ipi_message[NR_CPUS] __cacheline_aligned; -extern unsigned int default_distrib_server; -extern unsigned int interrupt_server_size; - #endif /* _PPC64_KERNEL_XICS_H */ diff --git a/include/asm-s390/bug.h b/include/asm-s390/bug.h index 2b8d6d4dffcf..a2e7430aafa6 100644 --- a/include/asm-s390/bug.h +++ b/include/asm-s390/bug.h @@ -3,12 +3,15 @@ #include <linux/kernel.h> +#ifdef CONFIG_BUG #define BUG() do { \ printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__); \ __asm__ __volatile__(".long 0"); \ } while (0) #define HAVE_ARCH_BUG +#endif + #include <asm-generic/bug.h> #endif diff --git a/include/asm-s390/cmb.h b/include/asm-s390/cmb.h index 1bfe2bd630b5..dae1dd4fb937 100644 --- a/include/asm-s390/cmb.h +++ b/include/asm-s390/cmb.h @@ -52,7 +52,7 @@ struct cmbdata { #define BIODASDREADALLCMB _IOWR(DASD_IOCTL_LETTER,33,struct cmbdata) #ifdef __KERNEL__ - +struct ccw_device; /** * enable_cmf() - switch on the channel measurement for a specific device * @cdev: The ccw device to be enabled diff --git a/include/asm-s390/debug.h b/include/asm-s390/debug.h index 28ef2354b1b2..6bbcdea42a86 100644 --- a/include/asm-s390/debug.h +++ b/include/asm-s390/debug.h @@ -43,7 +43,7 @@ struct __debug_entry{ #define DEBUG_OFF_LEVEL -1 /* level where debug is switched off */ #define DEBUG_FLUSH_ALL -1 /* parameter to flush all areas */ #define DEBUG_MAX_VIEWS 10 /* max number of views in proc fs */ -#define DEBUG_MAX_PROCF_LEN 16 /* max length for a proc file name */ +#define DEBUG_MAX_PROCF_LEN 64 /* max length for a proc file name */ #define DEBUG_DEFAULT_LEVEL 3 /* initial debug level */ #define DEBUG_DIR_ROOT "s390dbf" /* name of debug root directory in proc fs */ diff --git a/include/asm-s390/page.h b/include/asm-s390/page.h index 614e2a93c703..2be287b9df88 100644 --- a/include/asm-s390/page.h +++ b/include/asm-s390/page.h @@ -16,6 +16,8 @@ #define PAGE_SHIFT 12 #define PAGE_SIZE (1UL << PAGE_SHIFT) #define PAGE_MASK (~(PAGE_SIZE-1)) +#define PAGE_DEFAULT_ACC 0 +#define PAGE_DEFAULT_KEY (PAGE_DEFAULT_ACC << 4) #ifdef __KERNEL__ #ifndef __ASSEMBLY__ diff --git a/include/asm-s390/processor.h b/include/asm-s390/processor.h index 88c272ca48bf..fb46e9090b50 100644 --- a/include/asm-s390/processor.h +++ b/include/asm-s390/processor.h @@ -245,7 +245,7 @@ static inline void enabled_wait(void) psw_t wait_psw; wait_psw.mask = PSW_BASE_BITS | PSW_MASK_IO | PSW_MASK_EXT | - PSW_MASK_MCHECK | PSW_MASK_WAIT; + PSW_MASK_MCHECK | PSW_MASK_WAIT | PSW_DEFAULT_KEY; #ifndef __s390x__ asm volatile ( " basr %0,0\n" diff --git a/include/asm-s390/ptrace.h b/include/asm-s390/ptrace.h index 1dc80666e97e..4eff8f2e3bf1 100644 --- a/include/asm-s390/ptrace.h +++ b/include/asm-s390/ptrace.h @@ -185,6 +185,7 @@ #include <linux/stddef.h> #include <linux/types.h> #include <asm/setup.h> +#include <asm/page.h> typedef union { @@ -235,6 +236,7 @@ typedef struct #define PSW_ADDR_INSN 0x7FFFFFFFUL #define PSW_BASE_BITS 0x00080000UL +#define PSW_DEFAULT_KEY (((unsigned long) PAGE_DEFAULT_ACC) << 20) #define PSW_ASC_PRIMARY 0x00000000UL #define PSW_ASC_ACCREG 0x00004000UL @@ -260,6 +262,7 @@ typedef struct #define PSW_BASE_BITS 0x0000000180000000UL #define PSW_BASE32_BITS 0x0000000080000000UL +#define PSW_DEFAULT_KEY (((unsigned long) PAGE_DEFAULT_ACC) << 52) #define PSW_ASC_PRIMARY 0x0000000000000000UL #define PSW_ASC_ACCREG 0x0000400000000000UL @@ -268,14 +271,15 @@ typedef struct #define PSW_USER32_BITS (PSW_BASE32_BITS | PSW_MASK_DAT | PSW_ASC_HOME | \ PSW_MASK_IO | PSW_MASK_EXT | PSW_MASK_MCHECK | \ - PSW_MASK_PSTATE) + PSW_MASK_PSTATE | PSW_DEFAULT_KEY) #endif /* __s390x__ */ -#define PSW_KERNEL_BITS (PSW_BASE_BITS | PSW_MASK_DAT | PSW_ASC_PRIMARY) +#define PSW_KERNEL_BITS (PSW_BASE_BITS | PSW_MASK_DAT | PSW_ASC_PRIMARY | \ + PSW_DEFAULT_KEY) #define PSW_USER_BITS (PSW_BASE_BITS | PSW_MASK_DAT | PSW_ASC_HOME | \ PSW_MASK_IO | PSW_MASK_EXT | PSW_MASK_MCHECK | \ - PSW_MASK_PSTATE) + PSW_MASK_PSTATE | PSW_DEFAULT_KEY) /* This macro merges a NEW PSW mask specified by the user into the currently active PSW mask CURRENT, modifying only those @@ -470,6 +474,12 @@ struct user_regs_struct extern void show_regs(struct pt_regs * regs); #endif +static inline void +psw_set_key(unsigned int key) +{ + asm volatile ( "spka 0(%0)" : : "d" (key) ); +} + #endif /* __ASSEMBLY__ */ #endif /* _S390_PTRACE_H */ diff --git a/include/asm-s390/siginfo.h b/include/asm-s390/siginfo.h index 72303537b732..e0ff1ab054be 100644 --- a/include/asm-s390/siginfo.h +++ b/include/asm-s390/siginfo.h @@ -13,12 +13,6 @@ #define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int)) #endif -#ifdef CONFIG_ARCH_S390X -#define SIGEV_PAD_SIZE ((SIGEV_MAX_SIZE/sizeof(int)) - 4) -#else -#define SIGEV_PAD_SIZE ((SIGEV_MAX_SIZE/sizeof(int)) - 3) -#endif - #include <asm-generic/siginfo.h> #endif diff --git a/include/asm-s390/signal.h b/include/asm-s390/signal.h index f273cdcd1cf6..3d6e11c6c1fd 100644 --- a/include/asm-s390/signal.h +++ b/include/asm-s390/signal.h @@ -117,30 +117,7 @@ typedef unsigned long sigset_t; #define MINSIGSTKSZ 2048 #define SIGSTKSZ 8192 -#ifdef __KERNEL__ - -/* - * These values of sa_flags are used only by the kernel as part of the - * irq handling routines. - * - * SA_INTERRUPT is also used by the irq handling routines. - * SA_SHIRQ is for shared interrupt support on PCI and EISA. - */ -#define SA_PROBE SA_ONESHOT -#define SA_SAMPLE_RANDOM SA_RESTART -#define SA_SHIRQ 0x04000000 -#endif - -#define SIG_BLOCK 0 /* for blocking signals */ -#define SIG_UNBLOCK 1 /* for unblocking signals */ -#define SIG_SETMASK 2 /* for setting the signal mask */ - -/* Type of a signal handler. */ -typedef void (*__sighandler_t)(int); - -#define SIG_DFL ((__sighandler_t)0) /* default signal handling */ -#define SIG_IGN ((__sighandler_t)1) /* ignore signal */ -#define SIG_ERR ((__sighandler_t)-1) /* error return from signal */ +#include <asm-generic/signal.h> #ifdef __KERNEL__ struct old_sigaction { diff --git a/include/asm-sh/bug.h b/include/asm-sh/bug.h index 70172217140f..70508a360cd6 100644 --- a/include/asm-sh/bug.h +++ b/include/asm-sh/bug.h @@ -3,6 +3,7 @@ #include <linux/config.h> +#ifdef CONFIG_BUG /* * Tell the user there is some problem. */ @@ -12,6 +13,8 @@ } while (0) #define HAVE_ARCH_BUG +#endif + #include <asm-generic/bug.h> #endif diff --git a/include/asm-sh/checksum.h b/include/asm-sh/checksum.h index 5113c7f8a739..5ebd0f24299e 100644 --- a/include/asm-sh/checksum.h +++ b/include/asm-sh/checksum.h @@ -42,7 +42,7 @@ asmlinkage unsigned int csum_partial_copy_generic(const unsigned char *src, unsi * passed in an incorrect kernel address to one of these functions. * * If you use these functions directly please don't forget the - * verify_area(). + * access_ok(). */ static __inline__ unsigned int csum_partial_copy_nocheck (const unsigned char *src, unsigned char *dst, diff --git a/include/asm-sh/floppy.h b/include/asm-sh/floppy.h index f030ca08052b..38d7a2942476 100644 --- a/include/asm-sh/floppy.h +++ b/include/asm-sh/floppy.h @@ -227,7 +227,7 @@ static int hard_dma_setup(char *addr, unsigned long size, int mode, int io) return 0; } -struct fd_routine_l { +static struct fd_routine_l { int (*_request_dma)(unsigned int dmanr, const char * device_id); void (*_free_dma)(unsigned int dmanr); int (*_get_dma_residue)(unsigned int dummy); diff --git a/include/asm-sh/signal.h b/include/asm-sh/signal.h index 0a7ff717c245..d6e8eb0e65c7 100644 --- a/include/asm-sh/signal.h +++ b/include/asm-sh/signal.h @@ -108,30 +108,7 @@ typedef unsigned long sigset_t; #define MINSIGSTKSZ 2048 #define SIGSTKSZ 8192 -#ifdef __KERNEL__ - -/* - * These values of sa_flags are used only by the kernel as part of the - * irq handling routines. - * - * SA_INTERRUPT is also used by the irq handling routines. - * SA_SHIRQ is for shared interrupt support on PCI and EISA. - */ -#define SA_PROBE SA_ONESHOT -#define SA_SAMPLE_RANDOM SA_RESTART -#define SA_SHIRQ 0x04000000 -#endif - -#define SIG_BLOCK 0 /* for blocking signals */ -#define SIG_UNBLOCK 1 /* for unblocking signals */ -#define SIG_SETMASK 2 /* for setting the signal mask */ - -/* Type of a signal handler. */ -typedef void (*__sighandler_t)(int); - -#define SIG_DFL ((__sighandler_t)0) /* default signal handling */ -#define SIG_IGN ((__sighandler_t)1) /* ignore signal */ -#define SIG_ERR ((__sighandler_t)-1) /* error return from signal */ +#include <asm-generic/signal.h> #ifdef __KERNEL__ struct old_sigaction { diff --git a/include/asm-sh64/bug.h b/include/asm-sh64/bug.h index 3acd54d59566..5d659ec28e10 100644 --- a/include/asm-sh64/bug.h +++ b/include/asm-sh64/bug.h @@ -17,10 +17,6 @@ BUG(); \ } while(0) -#define PAGE_BUG(page) do { \ - BUG(); \ -} while (0) - #define WARN_ON(condition) do { \ if (unlikely((condition)!=0)) { \ printk("Badness in %s at %s:%d\n", __FUNCTION__, __FILE__, __LINE__); \ diff --git a/include/asm-sh64/checksum.h b/include/asm-sh64/checksum.h index aa3911a99490..fd034e9ae6e3 100644 --- a/include/asm-sh64/checksum.h +++ b/include/asm-sh64/checksum.h @@ -34,7 +34,7 @@ asmlinkage unsigned int csum_partial(const unsigned char *buff, int len, * passed in an incorrect kernel address to one of these functions. * * If you use these functions directly please don't forget the - * verify_area(). + * access_ok(). */ diff --git a/include/asm-sh64/signal.h b/include/asm-sh64/signal.h index 77957e9b92d9..2400dc688a65 100644 --- a/include/asm-sh64/signal.h +++ b/include/asm-sh64/signal.h @@ -107,30 +107,7 @@ typedef struct { #define MINSIGSTKSZ 2048 #define SIGSTKSZ THREAD_SIZE -#ifdef __KERNEL__ - -/* - * These values of sa_flags are used only by the kernel as part of the - * irq handling routines. - * - * SA_INTERRUPT is also used by the irq handling routines. - * SA_SHIRQ is for shared interrupt support on PCI and EISA. - */ -#define SA_PROBE SA_ONESHOT -#define SA_SAMPLE_RANDOM SA_RESTART -#define SA_SHIRQ 0x04000000 -#endif - -#define SIG_BLOCK 0 /* for blocking signals */ -#define SIG_UNBLOCK 1 /* for unblocking signals */ -#define SIG_SETMASK 2 /* for setting the signal mask */ - -/* Type of a signal handler. */ -typedef void (*__sighandler_t)(int); - -#define SIG_DFL ((__sighandler_t)0) /* default signal handling */ -#define SIG_IGN ((__sighandler_t)1) /* ignore signal */ -#define SIG_ERR ((__sighandler_t)-1) /* error return from signal */ +#include <asm-generic/signal.h> #ifdef __KERNEL__ struct old_sigaction { diff --git a/include/asm-sparc/bug.h b/include/asm-sparc/bug.h index 0d30a67d87a3..04151208189f 100644 --- a/include/asm-sparc/bug.h +++ b/include/asm-sparc/bug.h @@ -1,6 +1,7 @@ #ifndef _SPARC_BUG_H #define _SPARC_BUG_H +#ifdef CONFIG_BUG /* Only use the inline asm until a gcc release that can handle __builtin_trap * -rob 2003-06-25 * @@ -26,6 +27,8 @@ extern void do_BUG(const char *file, int line); #endif #define HAVE_ARCH_BUG +#endif + #include <asm-generic/bug.h> #endif diff --git a/include/asm-sparc/errno.h b/include/asm-sparc/errno.h index 8c01c5f3b06d..ed41c8bac1fa 100644 --- a/include/asm-sparc/errno.h +++ b/include/asm-sparc/errno.h @@ -107,4 +107,8 @@ #define EKEYREVOKED 130 /* Key has been revoked */ #define EKEYREJECTED 131 /* Key was rejected by service */ +/* for robust mutexes */ +#define EOWNERDEAD 132 /* Owner died */ +#define ENOTRECOVERABLE 133 /* State not recoverable */ + #endif diff --git a/include/asm-sparc/floppy.h b/include/asm-sparc/floppy.h index 780ee7ff9dc3..caf926116506 100644 --- a/include/asm-sparc/floppy.h +++ b/include/asm-sparc/floppy.h @@ -227,7 +227,7 @@ static __inline__ void sun_fd_disable_dma(void) doing_pdma = 0; if (pdma_base) { mmu_unlockarea(pdma_base, pdma_areasize); - pdma_base = 0; + pdma_base = NULL; } } diff --git a/include/asm-sparc/mxcc.h b/include/asm-sparc/mxcc.h index efe4e843122d..60ef9d6fe7bc 100644 --- a/include/asm-sparc/mxcc.h +++ b/include/asm-sparc/mxcc.h @@ -115,8 +115,8 @@ extern __inline__ unsigned long mxcc_get_creg(void) { unsigned long mxcc_control; - __asm__ __volatile__("set -1, %%g2\n\t" - "set -1, %%g3\n\t" + __asm__ __volatile__("set 0xffffffff, %%g2\n\t" + "set 0xffffffff, %%g3\n\t" "stda %%g2, [%1] %2\n\t" "lda [%3] %2, %0\n\t" : "=r" (mxcc_control) : diff --git a/include/asm-sparc/signal.h b/include/asm-sparc/signal.h index d8211cb6e6b4..aa9960ad0ca9 100644 --- a/include/asm-sparc/signal.h +++ b/include/asm-sparc/signal.h @@ -143,7 +143,6 @@ struct sigstack { #define SA_ONESHOT _SV_RESET #define SA_INTERRUPT 0x10u #define SA_NOMASK 0x20u -#define SA_SHIRQ 0x40u #define SA_NOCLDWAIT 0x100u #define SA_SIGINFO 0x200u @@ -162,11 +161,6 @@ struct sigstack { #ifdef __KERNEL__ /* - * These values of sa_flags are used only by the kernel as part of the - * irq handling routines. - * - * SA_INTERRUPT is also used by the irq handling routines. - * * DJHR * SA_STATIC_ALLOC is used for the SPARC system to indicate that this * interrupt handler's irq structure should be statically allocated @@ -177,21 +171,10 @@ struct sigstack { * statically allocated data.. which is NOT GOOD. * */ -#define SA_PROBE SA_ONESHOT -#define SA_SAMPLE_RANDOM SA_RESTART #define SA_STATIC_ALLOC 0x80 #endif -/* Type of a signal handler. */ -#ifdef __KERNEL__ -typedef void (*__sighandler_t)(int, int, struct sigcontext *, char *); -#else -typedef void (*__sighandler_t)(int); -#endif - -#define SIG_DFL ((__sighandler_t)0) /* default signal handling */ -#define SIG_IGN ((__sighandler_t)1) /* ignore signal */ -#define SIG_ERR ((__sighandler_t)-1) /* error return from signal */ +#include <asm-generic/signal.h> #ifdef __KERNEL__ struct __new_sigaction { diff --git a/include/asm-sparc/uaccess.h b/include/asm-sparc/uaccess.h index 3f47889883b7..f461144067ee 100644 --- a/include/asm-sparc/uaccess.h +++ b/include/asm-sparc/uaccess.h @@ -18,7 +18,7 @@ #ifndef __ASSEMBLY__ -/* Sparc is not segmented, however we need to be able to fool verify_area() +/* Sparc is not segmented, however we need to be able to fool access_ok() * when doing system calls from kernel mode legitimately. * * "For historical reasons, these macros are grossly misnamed." -Linus diff --git a/include/asm-sparc64/bug.h b/include/asm-sparc64/bug.h index 25c5b1dfe378..516bb27f3fc4 100644 --- a/include/asm-sparc64/bug.h +++ b/include/asm-sparc64/bug.h @@ -1,6 +1,7 @@ #ifndef _SPARC64_BUG_H #define _SPARC64_BUG_H +#ifdef CONFIG_BUG #include <linux/compiler.h> #ifdef CONFIG_DEBUG_BUGVERBOSE @@ -14,6 +15,8 @@ extern void do_BUG(const char *file, int line); #endif #define HAVE_ARCH_BUG +#endif + #include <asm-generic/bug.h> #endif diff --git a/include/asm-sparc64/errno.h b/include/asm-sparc64/errno.h index cc98a73b55a7..ea3509ee1b0b 100644 --- a/include/asm-sparc64/errno.h +++ b/include/asm-sparc64/errno.h @@ -107,4 +107,8 @@ #define EKEYREVOKED 130 /* Key has been revoked */ #define EKEYREJECTED 131 /* Key was rejected by service */ +/* for robust mutexes */ +#define EOWNERDEAD 132 /* Owner died */ +#define ENOTRECOVERABLE 133 /* State not recoverable */ + #endif /* !(_SPARC64_ERRNO_H) */ diff --git a/include/asm-sparc64/mostek.h b/include/asm-sparc64/mostek.h index ccf2f5f82d7f..09b5aba6678a 100644 --- a/include/asm-sparc64/mostek.h +++ b/include/asm-sparc64/mostek.h @@ -38,7 +38,7 @@ * * We now deal with physical addresses for I/O to the chip. -DaveM */ -static __inline__ u8 mostek_read(unsigned long addr) +static __inline__ u8 mostek_read(void __iomem *addr) { u8 ret; @@ -48,7 +48,7 @@ static __inline__ u8 mostek_read(unsigned long addr) return ret; } -static __inline__ void mostek_write(unsigned long addr, u8 val) +static __inline__ void mostek_write(void __iomem *addr, u8 val) { __asm__ __volatile__("stba %0, [%1] %2" : /* no outputs */ @@ -67,7 +67,7 @@ static __inline__ void mostek_write(unsigned long addr, u8 val) #define MOSTEK_YEAR 0x07ffUL extern spinlock_t mostek_lock; -extern unsigned long mstk48t02_regs; +extern void __iomem *mstk48t02_regs; /* Control register values. */ #define MSTK_CREG_WRITE 0x80 /* Must set this before placing values. */ diff --git a/include/asm-sparc64/parport.h b/include/asm-sparc64/parport.h index ab88349ddadc..b7e635544cec 100644 --- a/include/asm-sparc64/parport.h +++ b/include/asm-sparc64/parport.h @@ -13,6 +13,12 @@ #define PARPORT_PC_MAX_PORTS PARPORT_MAX +/* + * While sparc64 doesn't have an ISA DMA API, we provide something that looks + * close enough to make parport_pc happy + */ +#define HAS_DMA + static struct sparc_ebus_info { struct ebus_dma_info info; unsigned int addr; diff --git a/include/asm-sparc64/pgalloc.h b/include/asm-sparc64/pgalloc.h index 2c28e1f605b7..b9b1914aae63 100644 --- a/include/asm-sparc64/pgalloc.h +++ b/include/asm-sparc64/pgalloc.h @@ -122,17 +122,12 @@ static __inline__ void free_pmd_slow(pmd_t *pmd) #define pmd_populate(MM,PMD,PTE_PAGE) \ pmd_populate_kernel(MM,PMD,page_address(PTE_PAGE)) -extern pte_t *__pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address); - -static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address) -{ - return __pte_alloc_one_kernel(mm, address); -} +extern pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address); static inline struct page * pte_alloc_one(struct mm_struct *mm, unsigned long addr) { - pte_t *pte = __pte_alloc_one_kernel(mm, addr); + pte_t *pte = pte_alloc_one_kernel(mm, addr); if (pte) return virt_to_page(pte); diff --git a/include/asm-sparc64/pgtable.h b/include/asm-sparc64/pgtable.h index af9bf175a223..ae2cd5b09a7c 100644 --- a/include/asm-sparc64/pgtable.h +++ b/include/asm-sparc64/pgtable.h @@ -416,6 +416,11 @@ extern int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long from, unsigned long pfn, unsigned long size, pgprot_t prot); +/* Clear virtual and physical cachability, set side-effect bit. */ +#define pgprot_noncached(prot) \ + (__pgprot((pgprot_val(prot) & ~(_PAGE_CP | _PAGE_CV)) | \ + _PAGE_E)) + /* * For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in * its high 4 bits. These macros/functions put it there or get it from there. diff --git a/include/asm-sparc64/siginfo.h b/include/asm-sparc64/siginfo.h index 7160449e7cab..df17e47abc1c 100644 --- a/include/asm-sparc64/siginfo.h +++ b/include/asm-sparc64/siginfo.h @@ -3,8 +3,6 @@ #define SI_PAD_SIZE32 ((SI_MAX_SIZE/sizeof(int)) - 3) -#define SIGEV_PAD_SIZE ((SIGEV_MAX_SIZE/sizeof(int)) - 4) - #define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int)) #define __ARCH_SI_TRAPNO #define __ARCH_SI_BAND_T int diff --git a/include/asm-sparc64/signal.h b/include/asm-sparc64/signal.h index 6428e366c38c..becdf1bc5924 100644 --- a/include/asm-sparc64/signal.h +++ b/include/asm-sparc64/signal.h @@ -145,7 +145,6 @@ struct sigstack { #define SA_ONESHOT _SV_RESET #define SA_INTERRUPT 0x10u #define SA_NOMASK 0x20u -#define SA_SHIRQ 0x40u #define SA_NOCLDWAIT 0x100u #define SA_SIGINFO 0x200u @@ -165,11 +164,6 @@ struct sigstack { #ifdef __KERNEL__ /* - * These values of sa_flags are used only by the kernel as part of the - * irq handling routines. - * - * SA_INTERRUPT is also used by the irq handling routines. - * * DJHR * SA_STATIC_ALLOC is used for the SPARC system to indicate that this * interrupt handler's irq structure should be statically allocated @@ -180,26 +174,10 @@ struct sigstack { * statically allocated data.. which is NOT GOOD. * */ -#define SA_PROBE SA_ONESHOT -#define SA_SAMPLE_RANDOM SA_RESTART #define SA_STATIC_ALLOC 0x80 #endif -/* Type of a signal handler. */ -#ifdef __KERNEL__ -typedef void __signalfn_t(int); -typedef __signalfn_t __user *__sighandler_t; - -typedef void __restorefn_t(void); -typedef __restorefn_t __user *__sigrestore_t; -#else -typedef void (*__sighandler_t)(int); -typedef void (*__sigrestore_t)(void); -#endif - -#define SIG_DFL ((__sighandler_t)0) /* default signal handling */ -#define SIG_IGN ((__sighandler_t)1) /* ignore signal */ -#define SIG_ERR ((__sighandler_t)-1) /* error return from signal */ +#include <asm-generic/signal.h> struct __new_sigaction { __sighandler_t sa_handler; diff --git a/include/asm-sparc64/spinlock.h b/include/asm-sparc64/spinlock.h index d1f91a4f24ae..db7581bdb531 100644 --- a/include/asm-sparc64/spinlock.h +++ b/include/asm-sparc64/spinlock.h @@ -44,7 +44,7 @@ typedef struct { #define spin_unlock_wait(lp) \ do { membar("#LoadLoad"); \ -} while(lp->lock) +} while((lp)->lock) static inline void _raw_spin_lock(spinlock_t *lock) { @@ -149,7 +149,7 @@ typedef struct { unsigned int break_lock; #endif } rwlock_t; -#define RW_LOCK_UNLOCKED {0,} +#define RW_LOCK_UNLOCKED (rwlock_t) {0,} #define rwlock_init(lp) do { *(lp) = RW_LOCK_UNLOCKED; } while(0) static void inline __read_lock(rwlock_t *lock) diff --git a/include/asm-um/arch-signal-i386.h b/include/asm-um/arch-signal-i386.h index 99a9de4728da..e69de29bb2d1 100644 --- a/include/asm-um/arch-signal-i386.h +++ b/include/asm-um/arch-signal-i386.h @@ -1,24 +0,0 @@ -/* - * Copyright (C) 2002 Jeff Dike (jdike@karaya.com) - * Licensed under the GPL - */ - -#ifndef __UM_ARCH_SIGNAL_I386_H -#define __UM_ARCH_SIGNAL_I386_H - -struct arch_signal_context { - unsigned long extrasigs[_NSIG_WORDS]; -}; - -#endif - -/* - * Overrides for Emacs so that we follow Linus's tabbing style. - * Emacs will notice this stuff at the end of the file and automatically - * adjust the settings for this buffer only. This must remain at the end - * of the file. - * --------------------------------------------------------------------------- - * Local variables: - * c-file-style: "linux" - * End: - */ diff --git a/include/asm-um/archparam-i386.h b/include/asm-um/archparam-i386.h index 6f78de5b621b..49e89b8d7e58 100644 --- a/include/asm-um/archparam-i386.h +++ b/include/asm-um/archparam-i386.h @@ -6,143 +6,6 @@ #ifndef __UM_ARCHPARAM_I386_H #define __UM_ARCHPARAM_I386_H -/********* Bits for asm-um/elf.h ************/ - -#include <asm/user.h> - -extern char * elf_aux_platform; -#define ELF_PLATFORM (elf_aux_platform) - -#define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3) - -typedef struct user_i387_struct elf_fpregset_t; -typedef unsigned long elf_greg_t; - -#define ELF_NGREG (sizeof (struct user_regs_struct) / sizeof(elf_greg_t)) -typedef elf_greg_t elf_gregset_t[ELF_NGREG]; - -#define ELF_DATA ELFDATA2LSB -#define ELF_ARCH EM_386 - -#define ELF_PLAT_INIT(regs, load_addr) do { \ - PT_REGS_EBX(regs) = 0; \ - PT_REGS_ECX(regs) = 0; \ - PT_REGS_EDX(regs) = 0; \ - PT_REGS_ESI(regs) = 0; \ - PT_REGS_EDI(regs) = 0; \ - PT_REGS_EBP(regs) = 0; \ - PT_REGS_EAX(regs) = 0; \ -} while(0) - -/* Shamelessly stolen from include/asm-i386/elf.h */ - -#define ELF_CORE_COPY_REGS(pr_reg, regs) do { \ - pr_reg[0] = PT_REGS_EBX(regs); \ - pr_reg[1] = PT_REGS_ECX(regs); \ - pr_reg[2] = PT_REGS_EDX(regs); \ - pr_reg[3] = PT_REGS_ESI(regs); \ - pr_reg[4] = PT_REGS_EDI(regs); \ - pr_reg[5] = PT_REGS_EBP(regs); \ - pr_reg[6] = PT_REGS_EAX(regs); \ - pr_reg[7] = PT_REGS_DS(regs); \ - pr_reg[8] = PT_REGS_ES(regs); \ - /* fake once used fs and gs selectors? */ \ - pr_reg[9] = PT_REGS_DS(regs); \ - pr_reg[10] = PT_REGS_DS(regs); \ - pr_reg[11] = PT_REGS_SYSCALL_NR(regs); \ - pr_reg[12] = PT_REGS_IP(regs); \ - pr_reg[13] = PT_REGS_CS(regs); \ - pr_reg[14] = PT_REGS_EFLAGS(regs); \ - pr_reg[15] = PT_REGS_SP(regs); \ - pr_reg[16] = PT_REGS_SS(regs); \ -} while(0); - - -extern unsigned long vsyscall_ehdr; -extern unsigned long vsyscall_end; -extern unsigned long __kernel_vsyscall; - -#define VSYSCALL_BASE vsyscall_ehdr -#define VSYSCALL_END vsyscall_end - -/* - * This is the range that is readable by user mode, and things - * acting like user mode such as get_user_pages. - */ -#define FIXADDR_USER_START VSYSCALL_BASE -#define FIXADDR_USER_END VSYSCALL_END - -/* - * Architecture-neutral AT_ values in 0-17, leave some room - * for more of them, start the x86-specific ones at 32. - */ -#define AT_SYSINFO 32 -#define AT_SYSINFO_EHDR 33 - -#define ARCH_DLINFO \ -do { \ - if ( vsyscall_ehdr ) { \ - NEW_AUX_ENT(AT_SYSINFO, __kernel_vsyscall); \ - NEW_AUX_ENT(AT_SYSINFO_EHDR, vsyscall_ehdr); \ - } \ -} while (0) - -/* - * These macros parameterize elf_core_dump in fs/binfmt_elf.c to write out - * extra segments containing the vsyscall DSO contents. Dumping its - * contents makes post-mortem fully interpretable later without matching up - * the same kernel and hardware config to see what PC values meant. - * Dumping its extra ELF program headers includes all the other information - * a debugger needs to easily find how the vsyscall DSO was being used. - */ -#define ELF_CORE_EXTRA_PHDRS \ - (vsyscall_ehdr ? (((struct elfhdr *)vsyscall_ehdr)->e_phnum) : 0 ) - -#define ELF_CORE_WRITE_EXTRA_PHDRS \ -if ( vsyscall_ehdr ) { \ - const struct elfhdr *const ehdrp = (struct elfhdr *)vsyscall_ehdr; \ - const struct elf_phdr *const phdrp = \ - (const struct elf_phdr *) (vsyscall_ehdr + ehdrp->e_phoff); \ - int i; \ - Elf32_Off ofs = 0; \ - for (i = 0; i < ehdrp->e_phnum; ++i) { \ - struct elf_phdr phdr = phdrp[i]; \ - if (phdr.p_type == PT_LOAD) { \ - ofs = phdr.p_offset = offset; \ - offset += phdr.p_filesz; \ - } \ - else \ - phdr.p_offset += ofs; \ - phdr.p_paddr = 0; /* match other core phdrs */ \ - DUMP_WRITE(&phdr, sizeof(phdr)); \ - } \ -} -#define ELF_CORE_WRITE_EXTRA_DATA \ -if ( vsyscall_ehdr ) { \ - const struct elfhdr *const ehdrp = (struct elfhdr *)vsyscall_ehdr; \ - const struct elf_phdr *const phdrp = \ - (const struct elf_phdr *) (vsyscall_ehdr + ehdrp->e_phoff); \ - int i; \ - for (i = 0; i < ehdrp->e_phnum; ++i) { \ - if (phdrp[i].p_type == PT_LOAD) \ - DUMP_WRITE((void *) phdrp[i].p_vaddr, \ - phdrp[i].p_filesz); \ - } \ -} - -#define R_386_NONE 0 -#define R_386_32 1 -#define R_386_PC32 2 -#define R_386_GOT32 3 -#define R_386_PLT32 4 -#define R_386_COPY 5 -#define R_386_GLOB_DAT 6 -#define R_386_JMP_SLOT 7 -#define R_386_RELATIVE 8 -#define R_386_GOTOFF 9 -#define R_386_GOTPC 10 -#define R_386_NUM 11 - /********* Nothing for asm-um/hardirq.h **********/ /********* Nothing for asm-um/hw_irq.h **********/ diff --git a/include/asm-um/archparam-ppc.h b/include/asm-um/archparam-ppc.h index 0ebced92a762..172cd6ffacc4 100644 --- a/include/asm-um/archparam-ppc.h +++ b/include/asm-um/archparam-ppc.h @@ -1,26 +1,6 @@ #ifndef __UM_ARCHPARAM_PPC_H #define __UM_ARCHPARAM_PPC_H -/********* Bits for asm-um/elf.h ************/ - -#define ELF_PLATFORM (0) - -#define ELF_ET_DYN_BASE (0x08000000) - -/* the following stolen from asm-ppc/elf.h */ -#define ELF_NGREG 48 /* includes nip, msr, lr, etc. */ -#define ELF_NFPREG 33 /* includes fpscr */ -/* General registers */ -typedef unsigned long elf_greg_t; -typedef elf_greg_t elf_gregset_t[ELF_NGREG]; - -/* Floating point registers */ -typedef double elf_fpreg_t; -typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; - -#define ELF_DATA ELFDATA2MSB -#define ELF_ARCH EM_PPC - /********* Bits for asm-um/hw_irq.h **********/ struct hw_interrupt_type; diff --git a/include/asm-um/archparam-x86_64.h b/include/asm-um/archparam-x86_64.h index 96321c4892f1..270ed9586b68 100644 --- a/include/asm-um/archparam-x86_64.h +++ b/include/asm-um/archparam-x86_64.h @@ -7,42 +7,6 @@ #ifndef __UM_ARCHPARAM_X86_64_H #define __UM_ARCHPARAM_X86_64_H -#include <asm/user.h> - -#define ELF_PLATFORM "x86_64" - -#define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3) - -typedef unsigned long elf_greg_t; -typedef struct { } elf_fpregset_t; - -#define ELF_NGREG (sizeof (struct user_regs_struct) / sizeof(elf_greg_t)) -typedef elf_greg_t elf_gregset_t[ELF_NGREG]; - -#define ELF_DATA ELFDATA2LSB -#define ELF_ARCH EM_X86_64 - -#define ELF_PLAT_INIT(regs, load_addr) do { \ - PT_REGS_RBX(regs) = 0; \ - PT_REGS_RCX(regs) = 0; \ - PT_REGS_RDX(regs) = 0; \ - PT_REGS_RSI(regs) = 0; \ - PT_REGS_RDI(regs) = 0; \ - PT_REGS_RBP(regs) = 0; \ - PT_REGS_RAX(regs) = 0; \ - PT_REGS_R8(regs) = 0; \ - PT_REGS_R9(regs) = 0; \ - PT_REGS_R10(regs) = 0; \ - PT_REGS_R11(regs) = 0; \ - PT_REGS_R12(regs) = 0; \ - PT_REGS_R13(regs) = 0; \ - PT_REGS_R14(regs) = 0; \ - PT_REGS_R15(regs) = 0; \ -} while (0) - -#ifdef TIF_IA32 /* XXX */ - clear_thread_flag(TIF_IA32); -#endif /* No user-accessible fixmap addresses, i.e. vsyscall */ #define FIXADDR_USER_START 0 diff --git a/include/asm-um/common.lds.S b/include/asm-um/common.lds.S index a3d6aab0e74d..1010153faaf9 100644 --- a/include/asm-um/common.lds.S +++ b/include/asm-um/common.lds.S @@ -8,11 +8,6 @@ _sdata = .; PROVIDE (sdata = .); - . = ALIGN(16); /* Exception table */ - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - RODATA .unprotected : { *(.unprotected) } @@ -20,6 +15,10 @@ PROVIDE (_unprotected_end = .); . = ALIGN(4096); + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + __uml_setup_start = .; .uml.setup.init : { *(.uml.setup.init) } __uml_setup_end = .; diff --git a/include/asm-um/delay.h b/include/asm-um/delay.h index 40695576ca60..0985bda66750 100644 --- a/include/asm-um/delay.h +++ b/include/asm-um/delay.h @@ -4,4 +4,6 @@ #include "asm/arch/delay.h" #include "asm/archparam.h" +#define MILLION 1000000 + #endif diff --git a/include/asm-um/elf-i386.h b/include/asm-um/elf-i386.h new file mode 100644 index 000000000000..b72e23519e00 --- /dev/null +++ b/include/asm-um/elf-i386.h @@ -0,0 +1,169 @@ +/* + * Copyright (C) 2000 - 2003 Jeff Dike (jdike@addtoit.com) + * Licensed under the GPL + */ +#ifndef __UM_ELF_I386_H +#define __UM_ELF_I386_H + +#include "user.h" + +#define R_386_NONE 0 +#define R_386_32 1 +#define R_386_PC32 2 +#define R_386_GOT32 3 +#define R_386_PLT32 4 +#define R_386_COPY 5 +#define R_386_GLOB_DAT 6 +#define R_386_JMP_SLOT 7 +#define R_386_RELATIVE 8 +#define R_386_GOTOFF 9 +#define R_386_GOTPC 10 +#define R_386_NUM 11 + +typedef unsigned long elf_greg_t; + +#define ELF_NGREG (sizeof (struct user_regs_struct) / sizeof(elf_greg_t)) +typedef elf_greg_t elf_gregset_t[ELF_NGREG]; + +typedef struct user_i387_struct elf_fpregset_t; + +/* + * This is used to ensure we don't load something for the wrong architecture. + */ +#define elf_check_arch(x) \ + (((x)->e_machine == EM_386) || ((x)->e_machine == EM_486)) + +#define ELF_CLASS ELFCLASS32 +#define ELF_DATA ELFDATA2LSB +#define ELF_ARCH EM_386 + +#define ELF_PLAT_INIT(regs, load_addr) do { \ + PT_REGS_EBX(regs) = 0; \ + PT_REGS_ECX(regs) = 0; \ + PT_REGS_EDX(regs) = 0; \ + PT_REGS_ESI(regs) = 0; \ + PT_REGS_EDI(regs) = 0; \ + PT_REGS_EBP(regs) = 0; \ + PT_REGS_EAX(regs) = 0; \ +} while(0) + +#define USE_ELF_CORE_DUMP +#define ELF_EXEC_PAGESIZE 4096 + +#define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3) + +/* Shamelessly stolen from include/asm-i386/elf.h */ + +#define ELF_CORE_COPY_REGS(pr_reg, regs) do { \ + pr_reg[0] = PT_REGS_EBX(regs); \ + pr_reg[1] = PT_REGS_ECX(regs); \ + pr_reg[2] = PT_REGS_EDX(regs); \ + pr_reg[3] = PT_REGS_ESI(regs); \ + pr_reg[4] = PT_REGS_EDI(regs); \ + pr_reg[5] = PT_REGS_EBP(regs); \ + pr_reg[6] = PT_REGS_EAX(regs); \ + pr_reg[7] = PT_REGS_DS(regs); \ + pr_reg[8] = PT_REGS_ES(regs); \ + /* fake once used fs and gs selectors? */ \ + pr_reg[9] = PT_REGS_DS(regs); \ + pr_reg[10] = PT_REGS_DS(regs); \ + pr_reg[11] = PT_REGS_SYSCALL_NR(regs); \ + pr_reg[12] = PT_REGS_IP(regs); \ + pr_reg[13] = PT_REGS_CS(regs); \ + pr_reg[14] = PT_REGS_EFLAGS(regs); \ + pr_reg[15] = PT_REGS_SP(regs); \ + pr_reg[16] = PT_REGS_SS(regs); \ +} while(0); + +extern long elf_aux_hwcap; +#define ELF_HWCAP (elf_aux_hwcap) + +extern char * elf_aux_platform; +#define ELF_PLATFORM (elf_aux_platform) + +#define SET_PERSONALITY(ex, ibcs2) do ; while(0) + +extern unsigned long vsyscall_ehdr; +extern unsigned long vsyscall_end; +extern unsigned long __kernel_vsyscall; + +#define VSYSCALL_BASE vsyscall_ehdr +#define VSYSCALL_END vsyscall_end + +/* + * This is the range that is readable by user mode, and things + * acting like user mode such as get_user_pages. + */ +#define FIXADDR_USER_START VSYSCALL_BASE +#define FIXADDR_USER_END VSYSCALL_END + +/* + * Architecture-neutral AT_ values in 0-17, leave some room + * for more of them, start the x86-specific ones at 32. + */ +#define AT_SYSINFO 32 +#define AT_SYSINFO_EHDR 33 + +#define ARCH_DLINFO \ +do { \ + if ( vsyscall_ehdr ) { \ + NEW_AUX_ENT(AT_SYSINFO, __kernel_vsyscall); \ + NEW_AUX_ENT(AT_SYSINFO_EHDR, vsyscall_ehdr); \ + } \ +} while (0) + +/* + * These macros parameterize elf_core_dump in fs/binfmt_elf.c to write out + * extra segments containing the vsyscall DSO contents. Dumping its + * contents makes post-mortem fully interpretable later without matching up + * the same kernel and hardware config to see what PC values meant. + * Dumping its extra ELF program headers includes all the other information + * a debugger needs to easily find how the vsyscall DSO was being used. + */ +#define ELF_CORE_EXTRA_PHDRS \ + (vsyscall_ehdr ? (((struct elfhdr *)vsyscall_ehdr)->e_phnum) : 0 ) + +#define ELF_CORE_WRITE_EXTRA_PHDRS \ +if ( vsyscall_ehdr ) { \ + const struct elfhdr *const ehdrp = (struct elfhdr *)vsyscall_ehdr; \ + const struct elf_phdr *const phdrp = \ + (const struct elf_phdr *) (vsyscall_ehdr + ehdrp->e_phoff); \ + int i; \ + Elf32_Off ofs = 0; \ + for (i = 0; i < ehdrp->e_phnum; ++i) { \ + struct elf_phdr phdr = phdrp[i]; \ + if (phdr.p_type == PT_LOAD) { \ + ofs = phdr.p_offset = offset; \ + offset += phdr.p_filesz; \ + } \ + else \ + phdr.p_offset += ofs; \ + phdr.p_paddr = 0; /* match other core phdrs */ \ + DUMP_WRITE(&phdr, sizeof(phdr)); \ + } \ +} +#define ELF_CORE_WRITE_EXTRA_DATA \ +if ( vsyscall_ehdr ) { \ + const struct elfhdr *const ehdrp = (struct elfhdr *)vsyscall_ehdr; \ + const struct elf_phdr *const phdrp = \ + (const struct elf_phdr *) (vsyscall_ehdr + ehdrp->e_phoff); \ + int i; \ + for (i = 0; i < ehdrp->e_phnum; ++i) { \ + if (phdrp[i].p_type == PT_LOAD) \ + DUMP_WRITE((void *) phdrp[i].p_vaddr, \ + phdrp[i].p_filesz); \ + } \ +} + +#endif + +/* + * Overrides for Emacs so that we follow Linus's tabbing style. + * Emacs will notice this stuff at the end of the file and automatically + * adjust the settings for this buffer only. This must remain at the end + * of the file. + * --------------------------------------------------------------------------- + * Local variables: + * c-file-style: "linux" + * End: + */ diff --git a/include/asm-um/elf-ppc.h b/include/asm-um/elf-ppc.h new file mode 100644 index 000000000000..2998cf925042 --- /dev/null +++ b/include/asm-um/elf-ppc.h @@ -0,0 +1,54 @@ +#ifndef __UM_ELF_PPC_H +#define __UM_ELF_PPC_H + +#include "linux/config.h" + +extern long elf_aux_hwcap; +#define ELF_HWCAP (elf_aux_hwcap) + +#define SET_PERSONALITY(ex, ibcs2) do ; while(0) + +#define ELF_EXEC_PAGESIZE 4096 + +#define elf_check_arch(x) (1) + +#ifdef CONFIG_64_BIT +#define ELF_CLASS ELFCLASS64 +#else +#define ELF_CLASS ELFCLASS32 +#endif + +#define USE_ELF_CORE_DUMP + +#define R_386_NONE 0 +#define R_386_32 1 +#define R_386_PC32 2 +#define R_386_GOT32 3 +#define R_386_PLT32 4 +#define R_386_COPY 5 +#define R_386_GLOB_DAT 6 +#define R_386_JMP_SLOT 7 +#define R_386_RELATIVE 8 +#define R_386_GOTOFF 9 +#define R_386_GOTPC 10 +#define R_386_NUM 11 + +#define ELF_PLATFORM (0) + +#define ELF_ET_DYN_BASE (0x08000000) + +/* the following stolen from asm-ppc/elf.h */ +#define ELF_NGREG 48 /* includes nip, msr, lr, etc. */ +#define ELF_NFPREG 33 /* includes fpscr */ +/* General registers */ +typedef unsigned long elf_greg_t; +typedef elf_greg_t elf_gregset_t[ELF_NGREG]; + +/* Floating point registers */ +typedef double elf_fpreg_t; +typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; + +#define ELF_DATA ELFDATA2MSB +#define ELF_ARCH EM_PPC + +#endif diff --git a/include/asm-um/elf-x86_64.h b/include/asm-um/elf-x86_64.h new file mode 100644 index 000000000000..19309d001aa0 --- /dev/null +++ b/include/asm-um/elf-x86_64.h @@ -0,0 +1,73 @@ +/* + * Copyright 2003 PathScale, Inc. + * + * Licensed under the GPL + */ +#ifndef __UM_ELF_X86_64_H +#define __UM_ELF_X86_64_H + +#include <asm/user.h> + +typedef unsigned long elf_greg_t; + +#define ELF_NGREG (sizeof (struct user_regs_struct) / sizeof(elf_greg_t)) +typedef elf_greg_t elf_gregset_t[ELF_NGREG]; + +typedef struct { } elf_fpregset_t; + +/* + * This is used to ensure we don't load something for the wrong architecture. + */ +#define elf_check_arch(x) \ + ((x)->e_machine == EM_X86_64) + +#define ELF_CLASS ELFCLASS64 +#define ELF_DATA ELFDATA2LSB +#define ELF_ARCH EM_X86_64 + +#define ELF_PLAT_INIT(regs, load_addr) do { \ + PT_REGS_RBX(regs) = 0; \ + PT_REGS_RCX(regs) = 0; \ + PT_REGS_RDX(regs) = 0; \ + PT_REGS_RSI(regs) = 0; \ + PT_REGS_RDI(regs) = 0; \ + PT_REGS_RBP(regs) = 0; \ + PT_REGS_RAX(regs) = 0; \ + PT_REGS_R8(regs) = 0; \ + PT_REGS_R9(regs) = 0; \ + PT_REGS_R10(regs) = 0; \ + PT_REGS_R11(regs) = 0; \ + PT_REGS_R12(regs) = 0; \ + PT_REGS_R13(regs) = 0; \ + PT_REGS_R14(regs) = 0; \ + PT_REGS_R15(regs) = 0; \ +} while (0) + +#ifdef TIF_IA32 /* XXX */ + clear_thread_flag(TIF_IA32); \ +#endif + +#define USE_ELF_CORE_DUMP +#define ELF_EXEC_PAGESIZE 4096 + +#define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3) + +extern long elf_aux_hwcap; +#define ELF_HWCAP (elf_aux_hwcap) + +#define ELF_PLATFORM "x86_64" + +#define SET_PERSONALITY(ex, ibcs2) do ; while(0) + +#endif + +/* + * Overrides for Emacs so that we follow Linus's tabbing style. + * Emacs will notice this stuff at the end of the file and automatically + * adjust the settings for this buffer only. This must remain at the end + * of the file. + * --------------------------------------------------------------------------- + * Local variables: + * c-file-style: "linux" + * End: + */ diff --git a/include/asm-um/elf.h b/include/asm-um/elf.h index b3a7258f9971..e69de29bb2d1 100644 --- a/include/asm-um/elf.h +++ b/include/asm-um/elf.h @@ -1,37 +0,0 @@ -#ifndef __UM_ELF_H -#define __UM_ELF_H - -#include "linux/config.h" -#include "asm/archparam.h" - -extern long elf_aux_hwcap; -#define ELF_HWCAP (elf_aux_hwcap) - -#define SET_PERSONALITY(ex, ibcs2) do ; while(0) - -#define ELF_EXEC_PAGESIZE 4096 - -#define elf_check_arch(x) (1) - -#ifdef CONFIG_64_BIT -#define ELF_CLASS ELFCLASS64 -#else -#define ELF_CLASS ELFCLASS32 -#endif - -#define USE_ELF_CORE_DUMP - -#define R_386_NONE 0 -#define R_386_32 1 -#define R_386_PC32 2 -#define R_386_GOT32 3 -#define R_386_PLT32 4 -#define R_386_COPY 5 -#define R_386_GLOB_DAT 6 -#define R_386_JMP_SLOT 7 -#define R_386_RELATIVE 8 -#define R_386_GOTOFF 9 -#define R_386_GOTPC 10 -#define R_386_NUM 11 - -#endif diff --git a/include/asm-um/fixmap.h b/include/asm-um/fixmap.h index 900f3fbb9fab..ae0ca3932d50 100644 --- a/include/asm-um/fixmap.h +++ b/include/asm-um/fixmap.h @@ -4,6 +4,7 @@ #include <linux/config.h> #include <asm/kmap_types.h> #include <asm/archparam.h> +#include <asm/elf.h> /* * Here we define all the compile-time 'special' virtual diff --git a/include/asm-um/ipc.h b/include/asm-um/ipc.h index e2ddc47f3e52..a46e3d9c2a3f 100644 --- a/include/asm-um/ipc.h +++ b/include/asm-um/ipc.h @@ -1,6 +1 @@ -#ifndef __UM_IPC_H -#define __UM_IPC_H - -#include "asm/arch/ipc.h" - -#endif +#include <asm-generic/ipc.h> diff --git a/include/asm-um/linkage.h b/include/asm-um/linkage.h index 27011652b015..7dfce37adc8b 100644 --- a/include/asm-um/linkage.h +++ b/include/asm-um/linkage.h @@ -1,7 +1,6 @@ -#ifndef __ASM_LINKAGE_H -#define __ASM_LINKAGE_H +#ifndef __ASM_UM_LINKAGE_H +#define __ASM_UM_LINKAGE_H -#define FASTCALL(x) x __attribute__((regparm(3))) -#define fastcall __attribute__((regparm(3))) +#include "asm/arch/linkage.h" #endif diff --git a/include/asm-um/page.h b/include/asm-um/page.h index 3620a08dc9f3..504ea8e486b0 100644 --- a/include/asm-um/page.h +++ b/include/asm-um/page.h @@ -27,7 +27,7 @@ struct page; #define clear_user_page(page, vaddr, pg) clear_page(page) #define copy_user_page(to, from, vaddr, pg) copy_page(to, from) -#if defined(CONFIG_3_LEVEL_PGTABLES) && !defined(CONFIG_64_BIT) +#if defined(CONFIG_3_LEVEL_PGTABLES) && !defined(CONFIG_64BIT) typedef struct { unsigned long pte_low, pte_high; } pte_t; typedef struct { unsigned long long pmd; } pmd_t; @@ -45,6 +45,9 @@ typedef struct { unsigned long pgd; } pgd_t; ({ (pte).pte_high = (phys) >> 32; \ (pte).pte_low = (phys) | pgprot_val(prot); }) +#define pmd_val(x) ((x).pmd) +#define __pmd(x) ((pmd_t) { (x) } ) + typedef unsigned long long pfn_t; typedef unsigned long long phys_t; diff --git a/include/asm-um/pgtable-3level.h b/include/asm-um/pgtable-3level.h index bdbc3f97e20b..65e8bfc55fc4 100644 --- a/include/asm-um/pgtable-3level.h +++ b/include/asm-um/pgtable-3level.h @@ -145,11 +145,11 @@ static inline pmd_t pfn_pmd(pfn_t page_nr, pgprot_t pgprot) */ #define PTE_FILE_MAX_BITS 32 -#ifdef CONFIG_64_BIT +#ifdef CONFIG_64BIT #define pte_to_pgoff(p) ((p).pte >> 32) -#define pgoff_to_pte(off) ((pte_t) { ((off) < 32) | _PAGE_FILE }) +#define pgoff_to_pte(off) ((pte_t) { ((off) << 32) | _PAGE_FILE }) #else diff --git a/include/asm-um/pgtable.h b/include/asm-um/pgtable.h index 71f9c0c78c0c..510e513c7f88 100644 --- a/include/asm-um/pgtable.h +++ b/include/asm-um/pgtable.h @@ -106,7 +106,7 @@ extern unsigned long end_iomem; /* * Define this if things work differently on an i386 and an i486: * it will (on an i486) warn about kernel memory accesses that are - * done without a 'verify_area(VERIFY_WRITE,..)' + * done without a 'access_ok(VERIFY_WRITE,..)' */ #undef TEST_VERIFY_AREA diff --git a/include/asm-um/processor-generic.h b/include/asm-um/processor-generic.h index 038ba6fc88b8..b2fc94fbc2d9 100644 --- a/include/asm-um/processor-generic.h +++ b/include/asm-um/processor-generic.h @@ -17,12 +17,13 @@ struct task_struct; struct mm_struct; struct thread_struct { + /* This flag is set to 1 before calling do_fork (and analyzed in + * copy_thread) to mark that we are begin called from userspace (fork / + * vfork / clone), and reset to 0 after. It is left to 0 when called + * from kernelspace (i.e. kernel_thread() or fork_idle(), as of 2.6.11). */ int forking; int nsyscalls; struct pt_regs regs; - unsigned long cr2; - int err; - unsigned long trap_no; int singlestep_syscall; void *fault_addr; void *fault_catcher; @@ -70,8 +71,6 @@ struct thread_struct { .forking = 0, \ .nsyscalls = 0, \ .regs = EMPTY_REGS, \ - .cr2 = 0, \ - .err = 0, \ .fault_addr = NULL, \ .prev_sched = NULL, \ .temp_stack = 0, \ @@ -89,7 +88,11 @@ extern struct task_struct *alloc_task_struct(void); extern void release_thread(struct task_struct *); extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags); extern void dump_thread(struct pt_regs *regs, struct user *u); -extern void prepare_to_copy(struct task_struct *tsk); + +static inline void prepare_to_copy(struct task_struct *tsk) +{ +} + extern unsigned long thread_saved_pc(struct task_struct *t); diff --git a/include/asm-um/processor-i386.h b/include/asm-um/processor-i386.h index 2deb8f1adbf1..431bad3ae9d7 100644 --- a/include/asm-um/processor-i386.h +++ b/include/asm-um/processor-i386.h @@ -9,13 +9,18 @@ extern int host_has_xmm; extern int host_has_cmov; +/* include faultinfo structure */ +#include "sysdep/faultinfo.h" + struct arch_thread { unsigned long debugregs[8]; int debugregs_seq; + struct faultinfo faultinfo; }; #define INIT_ARCH_THREAD { .debugregs = { [ 0 ... 7 ] = 0 }, \ - .debugregs_seq = 0 } + .debugregs_seq = 0, \ + .faultinfo = { 0, 0, 0 } } #include "asm/arch/user.h" diff --git a/include/asm-um/processor-x86_64.h b/include/asm-um/processor-x86_64.h index a1ae3a4cd938..0beb9a42ae05 100644 --- a/include/asm-um/processor-x86_64.h +++ b/include/asm-um/processor-x86_64.h @@ -7,9 +7,13 @@ #ifndef __UM_PROCESSOR_X86_64_H #define __UM_PROCESSOR_X86_64_H -#include "asm/arch/user.h" +/* include faultinfo structure */ +#include "sysdep/faultinfo.h" struct arch_thread { + unsigned long debugregs[8]; + int debugregs_seq; + struct faultinfo faultinfo; }; /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */ @@ -20,7 +24,11 @@ extern inline void rep_nop(void) #define cpu_relax() rep_nop() -#define INIT_ARCH_THREAD { } +#define INIT_ARCH_THREAD { .debugregs = { [ 0 ... 7 ] = 0 }, \ + .debugregs_seq = 0, \ + .faultinfo = { 0, 0, 0 } } + +#include "asm/arch/user.h" #define current_text_addr() \ ({ void *pc; __asm__("movq $1f,%0\n1:":"=g" (pc)); pc; }) diff --git a/include/asm-um/ptrace-i386.h b/include/asm-um/ptrace-i386.h index 9e47590ec293..04222f35c43e 100644 --- a/include/asm-um/ptrace-i386.h +++ b/include/asm-um/ptrace-i386.h @@ -6,6 +6,8 @@ #ifndef __UM_PTRACE_I386_H #define __UM_PTRACE_I386_H +#define HOST_AUDIT_ARCH AUDIT_ARCH_I386 + #include "sysdep/ptrace.h" #include "asm/ptrace-generic.h" diff --git a/include/asm-um/ptrace-x86_64.h b/include/asm-um/ptrace-x86_64.h index c34be39b78b2..be51219a8ffe 100644 --- a/include/asm-um/ptrace-x86_64.h +++ b/include/asm-um/ptrace-x86_64.h @@ -14,6 +14,8 @@ #include "asm/ptrace-generic.h" #undef signal_fault +#define HOST_AUDIT_ARCH AUDIT_ARCH_X86_64 + void signal_fault(struct pt_regs_subarch *regs, void *frame, char *where); #define FS_BASE (21 * sizeof(unsigned long)) diff --git a/include/asm-um/setup.h b/include/asm-um/setup.h index c85252e803c1..99f086301f4c 100644 --- a/include/asm-um/setup.h +++ b/include/asm-um/setup.h @@ -2,7 +2,8 @@ #define SETUP_H_INCLUDED /* POSIX mandated with _POSIX_ARG_MAX that we can rely on 4096 chars in the - * command line, so this choice is ok.*/ + * command line, so this choice is ok. + */ #define COMMAND_LINE_SIZE 4096 diff --git a/include/asm-um/thread_info.h b/include/asm-um/thread_info.h index bffb577bc54e..a10ea155907e 100644 --- a/include/asm-um/thread_info.h +++ b/include/asm-um/thread_info.h @@ -72,12 +72,14 @@ static inline struct thread_info *current_thread_info(void) */ #define TIF_RESTART_BLOCK 4 #define TIF_MEMDIE 5 +#define TIF_SYSCALL_AUDIT 6 #define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE) #define _TIF_SIGPENDING (1 << TIF_SIGPENDING) #define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED) #define _TIF_POLLING_NRFLAG (1 << TIF_POLLING_NRFLAG) -#define _TIF_RESTART_BLOCK (1 << TIF_RESTART_BLOCK) +#define _TIF_MEMDIE (1 << TIF_MEMDIE) +#define _TIF_SYSCALL_AUDIT (1 << TIF_SYSCALL_AUDIT) #endif diff --git a/include/asm-v850/bug.h b/include/asm-v850/bug.h index c778916bf7f2..b0ed2d35f3e8 100644 --- a/include/asm-v850/bug.h +++ b/include/asm-v850/bug.h @@ -14,9 +14,12 @@ #ifndef __V850_BUG_H__ #define __V850_BUG_H__ +#ifdef CONFIG_BUG extern void __bug (void) __attribute__ ((noreturn)); #define BUG() __bug() #define HAVE_ARCH_BUG +#endif + #include <asm-generic/bug.h> #endif /* __V850_BUG_H__ */ diff --git a/include/asm-v850/signal.h b/include/asm-v850/signal.h index 407db875899c..cb52caa69925 100644 --- a/include/asm-v850/signal.h +++ b/include/asm-v850/signal.h @@ -110,32 +110,7 @@ typedef unsigned long sigset_t; #define MINSIGSTKSZ 2048 #define SIGSTKSZ 8192 - -#ifdef __KERNEL__ -/* - * These values of sa_flags are used only by the kernel as part of the - * irq handling routines. - * - * SA_INTERRUPT is also used by the irq handling routines. - * SA_SHIRQ is for shared interrupt support on PCI and EISA. - */ -#define SA_PROBE SA_ONESHOT -#define SA_SAMPLE_RANDOM SA_RESTART -#define SA_SHIRQ 0x04000000 -#endif /* __KERNEL__ */ - - -#define SIG_BLOCK 0 /* for blocking signals */ -#define SIG_UNBLOCK 1 /* for unblocking signals */ -#define SIG_SETMASK 2 /* for setting the signal mask */ - -/* Type of a signal handler. */ -typedef void (*__sighandler_t)(int); - -#define SIG_DFL ((__sighandler_t)0) /* default signal handling */ -#define SIG_IGN ((__sighandler_t)1) /* ignore signal */ -#define SIG_ERR ((__sighandler_t)-1) /* error return from signal */ - +#include <asm-generic/signal.h> #ifdef __KERNEL__ diff --git a/include/asm-x86_64/apic.h b/include/asm-x86_64/apic.h index c025cc3ef789..e4b1017b8b2b 100644 --- a/include/asm-x86_64/apic.h +++ b/include/asm-x86_64/apic.h @@ -99,7 +99,6 @@ extern void disable_APIC_timer(void); extern void enable_APIC_timer(void); extern void clustered_apic_check(void); -extern int check_nmi_watchdog(void); extern void nmi_watchdog_default(void); extern int setup_nmi_watchdog(char *); diff --git a/include/asm-x86_64/bootsetup.h b/include/asm-x86_64/bootsetup.h index b570a484dc50..b829f7b534be 100644 --- a/include/asm-x86_64/bootsetup.h +++ b/include/asm-x86_64/bootsetup.h @@ -2,7 +2,8 @@ #ifndef _X86_64_BOOTSETUP_H #define _X86_64_BOOTSETUP_H 1 -extern char x86_boot_params[2048]; +#define BOOT_PARAM_SIZE 4096 +extern char x86_boot_params[BOOT_PARAM_SIZE]; /* * This is set up by the setup-routine at boot-time diff --git a/include/asm-x86_64/bug.h b/include/asm-x86_64/bug.h index 19aed6e78fec..bdbf66eab6ee 100644 --- a/include/asm-x86_64/bug.h +++ b/include/asm-x86_64/bug.h @@ -15,11 +15,13 @@ struct bug_frame { unsigned short line; } __attribute__((packed)); +#ifdef CONFIG_BUG #define HAVE_ARCH_BUG #define BUG() \ asm volatile("ud2 ; .quad %c1 ; .short %c0" :: \ "i"(__LINE__), "i" (__stringify(__FILE__))) void out_of_line_bug(void); -#include <asm-generic/bug.h> +#endif +#include <asm-generic/bug.h> #endif diff --git a/include/asm-x86_64/cpufeature.h b/include/asm-x86_64/cpufeature.h index e68ad97a6319..aea308c65709 100644 --- a/include/asm-x86_64/cpufeature.h +++ b/include/asm-x86_64/cpufeature.h @@ -7,7 +7,7 @@ #ifndef __ASM_X8664_CPUFEATURE_H #define __ASM_X8664_CPUFEATURE_H -#define NCAPINTS 6 +#define NCAPINTS 7 /* N 32-bit words worth of info */ /* Intel-defined CPU features, CPUID level 0x00000001, word 0 */ #define X86_FEATURE_FPU (0*32+ 0) /* Onboard FPU */ @@ -74,9 +74,15 @@ #define X86_FEATURE_CX16 (4*32+13) /* CMPXCHG16B */ #define X86_FEATURE_XTPR (4*32+14) /* Send Task Priority Messages */ -/* More extended AMD flags: CPUID level 0x80000001, ecx, word 5 */ -#define X86_FEATURE_LAHF_LM (5*32+ 0) /* LAHF/SAHF in long mode */ -#define X86_FEATURE_CMP_LEGACY (5*32+ 1) /* If yes HyperThreading not valid */ +/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */ +#define X86_FEATURE_XSTORE (5*32+ 2) /* on-CPU RNG present (xstore insn) */ +#define X86_FEATURE_XSTORE_EN (5*32+ 3) /* on-CPU RNG enabled */ +#define X86_FEATURE_XCRYPT (5*32+ 6) /* on-CPU crypto (xcrypt insn) */ +#define X86_FEATURE_XCRYPT_EN (5*32+ 7) /* on-CPU crypto enabled */ + +/* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */ +#define X86_FEATURE_LAHF_LM (6*32+ 0) /* LAHF/SAHF in long mode */ +#define X86_FEATURE_CMP_LEGACY (6*32+ 1) /* If yes HyperThreading not valid */ #define cpu_has(c, bit) test_bit(bit, (c)->x86_capability) #define boot_cpu_has(bit) test_bit(bit, boot_cpu_data.x86_capability) diff --git a/include/asm-x86_64/e820.h b/include/asm-x86_64/e820.h index 08f83a4b4f4a..8e94edf0b984 100644 --- a/include/asm-x86_64/e820.h +++ b/include/asm-x86_64/e820.h @@ -14,7 +14,7 @@ #include <linux/mmzone.h> #define E820MAP 0x2d0 /* our map */ -#define E820MAX 32 /* number of entries in E820MAP */ +#define E820MAX 128 /* number of entries in E820MAP */ #define E820NR 0x1e8 /* # entries in E820MAP */ #define E820_RAM 1 diff --git a/include/asm-x86_64/floppy.h b/include/asm-x86_64/floppy.h index bca9b28a1a0a..af7ded63b517 100644 --- a/include/asm-x86_64/floppy.h +++ b/include/asm-x86_64/floppy.h @@ -223,7 +223,7 @@ static int hard_dma_setup(char *addr, unsigned long size, int mode, int io) return 0; } -struct fd_routine_l { +static struct fd_routine_l { int (*_request_dma)(unsigned int dmanr, const char * device_id); void (*_free_dma)(unsigned int dmanr); int (*_get_dma_residue)(unsigned int dummy); diff --git a/include/asm-x86_64/siginfo.h b/include/asm-x86_64/siginfo.h index 7bc15985f124..d09a1e6e7246 100644 --- a/include/asm-x86_64/siginfo.h +++ b/include/asm-x86_64/siginfo.h @@ -3,8 +3,6 @@ #define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int)) -#define SIGEV_PAD_SIZE ((SIGEV_MAX_SIZE/sizeof(int)) - 4) - #include <asm-generic/siginfo.h> #endif diff --git a/include/asm-x86_64/signal.h b/include/asm-x86_64/signal.h index 643a20d73765..fe9b96d94815 100644 --- a/include/asm-x86_64/signal.h +++ b/include/asm-x86_64/signal.h @@ -116,35 +116,9 @@ typedef unsigned long sigset_t; #define MINSIGSTKSZ 2048 #define SIGSTKSZ 8192 -#ifdef __KERNEL__ - -/* - * These values of sa_flags are used only by the kernel as part of the - * irq handling routines. - * - * SA_INTERRUPT is also used by the irq handling routines. - * SA_SHIRQ is for shared interrupt support on PCI and EISA. - */ -#define SA_PROBE SA_ONESHOT -#define SA_SAMPLE_RANDOM SA_RESTART -#define SA_SHIRQ 0x04000000 -#endif - -#define SIG_BLOCK 0 /* for blocking signals */ -#define SIG_UNBLOCK 1 /* for unblocking signals */ -#define SIG_SETMASK 2 /* for setting the signal mask */ +#include <asm-generic/signal.h> #ifndef __ASSEMBLY__ -/* Type of a signal handler. */ -typedef void __signalfn_t(int); -typedef __signalfn_t __user *__sighandler_t; - -typedef void __restorefn_t(void); -typedef __restorefn_t __user *__sigrestore_t; - -#define SIG_DFL ((__sighandler_t)0) /* default signal handling */ -#define SIG_IGN ((__sighandler_t)1) /* ignore signal */ -#define SIG_ERR ((__sighandler_t)-1) /* error return from signal */ struct sigaction { __sighandler_t sa_handler; diff --git a/include/asm-x86_64/unistd.h b/include/asm-x86_64/unistd.h index 3d65d240dc95..3c9af6fd4332 100644 --- a/include/asm-x86_64/unistd.h +++ b/include/asm-x86_64/unistd.h @@ -76,7 +76,7 @@ __SYSCALL(__NR_madvise, sys_madvise) #define __NR_shmget 29 __SYSCALL(__NR_shmget, sys_shmget) #define __NR_shmat 30 -__SYSCALL(__NR_shmat, wrap_sys_shmat) +__SYSCALL(__NR_shmat, sys_shmat) #define __NR_shmctl 31 __SYSCALL(__NR_shmctl, sys_shmctl) diff --git a/include/linux/audit.h b/include/linux/audit.h index 3628f7cfb178..19f04b049798 100644 --- a/include/linux/audit.h +++ b/include/linux/audit.h @@ -1,4 +1,4 @@ -/* audit.h -- Auditing support -*- linux-c -*- +/* audit.h -- Auditing support * * Copyright 2003-2004 Red Hat Inc., Durham, North Carolina. * All Rights Reserved. @@ -24,6 +24,9 @@ #ifndef _LINUX_AUDIT_H_ #define _LINUX_AUDIT_H_ +#include <linux/sched.h> +#include <linux/elf.h> + /* Request and reply types */ #define AUDIT_GET 1000 /* Get status */ #define AUDIT_SET 1001 /* Set status (enable/disable/auditd) */ @@ -67,6 +70,7 @@ #define AUDIT_FSGID 8 #define AUDIT_LOGINUID 9 #define AUDIT_PERS 10 +#define AUDIT_ARCH 11 /* These are ONLY useful when checking * at syscall exit time (AUDIT_AT_EXIT). */ @@ -96,6 +100,38 @@ #define AUDIT_FAIL_PRINTK 1 #define AUDIT_FAIL_PANIC 2 +/* distinguish syscall tables */ +#define __AUDIT_ARCH_64BIT 0x80000000 +#define __AUDIT_ARCH_LE 0x40000000 +#define AUDIT_ARCH_ALPHA (EM_ALPHA|__AUDIT_ARCH_64BIT|__AUDIT_ARCH_LE) +#define AUDIT_ARCH_ARM (EM_ARM|__AUDIT_ARCH_LE) +#define AUDIT_ARCH_ARMEB (EM_ARM) +#define AUDIT_ARCH_CRIS (EM_CRIS|__AUDIT_ARCH_LE) +#define AUDIT_ARCH_FRV (EM_FRV) +#define AUDIT_ARCH_H8300 (EM_H8_300) +#define AUDIT_ARCH_I386 (EM_386|__AUDIT_ARCH_LE) +#define AUDIT_ARCH_IA64 (EM_IA_64|__AUDIT_ARCH_64BIT|__AUDIT_ARCH_LE) +#define AUDIT_ARCH_M32R (EM_M32R) +#define AUDIT_ARCH_M68K (EM_68K) +#define AUDIT_ARCH_MIPS (EM_MIPS) +#define AUDIT_ARCH_MIPSEL (EM_MIPS|__AUDIT_ARCH_LE) +#define AUDIT_ARCH_MIPS64 (EM_MIPS|__AUDIT_ARCH_64BIT) +#define AUDIT_ARCH_MIPSEL64 (EM_MIPS|__AUDIT_ARCH_64BIT|__AUDIT_ARCH_LE) +#define AUDIT_ARCH_PARISC (EM_PARISC) +#define AUDIT_ARCH_PARISC64 (EM_PARISC|__AUDIT_ARCH_64BIT) +#define AUDIT_ARCH_PPC (EM_PPC) +#define AUDIT_ARCH_PPC64 (EM_PPC64|__AUDIT_ARCH_64BIT) +#define AUDIT_ARCH_S390 (EM_S390) +#define AUDIT_ARCH_S390X (EM_S390|__AUDIT_ARCH_64BIT) +#define AUDIT_ARCH_SH (EM_SH) +#define AUDIT_ARCH_SHEL (EM_SH|__AUDIT_ARCH_LE) +#define AUDIT_ARCH_SH64 (EM_SH|__AUDIT_ARCH_64BIT) +#define AUDIT_ARCH_SHEL64 (EM_SH|__AUDIT_ARCH_64BIT|__AUDIT_ARCH_LE) +#define AUDIT_ARCH_SPARC (EM_SPARC) +#define AUDIT_ARCH_SPARC64 (EM_SPARC64|__AUDIT_ARCH_64BIT) +#define AUDIT_ARCH_V850 (EM_V850|__AUDIT_ARCH_LE) +#define AUDIT_ARCH_X86_64 (EM_X86_64|__AUDIT_ARCH_64BIT|__AUDIT_ARCH_LE) + #ifndef __KERNEL__ struct audit_message { struct nlmsghdr nlh; @@ -129,32 +165,36 @@ struct audit_buffer; struct audit_context; struct inode; +#define AUDITSC_INVALID 0 +#define AUDITSC_SUCCESS 1 +#define AUDITSC_FAILURE 2 +#define AUDITSC_RESULT(x) ( ((long)(x))<0?AUDITSC_FAILURE:AUDITSC_SUCCESS ) #ifdef CONFIG_AUDITSYSCALL /* These are defined in auditsc.c */ /* Public API */ extern int audit_alloc(struct task_struct *task); extern void audit_free(struct task_struct *task); -extern void audit_syscall_entry(struct task_struct *task, +extern void audit_syscall_entry(struct task_struct *task, int arch, int major, unsigned long a0, unsigned long a1, unsigned long a2, unsigned long a3); -extern void audit_syscall_exit(struct task_struct *task, int return_code); +extern void audit_syscall_exit(struct task_struct *task, int failed, long return_code); extern void audit_getname(const char *name); extern void audit_putname(const char *name); extern void audit_inode(const char *name, const struct inode *inode); /* Private API (for audit.c only) */ extern int audit_receive_filter(int type, int pid, int uid, int seq, - void *data); + void *data, uid_t loginuid); extern void audit_get_stamp(struct audit_context *ctx, - struct timespec *t, int *serial); -extern int audit_set_loginuid(struct audit_context *ctx, uid_t loginuid); + struct timespec *t, unsigned int *serial); +extern int audit_set_loginuid(struct task_struct *task, uid_t loginuid); extern uid_t audit_get_loginuid(struct audit_context *ctx); extern int audit_ipc_perms(unsigned long qbytes, uid_t uid, gid_t gid, mode_t mode); #else #define audit_alloc(t) ({ 0; }) #define audit_free(t) do { ; } while (0) -#define audit_syscall_entry(t,a,b,c,d,e) do { ; } while (0) -#define audit_syscall_exit(t,r) do { ; } while (0) +#define audit_syscall_entry(t,ta,a,b,c,d,e) do { ; } while (0) +#define audit_syscall_exit(t,f,r) do { ; } while (0) #define audit_getname(n) do { ; } while (0) #define audit_putname(n) do { ; } while (0) #define audit_inode(n,i) do { ; } while (0) @@ -174,11 +214,15 @@ extern void audit_log_format(struct audit_buffer *ab, const char *fmt, ...) __attribute__((format(printf,2,3))); extern void audit_log_end(struct audit_buffer *ab); +extern void audit_log_hex(struct audit_buffer *ab, + const unsigned char *buf, + size_t len); +extern void audit_log_untrustedstring(struct audit_buffer *ab, + const char *string); extern void audit_log_d_path(struct audit_buffer *ab, const char *prefix, struct dentry *dentry, struct vfsmount *vfsmnt); - /* Private API (for auditsc.c only) */ extern void audit_send_reply(int pid, int seq, int type, int done, int multi, @@ -190,6 +234,8 @@ extern void audit_log_lost(const char *message); #define audit_log_vformat(b,f,a) do { ; } while (0) #define audit_log_format(b,f,...) do { ; } while (0) #define audit_log_end(b) do { ; } while (0) +#define audit_log_hex(a,b,l) do { ; } while (0) +#define audit_log_untrustedstring(a,s) do { ; } while (0) #define audit_log_d_path(b,p,d,v) do { ; } while (0) #endif #endif diff --git a/include/linux/auto_fs4.h b/include/linux/auto_fs4.h index d1c7b0ec7c22..a1657fb99516 100644 --- a/include/linux/auto_fs4.h +++ b/include/linux/auto_fs4.h @@ -23,7 +23,7 @@ #define AUTOFS_MIN_PROTO_VERSION 3 #define AUTOFS_MAX_PROTO_VERSION 4 -#define AUTOFS_PROTO_SUBVERSION 5 +#define AUTOFS_PROTO_SUBVERSION 6 /* Mask for expire behaviour */ #define AUTOFS_EXP_IMMEDIATE 1 diff --git a/include/linux/awe_voice.h b/include/linux/awe_voice.h index da0e27de752c..4bf9f33048e2 100644 --- a/include/linux/awe_voice.h +++ b/include/linux/awe_voice.h @@ -29,9 +29,9 @@ #define SAMPLE_TYPE_AWE32 0x20 #endif -#ifndef _PATCHKEY -#define _PATCHKEY(id) ((id<<8)|0xfd) -#endif +#define _LINUX_PATCHKEY_H_INDIRECT +#include <linux/patchkey.h> +#undef _LINUX_PATCHKEY_H_INDIRECT /*---------------------------------------------------------------- * patch information record diff --git a/include/linux/binfmts.h b/include/linux/binfmts.h index 54f820832c73..7e736e201c46 100644 --- a/include/linux/binfmts.h +++ b/include/linux/binfmts.h @@ -77,7 +77,6 @@ extern int flush_old_exec(struct linux_binprm * bprm); extern int setup_arg_pages(struct linux_binprm * bprm, unsigned long stack_top, int executable_stack); -extern int copy_strings(int argc,char __user * __user * argv,struct linux_binprm *bprm); extern int copy_strings_kernel(int argc,char ** argv,struct linux_binprm *bprm); extern void compute_creds(struct linux_binprm *binprm); extern int do_coredump(long signr, int exit_code, struct pt_regs * regs); diff --git a/include/linux/compiler-gcc2.h b/include/linux/compiler-gcc2.h index 5a359153ffd9..ebed17660c5f 100644 --- a/include/linux/compiler-gcc2.h +++ b/include/linux/compiler-gcc2.h @@ -22,3 +22,8 @@ # define __attribute_pure__ __attribute__((pure)) # define __attribute_const__ __attribute__((__const__)) #endif + +/* GCC 2.95.x/2.96 recognize __va_copy, but not va_copy. Actually later GCC's + * define both va_copy and __va_copy, but the latter may go away, so limit this + * to this header */ +#define va_copy __va_copy diff --git a/include/linux/compiler.h b/include/linux/compiler.h index 487725cf0d0d..d7378215b851 100644 --- a/include/linux/compiler.h +++ b/include/linux/compiler.h @@ -90,6 +90,12 @@ extern void __chk_io_ptr(void __iomem *); # define __deprecated /* unimplemented */ #endif +#ifdef MODULE +#define __deprecated_for_modules __deprecated +#else +#define __deprecated_for_modules +#endif + #ifndef __must_check #define __must_check #endif diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h index 910eca35583d..f21af067d015 100644 --- a/include/linux/cpufreq.h +++ b/include/linux/cpufreq.h @@ -103,6 +103,7 @@ struct cpufreq_policy { #define CPUFREQ_PRECHANGE (0) #define CPUFREQ_POSTCHANGE (1) #define CPUFREQ_RESUMECHANGE (8) +#define CPUFREQ_SUSPENDCHANGE (9) struct cpufreq_freqs { unsigned int cpu; /* cpu nr */ @@ -200,6 +201,7 @@ struct cpufreq_driver { /* optional */ int (*exit) (struct cpufreq_policy *policy); + int (*suspend) (struct cpufreq_policy *policy, u32 state); int (*resume) (struct cpufreq_policy *policy); struct freq_attr **attr; }; @@ -211,7 +213,8 @@ struct cpufreq_driver { #define CPUFREQ_CONST_LOOPS 0x02 /* loops_per_jiffy or other kernel * "constants" aren't affected by * frequency transitions */ - +#define CPUFREQ_PM_NO_WARN 0x04 /* don't warn on suspend/resume speed + * mismatches */ int cpufreq_register_driver(struct cpufreq_driver *driver_data); int cpufreq_unregister_driver(struct cpufreq_driver *driver_data); diff --git a/include/linux/edd.h b/include/linux/edd.h index c6e6747a401d..162512b886f7 100644 --- a/include/linux/edd.h +++ b/include/linux/edd.h @@ -32,7 +32,7 @@ #define EDDNR 0x1e9 /* addr of number of edd_info structs at EDDBUF in boot_params - treat this as 1 byte */ -#define EDDBUF 0x600 /* addr of edd_info structs in boot_params */ +#define EDDBUF 0xd00 /* addr of edd_info structs in boot_params */ #define EDDMAXNR 6 /* number of edd_info structs starting at EDDBUF */ #define EDDEXTSIZE 8 /* change these if you muck with the structures */ #define EDDPARMSIZE 74 diff --git a/include/linux/etherdevice.h b/include/linux/etherdevice.h index 396c48cbaeb1..220748b7abea 100644 --- a/include/linux/etherdevice.h +++ b/include/linux/etherdevice.h @@ -7,7 +7,7 @@ * * Version: @(#)eth.h 1.0.4 05/13/93 * - * Authors: Ross Biro, <bir7@leland.Stanford.Edu> + * Authors: Ross Biro * Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG> * * Relocated to include/linux where it belongs by Alan Cox diff --git a/include/linux/fb.h b/include/linux/fb.h index b45d3e2d711a..b468bf496547 100644 --- a/include/linux/fb.h +++ b/include/linux/fb.h @@ -563,6 +563,9 @@ struct fb_ops { int (*fb_setcolreg)(unsigned regno, unsigned red, unsigned green, unsigned blue, unsigned transp, struct fb_info *info); + /* set color registers in batch */ + int (*fb_setcmap)(struct fb_cmap *cmap, struct fb_info *info); + /* blank display */ int (*fb_blank)(int blank, struct fb_info *info); diff --git a/include/linux/fddidevice.h b/include/linux/fddidevice.h index 2e5ee47f3e1e..002f6367697d 100644 --- a/include/linux/fddidevice.h +++ b/include/linux/fddidevice.h @@ -10,7 +10,7 @@ * Author: Lawrence V. Stefani, <stefani@lkg.dec.com> * * fddidevice.h is based on previous trdevice.h work by - * Ross Biro, <bir7@leland.Stanford.Edu> + * Ross Biro * Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG> * Alan Cox, <gw4pts@gw4pts.ampr.org> * diff --git a/include/linux/fs.h b/include/linux/fs.h index 5df687d940fa..0180102dace1 100644 --- a/include/linux/fs.h +++ b/include/linux/fs.h @@ -1053,83 +1053,87 @@ static inline void file_accessed(struct file *file) int sync_inode(struct inode *inode, struct writeback_control *wbc); /** - * &export_operations - for nfsd to communicate with file systems - * decode_fh: decode a file handle fragment and return a &struct dentry - * encode_fh: encode a file handle fragment from a dentry - * get_name: find the name for a given inode in a given directory - * get_parent: find the parent of a given directory - * get_dentry: find a dentry for the inode given a file handle sub-fragment + * struct export_operations - for nfsd to communicate with file systems + * @decode_fh: decode a file handle fragment and return a &struct dentry + * @encode_fh: encode a file handle fragment from a dentry + * @get_name: find the name for a given inode in a given directory + * @get_parent: find the parent of a given directory + * @get_dentry: find a dentry for the inode given a file handle sub-fragment * * Description: * The export_operations structure provides a means for nfsd to communicate * with a particular exported file system - particularly enabling nfsd and * the filesystem to co-operate when dealing with file handles. * - * export_operations contains two basic operation for dealing with file handles, - * decode_fh() and encode_fh(), and allows for some other operations to be defined - * which standard helper routines use to get specific information from the - * filesystem. + * export_operations contains two basic operation for dealing with file + * handles, decode_fh() and encode_fh(), and allows for some other + * operations to be defined which standard helper routines use to get + * specific information from the filesystem. * * nfsd encodes information use to determine which filesystem a filehandle - * applies to in the initial part of the file handle. The remainder, termed a - * file handle fragment, is controlled completely by the filesystem. - * The standard helper routines assume that this fragment will contain one or two - * sub-fragments, one which identifies the file, and one which may be used to - * identify the (a) directory containing the file. + * applies to in the initial part of the file handle. The remainder, termed + * a file handle fragment, is controlled completely by the filesystem. The + * standard helper routines assume that this fragment will contain one or + * two sub-fragments, one which identifies the file, and one which may be + * used to identify the (a) directory containing the file. * * In some situations, nfsd needs to get a dentry which is connected into a - * specific part of the file tree. To allow for this, it passes the function - * acceptable() together with a @context which can be used to see if the dentry - * is acceptable. As there can be multiple dentrys for a given file, the filesystem - * should check each one for acceptability before looking for the next. As soon - * as an acceptable one is found, it should be returned. + * specific part of the file tree. To allow for this, it passes the + * function acceptable() together with a @context which can be used to see + * if the dentry is acceptable. As there can be multiple dentrys for a + * given file, the filesystem should check each one for acceptability before + * looking for the next. As soon as an acceptable one is found, it should + * be returned. * * decode_fh: - * @decode_fh is given a &struct super_block (@sb), a file handle fragment (@fh, @fh_len) - * and an acceptability testing function (@acceptable, @context). It should return - * a &struct dentry which refers to the same file that the file handle fragment refers - * to, and which passes the acceptability test. If it cannot, it should return - * a %NULL pointer if the file was found but no acceptable &dentries were available, or - * a %ERR_PTR error code indicating why it couldn't be found (e.g. %ENOENT or %ENOMEM). + * @decode_fh is given a &struct super_block (@sb), a file handle fragment + * (@fh, @fh_len) and an acceptability testing function (@acceptable, + * @context). It should return a &struct dentry which refers to the same + * file that the file handle fragment refers to, and which passes the + * acceptability test. If it cannot, it should return a %NULL pointer if + * the file was found but no acceptable &dentries were available, or a + * %ERR_PTR error code indicating why it couldn't be found (e.g. %ENOENT or + * %ENOMEM). * * encode_fh: - * @encode_fh should store in the file handle fragment @fh (using at most @max_len bytes) - * information that can be used by @decode_fh to recover the file refered to by the - * &struct dentry @de. If the @connectable flag is set, the encode_fh() should store - * sufficient information so that a good attempt can be made to find not only - * the file but also it's place in the filesystem. This typically means storing - * a reference to de->d_parent in the filehandle fragment. - * encode_fh() should return the number of bytes stored or a negative error code - * such as %-ENOSPC + * @encode_fh should store in the file handle fragment @fh (using at most + * @max_len bytes) information that can be used by @decode_fh to recover the + * file refered to by the &struct dentry @de. If the @connectable flag is + * set, the encode_fh() should store sufficient information so that a good + * attempt can be made to find not only the file but also it's place in the + * filesystem. This typically means storing a reference to de->d_parent in + * the filehandle fragment. encode_fh() should return the number of bytes + * stored or a negative error code such as %-ENOSPC * * get_name: - * @get_name should find a name for the given @child in the given @parent directory. - * The name should be stored in the @name (with the understanding that it is already - * pointing to a a %NAME_MAX+1 sized buffer. get_name() should return %0 on success, - * a negative error code or error. - * @get_name will be called without @parent->i_sem held. + * @get_name should find a name for the given @child in the given @parent + * directory. The name should be stored in the @name (with the + * understanding that it is already pointing to a a %NAME_MAX+1 sized + * buffer. get_name() should return %0 on success, a negative error code + * or error. @get_name will be called without @parent->i_sem held. * * get_parent: - * @get_parent should find the parent directory for the given @child which is also - * a directory. In the event that it cannot be found, or storage space cannot be - * allocated, a %ERR_PTR should be returned. + * @get_parent should find the parent directory for the given @child which + * is also a directory. In the event that it cannot be found, or storage + * space cannot be allocated, a %ERR_PTR should be returned. * * get_dentry: - * Given a &super_block (@sb) and a pointer to a file-system specific inode identifier, - * possibly an inode number, (@inump) get_dentry() should find the identified inode and - * return a dentry for that inode. - * Any suitable dentry can be returned including, if necessary, a new dentry created - * with d_alloc_root. The caller can then find any other extant dentrys by following the - * d_alias links. If a new dentry was created using d_alloc_root, DCACHE_NFSD_DISCONNECTED - * should be set, and the dentry should be d_rehash()ed. + * Given a &super_block (@sb) and a pointer to a file-system specific inode + * identifier, possibly an inode number, (@inump) get_dentry() should find + * the identified inode and return a dentry for that inode. Any suitable + * dentry can be returned including, if necessary, a new dentry created with + * d_alloc_root. The caller can then find any other extant dentrys by + * following the d_alias links. If a new dentry was created using + * d_alloc_root, DCACHE_NFSD_DISCONNECTED should be set, and the dentry + * should be d_rehash()ed. * - * If the inode cannot be found, either a %NULL pointer or an %ERR_PTR code can be returned. - * The @inump will be whatever was passed to nfsd_find_fh_dentry() in either the - * @obj or @parent parameters. + * If the inode cannot be found, either a %NULL pointer or an %ERR_PTR code + * can be returned. The @inump will be whatever was passed to + * nfsd_find_fh_dentry() in either the @obj or @parent parameters. * * Locking rules: - * get_parent is called with child->d_inode->i_sem down - * get_name is not (which is possibly inconsistent) + * get_parent is called with child->d_inode->i_sem down + * get_name is not (which is possibly inconsistent) */ struct export_operations { @@ -1337,7 +1341,7 @@ extern int fs_may_remount_ro(struct super_block *); extern int check_disk_change(struct block_device *); extern int invalidate_inodes(struct super_block *); -extern int __invalidate_device(struct block_device *, int); +extern int __invalidate_device(struct block_device *); extern int invalidate_partition(struct gendisk *, int); unsigned long invalidate_mapping_pages(struct address_space *mapping, pgoff_t start, pgoff_t end); diff --git a/include/linux/gfp.h b/include/linux/gfp.h index 848a1baac079..af7407e8cfc5 100644 --- a/include/linux/gfp.h +++ b/include/linux/gfp.h @@ -38,14 +38,16 @@ struct vm_area_struct; #define __GFP_NO_GROW 0x2000u /* Slab internal usage */ #define __GFP_COMP 0x4000u /* Add compound page metadata */ #define __GFP_ZERO 0x8000u /* Return zeroed page on success */ +#define __GFP_NOMEMALLOC 0x10000u /* Don't use emergency reserves */ -#define __GFP_BITS_SHIFT 16 /* Room for 16 __GFP_FOO bits */ +#define __GFP_BITS_SHIFT 20 /* Room for 20 __GFP_FOO bits */ #define __GFP_BITS_MASK ((1 << __GFP_BITS_SHIFT) - 1) /* if you forget to add the bitmask here kernel will crash, period */ #define GFP_LEVEL_MASK (__GFP_WAIT|__GFP_HIGH|__GFP_IO|__GFP_FS| \ __GFP_COLD|__GFP_NOWARN|__GFP_REPEAT| \ - __GFP_NOFAIL|__GFP_NORETRY|__GFP_NO_GROW|__GFP_COMP) + __GFP_NOFAIL|__GFP_NORETRY|__GFP_NO_GROW|__GFP_COMP| \ + __GFP_NOMEMALLOC) #define GFP_ATOMIC (__GFP_HIGH) #define GFP_NOIO (__GFP_WAIT) diff --git a/include/linux/hippidevice.h b/include/linux/hippidevice.h index 89b3a4a5b761..9debe6bbe5f0 100644 --- a/include/linux/hippidevice.h +++ b/include/linux/hippidevice.h @@ -10,7 +10,7 @@ * Author: Jes Sorensen, <Jes.Sorensen@cern.ch> * * hippidevice.h is based on previous fddidevice.h work by - * Ross Biro, <bir7@leland.Stanford.Edu> + * Ross Biro * Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG> * Alan Cox, <gw4pts@gw4pts.ampr.org> * Lawrence V. Stefani, <stefani@lkg.dec.com> diff --git a/include/linux/if.h b/include/linux/if.h index 110282dbd3e0..d73a9d62f208 100644 --- a/include/linux/if.h +++ b/include/linux/if.h @@ -8,7 +8,7 @@ * Version: @(#)if.h 1.0.2 04/18/93 * * Authors: Original taken from Berkeley UNIX 4.3, (c) UCB 1982-1988 - * Ross Biro, <bir7@leland.Stanford.Edu> + * Ross Biro * Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG> * * This program is free software; you can redistribute it and/or diff --git a/include/linux/if_arp.h b/include/linux/if_arp.h index bbf49bcd7705..0856548a2a08 100644 --- a/include/linux/if_arp.h +++ b/include/linux/if_arp.h @@ -9,7 +9,7 @@ * * Authors: Original taken from Berkeley UNIX 4.3, (c) UCB 1986-1988 * Portions taken from the KA9Q/NOS (v2.00m PA0GRI) source. - * Ross Biro, <bir7@leland.Stanford.Edu> + * Ross Biro * Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG> * Florian La Roche, * Jonathan Layes <layes@loran.com> diff --git a/include/linux/if_ltalk.h b/include/linux/if_ltalk.h index e75e832b7ff0..76525760ba48 100644 --- a/include/linux/if_ltalk.h +++ b/include/linux/if_ltalk.h @@ -6,7 +6,7 @@ #define LTALK_ALEN 1 #ifdef __KERNEL__ -extern void ltalk_setup(struct net_device *); +extern struct net_device *alloc_ltalkdev(int sizeof_priv); #endif #endif diff --git a/include/linux/input.h b/include/linux/input.h index b70df8fe60e6..72731d7d189e 100644 --- a/include/linux/input.h +++ b/include/linux/input.h @@ -328,6 +328,11 @@ struct input_absinfo { #define KEY_BRIGHTNESSUP 225 #define KEY_MEDIA 226 +#define KEY_SWITCHVIDEOMODE 227 +#define KEY_KBDILLUMTOGGLE 228 +#define KEY_KBDILLUMDOWN 229 +#define KEY_KBDILLUMUP 230 + #define KEY_UNKNOWN 240 #define BTN_MISC 0x100 diff --git a/include/linux/iso_fs.h b/include/linux/iso_fs.h index 099039d4b10d..47967878bfef 100644 --- a/include/linux/iso_fs.h +++ b/include/linux/iso_fs.h @@ -1,4 +1,3 @@ - #ifndef _ISOFS_FS_H #define _ISOFS_FS_H @@ -163,150 +162,4 @@ struct iso_directory_record { #define ISOFS_SUPER_MAGIC 0x9660 -#ifdef __KERNEL__ -/* Number conversion inlines, named after the section in ISO 9660 - they correspond to. */ - -#include <asm/byteorder.h> -#include <asm/unaligned.h> -#include <linux/iso_fs_i.h> -#include <linux/iso_fs_sb.h> - -static inline struct isofs_sb_info *ISOFS_SB(struct super_block *sb) -{ - return sb->s_fs_info; -} - -static inline struct iso_inode_info *ISOFS_I(struct inode *inode) -{ - return container_of(inode, struct iso_inode_info, vfs_inode); -} - -static inline int isonum_711(char *p) -{ - return *(u8 *)p; -} -static inline int isonum_712(char *p) -{ - return *(s8 *)p; -} -static inline unsigned int isonum_721(char *p) -{ - return le16_to_cpu(get_unaligned((__le16 *)p)); -} -static inline unsigned int isonum_722(char *p) -{ - return be16_to_cpu(get_unaligned((__le16 *)p)); -} -static inline unsigned int isonum_723(char *p) -{ - /* Ignore bigendian datum due to broken mastering programs */ - return le16_to_cpu(get_unaligned((__le16 *)p)); -} -static inline unsigned int isonum_731(char *p) -{ - return le32_to_cpu(get_unaligned((__le32 *)p)); -} -static inline unsigned int isonum_732(char *p) -{ - return be32_to_cpu(get_unaligned((__le32 *)p)); -} -static inline unsigned int isonum_733(char *p) -{ - /* Ignore bigendian datum due to broken mastering programs */ - return le32_to_cpu(get_unaligned((__le32 *)p)); -} -extern int iso_date(char *, int); - -struct inode; /* To make gcc happy */ - -extern int parse_rock_ridge_inode(struct iso_directory_record *, struct inode *); -extern int get_rock_ridge_filename(struct iso_directory_record *, char *, struct inode *); -extern int isofs_name_translate(struct iso_directory_record *, char *, struct inode *); - -int get_joliet_filename(struct iso_directory_record *, unsigned char *, struct inode *); -int get_acorn_filename(struct iso_directory_record *, char *, struct inode *); - -extern struct dentry *isofs_lookup(struct inode *, struct dentry *, struct nameidata *); -extern struct buffer_head *isofs_bread(struct inode *, sector_t); -extern int isofs_get_blocks(struct inode *, sector_t, struct buffer_head **, unsigned long); - -extern struct inode *isofs_iget(struct super_block *sb, - unsigned long block, - unsigned long offset); - -/* Because the inode number is no longer relevant to finding the - * underlying meta-data for an inode, we are free to choose a more - * convenient 32-bit number as the inode number. The inode numbering - * scheme was recommended by Sergey Vlasov and Eric Lammerts. */ -static inline unsigned long isofs_get_ino(unsigned long block, - unsigned long offset, - unsigned long bufbits) -{ - return (block << (bufbits - 5)) | (offset >> 5); -} - -/* Every directory can have many redundant directory entries scattered - * throughout the directory tree. First there is the directory entry - * with the name of the directory stored in the parent directory. - * Then, there is the "." directory entry stored in the directory - * itself. Finally, there are possibly many ".." directory entries - * stored in all the subdirectories. - * - * In order for the NFS get_parent() method to work and for the - * general consistency of the dcache, we need to make sure the - * "i_iget5_block" and "i_iget5_offset" all point to exactly one of - * the many redundant entries for each directory. We normalize the - * block and offset by always making them point to the "." directory. - * - * Notice that we do not use the entry for the directory with the name - * that is located in the parent directory. Even though choosing this - * first directory is more natural, it is much easier to find the "." - * entry in the NFS get_parent() method because it is implicitly - * encoded in the "extent + ext_attr_length" fields of _all_ the - * redundant entries for the directory. Thus, it can always be - * reached regardless of which directory entry you have in hand. - * - * This works because the "." entry is simply the first directory - * record when you start reading the file that holds all the directory - * records, and this file starts at "extent + ext_attr_length" blocks. - * Because the "." entry is always the first entry listed in the - * directories file, the normalized "offset" value is always 0. - * - * You should pass the directory entry in "de". On return, "block" - * and "offset" will hold normalized values. Only directories are - * affected making it safe to call even for non-directory file - * types. */ -static inline void -isofs_normalize_block_and_offset(struct iso_directory_record* de, - unsigned long *block, - unsigned long *offset) -{ - /* Only directories are normalized. */ - if (de->flags[0] & 2) { - *offset = 0; - *block = (unsigned long)isonum_733(de->extent) - + (unsigned long)isonum_711(de->ext_attr_length); - } -} - -extern struct inode_operations isofs_dir_inode_operations; -extern struct file_operations isofs_dir_operations; -extern struct address_space_operations isofs_symlink_aops; -extern struct export_operations isofs_export_ops; - -/* The following macros are used to check for memory leaks. */ -#ifdef LEAK_CHECK -#define free_s leak_check_free_s -#define malloc leak_check_malloc -#define sb_bread leak_check_bread -#define brelse leak_check_brelse -extern void * leak_check_malloc(unsigned int size); -extern void leak_check_free_s(void * obj, int size); -extern struct buffer_head * leak_check_bread(struct super_block *sb, int block); -extern void leak_check_brelse(struct buffer_head * bh); -#endif /* LEAK_CHECK */ - -#endif /* __KERNEL__ */ - #endif diff --git a/include/linux/iso_fs_i.h b/include/linux/iso_fs_i.h deleted file mode 100644 index 59065e939eaa..000000000000 --- a/include/linux/iso_fs_i.h +++ /dev/null @@ -1,27 +0,0 @@ -#ifndef _ISO_FS_I -#define _ISO_FS_I - -#include <linux/fs.h> - -enum isofs_file_format { - isofs_file_normal = 0, - isofs_file_sparse = 1, - isofs_file_compressed = 2, -}; - -/* - * iso fs inode data in memory - */ -struct iso_inode_info { - unsigned long i_iget5_block; - unsigned long i_iget5_offset; - unsigned int i_first_extent; - unsigned char i_file_format; - unsigned char i_format_parm[3]; - unsigned long i_next_section_block; - unsigned long i_next_section_offset; - off_t i_section_size; - struct inode vfs_inode; -}; - -#endif diff --git a/include/linux/iso_fs_sb.h b/include/linux/iso_fs_sb.h deleted file mode 100644 index 043b97b55b8d..000000000000 --- a/include/linux/iso_fs_sb.h +++ /dev/null @@ -1,34 +0,0 @@ -#ifndef _ISOFS_FS_SB -#define _ISOFS_FS_SB - -/* - * iso9660 super-block data in memory - */ -struct isofs_sb_info { - unsigned long s_ninodes; - unsigned long s_nzones; - unsigned long s_firstdatazone; - unsigned long s_log_zone_size; - unsigned long s_max_size; - - unsigned char s_high_sierra; /* A simple flag */ - unsigned char s_mapping; - int s_rock_offset; /* offset of SUSP fields within SU area */ - unsigned char s_rock; - unsigned char s_joliet_level; - unsigned char s_utf8; - unsigned char s_cruft; /* Broken disks with high - byte of length containing - junk */ - unsigned char s_unhide; - unsigned char s_nosuid; - unsigned char s_nodev; - unsigned char s_nocompress; - - mode_t s_mode; - gid_t s_gid; - uid_t s_uid; - struct nls_table *s_nls_iocharset; /* Native language support table */ -}; - -#endif diff --git a/include/linux/ixjuser.h b/include/linux/ixjuser.h index 88121166d715..fd1756d3a47e 100644 --- a/include/linux/ixjuser.h +++ b/include/linux/ixjuser.h @@ -42,8 +42,6 @@ * *****************************************************************************/ -static char ixjuser_h_rcsid[] = "$Id: ixjuser.h,v 4.1 2001/08/05 00:17:37 craigs Exp $"; - #include <linux/telephony.h> diff --git a/include/linux/kernel.h b/include/linux/kernel.h index 7c1cba4a5278..e25b97062ce1 100644 --- a/include/linux/kernel.h +++ b/include/linux/kernel.h @@ -115,10 +115,19 @@ extern int __kernel_text_address(unsigned long addr); extern int kernel_text_address(unsigned long addr); extern int session_of_pgrp(int pgrp); +#ifdef CONFIG_PRINTK asmlinkage int vprintk(const char *fmt, va_list args) __attribute__ ((format (printf, 1, 0))); asmlinkage int printk(const char * fmt, ...) __attribute__ ((format (printf, 1, 2))); +#else +static inline int vprintk(const char *s, va_list args) + __attribute__ ((format (printf, 1, 0))); +static inline int vprintk(const char *s, va_list args) { return 0; } +static inline int printk(const char *s, ...) + __attribute__ ((format (printf, 1, 2))); +static inline int printk(const char *s, ...) { return 0; } +#endif unsigned long int_sqrt(unsigned long); diff --git a/include/linux/kprobes.h b/include/linux/kprobes.h index f20c163de4f5..99ddba5a4e00 100644 --- a/include/linux/kprobes.h +++ b/include/linux/kprobes.h @@ -43,6 +43,9 @@ typedef int (*kprobe_fault_handler_t) (struct kprobe *, struct pt_regs *, struct kprobe { struct hlist_node hlist; + /* list of kprobes for multi-handler support */ + struct list_head list; + /* location of the probe point */ kprobe_opcode_t *addr; diff --git a/include/linux/mm.h b/include/linux/mm.h index c74a74ca401d..17518fe0b311 100644 --- a/include/linux/mm.h +++ b/include/linux/mm.h @@ -637,9 +637,9 @@ extern unsigned long do_mremap(unsigned long addr, * These functions are passed a count `nr_to_scan' and a gfpmask. They should * scan `nr_to_scan' objects, attempting to free them. * - * The callback must the number of objects which remain in the cache. + * The callback must return the number of objects which remain in the cache. * - * The callback will be passes nr_to_scan == 0 when the VM is querying the + * The callback will be passed nr_to_scan == 0 when the VM is querying the * cache size, so a fastpath for that case is appropriate. */ typedef int (*shrinker_t)(int nr_to_scan, unsigned int gfp_mask); @@ -726,6 +726,7 @@ extern void __vma_link_rb(struct mm_struct *, struct vm_area_struct *, extern struct vm_area_struct *copy_vma(struct vm_area_struct **, unsigned long addr, unsigned long len, pgoff_t pgoff); extern void exit_mmap(struct mm_struct *); +extern int may_expand_vm(struct mm_struct *mm, unsigned long npages); extern unsigned long get_unmapped_area(struct file *, unsigned long, unsigned long, unsigned long, unsigned long); diff --git a/include/linux/mpage.h b/include/linux/mpage.h index dea1b0083661..3ca880463c47 100644 --- a/include/linux/mpage.h +++ b/include/linux/mpage.h @@ -20,9 +20,6 @@ int mpage_writepages(struct address_space *mapping, struct writeback_control *wbc, get_block_t get_block); int mpage_writepage(struct page *page, get_block_t *get_block, struct writeback_control *wbc); -int __mpage_writepages(struct address_space *mapping, - struct writeback_control *wbc, get_block_t get_block, - writepage_t writepage); static inline int generic_writepages(struct address_space *mapping, struct writeback_control *wbc) diff --git a/include/linux/net.h b/include/linux/net.h index 7823b3482506..6d997ff3f103 100644 --- a/include/linux/net.h +++ b/include/linux/net.h @@ -7,7 +7,7 @@ * Version: @(#)net.h 1.0.3 05/25/93 * * Authors: Orest Zborowski, <obz@Kodak.COM> - * Ross Biro, <bir7@leland.Stanford.Edu> + * Ross Biro * Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG> * * This program is free software; you can redistribute it and/or @@ -64,19 +64,19 @@ typedef enum { #define SOCK_PASSCRED 3 #ifndef ARCH_HAS_SOCKET_TYPES -/** sock_type - Socket types - * +/** + * enum sock_type - Socket types + * @SOCK_STREAM: stream (connection) socket + * @SOCK_DGRAM: datagram (conn.less) socket + * @SOCK_RAW: raw socket + * @SOCK_RDM: reliably-delivered message + * @SOCK_SEQPACKET: sequential packet socket + * @SOCK_PACKET: linux specific way of getting packets at the dev level. + * For writing rarp and other similar things on the user level. + * * When adding some new socket type please * grep ARCH_HAS_SOCKET_TYPE include/asm-* /socket.h, at least MIPS * overrides this enum for binary compat reasons. - * - * @SOCK_STREAM - stream (connection) socket - * @SOCK_DGRAM - datagram (conn.less) socket - * @SOCK_RAW - raw socket - * @SOCK_RDM - reliably-delivered message - * @SOCK_SEQPACKET - sequential packet socket - * @SOCK_PACKET - linux specific way of getting packets at the dev level. - * For writing rarp and other similar things on the user level. */ enum sock_type { SOCK_STREAM = 1, @@ -93,15 +93,15 @@ enum sock_type { /** * struct socket - general BSD socket - * @state - socket state (%SS_CONNECTED, etc) - * @flags - socket flags (%SOCK_ASYNC_NOSPACE, etc) - * @ops - protocol specific socket operations - * @fasync_list - Asynchronous wake up list - * @file - File back pointer for gc - * @sk - internal networking protocol agnostic socket representation - * @wait - wait queue for several uses - * @type - socket type (%SOCK_STREAM, etc) - * @passcred - credentials (used only in Unix Sockets (aka PF_LOCAL)) + * @state: socket state (%SS_CONNECTED, etc) + * @flags: socket flags (%SOCK_ASYNC_NOSPACE, etc) + * @ops: protocol specific socket operations + * @fasync_list: Asynchronous wake up list + * @file: File back pointer for gc + * @sk: internal networking protocol agnostic socket representation + * @wait: wait queue for several uses + * @type: socket type (%SOCK_STREAM, etc) + * @passcred: credentials (used only in Unix Sockets (aka PF_LOCAL)) */ struct socket { socket_state state; diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h index 8d775be67833..ac11d73be4ce 100644 --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h @@ -7,7 +7,7 @@ * * Version: @(#)dev.h 1.0.10 08/12/93 * - * Authors: Ross Biro, <bir7@leland.Stanford.Edu> + * Authors: Ross Biro * Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG> * Corey Minyard <wf-rch!minyard@relay.EU.net> * Donald J. Becker, <becker@cesdis.gsfc.nasa.gov> diff --git a/include/linux/netfilter_ipv4.h b/include/linux/netfilter_ipv4.h index c9bacf9b2431..9e5750079e09 100644 --- a/include/linux/netfilter_ipv4.h +++ b/include/linux/netfilter_ipv4.h @@ -62,6 +62,9 @@ enum nf_ip_hook_priorities { NF_IP_PRI_FILTER = 0, NF_IP_PRI_NAT_SRC = 100, NF_IP_PRI_SELINUX_LAST = 225, + NF_IP_PRI_CONNTRACK_HELPER = INT_MAX - 2, + NF_IP_PRI_NAT_SEQ_ADJUST = INT_MAX - 1, + NF_IP_PRI_CONNTRACK_CONFIRM = INT_MAX, NF_IP_PRI_LAST = INT_MAX, }; diff --git a/include/linux/netlink.h b/include/linux/netlink.h index f731abdc1a29..b2738ac8bc99 100644 --- a/include/linux/netlink.h +++ b/include/linux/netlink.h @@ -110,6 +110,7 @@ struct netlink_skb_parms __u32 dst_pid; __u32 dst_groups; kernel_cap_t eff_cap; + __u32 loginuid; /* Login (audit) uid */ }; #define NETLINK_CB(skb) (*(struct netlink_skb_parms*)&((skb)->cb)) diff --git a/include/linux/page-flags.h b/include/linux/page-flags.h index 6b74fcf5bb63..39ab8c6b5652 100644 --- a/include/linux/page-flags.h +++ b/include/linux/page-flags.h @@ -131,6 +131,7 @@ struct page_state { unsigned long allocstall; /* direct reclaim calls */ unsigned long pgrotated; /* pages rotated to tail of the LRU */ + unsigned long nr_bounce; /* pages for bounce buffers */ }; extern void get_page_state(struct page_state *ret); diff --git a/include/linux/patchkey.h b/include/linux/patchkey.h new file mode 100644 index 000000000000..d974a6e92372 --- /dev/null +++ b/include/linux/patchkey.h @@ -0,0 +1,45 @@ +/* + * <linux/patchkey.h> -- definition of _PATCHKEY macro + * + * Copyright (C) 2005 Stuart Brady + * + * This exists because awe_voice.h defined its own _PATCHKEY and it wasn't + * clear whether removing this would break anything in userspace. + * + * Do not include this file directly. Please use <sys/soundcard.h> instead. + * For kernel code, use <linux/soundcard.h> + */ + +#ifndef _LINUX_PATCHKEY_H_INDIRECT +#error "patchkey.h included directly" +#endif + +#ifndef _LINUX_PATCHKEY_H +#define _LINUX_PATCHKEY_H + +/* Endian macros. */ +#ifdef __KERNEL__ +# include <asm/byteorder.h> +#else +# include <endian.h> +#endif + +#if defined(__KERNEL__) +# if defined(__BIG_ENDIAN) +# define _PATCHKEY(id) (0xfd00|id) +# elif defined(__LITTLE_ENDIAN) +# define _PATCHKEY(id) ((id<<8)|0x00fd) +# else +# error "could not determine byte order" +# endif +#elif defined(__BYTE_ORDER) +# if __BYTE_ORDER == __BIG_ENDIAN +# define _PATCHKEY(id) (0xfd00|id) +# elif __BYTE_ORDER == __LITTLE_ENDIAN +# define _PATCHKEY(id) ((id<<8)|0x00fd) +# else +# error "could not determine byte order" +# endif +#endif + +#endif /* _LINUX_PATCHKEY_H */ diff --git a/include/linux/pci.h b/include/linux/pci.h index 3c89148ae28a..b5238bd18830 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -671,6 +671,7 @@ struct pci_driver { int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ int (*resume) (struct pci_dev *dev); /* Device woken up */ int (*enable_wake) (struct pci_dev *dev, pci_power_t state, int enable); /* Enable wake event */ + void (*shutdown) (struct pci_dev *dev); struct device_driver driver; struct pci_dynids dynids; @@ -810,7 +811,6 @@ void pci_set_master(struct pci_dev *dev); int pci_set_mwi(struct pci_dev *dev); void pci_clear_mwi(struct pci_dev *dev); int pci_set_dma_mask(struct pci_dev *dev, u64 mask); -int pci_dac_set_dma_mask(struct pci_dev *dev, u64 mask); int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask); int pci_assign_resource(struct pci_dev *dev, int i); @@ -941,7 +941,6 @@ static inline void pci_set_master(struct pci_dev *dev) { } static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } static inline void pci_disable_device(struct pci_dev *dev) { } static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) { return -EIO; } -static inline int pci_dac_set_dma_mask(struct pci_dev *dev, u64 mask) { return -EIO; } static inline int pci_assign_resource(struct pci_dev *dev, int i) { return -EBUSY;} static inline int pci_register_driver(struct pci_driver *drv) { return 0;} static inline void pci_unregister_driver(struct pci_driver *drv) { } diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index f1f75fde8cd4..ae27792b5aa4 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -854,6 +854,7 @@ #define PCI_DEVICE_ID_MYLEX_DAC960_LA 0x0020 #define PCI_DEVICE_ID_MYLEX_DAC960_LP 0x0050 #define PCI_DEVICE_ID_MYLEX_DAC960_BA 0xBA56 +#define PCI_DEVICE_ID_MYLEX_DAC960_GEM 0xB166 #define PCI_VENDOR_ID_PICOP 0x1066 #define PCI_DEVICE_ID_PICOP_PT86C52X 0x0001 @@ -2062,6 +2063,7 @@ #define PCI_DEVICE_ID_AFAVLAB_P030 0x2182 #define PCI_VENDOR_ID_BROADCOM 0x14e4 +#define PCI_DEVICE_ID_TIGON3_5752 0x1600 #define PCI_DEVICE_ID_TIGON3_5700 0x1644 #define PCI_DEVICE_ID_TIGON3_5701 0x1645 #define PCI_DEVICE_ID_TIGON3_5702 0x1646 @@ -2414,6 +2416,8 @@ #define PCI_DEVICE_ID_INTEL_ICH7_1 0x27b9 #define PCI_DEVICE_ID_INTEL_ICH7_2 0x27c0 #define PCI_DEVICE_ID_INTEL_ICH7_3 0x27c1 +#define PCI_DEVICE_ID_INTEL_ICH7_30 0x27b0 +#define PCI_DEVICE_ID_INTEL_ICH7_31 0x27bd #define PCI_DEVICE_ID_INTEL_ICH7_5 0x27c4 #define PCI_DEVICE_ID_INTEL_ICH7_6 0x27c5 #define PCI_DEVICE_ID_INTEL_ICH7_7 0x27c8 diff --git a/include/linux/rcupdate.h b/include/linux/rcupdate.h index 4d747433916b..fd276adf0fd5 100644 --- a/include/linux/rcupdate.h +++ b/include/linux/rcupdate.h @@ -157,9 +157,9 @@ static inline int rcu_pending(int cpu) /** * rcu_read_lock - mark the beginning of an RCU read-side critical section. * - * When synchronize_kernel() is invoked on one CPU while other CPUs + * When synchronize_rcu() is invoked on one CPU while other CPUs * are within RCU read-side critical sections, then the - * synchronize_kernel() is guaranteed to block until after all the other + * synchronize_rcu() is guaranteed to block until after all the other * CPUs exit their critical sections. Similarly, if call_rcu() is invoked * on one CPU while other CPUs are within RCU read-side critical * sections, invocation of the corresponding RCU callback is deferred @@ -256,6 +256,21 @@ static inline int rcu_pending(int cpu) (p) = (v); \ }) +/** + * synchronize_sched - block until all CPUs have exited any non-preemptive + * kernel code sequences. + * + * This means that all preempt_disable code sequences, including NMI and + * hardware-interrupt handlers, in progress on entry will have completed + * before this primitive returns. However, this does not guarantee that + * softirq handlers will have completed, since in some kernels + * + * This primitive provides the guarantees made by the (deprecated) + * synchronize_kernel() API. In contrast, synchronize_rcu() only + * guarantees that rcu_read_lock() sections will have completed. + */ +#define synchronize_sched() synchronize_rcu() + extern void rcu_init(void); extern void rcu_check_callbacks(int cpu, int user); extern void rcu_restart_cpu(int cpu); @@ -265,7 +280,9 @@ extern void FASTCALL(call_rcu(struct rcu_head *head, void (*func)(struct rcu_head *head))); extern void FASTCALL(call_rcu_bh(struct rcu_head *head, void (*func)(struct rcu_head *head))); -extern void synchronize_kernel(void); +extern __deprecated_for_modules void synchronize_kernel(void); +extern void synchronize_rcu(void); +void synchronize_idle(void); #endif /* __KERNEL__ */ #endif /* __LINUX_RCUPDATE_H */ diff --git a/include/linux/reboot_fixups.h b/include/linux/reboot_fixups.h new file mode 100644 index 000000000000..480ea2d489d8 --- /dev/null +++ b/include/linux/reboot_fixups.h @@ -0,0 +1,10 @@ +#ifndef _LINUX_REBOOT_FIXUPS_H +#define _LINUX_REBOOT_FIXUPS_H + +#ifdef CONFIG_X86_REBOOTFIXUPS +extern void mach_reboot_fixups(void); +#else +#define mach_reboot_fixups() ((void)(0)) +#endif + +#endif /* _LINUX_REBOOT_FIXUPS_H */ diff --git a/include/linux/reiserfs_acl.h b/include/linux/reiserfs_acl.h index a57e973af0bd..2aef9c3f5ce8 100644 --- a/include/linux/reiserfs_acl.h +++ b/include/linux/reiserfs_acl.h @@ -5,18 +5,18 @@ #define REISERFS_ACL_VERSION 0x0001 typedef struct { - __u16 e_tag; - __u16 e_perm; - __u32 e_id; + __le16 e_tag; + __le16 e_perm; + __le32 e_id; } reiserfs_acl_entry; typedef struct { - __u16 e_tag; - __u16 e_perm; + __le16 e_tag; + __le16 e_perm; } reiserfs_acl_entry_short; typedef struct { - __u32 a_version; + __le32 a_version; } reiserfs_acl_header; static inline size_t reiserfs_acl_size(int count) diff --git a/include/linux/reiserfs_fs.h b/include/linux/reiserfs_fs.h index bccff8b17dc4..32148625fc2f 100644 --- a/include/linux/reiserfs_fs.h +++ b/include/linux/reiserfs_fs.h @@ -114,47 +114,47 @@ if( !( cond ) ) \ struct journal_params { - __u32 jp_journal_1st_block; /* where does journal start from on its + __le32 jp_journal_1st_block; /* where does journal start from on its * device */ - __u32 jp_journal_dev; /* journal device st_rdev */ - __u32 jp_journal_size; /* size of the journal */ - __u32 jp_journal_trans_max; /* max number of blocks in a transaction. */ - __u32 jp_journal_magic; /* random value made on fs creation (this + __le32 jp_journal_dev; /* journal device st_rdev */ + __le32 jp_journal_size; /* size of the journal */ + __le32 jp_journal_trans_max; /* max number of blocks in a transaction. */ + __le32 jp_journal_magic; /* random value made on fs creation (this * was sb_journal_block_count) */ - __u32 jp_journal_max_batch; /* max number of blocks to batch into a + __le32 jp_journal_max_batch; /* max number of blocks to batch into a * trans */ - __u32 jp_journal_max_commit_age; /* in seconds, how old can an async + __le32 jp_journal_max_commit_age; /* in seconds, how old can an async * commit be */ - __u32 jp_journal_max_trans_age; /* in seconds, how old can a transaction + __le32 jp_journal_max_trans_age; /* in seconds, how old can a transaction * be */ }; /* this is the super from 3.5.X, where X >= 10 */ struct reiserfs_super_block_v1 { - __u32 s_block_count; /* blocks count */ - __u32 s_free_blocks; /* free blocks count */ - __u32 s_root_block; /* root block number */ + __le32 s_block_count; /* blocks count */ + __le32 s_free_blocks; /* free blocks count */ + __le32 s_root_block; /* root block number */ struct journal_params s_journal; - __u16 s_blocksize; /* block size */ - __u16 s_oid_maxsize; /* max size of object id array, see + __le16 s_blocksize; /* block size */ + __le16 s_oid_maxsize; /* max size of object id array, see * get_objectid() commentary */ - __u16 s_oid_cursize; /* current size of object id array */ - __u16 s_umount_state; /* this is set to 1 when filesystem was + __le16 s_oid_cursize; /* current size of object id array */ + __le16 s_umount_state; /* this is set to 1 when filesystem was * umounted, to 2 - when not */ char s_magic[10]; /* reiserfs magic string indicates that * file system is reiserfs: * "ReIsErFs" or "ReIsEr2Fs" or "ReIsEr3Fs" */ - __u16 s_fs_state; /* it is set to used by fsck to mark which + __le16 s_fs_state; /* it is set to used by fsck to mark which * phase of rebuilding is done */ - __u32 s_hash_function_code; /* indicate, what hash function is being use + __le32 s_hash_function_code; /* indicate, what hash function is being use * to sort names in a directory*/ - __u16 s_tree_height; /* height of disk tree */ - __u16 s_bmap_nr; /* amount of bitmap blocks needed to address + __le16 s_tree_height; /* height of disk tree */ + __le16 s_bmap_nr; /* amount of bitmap blocks needed to address * each block of file system */ - __u16 s_version; /* this field is only reliable on filesystem + __le16 s_version; /* this field is only reliable on filesystem * with non-standard journal */ - __u16 s_reserved_for_journal; /* size in blocks of journal area on main + __le16 s_reserved_for_journal; /* size in blocks of journal area on main * device, we need to keep after * making fs with non-standard journal */ } __attribute__ ((__packed__)); @@ -165,8 +165,8 @@ struct reiserfs_super_block_v1 struct reiserfs_super_block { struct reiserfs_super_block_v1 s_v1; - __u32 s_inode_generation; - __u32 s_flags; /* Right now used only by inode-attributes, if enabled */ + __le32 s_inode_generation; + __le32 s_flags; /* Right now used only by inode-attributes, if enabled */ unsigned char s_uuid[16]; /* filesystem unique identifier */ unsigned char s_label[16]; /* filesystem volume label */ char s_unused[88] ; /* zero filled by mkreiserfs and @@ -225,7 +225,7 @@ struct reiserfs_super_block #define SB_ONDISK_JOURNAL_DEVICE(s) \ le32_to_cpu ((SB_ONDISK_JP(s)->jp_journal_dev)) #define SB_ONDISK_RESERVED_FOR_JOURNAL(s) \ - le32_to_cpu ((SB_V1_DISK_SUPER_BLOCK(s)->s_reserved_for_journal)) + le16_to_cpu ((SB_V1_DISK_SUPER_BLOCK(s)->s_reserved_for_journal)) #define is_block_in_log_or_reserved_area(s, block) \ block >= SB_JOURNAL_1st_RESERVED_BLOCK(s) \ @@ -269,7 +269,7 @@ int is_reiserfs_jr (struct reiserfs_super_block * rs); #define QUOTA_EXCEEDED -6 typedef __u32 b_blocknr_t; -typedef __u32 unp_t; +typedef __le32 unp_t; struct unfm_nodeinfo { unp_t unfm_nodenum; @@ -376,78 +376,57 @@ static inline struct reiserfs_sb_info *REISERFS_SB(const struct super_block *sb) // directories use this key as well as old files // struct offset_v1 { - __u32 k_offset; - __u32 k_uniqueness; + __le32 k_offset; + __le32 k_uniqueness; } __attribute__ ((__packed__)); struct offset_v2 { -#ifdef __LITTLE_ENDIAN - /* little endian version */ - __u64 k_offset:60; - __u64 k_type: 4; -#else - /* big endian version */ - __u64 k_type: 4; - __u64 k_offset:60; -#endif + __le64 v; } __attribute__ ((__packed__)); -#ifndef __LITTLE_ENDIAN -typedef union { - struct offset_v2 offset_v2; - __u64 linear; -} __attribute__ ((__packed__)) offset_v2_esafe_overlay; - static inline __u16 offset_v2_k_type( const struct offset_v2 *v2 ) { - offset_v2_esafe_overlay tmp = *(const offset_v2_esafe_overlay *)v2; - tmp.linear = le64_to_cpu( tmp.linear ); - return (tmp.offset_v2.k_type <= TYPE_MAXTYPE)?tmp.offset_v2.k_type:TYPE_ANY; + __u8 type = le64_to_cpu(v2->v) >> 60; + return (type <= TYPE_MAXTYPE)?type:TYPE_ANY; } static inline void set_offset_v2_k_type( struct offset_v2 *v2, int type ) { - offset_v2_esafe_overlay *tmp = (offset_v2_esafe_overlay *)v2; - tmp->linear = le64_to_cpu(tmp->linear); - tmp->offset_v2.k_type = type; - tmp->linear = cpu_to_le64(tmp->linear); + v2->v = (v2->v & cpu_to_le64(~0ULL>>4)) | cpu_to_le64((__u64)type<<60); } static inline loff_t offset_v2_k_offset( const struct offset_v2 *v2 ) { - offset_v2_esafe_overlay tmp = *(const offset_v2_esafe_overlay *)v2; - tmp.linear = le64_to_cpu( tmp.linear ); - return tmp.offset_v2.k_offset; + return le64_to_cpu(v2->v) & (~0ULL>>4); } static inline void set_offset_v2_k_offset( struct offset_v2 *v2, loff_t offset ){ - offset_v2_esafe_overlay *tmp = (offset_v2_esafe_overlay *)v2; - tmp->linear = le64_to_cpu(tmp->linear); - tmp->offset_v2.k_offset = offset; - tmp->linear = cpu_to_le64(tmp->linear); + offset &= (~0ULL>>4); + v2->v = (v2->v & cpu_to_le64(15ULL<<60)) | cpu_to_le64(offset); } -#else -# define offset_v2_k_type(v2) ((v2)->k_type) -# define set_offset_v2_k_type(v2,val) (offset_v2_k_type(v2) = (val)) -# define offset_v2_k_offset(v2) ((v2)->k_offset) -# define set_offset_v2_k_offset(v2,val) (offset_v2_k_offset(v2) = (val)) -#endif /* Key of an item determines its location in the S+tree, and is composed of 4 components */ struct reiserfs_key { - __u32 k_dir_id; /* packing locality: by default parent + __le32 k_dir_id; /* packing locality: by default parent directory object id */ - __u32 k_objectid; /* object identifier */ + __le32 k_objectid; /* object identifier */ union { struct offset_v1 k_offset_v1; struct offset_v2 k_offset_v2; } __attribute__ ((__packed__)) u; } __attribute__ ((__packed__)); +struct in_core_key { + __u32 k_dir_id; /* packing locality: by default parent + directory object id */ + __u32 k_objectid; /* object identifier */ + __u64 k_offset; + __u8 k_type; +}; struct cpu_key { - struct reiserfs_key on_disk_key; + struct in_core_key on_disk_key; int version; int key_length; /* 3 in all cases but direct2indirect and indirect2direct conversion */ @@ -508,15 +487,15 @@ struct item_head item. Note that the key, not this field, is used to determine the item type, and thus which field this union contains. */ - __u16 ih_free_space_reserved; + __le16 ih_free_space_reserved; /* Iff this is a directory item, this field equals the number of directory entries in the directory item. */ - __u16 ih_entry_count; + __le16 ih_entry_count; } __attribute__ ((__packed__)) u; - __u16 ih_item_len; /* total size of the item body */ - __u16 ih_item_location; /* an offset to the item body + __le16 ih_item_len; /* total size of the item body */ + __le16 ih_item_location; /* an offset to the item body * within the block */ - __u16 ih_version; /* 0 for all old items, 2 for new + __le16 ih_version; /* 0 for all old items, 2 for new ones. Highest bit is set by fsck temporary, cleaned after all done */ @@ -670,43 +649,29 @@ static inline void set_le_ih_k_type (struct item_head * ih, int type) // static inline loff_t cpu_key_k_offset (const struct cpu_key * key) { - return (key->version == KEY_FORMAT_3_5) ? - key->on_disk_key.u.k_offset_v1.k_offset : - key->on_disk_key.u.k_offset_v2.k_offset; + return key->on_disk_key.k_offset; } static inline loff_t cpu_key_k_type (const struct cpu_key * key) { - return (key->version == KEY_FORMAT_3_5) ? - uniqueness2type (key->on_disk_key.u.k_offset_v1.k_uniqueness) : - key->on_disk_key.u.k_offset_v2.k_type; + return key->on_disk_key.k_type; } static inline void set_cpu_key_k_offset (struct cpu_key * key, loff_t offset) { - (key->version == KEY_FORMAT_3_5) ? - (key->on_disk_key.u.k_offset_v1.k_offset = offset) : - (key->on_disk_key.u.k_offset_v2.k_offset = offset); + key->on_disk_key.k_offset = offset; } - static inline void set_cpu_key_k_type (struct cpu_key * key, int type) { - (key->version == KEY_FORMAT_3_5) ? - (key->on_disk_key.u.k_offset_v1.k_uniqueness = type2uniqueness (type)): - (key->on_disk_key.u.k_offset_v2.k_type = type); + key->on_disk_key.k_type = type; } - static inline void cpu_key_k_offset_dec (struct cpu_key * key) { - if (key->version == KEY_FORMAT_3_5) - key->on_disk_key.u.k_offset_v1.k_offset --; - else - key->on_disk_key.u.k_offset_v2.k_offset --; + key->on_disk_key.k_offset --; } - #define is_direntry_cpu_key(key) (cpu_key_k_type (key) == TYPE_DIRENTRY) #define is_direct_cpu_key(key) (cpu_key_k_type (key) == TYPE_DIRECT) #define is_indirect_cpu_key(key) (cpu_key_k_type (key) == TYPE_INDIRECT) @@ -752,10 +717,10 @@ extern struct reiserfs_key root_key; /* Header of a disk block. More precisely, header of a formatted leaf or internal node, and not the header of an unformatted node. */ struct block_head { - __u16 blk_level; /* Level of a block in the tree. */ - __u16 blk_nr_item; /* Number of keys/items in a block. */ - __u16 blk_free_space; /* Block free space in bytes. */ - __u16 blk_reserved; + __le16 blk_level; /* Level of a block in the tree. */ + __le16 blk_nr_item; /* Number of keys/items in a block. */ + __le16 blk_free_space; /* Block free space in bytes. */ + __le16 blk_reserved; /* dump this in v4/planA */ struct reiserfs_key blk_right_delim_key; /* kept only for compatibility */ }; @@ -819,19 +784,19 @@ struct block_head { // struct stat_data_v1 { - __u16 sd_mode; /* file type, permissions */ - __u16 sd_nlink; /* number of hard links */ - __u16 sd_uid; /* owner */ - __u16 sd_gid; /* group */ - __u32 sd_size; /* file size */ - __u32 sd_atime; /* time of last access */ - __u32 sd_mtime; /* time file was last modified */ - __u32 sd_ctime; /* time inode (stat data) was last changed (except changes to sd_atime and sd_mtime) */ + __le16 sd_mode; /* file type, permissions */ + __le16 sd_nlink; /* number of hard links */ + __le16 sd_uid; /* owner */ + __le16 sd_gid; /* group */ + __le32 sd_size; /* file size */ + __le32 sd_atime; /* time of last access */ + __le32 sd_mtime; /* time file was last modified */ + __le32 sd_ctime; /* time inode (stat data) was last changed (except changes to sd_atime and sd_mtime) */ union { - __u32 sd_rdev; - __u32 sd_blocks; /* number of blocks file uses */ + __le32 sd_rdev; + __le32 sd_blocks; /* number of blocks file uses */ } __attribute__ ((__packed__)) u; - __u32 sd_first_direct_byte; /* first byte of file which is stored + __le32 sd_first_direct_byte; /* first byte of file which is stored in a direct item: except that if it equals 1 it is a symlink and if it equals ~(__u32)0 there is no @@ -897,20 +862,20 @@ struct stat_data_v1 /* Stat Data on disk (reiserfs version of UFS disk inode minus the address blocks) */ struct stat_data { - __u16 sd_mode; /* file type, permissions */ - __u16 sd_attrs; /* persistent inode flags */ - __u32 sd_nlink; /* number of hard links */ - __u64 sd_size; /* file size */ - __u32 sd_uid; /* owner */ - __u32 sd_gid; /* group */ - __u32 sd_atime; /* time of last access */ - __u32 sd_mtime; /* time file was last modified */ - __u32 sd_ctime; /* time inode (stat data) was last changed (except changes to sd_atime and sd_mtime) */ - __u32 sd_blocks; + __le16 sd_mode; /* file type, permissions */ + __le16 sd_attrs; /* persistent inode flags */ + __le32 sd_nlink; /* number of hard links */ + __le64 sd_size; /* file size */ + __le32 sd_uid; /* owner */ + __le32 sd_gid; /* group */ + __le32 sd_atime; /* time of last access */ + __le32 sd_mtime; /* time file was last modified */ + __le32 sd_ctime; /* time inode (stat data) was last changed (except changes to sd_atime and sd_mtime) */ + __le32 sd_blocks; union { - __u32 sd_rdev; - __u32 sd_generation; - //__u32 sd_first_direct_byte; + __le32 sd_rdev; + __le32 sd_generation; + //__le32 sd_first_direct_byte; /* first byte of file which is stored in a direct item: except that if it equals 1 it is a symlink and if it equals @@ -993,12 +958,12 @@ struct stat_data { struct reiserfs_de_head { - __u32 deh_offset; /* third component of the directory entry key */ - __u32 deh_dir_id; /* objectid of the parent directory of the object, that is referenced + __le32 deh_offset; /* third component of the directory entry key */ + __le32 deh_dir_id; /* objectid of the parent directory of the object, that is referenced by directory entry */ - __u32 deh_objectid; /* objectid of the object, that is referenced by directory entry */ - __u16 deh_location; /* offset of name in the whole item */ - __u16 deh_state; /* whether 1) entry contains stat data (for future), and 2) whether + __le32 deh_objectid; /* objectid of the object, that is referenced by directory entry */ + __le16 deh_location; /* offset of name in the whole item */ + __le16 deh_state; /* whether 1) entry contains stat data (for future), and 2) whether entry is hidden (unlinked) */ } __attribute__ ((__packed__)); #define DEH_SIZE sizeof(struct reiserfs_de_head) @@ -1058,10 +1023,10 @@ struct reiserfs_de_head #define de_visible(deh) test_bit_unaligned (DEH_Visible, &((deh)->deh_state)) #define de_hidden(deh) !test_bit_unaligned (DEH_Visible, &((deh)->deh_state)) -extern void make_empty_dir_item_v1 (char * body, __u32 dirid, __u32 objid, - __u32 par_dirid, __u32 par_objid); -extern void make_empty_dir_item (char * body, __u32 dirid, __u32 objid, - __u32 par_dirid, __u32 par_objid); +extern void make_empty_dir_item_v1 (char * body, __le32 dirid, __le32 objid, + __le32 par_dirid, __le32 par_objid); +extern void make_empty_dir_item (char * body, __le32 dirid, __le32 objid, + __le32 par_dirid, __le32 par_objid); /* array of the entry headers */ /* get item body */ @@ -1160,9 +1125,9 @@ struct reiserfs_dir_entry /* Disk child pointer: The pointer from an internal node of the tree to a node that is on disk. */ struct disk_child { - __u32 dc_block_number; /* Disk child's block number. */ - __u16 dc_size; /* Disk child's used space. */ - __u16 dc_reserved; + __le32 dc_block_number; /* Disk child's block number. */ + __le16 dc_size; /* Disk child's used space. */ + __le16 dc_reserved; }; #define DC_SIZE (sizeof(struct disk_child)) @@ -1476,7 +1441,7 @@ struct tree_balance int fs_gen; /* saved value of `reiserfs_generation' counter see FILESYSTEM_CHANGED() macro in reiserfs_fs.h */ #ifdef DISPLACE_NEW_PACKING_LOCALITIES - struct reiserfs_key key; /* key pointer, to pass to block allocator or + struct in_core_key key; /* key pointer, to pass to block allocator or another low-level subsystem */ #endif } ; @@ -1630,10 +1595,10 @@ struct reiserfs_iget_args { /* first block written in a commit. */ struct reiserfs_journal_desc { - __u32 j_trans_id ; /* id of commit */ - __u32 j_len ; /* length of commit. len +1 is the commit block */ - __u32 j_mount_id ; /* mount id of this trans*/ - __u32 j_realblock[1] ; /* real locations for each block */ + __le32 j_trans_id ; /* id of commit */ + __le32 j_len ; /* length of commit. len +1 is the commit block */ + __le32 j_mount_id ; /* mount id of this trans*/ + __le32 j_realblock[1] ; /* real locations for each block */ } ; #define get_desc_trans_id(d) le32_to_cpu((d)->j_trans_id) @@ -1646,9 +1611,9 @@ struct reiserfs_journal_desc { /* last block written in a commit */ struct reiserfs_journal_commit { - __u32 j_trans_id ; /* must match j_trans_id from the desc block */ - __u32 j_len ; /* ditto */ - __u32 j_realblock[1] ; /* real locations for each block */ + __le32 j_trans_id ; /* must match j_trans_id from the desc block */ + __le32 j_len ; /* ditto */ + __le32 j_realblock[1] ; /* real locations for each block */ } ; #define get_commit_trans_id(c) le32_to_cpu((c)->j_trans_id) @@ -1663,9 +1628,9 @@ struct reiserfs_journal_commit { ** and this transaction does not need to be replayed. */ struct reiserfs_journal_header { - __u32 j_last_flush_trans_id ; /* id of last fully flushed transaction */ - __u32 j_first_unflushed_offset ; /* offset in the log of where to start replay after a crash */ - __u32 j_mount_id ; + __le32 j_last_flush_trans_id ; /* id of last fully flushed transaction */ + __le32 j_first_unflushed_offset ; /* offset in the log of where to start replay after a crash */ + __le32 j_mount_id ; /* 12 */ struct journal_params jh_journal; } ; @@ -2117,7 +2082,7 @@ struct buffer_head * get_FEB (struct tree_balance *); struct __reiserfs_blocknr_hint { struct inode * inode; /* inode passed to allocator, if we allocate unf. nodes */ long block; /* file offset, in blocks */ - struct reiserfs_key key; + struct in_core_key key; struct path * path; /* search path, used by allocator to deternine search_start by * various ways */ struct reiserfs_transaction_handle * th; /* transaction handle is needed to log super blocks and @@ -2144,7 +2109,7 @@ void reiserfs_init_alloc_options (struct super_block *s); * to use for a new object underneat it. The locality is returned * in disk byte order (le). */ -u32 reiserfs_choose_packing(struct inode *dir); +__le32 reiserfs_choose_packing(struct inode *dir); int is_reusable (struct super_block * s, b_blocknr_t block, int bit_value); void reiserfs_free_block (struct reiserfs_transaction_handle *th, struct inode *, b_blocknr_t, int for_unformatted); diff --git a/include/linux/reiserfs_xattr.h b/include/linux/reiserfs_xattr.h index 1eaa48eca811..9244c5748820 100644 --- a/include/linux/reiserfs_xattr.h +++ b/include/linux/reiserfs_xattr.h @@ -10,8 +10,8 @@ #define REISERFS_XATTR_MAGIC 0x52465841 /* "RFXA" */ struct reiserfs_xattr_header { - __u32 h_magic; /* magic number for identification */ - __u32 h_hash; /* hash of the value */ + __le32 h_magic; /* magic number for identification */ + __le32 h_hash; /* hash of the value */ }; #ifdef __KERNEL__ diff --git a/include/linux/rtnetlink.h b/include/linux/rtnetlink.h index 32e52769a00b..91ac97c20777 100644 --- a/include/linux/rtnetlink.h +++ b/include/linux/rtnetlink.h @@ -89,10 +89,14 @@ enum { RTM_GETANYCAST = 62, #define RTM_GETANYCAST RTM_GETANYCAST - RTM_MAX, -#define RTM_MAX RTM_MAX + __RTM_MAX, +#define RTM_MAX (((__RTM_MAX + 3) & ~3) - 1) }; +#define RTM_NR_MSGTYPES (RTM_MAX + 1 - RTM_BASE) +#define RTM_NR_FAMILIES (RTM_NR_MSGTYPES >> 2) +#define RTM_FAM(cmd) (((cmd) - RTM_BASE) >> 2) + /* Generic structure for encapsulation of optional route information. It is reminiscent of sockaddr, but with sa_family replaced diff --git a/include/linux/sched.h b/include/linux/sched.h index 1cced971232c..4dbb109022f3 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h @@ -578,7 +578,7 @@ struct task_struct { unsigned long flags; /* per process flags, defined below */ unsigned long ptrace; - int lock_depth; /* Lock depth */ + int lock_depth; /* BKL lock depth */ int prio, static_prio; struct list_head run_list; @@ -661,7 +661,10 @@ struct task_struct { struct key *thread_keyring; /* keyring private to this thread */ #endif int oomkilladj; /* OOM kill score adjustment (bit shift). */ - char comm[TASK_COMM_LEN]; + char comm[TASK_COMM_LEN]; /* executable name excluding path + - access with [gs]et_task_comm (which lock + it with task_lock()) + - initialized normally by flush_old_exec */ /* file system info */ int link_count, total_link_count; /* ipc stuff */ @@ -845,6 +848,7 @@ extern void sched_idle_next(void); extern void set_user_nice(task_t *p, long nice); extern int task_prio(const task_t *p); extern int task_nice(const task_t *p); +extern int can_nice(const task_t *p, const int nice); extern int task_curr(const task_t *p); extern int idle_cpu(int cpu); extern int sched_setscheduler(struct task_struct *, int, struct sched_param *); @@ -1011,7 +1015,6 @@ extern int copy_thread(int, unsigned long, unsigned long, unsigned long, struct extern void flush_thread(void); extern void exit_thread(void); -extern void exit_mm(struct task_struct *); extern void exit_files(struct task_struct *); extern void exit_signal(struct task_struct *); extern void __exit_signal(struct task_struct *); diff --git a/include/linux/signal.h b/include/linux/signal.h index 99c97ad026c8..0a98f5ec5cae 100644 --- a/include/linux/signal.h +++ b/include/linux/signal.h @@ -9,6 +9,17 @@ #ifdef __KERNEL__ /* + * These values of sa_flags are used only by the kernel as part of the + * irq handling routines. + * + * SA_INTERRUPT is also used by the irq handling routines. + * SA_SHIRQ is for shared interrupt support on PCI and EISA. + */ +#define SA_PROBE SA_ONESHOT +#define SA_SAMPLE_RANDOM SA_RESTART +#define SA_SHIRQ 0x04000000 + +/* * Real Time signals may be queued. */ @@ -209,6 +220,12 @@ static inline void init_sigpending(struct sigpending *sig) INIT_LIST_HEAD(&sig->list); } +/* Test if 'sig' is valid signal. Use this instead of testing _NSIG directly */ +static inline int valid_signal(unsigned long sig) +{ + return sig <= _NSIG ? 1 : 0; +} + extern int group_send_sig_info(int sig, struct siginfo *info, struct task_struct *p); extern int __group_send_sig_info(int, struct siginfo *, struct task_struct *); extern long do_sigpending(void __user *, unsigned long); diff --git a/include/linux/skbuff.h b/include/linux/skbuff.h index 22b701819619..cc04f5cd2286 100644 --- a/include/linux/skbuff.h +++ b/include/linux/skbuff.h @@ -167,13 +167,14 @@ struct skb_shared_info { * @h: Transport layer header * @nh: Network layer header * @mac: Link layer header - * @dst: FIXME: Describe this field + * @dst: destination entry + * @sp: the security path, used for xfrm * @cb: Control buffer. Free for use by every layer. Put private vars here * @len: Length of actual data * @data_len: Data length * @mac_len: Length of link layer header * @csum: Checksum - * @__unused: Dead field, may be reused + * @local_df: allow local fragmentation * @cloned: Head may be cloned (check refcnt to be sure) * @nohdr: Payload reference only, must not modify header * @pkt_type: Packet class @@ -968,6 +969,7 @@ static inline void __skb_queue_purge(struct sk_buff_head *list) kfree_skb(skb); } +#ifndef CONFIG_HAVE_ARCH_DEV_ALLOC_SKB /** * __dev_alloc_skb - allocate an skbuff for sending * @length: length to allocate @@ -980,7 +982,6 @@ static inline void __skb_queue_purge(struct sk_buff_head *list) * * %NULL is returned in there is no free memory. */ -#ifndef CONFIG_HAVE_ARCH_DEV_ALLOC_SKB static inline struct sk_buff *__dev_alloc_skb(unsigned int length, int gfp_mask) { diff --git a/include/linux/slab.h b/include/linux/slab.h index 3e3c3ab8ff94..7d66385ae750 100644 --- a/include/linux/slab.h +++ b/include/linux/slab.h @@ -62,16 +62,9 @@ extern kmem_cache_t *kmem_cache_create(const char *, size_t, size_t, unsigned lo extern int kmem_cache_destroy(kmem_cache_t *); extern int kmem_cache_shrink(kmem_cache_t *); extern void *kmem_cache_alloc(kmem_cache_t *, unsigned int __nocast); -#ifdef CONFIG_NUMA -extern void *kmem_cache_alloc_node(kmem_cache_t *, int); -#else -static inline void *kmem_cache_alloc_node(kmem_cache_t *cachep, int node) -{ - return kmem_cache_alloc(cachep, GFP_KERNEL); -} -#endif extern void kmem_cache_free(kmem_cache_t *, void *); extern unsigned int kmem_cache_size(kmem_cache_t *); +extern kmem_cache_t *kmem_find_general_cachep(size_t size, int gfpflags); /* Size description struct for general caches. */ struct cache_sizes { @@ -109,6 +102,20 @@ extern void *kcalloc(size_t, size_t, unsigned int __nocast); extern void kfree(const void *); extern unsigned int ksize(const void *); +#ifdef CONFIG_NUMA +extern void *kmem_cache_alloc_node(kmem_cache_t *, int flags, int node); +extern void *kmalloc_node(size_t size, int flags, int node); +#else +static inline void *kmem_cache_alloc_node(kmem_cache_t *cachep, int flags, int node) +{ + return kmem_cache_alloc(cachep, flags); +} +static inline void *kmalloc_node(size_t size, int flags, int node) +{ + return kmalloc(size, flags); +} +#endif + extern int FASTCALL(kmem_cache_reap(int)); extern int FASTCALL(kmem_ptr_validate(kmem_cache_t *cachep, void *ptr)); diff --git a/include/linux/sockios.h b/include/linux/sockios.h index 5eb33205cc04..e6b9d1d36ea2 100644 --- a/include/linux/sockios.h +++ b/include/linux/sockios.h @@ -7,7 +7,7 @@ * * Version: @(#)sockios.h 1.0.2 03/09/93 * - * Authors: Ross Biro, <bir7@leland.Stanford.Edu> + * Authors: Ross Biro * Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG> * * This program is free software; you can redistribute it and/or diff --git a/include/linux/soundcard.h b/include/linux/soundcard.h index 28d2d1881978..523d069c862c 100644 --- a/include/linux/soundcard.h +++ b/include/linux/soundcard.h @@ -39,6 +39,13 @@ /* In Linux we need to be prepared for cross compiling */ #include <linux/ioctl.h> +/* Endian macros. */ +#ifdef __KERNEL__ +# include <asm/byteorder.h> +#else +# include <endian.h> +#endif + /* * Supported card ID numbers (Should be somewhere else?) */ @@ -179,13 +186,26 @@ typedef struct seq_event_rec { * Some big endian/little endian handling macros */ -#if defined(_AIX) || defined(AIX) || defined(sparc) || defined(__sparc__) || defined(HPPA) || defined(PPC) || defined(__mc68000__) -/* Big endian machines */ -# define _PATCHKEY(id) (0xfd00|id) -# define AFMT_S16_NE AFMT_S16_BE -#else -# define _PATCHKEY(id) ((id<<8)|0xfd) -# define AFMT_S16_NE AFMT_S16_LE +#define _LINUX_PATCHKEY_H_INDIRECT +#include <linux/patchkey.h> +#undef _LINUX_PATCHKEY_H_INDIRECT + +#if defined(__KERNEL__) +# if defined(__BIG_ENDIAN) +# define AFMT_S16_NE AFMT_S16_BE +# elif defined(__LITTLE_ENDIAN) +# define AFMT_S16_NE AFMT_S16_LE +# else +# error "could not determine byte order" +# endif +#elif defined(__BYTE_ORDER) +# if __BYTE_ORDER == __BIG_ENDIAN +# define AFMT_S16_NE AFMT_S16_BE +# elif __BYTE_ORDER == __LITTLE_ENDIAN +# define AFMT_S16_NE AFMT_S16_LE +# else +# error "could not determine byte order" +# endif #endif /* diff --git a/include/linux/syscalls.h b/include/linux/syscalls.h index 757cd9be7743..c39f6f72cbbc 100644 --- a/include/linux/syscalls.h +++ b/include/linux/syscalls.h @@ -456,8 +456,7 @@ asmlinkage long sys_semctl(int semid, int semnum, int cmd, union semun arg); asmlinkage long sys_semtimedop(int semid, struct sembuf __user *sops, unsigned nsops, const struct timespec __user *timeout); -asmlinkage long sys_shmat(int shmid, char __user *shmaddr, - int shmflg, unsigned long __user *addr); +asmlinkage long sys_shmat(int shmid, char __user *shmaddr, int shmflg); asmlinkage long sys_shmget(key_t key, size_t size, int flag); asmlinkage long sys_shmdt(char __user *shmaddr); asmlinkage long sys_shmctl(int shmid, int cmd, struct shmid_ds __user *buf); diff --git a/include/linux/sysctl.h b/include/linux/sysctl.h index 358d52b0c445..772998147e3e 100644 --- a/include/linux/sysctl.h +++ b/include/linux/sysctl.h @@ -643,6 +643,7 @@ enum { NET_SCTP_MAX_BURST = 12, NET_SCTP_ADDIP_ENABLE = 13, NET_SCTP_PRSCTP_ENABLE = 14, + NET_SCTP_SNDBUF_POLICY = 15, }; /* /proc/sys/net/bridge */ diff --git a/include/linux/tc_act/tc_defact.h b/include/linux/tc_act/tc_defact.h new file mode 100644 index 000000000000..964f473af0f0 --- /dev/null +++ b/include/linux/tc_act/tc_defact.h @@ -0,0 +1,21 @@ +#ifndef __LINUX_TC_DEF_H +#define __LINUX_TC_DEF_H + +#include <linux/pkt_cls.h> + +struct tc_defact +{ + tc_gen; +}; + +enum +{ + TCA_DEF_UNSPEC, + TCA_DEF_TM, + TCA_DEF_PARMS, + TCA_DEF_DATA, + __TCA_DEF_MAX +}; +#define TCA_DEF_MAX (__TCA_DEF_MAX - 1) + +#endif diff --git a/include/linux/trdevice.h b/include/linux/trdevice.h index aaa1f337edcb..99e02ef54c47 100644 --- a/include/linux/trdevice.h +++ b/include/linux/trdevice.h @@ -7,7 +7,7 @@ * * Version: @(#)eth.h 1.0.4 05/13/93 * - * Authors: Ross Biro, <bir7@leland.Stanford.Edu> + * Authors: Ross Biro * Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG> * * Relocated to include/linux where it belongs by Alan Cox diff --git a/include/linux/xfrm.h b/include/linux/xfrm.h index f0df02ae68a4..fd2ef742a9fd 100644 --- a/include/linux/xfrm.h +++ b/include/linux/xfrm.h @@ -140,8 +140,11 @@ enum { XFRM_MSG_FLUSHPOLICY, #define XFRM_MSG_FLUSHPOLICY XFRM_MSG_FLUSHPOLICY - XFRM_MSG_MAX + __XFRM_MSG_MAX }; +#define XFRM_MSG_MAX (__XFRM_MSG_MAX - 1) + +#define XFRM_NR_MSGTYPES (XFRM_MSG_MAX + 1 - XFRM_MSG_BASE) struct xfrm_user_tmpl { struct xfrm_id id; diff --git a/include/net/act_generic.h b/include/net/act_generic.h new file mode 100644 index 000000000000..95b120781c14 --- /dev/null +++ b/include/net/act_generic.h @@ -0,0 +1,142 @@ +/* + * include/net/act_generic.h + * +*/ +#ifndef ACT_GENERIC_H +#define ACT_GENERIC_H +static inline int tcf_defact_release(struct tcf_defact *p, int bind) +{ + int ret = 0; + if (p) { + if (bind) { + p->bindcnt--; + } + p->refcnt--; + if (p->bindcnt <= 0 && p->refcnt <= 0) { + kfree(p->defdata); + tcf_hash_destroy(p); + ret = 1; + } + } + return ret; +} + +static inline int +alloc_defdata(struct tcf_defact *p, u32 datalen, void *defdata) +{ + p->defdata = kmalloc(datalen, GFP_KERNEL); + if (p->defdata == NULL) + return -ENOMEM; + p->datalen = datalen; + memcpy(p->defdata, defdata, datalen); + return 0; +} + +static inline int +realloc_defdata(struct tcf_defact *p, u32 datalen, void *defdata) +{ + /* safer to be just brute force for now */ + kfree(p->defdata); + return alloc_defdata(p, datalen, defdata); +} + +static inline int +tcf_defact_init(struct rtattr *rta, struct rtattr *est, + struct tc_action *a, int ovr, int bind) +{ + struct rtattr *tb[TCA_DEF_MAX]; + struct tc_defact *parm; + struct tcf_defact *p; + void *defdata; + u32 datalen = 0; + int ret = 0; + + if (rta == NULL || rtattr_parse_nested(tb, TCA_DEF_MAX, rta) < 0) + return -EINVAL; + + if (tb[TCA_DEF_PARMS - 1] == NULL || + RTA_PAYLOAD(tb[TCA_DEF_PARMS - 1]) < sizeof(*parm)) + return -EINVAL; + + parm = RTA_DATA(tb[TCA_DEF_PARMS - 1]); + defdata = RTA_DATA(tb[TCA_DEF_DATA - 1]); + if (defdata == NULL) + return -EINVAL; + + datalen = RTA_PAYLOAD(tb[TCA_DEF_DATA - 1]); + if (datalen <= 0) + return -EINVAL; + + p = tcf_hash_check(parm->index, a, ovr, bind); + if (p == NULL) { + p = tcf_hash_create(parm->index, est, a, sizeof(*p), ovr, bind); + if (p == NULL) + return -ENOMEM; + + ret = alloc_defdata(p, datalen, defdata); + if (ret < 0) { + kfree(p); + return ret; + } + ret = ACT_P_CREATED; + } else { + if (!ovr) { + tcf_defact_release(p, bind); + return -EEXIST; + } + realloc_defdata(p, datalen, defdata); + } + + spin_lock_bh(&p->lock); + p->action = parm->action; + spin_unlock_bh(&p->lock); + if (ret == ACT_P_CREATED) + tcf_hash_insert(p); + return ret; +} + +static inline int tcf_defact_cleanup(struct tc_action *a, int bind) +{ + struct tcf_defact *p = PRIV(a, defact); + + if (p != NULL) + return tcf_defact_release(p, bind); + return 0; +} + +static inline int +tcf_defact_dump(struct sk_buff *skb, struct tc_action *a, int bind, int ref) +{ + unsigned char *b = skb->tail; + struct tc_defact opt; + struct tcf_defact *p = PRIV(a, defact); + struct tcf_t t; + + opt.index = p->index; + opt.refcnt = p->refcnt - ref; + opt.bindcnt = p->bindcnt - bind; + opt.action = p->action; + RTA_PUT(skb, TCA_DEF_PARMS, sizeof(opt), &opt); + RTA_PUT(skb, TCA_DEF_DATA, p->datalen, p->defdata); + t.install = jiffies_to_clock_t(jiffies - p->tm.install); + t.lastuse = jiffies_to_clock_t(jiffies - p->tm.lastuse); + t.expires = jiffies_to_clock_t(p->tm.expires); + RTA_PUT(skb, TCA_DEF_TM, sizeof(t), &t); + return skb->len; + +rtattr_failure: + skb_trim(skb, b - skb->data); + return -1; +} + +#define tca_use_default_ops \ + .dump = tcf_defact_dump, \ + .cleanup = tcf_defact_cleanup, \ + .init = tcf_defact_init, \ + .walk = tcf_generic_walker, \ + +#define tca_use_default_defines(name) \ + static u32 idx_gen; \ + static struct tcf_defact *tcf_##name_ht[MY_TAB_SIZE]; \ + static DEFINE_RWLOCK(##name_lock); +#endif /* _NET_ACT_GENERIC_H */ diff --git a/include/net/addrconf.h b/include/net/addrconf.h index 7af9a13cb9be..a0ed93672176 100644 --- a/include/net/addrconf.h +++ b/include/net/addrconf.h @@ -17,6 +17,8 @@ #define IPV6_MAX_ADDRESSES 16 +#include <linux/in6.h> + struct prefix_info { __u8 type; __u8 length; @@ -43,9 +45,9 @@ struct prefix_info { #ifdef __KERNEL__ -#include <linux/in6.h> #include <linux/netdevice.h> #include <net/if_inet6.h> +#include <net/ipv6.h> #define IN6_ADDR_HSIZE 16 diff --git a/include/net/ax25.h b/include/net/ax25.h index fb95ecb6fe03..9e6368a54547 100644 --- a/include/net/ax25.h +++ b/include/net/ax25.h @@ -220,6 +220,14 @@ static __inline__ void ax25_cb_put(ax25_cb *ax25) } } +static inline unsigned short ax25_type_trans(struct sk_buff *skb, struct net_device *dev) +{ + skb->dev = dev; + skb->pkt_type = PACKET_HOST; + skb->mac.raw = skb->data; + return htons(ETH_P_AX25); +} + /* af_ax25.c */ extern struct hlist_head ax25_list; extern spinlock_t ax25_list_lock; @@ -305,7 +313,7 @@ extern ax25_cb *ax25_send_frame(struct sk_buff *, int, ax25_address *, ax25_addr extern void ax25_output(ax25_cb *, int, struct sk_buff *); extern void ax25_kick(ax25_cb *); extern void ax25_transmit_buffer(ax25_cb *, struct sk_buff *, int); -extern void ax25_queue_xmit(struct sk_buff *); +extern void ax25_queue_xmit(struct sk_buff *skb, struct net_device *dev); extern int ax25_check_iframes_acked(ax25_cb *, unsigned short); /* ax25_route.c */ diff --git a/include/net/icmp.h b/include/net/icmp.h index 3fc192478aa2..e5ef0d15fb45 100644 --- a/include/net/icmp.h +++ b/include/net/icmp.h @@ -7,7 +7,7 @@ * * Version: @(#)icmp.h 1.0.4 05/13/93 * - * Authors: Ross Biro, <bir7@leland.Stanford.Edu> + * Authors: Ross Biro * Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG> * * This program is free software; you can redistribute it and/or diff --git a/include/net/ip.h b/include/net/ip.h index b4db1375da2c..3f63992eb712 100644 --- a/include/net/ip.h +++ b/include/net/ip.h @@ -7,7 +7,7 @@ * * Version: @(#)ip.h 1.0.2 05/07/93 * - * Authors: Ross Biro, <bir7@leland.Stanford.Edu> + * Authors: Ross Biro * Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG> * Alan Cox, <gw4pts@gw4pts.ampr.org> * diff --git a/include/net/ipv6.h b/include/net/ipv6.h index 87c45cbfbaf6..771b47e30f86 100644 --- a/include/net/ipv6.h +++ b/include/net/ipv6.h @@ -416,7 +416,7 @@ extern void ipv6_push_frag_opts(struct sk_buff *skb, u8 *proto); extern int ipv6_skip_exthdr(const struct sk_buff *, int start, - u8 *nexthdrp, int len); + u8 *nexthdrp); extern int ipv6_ext_hdr(u8 nexthdr); diff --git a/include/net/pkt_sched.h b/include/net/pkt_sched.h index 87496e3aa330..fcb05a387dbe 100644 --- a/include/net/pkt_sched.h +++ b/include/net/pkt_sched.h @@ -140,7 +140,7 @@ psched_tod_diff(int delta_sec, int bound) if (bound <= 1000000 || delta_sec > (0x7FFFFFFF/1000000)-1) return bound; delta = delta_sec * 1000000; - if (delta > bound) + if (delta > bound || delta < 0) delta = bound; return delta; } @@ -156,7 +156,9 @@ psched_tod_diff(int delta_sec, int bound) __delta += 1000000; \ case 1: \ __delta += 1000000; \ - case 0: ; \ + case 0: \ + if (__delta > bound || __delta < 0) \ + __delta = bound; \ } \ __delta; \ }) diff --git a/include/net/route.h b/include/net/route.h index 22da7579d5de..efe92b239ef1 100644 --- a/include/net/route.h +++ b/include/net/route.h @@ -7,7 +7,7 @@ * * Version: @(#)route.h 1.0.4 05/27/93 * - * Authors: Ross Biro, <bir7@leland.Stanford.Edu> + * Authors: Ross Biro * Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG> * Fixes: * Alan Cox : Reformatted. Added ip_rt_local() diff --git a/include/net/sctp/sm.h b/include/net/sctp/sm.h index 5576db56324d..f4fcee104707 100644 --- a/include/net/sctp/sm.h +++ b/include/net/sctp/sm.h @@ -407,32 +407,38 @@ sctp_vtag_verify(const struct sctp_chunk *chunk, return 0; } -/* Check VTAG of the packet matches the sender's own tag OR its peer's - * tag and the T bit is set in the Chunk Flags. +/* Check VTAG of the packet matches the sender's own tag and the T bit is + * not set, OR its peer's tag and the T bit is set in the Chunk Flags. */ static inline int sctp_vtag_verify_either(const struct sctp_chunk *chunk, const struct sctp_association *asoc) { - /* RFC 2960 Section 8.5.1, sctpimpguide-06 Section 2.13.2 + /* RFC 2960 Section 8.5.1, sctpimpguide Section 2.41 * - * B) The receiver of a ABORT shall accept the packet if the - * Verification Tag field of the packet matches its own tag OR it - * is set to its peer's tag and the T bit is set in the Chunk - * Flags. Otherwise, the receiver MUST silently discard the packet - * and take no further action. - * - * (C) The receiver of a SHUTDOWN COMPLETE shall accept the - * packet if the Verification Tag field of the packet - * matches its own tag OR it is set to its peer's tag and - * the T bit is set in the Chunk Flags. Otherwise, the - * receiver MUST silently discard the packet and take no - * further action.... + * B) The receiver of a ABORT MUST accept the packet + * if the Verification Tag field of the packet matches its own tag + * and the T bit is not set + * OR + * it is set to its peer's tag and the T bit is set in the Chunk + * Flags. + * Otherwise, the receiver MUST silently discard the packet + * and take no further action. * + * C) The receiver of a SHUTDOWN COMPLETE shall accept the packet + * if the Verification Tag field of the packet matches its own tag + * and the T bit is not set + * OR + * it is set to its peer's tag and the T bit is set in the Chunk + * Flags. + * Otherwise, the receiver MUST silently discard the packet + * and take no further action. An endpoint MUST ignore the + * SHUTDOWN COMPLETE if it is not in the SHUTDOWN-ACK-SENT state. */ - if ((ntohl(chunk->sctp_hdr->vtag) == asoc->c.my_vtag) || - (sctp_test_T_bit(chunk) && (ntohl(chunk->sctp_hdr->vtag) - == asoc->c.peer_vtag))) { + if ((!sctp_test_T_bit(chunk) && + (ntohl(chunk->sctp_hdr->vtag) == asoc->c.my_vtag)) || + (sctp_test_T_bit(chunk) && + (ntohl(chunk->sctp_hdr->vtag) == asoc->c.peer_vtag))) { return 1; } diff --git a/include/net/sctp/structs.h b/include/net/sctp/structs.h index 7e64cf6bda1e..6c24d9cd3d66 100644 --- a/include/net/sctp/structs.h +++ b/include/net/sctp/structs.h @@ -154,6 +154,13 @@ extern struct sctp_globals { int max_retrans_path; int max_retrans_init; + /* + * Policy for preforming sctp/socket accounting + * 0 - do socket level accounting, all assocs share sk_sndbuf + * 1 - do sctp accounting, each asoc may use sk_sndbuf bytes + */ + int sndbuf_policy; + /* HB.interval - 30 seconds */ int hb_interval; @@ -207,6 +214,7 @@ extern struct sctp_globals { #define sctp_valid_cookie_life (sctp_globals.valid_cookie_life) #define sctp_cookie_preserve_enable (sctp_globals.cookie_preserve_enable) #define sctp_max_retrans_association (sctp_globals.max_retrans_association) +#define sctp_sndbuf_policy (sctp_globals.sndbuf_policy) #define sctp_max_retrans_path (sctp_globals.max_retrans_path) #define sctp_max_retrans_init (sctp_globals.max_retrans_init) #define sctp_hb_interval (sctp_globals.hb_interval) @@ -1212,7 +1220,8 @@ struct sctp_endpoint { /* Default timeouts. */ int timeouts[SCTP_NUM_TIMEOUT_TYPES]; - /* Various thresholds. */ + /* sendbuf acct. policy. */ + __u32 sndbuf_policy; /* Name for debugging output... */ char *debug_name; diff --git a/include/net/sock.h b/include/net/sock.h index be81cabd0da3..a9ef3a6a13f3 100644 --- a/include/net/sock.h +++ b/include/net/sock.h @@ -7,7 +7,7 @@ * * Version: @(#)sock.h 1.0.4 05/13/93 * - * Authors: Ross Biro, <bir7@leland.Stanford.Edu> + * Authors: Ross Biro * Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG> * Corey Minyard <wf-rch!minyard@relay.EU.net> * Florian La Roche <flla@stud.uni-sb.de> @@ -90,17 +90,17 @@ do { spin_lock_init(&((__sk)->sk_lock.slock)); \ struct sock; /** - * struct sock_common - minimal network layer representation of sockets - * @skc_family - network address family - * @skc_state - Connection state - * @skc_reuse - %SO_REUSEADDR setting - * @skc_bound_dev_if - bound device index if != 0 - * @skc_node - main hash linkage for various protocol lookup tables - * @skc_bind_node - bind hash linkage for various protocol lookup tables - * @skc_refcnt - reference count - * - * This is the minimal network layer representation of sockets, the header - * for struct sock and struct tcp_tw_bucket. + * struct sock_common - minimal network layer representation of sockets + * @skc_family: network address family + * @skc_state: Connection state + * @skc_reuse: %SO_REUSEADDR setting + * @skc_bound_dev_if: bound device index if != 0 + * @skc_node: main hash linkage for various protocol lookup tables + * @skc_bind_node: bind hash linkage for various protocol lookup tables + * @skc_refcnt: reference count + * + * This is the minimal network layer representation of sockets, the header + * for struct sock and struct tcp_tw_bucket. */ struct sock_common { unsigned short skc_family; @@ -114,60 +114,62 @@ struct sock_common { /** * struct sock - network layer representation of sockets - * @__sk_common - shared layout with tcp_tw_bucket - * @sk_shutdown - mask of %SEND_SHUTDOWN and/or %RCV_SHUTDOWN - * @sk_userlocks - %SO_SNDBUF and %SO_RCVBUF settings - * @sk_lock - synchronizer - * @sk_rcvbuf - size of receive buffer in bytes - * @sk_sleep - sock wait queue - * @sk_dst_cache - destination cache - * @sk_dst_lock - destination cache lock - * @sk_policy - flow policy - * @sk_rmem_alloc - receive queue bytes committed - * @sk_receive_queue - incoming packets - * @sk_wmem_alloc - transmit queue bytes committed - * @sk_write_queue - Packet sending queue - * @sk_omem_alloc - "o" is "option" or "other" - * @sk_wmem_queued - persistent queue size - * @sk_forward_alloc - space allocated forward - * @sk_allocation - allocation mode - * @sk_sndbuf - size of send buffer in bytes - * @sk_flags - %SO_LINGER (l_onoff), %SO_BROADCAST, %SO_KEEPALIVE, %SO_OOBINLINE settings - * @sk_no_check - %SO_NO_CHECK setting, wether or not checkup packets - * @sk_route_caps - route capabilities (e.g. %NETIF_F_TSO) - * @sk_lingertime - %SO_LINGER l_linger setting - * @sk_hashent - hash entry in several tables (e.g. tcp_ehash) - * @sk_backlog - always used with the per-socket spinlock held - * @sk_callback_lock - used with the callbacks in the end of this struct - * @sk_error_queue - rarely used - * @sk_prot - protocol handlers inside a network family - * @sk_err - last error - * @sk_err_soft - errors that don't cause failure but are the cause of a persistent failure not just 'timed out' - * @sk_ack_backlog - current listen backlog - * @sk_max_ack_backlog - listen backlog set in listen() - * @sk_priority - %SO_PRIORITY setting - * @sk_type - socket type (%SOCK_STREAM, etc) - * @sk_protocol - which protocol this socket belongs in this network family - * @sk_peercred - %SO_PEERCRED setting - * @sk_rcvlowat - %SO_RCVLOWAT setting - * @sk_rcvtimeo - %SO_RCVTIMEO setting - * @sk_sndtimeo - %SO_SNDTIMEO setting - * @sk_filter - socket filtering instructions - * @sk_protinfo - private area, net family specific, when not using slab - * @sk_timer - sock cleanup timer - * @sk_stamp - time stamp of last packet received - * @sk_socket - Identd and reporting IO signals - * @sk_user_data - RPC layer private data - * @sk_sndmsg_page - cached page for sendmsg - * @sk_sndmsg_off - cached offset for sendmsg - * @sk_send_head - front of stuff to transmit - * @sk_write_pending - a write to stream socket waits to start - * @sk_state_change - callback to indicate change in the state of the sock - * @sk_data_ready - callback to indicate there is data to be processed - * @sk_write_space - callback to indicate there is bf sending space available - * @sk_error_report - callback to indicate errors (e.g. %MSG_ERRQUEUE) - * @sk_backlog_rcv - callback to process the backlog - * @sk_destruct - called at sock freeing time, i.e. when all refcnt == 0 + * @__sk_common: shared layout with tcp_tw_bucket + * @sk_shutdown: mask of %SEND_SHUTDOWN and/or %RCV_SHUTDOWN + * @sk_userlocks: %SO_SNDBUF and %SO_RCVBUF settings + * @sk_lock: synchronizer + * @sk_rcvbuf: size of receive buffer in bytes + * @sk_sleep: sock wait queue + * @sk_dst_cache: destination cache + * @sk_dst_lock: destination cache lock + * @sk_policy: flow policy + * @sk_rmem_alloc: receive queue bytes committed + * @sk_receive_queue: incoming packets + * @sk_wmem_alloc: transmit queue bytes committed + * @sk_write_queue: Packet sending queue + * @sk_omem_alloc: "o" is "option" or "other" + * @sk_wmem_queued: persistent queue size + * @sk_forward_alloc: space allocated forward + * @sk_allocation: allocation mode + * @sk_sndbuf: size of send buffer in bytes + * @sk_flags: %SO_LINGER (l_onoff), %SO_BROADCAST, %SO_KEEPALIVE, %SO_OOBINLINE settings + * @sk_no_check: %SO_NO_CHECK setting, wether or not checkup packets + * @sk_route_caps: route capabilities (e.g. %NETIF_F_TSO) + * @sk_lingertime: %SO_LINGER l_linger setting + * @sk_hashent: hash entry in several tables (e.g. tcp_ehash) + * @sk_backlog: always used with the per-socket spinlock held + * @sk_callback_lock: used with the callbacks in the end of this struct + * @sk_error_queue: rarely used + * @sk_prot: protocol handlers inside a network family + * @sk_prot_creator: sk_prot of original sock creator (see ipv6_setsockopt, IPV6_ADDRFORM for instance) + * @sk_err: last error + * @sk_err_soft: errors that don't cause failure but are the cause of a persistent failure not just 'timed out' + * @sk_ack_backlog: current listen backlog + * @sk_max_ack_backlog: listen backlog set in listen() + * @sk_priority: %SO_PRIORITY setting + * @sk_type: socket type (%SOCK_STREAM, etc) + * @sk_protocol: which protocol this socket belongs in this network family + * @sk_peercred: %SO_PEERCRED setting + * @sk_rcvlowat: %SO_RCVLOWAT setting + * @sk_rcvtimeo: %SO_RCVTIMEO setting + * @sk_sndtimeo: %SO_SNDTIMEO setting + * @sk_filter: socket filtering instructions + * @sk_protinfo: private area, net family specific, when not using slab + * @sk_timer: sock cleanup timer + * @sk_stamp: time stamp of last packet received + * @sk_socket: Identd and reporting IO signals + * @sk_user_data: RPC layer private data + * @sk_sndmsg_page: cached page for sendmsg + * @sk_sndmsg_off: cached offset for sendmsg + * @sk_send_head: front of stuff to transmit + * @sk_security: used by security modules + * @sk_write_pending: a write to stream socket waits to start + * @sk_state_change: callback to indicate change in the state of the sock + * @sk_data_ready: callback to indicate there is data to be processed + * @sk_write_space: callback to indicate there is bf sending space available + * @sk_error_report: callback to indicate errors (e.g. %MSG_ERRQUEUE) + * @sk_backlog_rcv: callback to process the backlog + * @sk_destruct: called at sock freeing time, i.e. when all refcnt == 0 */ struct sock { /* @@ -217,6 +219,7 @@ struct sock { } sk_backlog; struct sk_buff_head sk_error_queue; struct proto *sk_prot; + struct proto *sk_prot_creator; rwlock_t sk_callback_lock; int sk_err, sk_err_soft; @@ -1223,8 +1226,8 @@ sock_recv_timestamp(struct msghdr *msg, struct sock *sk, struct sk_buff *skb) /** * sk_eat_skb - Release a skb if it is no longer needed - * @sk - socket to eat this skb from - * @skb - socket buffer to eat + * @sk: socket to eat this skb from + * @skb: socket buffer to eat * * This routine must be called with interrupts disabled or with the socket * locked so that the sk_buff queue operation is ok. diff --git a/include/net/tc_act/tc_defact.h b/include/net/tc_act/tc_defact.h new file mode 100644 index 000000000000..463aa671f95d --- /dev/null +++ b/include/net/tc_act/tc_defact.h @@ -0,0 +1,13 @@ +#ifndef __NET_TC_DEF_H +#define __NET_TC_DEF_H + +#include <net/act_api.h> + +struct tcf_defact +{ + tca_gen(defact); + u32 datalen; + void *defdata; +}; + +#endif diff --git a/include/net/tcp.h b/include/net/tcp.h index 503810a70e21..e71f8ba3e101 100644 --- a/include/net/tcp.h +++ b/include/net/tcp.h @@ -7,7 +7,7 @@ * * Version: @(#)tcp.h 1.0.5 05/23/93 * - * Authors: Ross Biro, <bir7@leland.Stanford.Edu> + * Authors: Ross Biro * Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG> * * This program is free software; you can redistribute it and/or @@ -1417,19 +1417,20 @@ tcp_nagle_check(const struct tcp_sock *tp, const struct sk_buff *skb, tcp_minshall_check(tp)))); } -extern void tcp_set_skb_tso_segs(struct sk_buff *, unsigned int); +extern void tcp_set_skb_tso_segs(struct sock *, struct sk_buff *); /* This checks if the data bearing packet SKB (usually sk->sk_send_head) * should be put on the wire right now. */ -static __inline__ int tcp_snd_test(const struct tcp_sock *tp, +static __inline__ int tcp_snd_test(struct sock *sk, struct sk_buff *skb, unsigned cur_mss, int nonagle) { + struct tcp_sock *tp = tcp_sk(sk); int pkts = tcp_skb_pcount(skb); if (!pkts) { - tcp_set_skb_tso_segs(skb, tp->mss_cache_std); + tcp_set_skb_tso_segs(sk, skb); pkts = tcp_skb_pcount(skb); } @@ -1490,7 +1491,7 @@ static __inline__ void __tcp_push_pending_frames(struct sock *sk, if (skb) { if (!tcp_skb_is_last(sk, skb)) nonagle = TCP_NAGLE_PUSH; - if (!tcp_snd_test(tp, skb, cur_mss, nonagle) || + if (!tcp_snd_test(sk, skb, cur_mss, nonagle) || tcp_write_xmit(sk, nonagle)) tcp_check_probe_timer(sk, tp); } @@ -1508,7 +1509,7 @@ static __inline__ int tcp_may_send_now(struct sock *sk, struct tcp_sock *tp) struct sk_buff *skb = sk->sk_send_head; return (skb && - tcp_snd_test(tp, skb, tcp_current_mss(sk, 1), + tcp_snd_test(sk, skb, tcp_current_mss(sk, 1), tcp_skb_is_last(sk, skb) ? TCP_NAGLE_PUSH : tp->nonagle)); } diff --git a/include/net/udp.h b/include/net/udp.h index c496d10101db..ac229b761dbc 100644 --- a/include/net/udp.h +++ b/include/net/udp.h @@ -7,7 +7,7 @@ * * Version: @(#)udp.h 1.0.2 05/07/93 * - * Authors: Ross Biro, <bir7@leland.Stanford.Edu> + * Authors: Ross Biro * Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG> * * Fixes: diff --git a/include/net/xfrm.h b/include/net/xfrm.h index 73e9a8ca3d3b..e142a256d5dc 100644 --- a/include/net/xfrm.h +++ b/include/net/xfrm.h @@ -1,6 +1,7 @@ #ifndef _NET_XFRM_H #define _NET_XFRM_H +#include <linux/compiler.h> #include <linux/xfrm.h> #include <linux/spinlock.h> #include <linux/list.h> @@ -516,6 +517,15 @@ struct xfrm_dst u32 child_mtu_cached; }; +static inline void xfrm_dst_destroy(struct xfrm_dst *xdst) +{ + dst_release(xdst->route); + if (likely(xdst->u.dst.xfrm)) + xfrm_state_put(xdst->u.dst.xfrm); +} + +extern void xfrm_dst_ifdown(struct dst_entry *dst, struct net_device *dev); + /* Decapsulation state, used by the input to store data during * decapsulation procedure, to be used later (during the policy * check diff --git a/include/video/edid.h b/include/video/edid.h index abc1b489c0db..b913f196131d 100644 --- a/include/video/edid.h +++ b/include/video/edid.h @@ -4,9 +4,6 @@ #ifdef __KERNEL__ #include <linux/config.h> -#ifdef CONFIG_PPC_OF -#include <linux/pci.h> -#endif #ifdef CONFIG_X86 struct edid_info { @@ -14,14 +11,8 @@ struct edid_info { }; extern struct edid_info edid_info; -extern char *get_EDID_from_BIOS(void *); - #endif /* CONFIG_X86 */ -#ifdef CONFIG_PPC_OF -extern char *get_EDID_from_OF(struct pci_dev *pdev); -#endif - #endif /* __KERNEL__ */ #endif /* __linux_video_edid_h__ */ diff --git a/include/video/tdfx.h b/include/video/tdfx.h index a896e4442060..04237676b17c 100644 --- a/include/video/tdfx.h +++ b/include/video/tdfx.h @@ -99,6 +99,8 @@ #define MISCINIT1_2DBLOCK_DIS BIT(15) #define DRAMINIT0_SGRAM_NUM BIT(26) #define DRAMINIT0_SGRAM_TYPE BIT(27) +#define DRAMINIT0_SGRAM_TYPE_MASK (BIT(27)|BIT(28)|BIT(29)) +#define DRAMINIT0_SGRAM_TYPE_SHIFT 27 #define DRAMINIT1_MEM_SDRAM BIT(30) #define VGAINIT0_VGA_DISABLE BIT(0) #define VGAINIT0_EXT_TIMING BIT(1) |
