diff options
Diffstat (limited to 'include/video')
| -rw-r--r-- | include/video/display_timing.h | 124 | ||||
| -rw-r--r-- | include/video/exynos_mipi_dsim.h | 1 | ||||
| -rw-r--r-- | include/video/mmp_disp.h | 352 | ||||
| -rw-r--r-- | include/video/of_display_timing.h | 20 | ||||
| -rw-r--r-- | include/video/of_videomode.h | 18 | ||||
| -rw-r--r-- | include/video/samsung_fimd.h | 205 | ||||
| -rw-r--r-- | include/video/videomode.h | 48 |
7 files changed, 662 insertions, 106 deletions
diff --git a/include/video/display_timing.h b/include/video/display_timing.h new file mode 100644 index 000000000000..71e9a383a981 --- /dev/null +++ b/include/video/display_timing.h @@ -0,0 +1,124 @@ +/* + * Copyright 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de> + * + * description of display timings + * + * This file is released under the GPLv2 + */ + +#ifndef __LINUX_DISPLAY_TIMING_H +#define __LINUX_DISPLAY_TIMING_H + +#include <linux/bitops.h> +#include <linux/types.h> + +/* VESA display monitor timing parameters */ +#define VESA_DMT_HSYNC_LOW BIT(0) +#define VESA_DMT_HSYNC_HIGH BIT(1) +#define VESA_DMT_VSYNC_LOW BIT(2) +#define VESA_DMT_VSYNC_HIGH BIT(3) + +/* display specific flags */ +#define DISPLAY_FLAGS_DE_LOW BIT(0) /* data enable flag */ +#define DISPLAY_FLAGS_DE_HIGH BIT(1) +#define DISPLAY_FLAGS_PIXDATA_POSEDGE BIT(2) /* drive data on pos. edge */ +#define DISPLAY_FLAGS_PIXDATA_NEGEDGE BIT(3) /* drive data on neg. edge */ +#define DISPLAY_FLAGS_INTERLACED BIT(4) +#define DISPLAY_FLAGS_DOUBLESCAN BIT(5) + +/* + * A single signal can be specified via a range of minimal and maximal values + * with a typical value, that lies somewhere inbetween. + */ +struct timing_entry { + u32 min; + u32 typ; + u32 max; +}; + +enum timing_entry_index { + TE_MIN = 0, + TE_TYP = 1, + TE_MAX = 2, +}; + +/* + * Single "mode" entry. This describes one set of signal timings a display can + * have in one setting. This struct can later be converted to struct videomode + * (see include/video/videomode.h). As each timing_entry can be defined as a + * range, one struct display_timing may become multiple struct videomodes. + * + * Example: hsync active high, vsync active low + * + * Active Video + * Video ______________________XXXXXXXXXXXXXXXXXXXXXX_____________________ + * |<- sync ->|<- back ->|<----- active ----->|<- front ->|<- sync.. + * | | porch | | porch | + * + * HSync _|¯¯¯¯¯¯¯¯¯¯|___________________________________________|¯¯¯¯¯¯¯¯¯ + * + * VSync ¯|__________|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_________ + */ +struct display_timing { + struct timing_entry pixelclock; + + struct timing_entry hactive; /* hor. active video */ + struct timing_entry hfront_porch; /* hor. front porch */ + struct timing_entry hback_porch; /* hor. back porch */ + struct timing_entry hsync_len; /* hor. sync len */ + + struct timing_entry vactive; /* ver. active video */ + struct timing_entry vfront_porch; /* ver. front porch */ + struct timing_entry vback_porch; /* ver. back porch */ + struct timing_entry vsync_len; /* ver. sync len */ + + unsigned int dmt_flags; /* VESA DMT flags */ + unsigned int data_flags; /* video data flags */ +}; + +/* + * This describes all timing settings a display provides. + * The native_mode is the default setting for this display. + * Drivers that can handle multiple videomodes should work with this struct and + * convert each entry to the desired end result. + */ +struct display_timings { + unsigned int num_timings; + unsigned int native_mode; + + struct display_timing **timings; +}; + +/* get value specified by index from struct timing_entry */ +static inline u32 display_timing_get_value(const struct timing_entry *te, + enum timing_entry_index index) +{ + switch (index) { + case TE_MIN: + return te->min; + break; + case TE_TYP: + return te->typ; + break; + case TE_MAX: + return te->max; + break; + default: + return te->typ; + } +} + +/* get one entry from struct display_timings */ +static inline struct display_timing *display_timings_get(const struct + display_timings *disp, + unsigned int index) +{ + if (disp->num_timings > index) + return disp->timings[index]; + else + return NULL; +} + +void display_timings_release(struct display_timings *disp); + +#endif diff --git a/include/video/exynos_mipi_dsim.h b/include/video/exynos_mipi_dsim.h index 83ce5e667d47..89dc88a171af 100644 --- a/include/video/exynos_mipi_dsim.h +++ b/include/video/exynos_mipi_dsim.h @@ -220,7 +220,6 @@ struct mipi_dsim_config { struct mipi_dsim_device { struct device *dev; int id; - struct resource *res; struct clk *clock; unsigned int irq; void __iomem *reg_base; diff --git a/include/video/mmp_disp.h b/include/video/mmp_disp.h new file mode 100644 index 000000000000..b9dd1fbb0082 --- /dev/null +++ b/include/video/mmp_disp.h @@ -0,0 +1,352 @@ +/* + * linux/include/video/mmp_disp.h + * Header file for Marvell MMP Display Controller + * + * Copyright (C) 2012 Marvell Technology Group Ltd. + * Authors: Zhou Zhu <zzhu3@marvell.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + * + */ + +#ifndef _MMP_DISP_H_ +#define _MMP_DISP_H_ +#include <linux/kthread.h> + +enum { + PIXFMT_UYVY = 0, + PIXFMT_VYUY, + PIXFMT_YUYV, + PIXFMT_YUV422P, + PIXFMT_YVU422P, + PIXFMT_YUV420P, + PIXFMT_YVU420P, + PIXFMT_RGB565 = 0x100, + PIXFMT_BGR565, + PIXFMT_RGB1555, + PIXFMT_BGR1555, + PIXFMT_RGB888PACK, + PIXFMT_BGR888PACK, + PIXFMT_RGB888UNPACK, + PIXFMT_BGR888UNPACK, + PIXFMT_RGBA888, + PIXFMT_BGRA888, + PIXFMT_RGB666, /* for output usage */ + PIXFMT_PSEUDOCOLOR = 0x200, +}; + +static inline int pixfmt_to_stride(int pix_fmt) +{ + switch (pix_fmt) { + case PIXFMT_RGB565: + case PIXFMT_BGR565: + case PIXFMT_RGB1555: + case PIXFMT_BGR1555: + case PIXFMT_UYVY: + case PIXFMT_VYUY: + case PIXFMT_YUYV: + return 2; + case PIXFMT_RGB888UNPACK: + case PIXFMT_BGR888UNPACK: + case PIXFMT_RGBA888: + case PIXFMT_BGRA888: + return 4; + case PIXFMT_RGB888PACK: + case PIXFMT_BGR888PACK: + return 3; + case PIXFMT_YUV422P: + case PIXFMT_YVU422P: + case PIXFMT_YUV420P: + case PIXFMT_YVU420P: + case PIXFMT_PSEUDOCOLOR: + return 1; + default: + return 0; + } +} + +/* parameters used by path/overlay */ +/* overlay related para: win/addr */ +struct mmp_win { + /* position/size of window */ + u16 xsrc; + u16 ysrc; + u16 xdst; + u16 ydst; + u16 xpos; + u16 ypos; + u16 left_crop; + u16 right_crop; + u16 up_crop; + u16 bottom_crop; + int pix_fmt; +}; + +struct mmp_addr { + /* phys address */ + u32 phys[6]; +}; + +/* path related para: mode */ +struct mmp_mode { + const char *name; + u32 refresh; + u32 xres; + u32 yres; + u32 left_margin; + u32 right_margin; + u32 upper_margin; + u32 lower_margin; + u32 hsync_len; + u32 vsync_len; + u32 hsync_invert; + u32 vsync_invert; + u32 invert_pixclock; + u32 pixclock_freq; + int pix_fmt_out; +}; + +/* main structures */ +struct mmp_path; +struct mmp_overlay; +struct mmp_panel; + +/* status types */ +enum { + MMP_OFF = 0, + MMP_ON, +}; + +static inline const char *stat_name(int stat) +{ + switch (stat) { + case MMP_OFF: + return "OFF"; + case MMP_ON: + return "ON"; + default: + return "UNKNOWNSTAT"; + } +} + +struct mmp_overlay_ops { + /* should be provided by driver */ + void (*set_fetch)(struct mmp_overlay *overlay, int fetch_id); + void (*set_onoff)(struct mmp_overlay *overlay, int status); + void (*set_win)(struct mmp_overlay *overlay, struct mmp_win *win); + int (*set_addr)(struct mmp_overlay *overlay, struct mmp_addr *addr); +}; + +/* overlay describes a z-order indexed slot in each path. */ +struct mmp_overlay { + int id; + const char *name; + struct mmp_path *path; + + /* overlay info: private data */ + int dmafetch_id; + struct mmp_addr addr; + struct mmp_win win; + + /* state */ + int open_count; + int status; + struct mutex access_ok; + + struct mmp_overlay_ops *ops; +}; + +/* panel type */ +enum { + PANELTYPE_ACTIVE = 0, + PANELTYPE_SMART, + PANELTYPE_TV, + PANELTYPE_DSI_CMD, + PANELTYPE_DSI_VIDEO, +}; + +struct mmp_panel { + /* use node to register to list */ + struct list_head node; + const char *name; + /* path name used to connect to proper path configed */ + const char *plat_path_name; + struct device *dev; + int panel_type; + void *plat_data; + int (*get_modelist)(struct mmp_panel *panel, + struct mmp_mode **modelist); + void (*set_mode)(struct mmp_panel *panel, + struct mmp_mode *mode); + void (*set_onoff)(struct mmp_panel *panel, + int status); +}; + +struct mmp_path_ops { + int (*check_status)(struct mmp_path *path); + struct mmp_overlay *(*get_overlay)(struct mmp_path *path, + int overlay_id); + int (*get_modelist)(struct mmp_path *path, + struct mmp_mode **modelist); + + /* follow ops should be provided by driver */ + void (*set_mode)(struct mmp_path *path, struct mmp_mode *mode); + void (*set_onoff)(struct mmp_path *path, int status); + /* todo: add query */ +}; + +/* path output types */ +enum { + PATH_OUT_PARALLEL, + PATH_OUT_DSI, + PATH_OUT_HDMI, +}; + +/* path is main part of mmp-disp */ +struct mmp_path { + /* use node to register to list */ + struct list_head node; + + /* init data */ + struct device *dev; + + int id; + const char *name; + int output_type; + struct mmp_panel *panel; + void *plat_data; + + /* dynamic use */ + struct mmp_mode mode; + + /* state */ + int open_count; + int status; + struct mutex access_ok; + + struct mmp_path_ops ops; + + /* layers */ + int overlay_num; + struct mmp_overlay overlays[0]; +}; + +extern struct mmp_path *mmp_get_path(const char *name); +static inline void mmp_path_set_mode(struct mmp_path *path, + struct mmp_mode *mode) +{ + if (path) + path->ops.set_mode(path, mode); +} +static inline void mmp_path_set_onoff(struct mmp_path *path, int status) +{ + if (path) + path->ops.set_onoff(path, status); +} +static inline int mmp_path_get_modelist(struct mmp_path *path, + struct mmp_mode **modelist) +{ + if (path) + return path->ops.get_modelist(path, modelist); + return 0; +} +static inline struct mmp_overlay *mmp_path_get_overlay( + struct mmp_path *path, int overlay_id) +{ + if (path) + return path->ops.get_overlay(path, overlay_id); + return NULL; +} +static inline void mmp_overlay_set_fetch(struct mmp_overlay *overlay, + int fetch_id) +{ + if (overlay) + overlay->ops->set_fetch(overlay, fetch_id); +} +static inline void mmp_overlay_set_onoff(struct mmp_overlay *overlay, + int status) +{ + if (overlay) + overlay->ops->set_onoff(overlay, status); +} +static inline void mmp_overlay_set_win(struct mmp_overlay *overlay, + struct mmp_win *win) +{ + if (overlay) + overlay->ops->set_win(overlay, win); +} +static inline int mmp_overlay_set_addr(struct mmp_overlay *overlay, + struct mmp_addr *addr) +{ + if (overlay) + return overlay->ops->set_addr(overlay, addr); + return 0; +} + +/* + * driver data is set from each detailed ctrl driver for path usage + * it defined a common interface that plat driver need to implement + */ +struct mmp_path_info { + /* driver data, set when registed*/ + const char *name; + struct device *dev; + int id; + int output_type; + int overlay_num; + void (*set_mode)(struct mmp_path *path, struct mmp_mode *mode); + void (*set_onoff)(struct mmp_path *path, int status); + struct mmp_overlay_ops *overlay_ops; + void *plat_data; +}; + +extern struct mmp_path *mmp_register_path( + struct mmp_path_info *info); +extern void mmp_unregister_path(struct mmp_path *path); +extern void mmp_register_panel(struct mmp_panel *panel); +extern void mmp_unregister_panel(struct mmp_panel *panel); + +/* defintions for platform data */ +/* interface for buffer driver */ +struct mmp_buffer_driver_mach_info { + const char *name; + const char *path_name; + int overlay_id; + int dmafetch_id; + int default_pixfmt; +}; + +/* interface for controllers driver */ +struct mmp_mach_path_config { + const char *name; + int overlay_num; + int output_type; + u32 path_config; + u32 link_config; +}; + +struct mmp_mach_plat_info { + const char *name; + const char *clk_name; + int path_num; + struct mmp_mach_path_config *paths; +}; + +/* interface for panel drivers */ +struct mmp_mach_panel_info { + const char *name; + void (*plat_set_onoff)(int status); + const char *plat_path_name; +}; +#endif /* _MMP_DISP_H_ */ diff --git a/include/video/of_display_timing.h b/include/video/of_display_timing.h new file mode 100644 index 000000000000..8016eb727cf3 --- /dev/null +++ b/include/video/of_display_timing.h @@ -0,0 +1,20 @@ +/* + * Copyright 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de> + * + * display timings of helpers + * + * This file is released under the GPLv2 + */ + +#ifndef __LINUX_OF_DISPLAY_TIMING_H +#define __LINUX_OF_DISPLAY_TIMING_H + +struct device_node; +struct display_timings; + +#define OF_USE_NATIVE_MODE -1 + +struct display_timings *of_get_display_timings(struct device_node *np); +int of_display_timings_exist(struct device_node *np); + +#endif diff --git a/include/video/of_videomode.h b/include/video/of_videomode.h new file mode 100644 index 000000000000..a07efcc51424 --- /dev/null +++ b/include/video/of_videomode.h @@ -0,0 +1,18 @@ +/* + * Copyright 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de> + * + * videomode of-helpers + * + * This file is released under the GPLv2 + */ + +#ifndef __LINUX_OF_VIDEOMODE_H +#define __LINUX_OF_VIDEOMODE_H + +struct device_node; +struct videomode; + +int of_get_videomode(struct device_node *np, struct videomode *vm, + int index); + +#endif /* __LINUX_OF_VIDEOMODE_H */ diff --git a/include/video/samsung_fimd.h b/include/video/samsung_fimd.h index e7554486a2b7..b0393209679b 100644 --- a/include/video/samsung_fimd.h +++ b/include/video/samsung_fimd.h @@ -8,12 +8,8 @@ * S3C Platform - new-style fimd and framebuffer register definitions * * This is the register set for the fimd and new style framebuffer interface - * found from the S3C2443 onwards into the S3C2416, S3C2450 and the - * S3C64XX series such as the S3C6400 and S3C6410. - * - * The file does not contain the cpu specific items which are based on - * whichever architecture is selected, it only contains the core of the - * register set. See <mach/regs-fb.h> to get the specifics. + * found from the S3C2443 onwards into the S3C2416, S3C2450, the + * S3C64XX series such as the S3C6400 and S3C6410, and EXYNOS series. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -22,10 +18,10 @@ /* VIDCON0 */ -#define VIDCON0 (0x00) +#define VIDCON0 0x00 #define VIDCON0_INTERLACE (1 << 29) #define VIDCON0_VIDOUT_MASK (0x7 << 26) -#define VIDCON0_VIDOUT_SHIFT (26) +#define VIDCON0_VIDOUT_SHIFT 26 #define VIDCON0_VIDOUT_RGB (0x0 << 26) #define VIDCON0_VIDOUT_TV (0x1 << 26) #define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26) @@ -35,7 +31,7 @@ #define VIDCON0_VIDOUT_WB_I80_LDI1 (0x7 << 26) #define VIDCON0_L1_DATA_MASK (0x7 << 23) -#define VIDCON0_L1_DATA_SHIFT (23) +#define VIDCON0_L1_DATA_SHIFT 23 #define VIDCON0_L1_DATA_16BPP (0x0 << 23) #define VIDCON0_L1_DATA_18BPP16 (0x1 << 23) #define VIDCON0_L1_DATA_18BPP9 (0x2 << 23) @@ -44,7 +40,7 @@ #define VIDCON0_L1_DATA_16BPP8 (0x5 << 23) #define VIDCON0_L0_DATA_MASK (0x7 << 20) -#define VIDCON0_L0_DATA_SHIFT (20) +#define VIDCON0_L0_DATA_SHIFT 20 #define VIDCON0_L0_DATA_16BPP (0x0 << 20) #define VIDCON0_L0_DATA_18BPP16 (0x1 << 20) #define VIDCON0_L0_DATA_18BPP9 (0x2 << 20) @@ -53,7 +49,7 @@ #define VIDCON0_L0_DATA_16BPP8 (0x5 << 20) #define VIDCON0_PNRMODE_MASK (0x3 << 17) -#define VIDCON0_PNRMODE_SHIFT (17) +#define VIDCON0_PNRMODE_SHIFT 17 #define VIDCON0_PNRMODE_RGB (0x0 << 17) #define VIDCON0_PNRMODE_BGR (0x1 << 17) #define VIDCON0_PNRMODE_SERIAL_RGB (0x2 << 17) @@ -61,14 +57,14 @@ #define VIDCON0_CLKVALUP (1 << 16) #define VIDCON0_CLKVAL_F_MASK (0xff << 6) -#define VIDCON0_CLKVAL_F_SHIFT (6) -#define VIDCON0_CLKVAL_F_LIMIT (0xff) +#define VIDCON0_CLKVAL_F_SHIFT 6 +#define VIDCON0_CLKVAL_F_LIMIT 0xff #define VIDCON0_CLKVAL_F(_x) ((_x) << 6) #define VIDCON0_VLCKFREE (1 << 5) #define VIDCON0_CLKDIR (1 << 4) #define VIDCON0_CLKSEL_MASK (0x3 << 2) -#define VIDCON0_CLKSEL_SHIFT (2) +#define VIDCON0_CLKSEL_SHIFT 2 #define VIDCON0_CLKSEL_HCLK (0x0 << 2) #define VIDCON0_CLKSEL_LCD (0x1 << 2) #define VIDCON0_CLKSEL_27M (0x3 << 2) @@ -76,17 +72,17 @@ #define VIDCON0_ENVID (1 << 1) #define VIDCON0_ENVID_F (1 << 0) -#define VIDCON1 (0x04) +#define VIDCON1 0x04 #define VIDCON1_LINECNT_MASK (0x7ff << 16) -#define VIDCON1_LINECNT_SHIFT (16) +#define VIDCON1_LINECNT_SHIFT 16 #define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff) #define VIDCON1_FSTATUS_EVEN (1 << 15) #define VIDCON1_VSTATUS_MASK (0x3 << 13) -#define VIDCON1_VSTATUS_SHIFT (13) +#define VIDCON1_VSTATUS_SHIFT 13 #define VIDCON1_VSTATUS_VSYNC (0x0 << 13) #define VIDCON1_VSTATUS_BACKPORCH (0x1 << 13) #define VIDCON1_VSTATUS_ACTIVE (0x2 << 13) -#define VIDCON1_VSTATUS_FRONTPORCH (0x0 << 13) +#define VIDCON1_VSTATUS_FRONTPORCH (0x3 << 13) #define VIDCON1_VCLK_MASK (0x3 << 9) #define VIDCON1_VCLK_HOLD (0x0 << 9) #define VIDCON1_VCLK_RUN (0x1 << 9) @@ -98,12 +94,12 @@ /* VIDCON2 */ -#define VIDCON2 (0x08) +#define VIDCON2 0x08 #define VIDCON2_EN601 (1 << 23) #define VIDCON2_TVFMTSEL_SW (1 << 14) #define VIDCON2_TVFMTSEL1_MASK (0x3 << 12) -#define VIDCON2_TVFMTSEL1_SHIFT (12) +#define VIDCON2_TVFMTSEL1_SHIFT 12 #define VIDCON2_TVFMTSEL1_RGB (0x0 << 12) #define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12) #define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12) @@ -115,74 +111,75 @@ * Might not be present in the S3C6410 documentation, * but tests prove it's there almost for sure; shouldn't hurt in any case. */ -#define PRTCON (0x0c) +#define PRTCON 0x0c #define PRTCON_PROTECT (1 << 11) /* VIDTCON0 */ -#define VIDTCON0 (0x10) +#define VIDTCON0 0x10 #define VIDTCON0_VBPDE_MASK (0xff << 24) -#define VIDTCON0_VBPDE_SHIFT (24) -#define VIDTCON0_VBPDE_LIMIT (0xff) +#define VIDTCON0_VBPDE_SHIFT 24 +#define VIDTCON0_VBPDE_LIMIT 0xff #define VIDTCON0_VBPDE(_x) ((_x) << 24) #define VIDTCON0_VBPD_MASK (0xff << 16) -#define VIDTCON0_VBPD_SHIFT (16) -#define VIDTCON0_VBPD_LIMIT (0xff) +#define VIDTCON0_VBPD_SHIFT 16 +#define VIDTCON0_VBPD_LIMIT 0xff #define VIDTCON0_VBPD(_x) ((_x) << 16) #define VIDTCON0_VFPD_MASK (0xff << 8) -#define VIDTCON0_VFPD_SHIFT (8) -#define VIDTCON0_VFPD_LIMIT (0xff) +#define VIDTCON0_VFPD_SHIFT 8 +#define VIDTCON0_VFPD_LIMIT 0xff #define VIDTCON0_VFPD(_x) ((_x) << 8) #define VIDTCON0_VSPW_MASK (0xff << 0) -#define VIDTCON0_VSPW_SHIFT (0) -#define VIDTCON0_VSPW_LIMIT (0xff) +#define VIDTCON0_VSPW_SHIFT 0 +#define VIDTCON0_VSPW_LIMIT 0xff #define VIDTCON0_VSPW(_x) ((_x) << 0) /* VIDTCON1 */ -#define VIDTCON1 (0x14) +#define VIDTCON1 0x14 #define VIDTCON1_VFPDE_MASK (0xff << 24) -#define VIDTCON1_VFPDE_SHIFT (24) -#define VIDTCON1_VFPDE_LIMIT (0xff) +#define VIDTCON1_VFPDE_SHIFT 24 +#define VIDTCON1_VFPDE_LIMIT 0xff #define VIDTCON1_VFPDE(_x) ((_x) << 24) #define VIDTCON1_HBPD_MASK (0xff << 16) -#define VIDTCON1_HBPD_SHIFT (16) -#define VIDTCON1_HBPD_LIMIT (0xff) +#define VIDTCON1_HBPD_SHIFT 16 +#define VIDTCON1_HBPD_LIMIT 0xff #define VIDTCON1_HBPD(_x) ((_x) << 16) #define VIDTCON1_HFPD_MASK (0xff << 8) -#define VIDTCON1_HFPD_SHIFT (8) -#define VIDTCON1_HFPD_LIMIT (0xff) +#define VIDTCON1_HFPD_SHIFT 8 +#define VIDTCON1_HFPD_LIMIT 0xff #define VIDTCON1_HFPD(_x) ((_x) << 8) #define VIDTCON1_HSPW_MASK (0xff << 0) -#define VIDTCON1_HSPW_SHIFT (0) -#define VIDTCON1_HSPW_LIMIT (0xff) +#define VIDTCON1_HSPW_SHIFT 0 +#define VIDTCON1_HSPW_LIMIT 0xff #define VIDTCON1_HSPW(_x) ((_x) << 0) -#define VIDTCON2 (0x18) -#define VIDTCON2 (0x18) +#define VIDTCON2 0x18 #define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800) >> 11) << 23) #define VIDTCON2_LINEVAL_MASK (0x7ff << 11) -#define VIDTCON2_LINEVAL_SHIFT (11) -#define VIDTCON2_LINEVAL_LIMIT (0x7ff) +#define VIDTCON2_LINEVAL_SHIFT 11 +#define VIDTCON2_LINEVAL_LIMIT 0x7ff #define VIDTCON2_LINEVAL(_x) (((_x) & 0x7ff) << 11) #define VIDTCON2_HOZVAL_E(_x) ((((_x) & 0x800) >> 11) << 22) #define VIDTCON2_HOZVAL_MASK (0x7ff << 0) -#define VIDTCON2_HOZVAL_SHIFT (0) -#define VIDTCON2_HOZVAL_LIMIT (0x7ff) +#define VIDTCON2_HOZVAL_SHIFT 0 +#define VIDTCON2_HOZVAL_LIMIT 0x7ff #define VIDTCON2_HOZVAL(_x) (((_x) & 0x7ff) << 0) /* WINCONx */ #define WINCON(_win) (0x20 + ((_win) * 4)) +#define WINCONx_CSCCON_EQ601 (0x0 << 28) +#define WINCONx_CSCCON_EQ709 (0x1 << 28) #define WINCONx_CSCWIDTH_MASK (0x3 << 26) -#define WINCONx_CSCWIDTH_SHIFT (26) +#define WINCONx_CSCWIDTH_SHIFT 26 #define WINCONx_CSCWIDTH_WIDE (0x0 << 26) #define WINCONx_CSCWIDTH_NARROW (0x3 << 26) #define WINCONx_ENLOCAL (1 << 22) @@ -195,14 +192,14 @@ #define WINCONx_WSWP (1 << 15) #define WINCONx_YCbCr (1 << 13) #define WINCONx_BURSTLEN_MASK (0x3 << 9) -#define WINCONx_BURSTLEN_SHIFT (9) +#define WINCONx_BURSTLEN_SHIFT 9 #define WINCONx_BURSTLEN_16WORD (0x0 << 9) #define WINCONx_BURSTLEN_8WORD (0x1 << 9) #define WINCONx_BURSTLEN_4WORD (0x2 << 9) #define WINCONx_ENWIN (1 << 0) #define WINCON0_BPPMODE_MASK (0xf << 2) -#define WINCON0_BPPMODE_SHIFT (2) +#define WINCON0_BPPMODE_SHIFT 2 #define WINCON0_BPPMODE_1BPP (0x0 << 2) #define WINCON0_BPPMODE_2BPP (0x1 << 2) #define WINCON0_BPPMODE_4BPP (0x2 << 2) @@ -215,7 +212,7 @@ #define WINCON1_LOCALSEL_CAMIF (1 << 23) #define WINCON1_BLD_PIX (1 << 6) #define WINCON1_BPPMODE_MASK (0xf << 2) -#define WINCON1_BPPMODE_SHIFT (2) +#define WINCON1_BPPMODE_SHIFT 2 #define WINCON1_BPPMODE_1BPP (0x0 << 2) #define WINCON1_BPPMODE_2BPP (0x1 << 2) #define WINCON1_BPPMODE_4BPP (0x2 << 2) @@ -234,7 +231,7 @@ #define WINCON1_ALPHA_SEL (1 << 1) /* S5PV210 */ -#define SHADOWCON (0x34) +#define SHADOWCON 0x34 #define SHADOWCON_WINx_PROTECT(_win) (1 << (10 + (_win))) /* DMA channels (all windows) */ #define SHADOWCON_CHx_ENABLE(_win) (1 << (_win)) @@ -243,52 +240,52 @@ /* VIDOSDx */ -#define VIDOSD_BASE (0x40) +#define VIDOSD_BASE 0x40 #define VIDOSDxA_TOPLEFT_X_E(_x) ((((_x) & 0x800) >> 11) << 23) #define VIDOSDxA_TOPLEFT_X_MASK (0x7ff << 11) -#define VIDOSDxA_TOPLEFT_X_SHIFT (11) -#define VIDOSDxA_TOPLEFT_X_LIMIT (0x7ff) +#define VIDOSDxA_TOPLEFT_X_SHIFT 11 +#define VIDOSDxA_TOPLEFT_X_LIMIT 0x7ff #define VIDOSDxA_TOPLEFT_X(_x) (((_x) & 0x7ff) << 11) #define VIDOSDxA_TOPLEFT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22) #define VIDOSDxA_TOPLEFT_Y_MASK (0x7ff << 0) -#define VIDOSDxA_TOPLEFT_Y_SHIFT (0) -#define VIDOSDxA_TOPLEFT_Y_LIMIT (0x7ff) +#define VIDOSDxA_TOPLEFT_Y_SHIFT 0 +#define VIDOSDxA_TOPLEFT_Y_LIMIT 0x7ff #define VIDOSDxA_TOPLEFT_Y(_x) (((_x) & 0x7ff) << 0) #define VIDOSDxB_BOTRIGHT_X_E(_x) ((((_x) & 0x800) >> 11) << 23) #define VIDOSDxB_BOTRIGHT_X_MASK (0x7ff << 11) -#define VIDOSDxB_BOTRIGHT_X_SHIFT (11) -#define VIDOSDxB_BOTRIGHT_X_LIMIT (0x7ff) +#define VIDOSDxB_BOTRIGHT_X_SHIFT 11 +#define VIDOSDxB_BOTRIGHT_X_LIMIT 0x7ff #define VIDOSDxB_BOTRIGHT_X(_x) (((_x) & 0x7ff) << 11) #define VIDOSDxB_BOTRIGHT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22) #define VIDOSDxB_BOTRIGHT_Y_MASK (0x7ff << 0) -#define VIDOSDxB_BOTRIGHT_Y_SHIFT (0) -#define VIDOSDxB_BOTRIGHT_Y_LIMIT (0x7ff) +#define VIDOSDxB_BOTRIGHT_Y_SHIFT 0 +#define VIDOSDxB_BOTRIGHT_Y_LIMIT 0x7ff #define VIDOSDxB_BOTRIGHT_Y(_x) (((_x) & 0x7ff) << 0) /* For VIDOSD[1..4]C */ #define VIDISD14C_ALPHA0_R(_x) ((_x) << 20) #define VIDISD14C_ALPHA0_G_MASK (0xf << 16) -#define VIDISD14C_ALPHA0_G_SHIFT (16) -#define VIDISD14C_ALPHA0_G_LIMIT (0xf) +#define VIDISD14C_ALPHA0_G_SHIFT 16 +#define VIDISD14C_ALPHA0_G_LIMIT 0xf #define VIDISD14C_ALPHA0_G(_x) ((_x) << 16) #define VIDISD14C_ALPHA0_B_MASK (0xf << 12) -#define VIDISD14C_ALPHA0_B_SHIFT (12) -#define VIDISD14C_ALPHA0_B_LIMIT (0xf) +#define VIDISD14C_ALPHA0_B_SHIFT 12 +#define VIDISD14C_ALPHA0_B_LIMIT 0xf #define VIDISD14C_ALPHA0_B(_x) ((_x) << 12) #define VIDISD14C_ALPHA1_R_MASK (0xf << 8) -#define VIDISD14C_ALPHA1_R_SHIFT (8) -#define VIDISD14C_ALPHA1_R_LIMIT (0xf) +#define VIDISD14C_ALPHA1_R_SHIFT 8 +#define VIDISD14C_ALPHA1_R_LIMIT 0xf #define VIDISD14C_ALPHA1_R(_x) ((_x) << 8) #define VIDISD14C_ALPHA1_G_MASK (0xf << 4) -#define VIDISD14C_ALPHA1_G_SHIFT (4) -#define VIDISD14C_ALPHA1_G_LIMIT (0xf) +#define VIDISD14C_ALPHA1_G_SHIFT 4 +#define VIDISD14C_ALPHA1_G_LIMIT 0xf #define VIDISD14C_ALPHA1_G(_x) ((_x) << 4) #define VIDISD14C_ALPHA1_B_MASK (0xf << 0) -#define VIDISD14C_ALPHA1_B_SHIFT (0) -#define VIDISD14C_ALPHA1_B_LIMIT (0xf) +#define VIDISD14C_ALPHA1_B_SHIFT 0 +#define VIDISD14C_ALPHA1_B_LIMIT 0xf #define VIDISD14C_ALPHA1_B(_x) ((_x) << 0) /* Video buffer addresses */ @@ -300,22 +297,22 @@ #define VIDW_BUF_SIZE_OFFSET_E(_x) ((((_x) & 0x2000) >> 13) << 27) #define VIDW_BUF_SIZE_OFFSET_MASK (0x1fff << 13) -#define VIDW_BUF_SIZE_OFFSET_SHIFT (13) -#define VIDW_BUF_SIZE_OFFSET_LIMIT (0x1fff) +#define VIDW_BUF_SIZE_OFFSET_SHIFT 13 +#define VIDW_BUF_SIZE_OFFSET_LIMIT 0x1fff #define VIDW_BUF_SIZE_OFFSET(_x) (((_x) & 0x1fff) << 13) #define VIDW_BUF_SIZE_PAGEWIDTH_E(_x) ((((_x) & 0x2000) >> 13) << 26) #define VIDW_BUF_SIZE_PAGEWIDTH_MASK (0x1fff << 0) -#define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT (0) -#define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT (0x1fff) +#define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT 0 +#define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT 0x1fff #define VIDW_BUF_SIZE_PAGEWIDTH(_x) (((_x) & 0x1fff) << 0) /* Interrupt controls and status */ -#define VIDINTCON0 (0x130) +#define VIDINTCON0 0x130 #define VIDINTCON0_FIFOINTERVAL_MASK (0x3f << 20) -#define VIDINTCON0_FIFOINTERVAL_SHIFT (20) -#define VIDINTCON0_FIFOINTERVAL_LIMIT (0x3f) +#define VIDINTCON0_FIFOINTERVAL_SHIFT 20 +#define VIDINTCON0_FIFOINTERVAL_LIMIT 0x3f #define VIDINTCON0_FIFOINTERVAL(_x) ((_x) << 20) #define VIDINTCON0_INT_SYSMAINCON (1 << 19) @@ -323,7 +320,7 @@ #define VIDINTCON0_INT_I80IFDONE (1 << 17) #define VIDINTCON0_FRAMESEL0_MASK (0x3 << 15) -#define VIDINTCON0_FRAMESEL0_SHIFT (15) +#define VIDINTCON0_FRAMESEL0_SHIFT 15 #define VIDINTCON0_FRAMESEL0_BACKPORCH (0x0 << 15) #define VIDINTCON0_FRAMESEL0_VSYNC (0x1 << 15) #define VIDINTCON0_FRAMESEL0_ACTIVE (0x2 << 15) @@ -338,7 +335,7 @@ #define VIDINTCON0_INT_FRAME (1 << 12) #define VIDINTCON0_FIFIOSEL_MASK (0x7f << 5) -#define VIDINTCON0_FIFIOSEL_SHIFT (5) +#define VIDINTCON0_FIFIOSEL_SHIFT 5 #define VIDINTCON0_FIFIOSEL_WINDOW0 (0x1 << 5) #define VIDINTCON0_FIFIOSEL_WINDOW1 (0x2 << 5) #define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5) @@ -346,7 +343,7 @@ #define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5) #define VIDINTCON0_FIFOLEVEL_MASK (0x7 << 2) -#define VIDINTCON0_FIFOLEVEL_SHIFT (2) +#define VIDINTCON0_FIFOLEVEL_SHIFT 2 #define VIDINTCON0_FIFOLEVEL_TO25PC (0x0 << 2) #define VIDINTCON0_FIFOLEVEL_TO50PC (0x1 << 2) #define VIDINTCON0_FIFOLEVEL_TO75PC (0x2 << 2) @@ -354,46 +351,46 @@ #define VIDINTCON0_FIFOLEVEL_FULL (0x4 << 2) #define VIDINTCON0_INT_FIFO_MASK (0x3 << 0) -#define VIDINTCON0_INT_FIFO_SHIFT (0) +#define VIDINTCON0_INT_FIFO_SHIFT 0 #define VIDINTCON0_INT_ENABLE (1 << 0) -#define VIDINTCON1 (0x134) +#define VIDINTCON1 0x134 #define VIDINTCON1_INT_I180 (1 << 2) #define VIDINTCON1_INT_FRAME (1 << 1) #define VIDINTCON1_INT_FIFO (1 << 0) /* Window colour-key control registers */ -#define WKEYCON (0x140) /* 6410,V210 */ +#define WKEYCON 0x140 -#define WKEYCON0 (0x00) -#define WKEYCON1 (0x04) +#define WKEYCON0 0x00 +#define WKEYCON1 0x04 #define WxKEYCON0_KEYBL_EN (1 << 26) #define WxKEYCON0_KEYEN_F (1 << 25) #define WxKEYCON0_DIRCON (1 << 24) #define WxKEYCON0_COMPKEY_MASK (0xffffff << 0) -#define WxKEYCON0_COMPKEY_SHIFT (0) -#define WxKEYCON0_COMPKEY_LIMIT (0xffffff) +#define WxKEYCON0_COMPKEY_SHIFT 0 +#define WxKEYCON0_COMPKEY_LIMIT 0xffffff #define WxKEYCON0_COMPKEY(_x) ((_x) << 0) #define WxKEYCON1_COLVAL_MASK (0xffffff << 0) -#define WxKEYCON1_COLVAL_SHIFT (0) -#define WxKEYCON1_COLVAL_LIMIT (0xffffff) +#define WxKEYCON1_COLVAL_SHIFT 0 +#define WxKEYCON1_COLVAL_LIMIT 0xffffff #define WxKEYCON1_COLVAL(_x) ((_x) << 0) /* Dithering control */ -#define DITHMODE (0x170) +#define DITHMODE 0x170 #define DITHMODE_R_POS_MASK (0x3 << 5) -#define DITHMODE_R_POS_SHIFT (5) +#define DITHMODE_R_POS_SHIFT 5 #define DITHMODE_R_POS_8BIT (0x0 << 5) #define DITHMODE_R_POS_6BIT (0x1 << 5) #define DITHMODE_R_POS_5BIT (0x2 << 5) #define DITHMODE_G_POS_MASK (0x3 << 3) -#define DITHMODE_G_POS_SHIFT (3) +#define DITHMODE_G_POS_SHIFT 3 #define DITHMODE_G_POS_8BIT (0x0 << 3) #define DITHMODE_G_POS_6BIT (0x1 << 3) #define DITHMODE_G_POS_5BIT (0x2 << 3) #define DITHMODE_B_POS_MASK (0x3 << 1) -#define DITHMODE_B_POS_SHIFT (1) +#define DITHMODE_B_POS_SHIFT 1 #define DITHMODE_B_POS_8BIT (0x0 << 1) #define DITHMODE_B_POS_6BIT (0x1 << 1) #define DITHMODE_B_POS_5BIT (0x2 << 1) @@ -403,18 +400,18 @@ #define WINxMAP(_win) (0x180 + ((_win) * 4)) #define WINxMAP_MAP (1 << 24) #define WINxMAP_MAP_COLOUR_MASK (0xffffff << 0) -#define WINxMAP_MAP_COLOUR_SHIFT (0) -#define WINxMAP_MAP_COLOUR_LIMIT (0xffffff) +#define WINxMAP_MAP_COLOUR_SHIFT 0 +#define WINxMAP_MAP_COLOUR_LIMIT 0xffffff #define WINxMAP_MAP_COLOUR(_x) ((_x) << 0) /* Winodw palette control */ -#define WPALCON (0x1A0) +#define WPALCON 0x1A0 #define WPALCON_PAL_UPDATE (1 << 9) #define WPALCON_W4PAL_16BPP_A555 (1 << 8) #define WPALCON_W3PAL_16BPP_A555 (1 << 7) #define WPALCON_W2PAL_16BPP_A555 (1 << 6) #define WPALCON_W1PAL_MASK (0x7 << 3) -#define WPALCON_W1PAL_SHIFT (3) +#define WPALCON_W1PAL_SHIFT 3 #define WPALCON_W1PAL_25BPP_A888 (0x0 << 3) #define WPALCON_W1PAL_24BPP (0x1 << 3) #define WPALCON_W1PAL_19BPP_A666 (0x2 << 3) @@ -423,7 +420,7 @@ #define WPALCON_W1PAL_16BPP_A555 (0x5 << 3) #define WPALCON_W1PAL_16BPP_565 (0x6 << 3) #define WPALCON_W0PAL_MASK (0x7 << 0) -#define WPALCON_W0PAL_SHIFT (0) +#define WPALCON_W0PAL_SHIFT 0 #define WPALCON_W0PAL_25BPP_A888 (0x0 << 0) #define WPALCON_W0PAL_24BPP (0x1 << 0) #define WPALCON_W0PAL_19BPP_A666 (0x2 << 0) @@ -433,13 +430,11 @@ #define WPALCON_W0PAL_16BPP_565 (0x6 << 0) /* Blending equation control */ -#define BLENDCON (0x260) +#define BLENDCON 0x260 #define BLENDCON_NEW_MASK (1 << 0) #define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0) #define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0) -#define S3C_FB_MAX_WIN (5) /* number of hardware windows available. */ - /* Notes on per-window bpp settings * * Value Win0 Win1 Win2 Win3 Win 4 @@ -462,8 +457,8 @@ */ /* FIMD Version 8 register offset definitions */ -#define FIMD_V8_VIDTCON0 (0x20010) -#define FIMD_V8_VIDTCON1 (0x20014) -#define FIMD_V8_VIDTCON2 (0x20018) -#define FIMD_V8_VIDTCON3 (0x2001C) -#define FIMD_V8_VIDCON1 (0x20004) +#define FIMD_V8_VIDTCON0 0x20010 +#define FIMD_V8_VIDTCON1 0x20014 +#define FIMD_V8_VIDTCON2 0x20018 +#define FIMD_V8_VIDTCON3 0x2001C +#define FIMD_V8_VIDCON1 0x20004 diff --git a/include/video/videomode.h b/include/video/videomode.h new file mode 100644 index 000000000000..a42156234dd4 --- /dev/null +++ b/include/video/videomode.h @@ -0,0 +1,48 @@ +/* + * Copyright 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de> + * + * generic videomode description + * + * This file is released under the GPLv2 + */ + +#ifndef __LINUX_VIDEOMODE_H +#define __LINUX_VIDEOMODE_H + +#include <linux/types.h> +#include <video/display_timing.h> + +/* + * Subsystem independent description of a videomode. + * Can be generated from struct display_timing. + */ +struct videomode { + unsigned long pixelclock; /* pixelclock in Hz */ + + u32 hactive; + u32 hfront_porch; + u32 hback_porch; + u32 hsync_len; + + u32 vactive; + u32 vfront_porch; + u32 vback_porch; + u32 vsync_len; + + unsigned int dmt_flags; /* VESA DMT flags */ + unsigned int data_flags; /* video data flags */ +}; + +/** + * videomode_from_timing - convert display timing to videomode + * @disp: structure with all possible timing entries + * @vm: return value + * @index: index into the list of display timings in devicetree + * + * DESCRIPTION: + * This function converts a struct display_timing to a struct videomode. + */ +int videomode_from_timing(const struct display_timings *disp, + struct videomode *vm, unsigned int index); + +#endif |
