diff options
Diffstat (limited to 'include/asm-blackfin/mach-bf533')
| -rw-r--r-- | include/asm-blackfin/mach-bf533/anomaly.h | 84 | ||||
| -rw-r--r-- | include/asm-blackfin/mach-bf533/bfin_serial_5xx.h | 2 | ||||
| -rw-r--r-- | include/asm-blackfin/mach-bf533/dma.h | 3 | ||||
| -rw-r--r-- | include/asm-blackfin/mach-bf533/portmux.h | 65 |
4 files changed, 148 insertions, 6 deletions
diff --git a/include/asm-blackfin/mach-bf533/anomaly.h b/include/asm-blackfin/mach-bf533/anomaly.h index a84d3909345e..7302f290b93d 100644 --- a/include/asm-blackfin/mach-bf533/anomaly.h +++ b/include/asm-blackfin/mach-bf533/anomaly.h @@ -43,7 +43,8 @@ #endif /* Issues that are common to 0.5, 0.4, and 0.3 silicon */ -#if (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3)) +#if (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_4) \ + || defined(CONFIG_BF_REV_0_3)) #define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in slot1 and store of a P register in slot 2 is not supported */ @@ -76,11 +77,16 @@ control */ #define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when killed in a particular stage*/ +#define ANOMALY_05000311 /* Erroneous flag pin operations under specific + sequences */ #define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC registers are interrupted */ -#define ANOMALY_05000311 /* Erroneous flag pin operations under specific sequences*/ - -#endif +#define ANOMALY_05000313 /* PPI Is Level-Sensitive on First Transfer */ +#define ANOMALY_05000315 /* Killed System MMR Write Completes Erroneously On + * Next System MMR Access */ +#define ANOMALY_05000319 /* Internal Voltage Regulator Values of 1.05V, 1.10V + * and 1.15V Not Allowed for LQFP Packages */ +#endif /* Issues that are common to 0.5, 0.4, and 0.3 silicon */ /* These issues only occur on 0.3 or 0.4 BF533 */ #if (defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3)) @@ -134,14 +140,14 @@ internal voltage regulator (VDDint) to increase. */ #define ANOMALY_05000270 /* High I/O activity causes the output voltage of the internal voltage regulator (VDDint) to decrease */ -#endif +#endif /* issues only occur on 0.3 or 0.4 BF533 */ /* These issues are only on 0.4 silicon */ #if (defined(CONFIG_BF_REV_0_4)) #define ANOMALY_05000234 /* Incorrect Revision Number in DSPID Register */ #define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel (TDM) */ -#endif +#endif /* issues are only on 0.4 silicon */ /* These issues are only on 0.3 silicon */ #if defined(CONFIG_BF_REV_0_3) @@ -170,6 +176,72 @@ #define ANOMALY_05000233 /* PPI_FS3 is not driven in 2 or 3 internal Frame Sync Transmit Mode */ #define ANOMALY_05000271 /* Spontaneous reset of Internal Voltage Regulator */ +#endif /* only on 0.3 silicon */ + +#if defined(CONFIG_BF_REV_0_2) +#define ANOMALY_05000067 /* Watchpoints (Hardware Breakpoints) are not + * supported */ +#define ANOMALY_05000109 /* Reserved bits in SYSCFG register not set at + * power on */ +#define ANOMALY_05000116 /* Trace Buffers may record discontinuities into + * emulation mode and/or exception, NMI, reset + * handlers */ +#define ANOMALY_05000123 /* DTEST_COMMAND initiated memory access may be + * incorrect if data cache or DMA is active */ +#define ANOMALY_05000124 /* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, + * or 1:1 */ +#define ANOMALY_05000125 /* Erroneous exception when enabling cache */ +#define ANOMALY_05000126 /* SPI clock polarity and phase bits incorrect + * during booting */ +#define ANOMALY_05000137 /* DMEM_CONTROL is not set on Reset */ +#define ANOMALY_05000138 /* SPI boot will not complete if there is a zero fill + * block in the loader file */ +#define ANOMALY_05000140 /* Allowing the SPORT RX FIFO to fill will cause an + * overflow */ +#define ANOMALY_05000141 /* An Infinite Stall occurs with a particular sequence + * of consecutive dual dag events */ +#define ANOMALY_05000142 /* Interrupts may be lost when a programmable input + * flag is configured to be edge sensitive */ +#define ANOMALY_05000143 /* A read from external memory may return a wrong + * value with data cache enabled */ +#define ANOMALY_05000144 /* DMA and TESTSET conflict when both are accessing + * external memory */ +#define ANOMALY_05000145 /* In PWM_OUT mode, you must enable the PPI block to + * generate a waveform from PPI_CLK */ +#define ANOMALY_05000146 /* MDMA may lose the first few words of a descriptor + * chain */ +#define ANOMALY_05000147 /* The source MDMA descriptor may stop with a DMA + * Error */ +#define ANOMALY_05000148 /* When booting from a 16-bit asynchronous memory + * device, the upper 8-bits of each word must be + * 0x00 */ +#define ANOMALY_05000153 /* Frame Delay in SPORT Multichannel Mode */ +#define ANOMALY_05000154 /* SPORT TFS signal is active in Multi-channel mode + * outside of valid channels */ +#define ANOMALY_05000155 /* Timer1 can not be used for PWMOUT mode when a + * certain PPI mode is in use */ +#define ANOMALY_05000157 /* A killed 32-bit System MMR write will lead to + * the next system MMR access thinking it should be + * 32-bit. */ +#define ANOMALY_05000163 /* SPORT transmit data is not gated by external frame + * sync in certain conditions */ +#define ANOMALY_05000168 /* SDRAM auto-refresh and subsequent Power Ups */ +#define ANOMALY_05000169 /* DATA CPLB page miss can result in lost + * write-through cache data writes */ +#define ANOMALY_05000173 /* DMA vs Core accesses to external memory */ +#define ANOMALY_05000174 /* Cache Fill Buffer Data lost */ +#define ANOMALY_05000175 /* Overlapping Sequencer and Memory Stalls */ +#define ANOMALY_05000176 /* Multiplication of (-1) by (-1) followed by an + * accumulator saturation */ +#define ANOMALY_05000181 /* Disabling the PPI resets the PPI configuration + * registers */ +#define ANOMALY_05000185 /* PPI TX Mode with 2 External Frame Syncs */ +#define ANOMALY_05000191 /* PPI does not invert the Driving PPICLK edge in + * Transmit Modes */ +#define ANOMALY_05000192 /* In PPI Transmit Modes with External Frame Syncs + * POLC */ +#define ANOMALY_05000206 /* Internal Voltage Regulator may not start up */ + #endif #endif /* _MACH_ANOMALY_H_ */ diff --git a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h index 23bf76aa3451..e043cafa3c42 100644 --- a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h @@ -78,6 +78,7 @@ struct bfin_serial_res { }; struct bfin_serial_res bfin_serial_resource[] = { + { 0xFFC00400, IRQ_UART_RX, #ifdef CONFIG_SERIAL_BFIN_DMA @@ -88,6 +89,7 @@ struct bfin_serial_res bfin_serial_resource[] = { CONFIG_UART0_CTS_PIN, CONFIG_UART0_RTS_PIN, #endif + } }; diff --git a/include/asm-blackfin/mach-bf533/dma.h b/include/asm-blackfin/mach-bf533/dma.h index bd9d5e94307d..16c672c01d80 100644 --- a/include/asm-blackfin/mach-bf533/dma.h +++ b/include/asm-blackfin/mach-bf533/dma.h @@ -51,4 +51,7 @@ #define CH_MEM_STREAM1_DEST 10 /* TX */ #define CH_MEM_STREAM1_SRC 11 /* RX */ +extern int channel2irq(unsigned int channel); +extern struct dma_register *base_addr[]; + #endif diff --git a/include/asm-blackfin/mach-bf533/portmux.h b/include/asm-blackfin/mach-bf533/portmux.h new file mode 100644 index 000000000000..b88d7a03ee3e --- /dev/null +++ b/include/asm-blackfin/mach-bf533/portmux.h @@ -0,0 +1,65 @@ +#ifndef _MACH_PORTMUX_H_ +#define _MACH_PORTMUX_H_ + +#define P_PPI0_CLK (P_DONTCARE) +#define P_PPI0_FS1 (P_DONTCARE) +#define P_PPI0_FS2 (P_DONTCARE) +#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF3)) +#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF4)) +#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF5)) +#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF6)) +#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF7)) +#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF8)) +#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF9)) +#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF10)) +#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF11)) +#define P_PPI0_D0 (P_DONTCARE) +#define P_PPI0_D1 (P_DONTCARE) +#define P_PPI0_D2 (P_DONTCARE) +#define P_PPI0_D3 (P_DONTCARE) +#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF15)) +#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF14)) +#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF13)) +#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF12)) + +#define P_SPORT1_TSCLK (P_DONTCARE) +#define P_SPORT1_RSCLK (P_DONTCARE) +#define P_SPORT0_TSCLK (P_DONTCARE) +#define P_SPORT0_RSCLK (P_DONTCARE) +#define P_UART0_RX (P_DONTCARE) +#define P_UART0_TX (P_DONTCARE) +#define P_SPORT1_DRSEC (P_DONTCARE) +#define P_SPORT1_RFS (P_DONTCARE) +#define P_SPORT1_DTPRI (P_DONTCARE) +#define P_SPORT1_DTSEC (P_DONTCARE) +#define P_SPORT1_TFS (P_DONTCARE) +#define P_SPORT1_DRPRI (P_DONTCARE) +#define P_SPORT0_DRSEC (P_DONTCARE) +#define P_SPORT0_RFS (P_DONTCARE) +#define P_SPORT0_DTPRI (P_DONTCARE) +#define P_SPORT0_DTSEC (P_DONTCARE) +#define P_SPORT0_TFS (P_DONTCARE) +#define P_SPORT0_DRPRI (P_DONTCARE) + +#define P_SPI0_MOSI (P_DONTCARE) +#define P_SPI0_MIS0 (P_DONTCARE) +#define P_SPI0_SCK (P_DONTCARE) +#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7)) +#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6)) +#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5)) +#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4)) +#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3)) +#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2)) +#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1)) +#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0)) + +#define P_TMR2 (P_DONTCARE) +#define P_TMR1 (P_DONTCARE) +#define P_TMR0 (P_DONTCARE) +#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF1)) + + + + + +#endif /* _MACH_PORTMUX_H_ */ |
