diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/net/arm/ks8695net.c | 2 | ||||
-rw-r--r-- | drivers/net/atlx/atl1.c | 2 | ||||
-rw-r--r-- | drivers/net/bnx2.h | 12 | ||||
-rw-r--r-- | drivers/net/sky2.c | 2 | ||||
-rw-r--r-- | drivers/net/wireless/rtlwifi/pci.c | 6 | ||||
-rw-r--r-- | drivers/tty/serial/mrst_max3110.c | 2 | ||||
-rw-r--r-- | drivers/usb/gadget/langwell_udc.c | 2 | ||||
-rw-r--r-- | drivers/usb/gadget/net2280.c | 2 | ||||
-rw-r--r-- | drivers/usb/musb/musb_gadget.c | 2 |
9 files changed, 16 insertions, 16 deletions
diff --git a/drivers/net/arm/ks8695net.c b/drivers/net/arm/ks8695net.c index c827a6097d02..8d0baeceaaa3 100644 --- a/drivers/net/arm/ks8695net.c +++ b/drivers/net/arm/ks8695net.c @@ -414,7 +414,7 @@ ks8695_tx_irq(int irq, void *dev_id) * Interrupt Status Register (Offset 0xF208) * Bit29: WAN MAC Receive Status * Bit16: LAN MAC Receive Status - * So, this Rx interrrupt enable/status bit number is equal + * So, this Rx interrupt enable/status bit number is equal * as Rx IRQ number. */ static inline u32 ks8695_get_rx_enable_bit(struct ks8695_priv *ksp) diff --git a/drivers/net/atlx/atl1.c b/drivers/net/atlx/atl1.c index 6f0e9403004b..c346e65e51ef 100644 --- a/drivers/net/atlx/atl1.c +++ b/drivers/net/atlx/atl1.c @@ -858,7 +858,7 @@ static s32 atl1_init_hw(struct atl1_hw *hw) atl1_init_flash_opcode(hw); if (!hw->phy_configured) { - /* enable GPHY LinkChange Interrrupt */ + /* enable GPHY LinkChange Interrupt */ ret_val = atl1_write_phy_reg(hw, 18, 0xC00); if (ret_val) return ret_val; diff --git a/drivers/net/bnx2.h b/drivers/net/bnx2.h index fc50d4267df8..99d31a7d6aaa 100644 --- a/drivers/net/bnx2.h +++ b/drivers/net/bnx2.h @@ -5617,7 +5617,7 @@ struct l2_fhdr { #define BNX2_TXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) #define BNX2_TXP_CPU_STATE_SOFT_HALTED (1L<<10) #define BNX2_TXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) -#define BNX2_TXP_CPU_STATE_INTERRRUPT (1L<<12) +#define BNX2_TXP_CPU_STATE_INTERRUPT (1L<<12) #define BNX2_TXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) #define BNX2_TXP_CPU_STATE_INST_FETCH_STALL (1L<<15) #define BNX2_TXP_CPU_STATE_BLOCKED_READ (1L<<31) @@ -5712,7 +5712,7 @@ struct l2_fhdr { #define BNX2_TPAT_CPU_STATE_FIO_ABORT_HALTED (1L<<8) #define BNX2_TPAT_CPU_STATE_SOFT_HALTED (1L<<10) #define BNX2_TPAT_CPU_STATE_SPAD_UNDERFLOW (1L<<11) -#define BNX2_TPAT_CPU_STATE_INTERRRUPT (1L<<12) +#define BNX2_TPAT_CPU_STATE_INTERRUPT (1L<<12) #define BNX2_TPAT_CPU_STATE_DATA_ACCESS_STALL (1L<<14) #define BNX2_TPAT_CPU_STATE_INST_FETCH_STALL (1L<<15) #define BNX2_TPAT_CPU_STATE_BLOCKED_READ (1L<<31) @@ -5807,7 +5807,7 @@ struct l2_fhdr { #define BNX2_RXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) #define BNX2_RXP_CPU_STATE_SOFT_HALTED (1L<<10) #define BNX2_RXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) -#define BNX2_RXP_CPU_STATE_INTERRRUPT (1L<<12) +#define BNX2_RXP_CPU_STATE_INTERRUPT (1L<<12) #define BNX2_RXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) #define BNX2_RXP_CPU_STATE_INST_FETCH_STALL (1L<<15) #define BNX2_RXP_CPU_STATE_BLOCKED_READ (1L<<31) @@ -5953,7 +5953,7 @@ struct l2_fhdr { #define BNX2_COM_CPU_STATE_FIO_ABORT_HALTED (1L<<8) #define BNX2_COM_CPU_STATE_SOFT_HALTED (1L<<10) #define BNX2_COM_CPU_STATE_SPAD_UNDERFLOW (1L<<11) -#define BNX2_COM_CPU_STATE_INTERRRUPT (1L<<12) +#define BNX2_COM_CPU_STATE_INTERRUPT (1L<<12) #define BNX2_COM_CPU_STATE_DATA_ACCESS_STALL (1L<<14) #define BNX2_COM_CPU_STATE_INST_FETCH_STALL (1L<<15) #define BNX2_COM_CPU_STATE_BLOCKED_READ (1L<<31) @@ -6119,7 +6119,7 @@ struct l2_fhdr { #define BNX2_CP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) #define BNX2_CP_CPU_STATE_SOFT_HALTED (1L<<10) #define BNX2_CP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) -#define BNX2_CP_CPU_STATE_INTERRRUPT (1L<<12) +#define BNX2_CP_CPU_STATE_INTERRUPT (1L<<12) #define BNX2_CP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) #define BNX2_CP_CPU_STATE_INST_FETCH_STALL (1L<<15) #define BNX2_CP_CPU_STATE_BLOCKED_READ (1L<<31) @@ -6291,7 +6291,7 @@ struct l2_fhdr { #define BNX2_MCP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) #define BNX2_MCP_CPU_STATE_SOFT_HALTED (1L<<10) #define BNX2_MCP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) -#define BNX2_MCP_CPU_STATE_INTERRRUPT (1L<<12) +#define BNX2_MCP_CPU_STATE_INTERRUPT (1L<<12) #define BNX2_MCP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) #define BNX2_MCP_CPU_STATE_INST_FETCH_STALL (1L<<15) #define BNX2_MCP_CPU_STATE_BLOCKED_READ (1L<<31) diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c index 57339da76326..d7f879dfb1c9 100644 --- a/drivers/net/sky2.c +++ b/drivers/net/sky2.c @@ -2057,7 +2057,7 @@ static void sky2_hw_down(struct sky2_port *sky2) sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); - /* Force any delayed status interrrupt and NAPI */ + /* Force any delayed status interrupt and NAPI */ sky2_write32(hw, STAT_LEV_TIMER_CNT, 0); sky2_write32(hw, STAT_TX_TIMER_CNT, 0); sky2_write32(hw, STAT_ISR_TIMER_CNT, 0); diff --git a/drivers/net/wireless/rtlwifi/pci.c b/drivers/net/wireless/rtlwifi/pci.c index 5efd57833489..c1ea65e5d036 100644 --- a/drivers/net/wireless/rtlwifi/pci.c +++ b/drivers/net/wireless/rtlwifi/pci.c @@ -488,7 +488,7 @@ static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw) struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); struct sk_buff *skb = NULL; struct ieee80211_tx_info *info = NULL; - int tid; /* should be int */ + int tid; if (!rtlpriv->rtlhal.earlymode_enable) return; @@ -1538,7 +1538,7 @@ static int rtl_pci_start(struct ieee80211_hw *hw) rtl_init_rx_config(hw); - /*should after adapter start and interrupt enable. */ + /*should be after adapter start and interrupt enable. */ set_hal_start(rtlhal); RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); @@ -1559,7 +1559,7 @@ static void rtl_pci_stop(struct ieee80211_hw *hw) u8 RFInProgressTimeOut = 0; /* - *should before disable interrrupt&adapter + *should be before disable interrupt&adapter *and will do it immediately. */ set_hal_stop(rtlhal); diff --git a/drivers/tty/serial/mrst_max3110.c b/drivers/tty/serial/mrst_max3110.c index a764bf99743b..fbd9261a0c2c 100644 --- a/drivers/tty/serial/mrst_max3110.c +++ b/drivers/tty/serial/mrst_max3110.c @@ -23,7 +23,7 @@ * 1 word. If SPI master controller doesn't support sclk frequency change, * then the char need be sent out one by one with some delay * - * 2. Currently only RX available interrrupt is used, no need for waiting TXE + * 2. Currently only RX available interrupt is used, no need for waiting TXE * interrupt for a low speed UART device */ diff --git a/drivers/usb/gadget/langwell_udc.c b/drivers/usb/gadget/langwell_udc.c index a06e2c27b435..ff4d40d77c30 100644 --- a/drivers/usb/gadget/langwell_udc.c +++ b/drivers/usb/gadget/langwell_udc.c @@ -2969,7 +2969,7 @@ static irqreturn_t langwell_irq(int irq, void *_dev) handle_port_change(dev); } - /* suspend interrrupt */ + /* suspend interrupt */ if (irq_sts & STS_SLI) { dev_vdbg(&dev->pdev->dev, "suspend interrupt\n"); handle_bus_suspend(dev); diff --git a/drivers/usb/gadget/net2280.c b/drivers/usb/gadget/net2280.c index 3dd40b4e675c..a218a4de5dc9 100644 --- a/drivers/usb/gadget/net2280.c +++ b/drivers/usb/gadget/net2280.c @@ -2481,7 +2481,7 @@ static void handle_stat1_irqs (struct net2280 *dev, u32 stat) mask = (1 << HIGH_SPEED) | (1 << FULL_SPEED); /* VBUS disconnect is indicated by VBUS_PIN and VBUS_INTERRUPT set. - * Root Port Reset is indicated by ROOT_PORT_RESET_INTERRRUPT set and + * Root Port Reset is indicated by ROOT_PORT_RESET_INTERRUPT set and * both HIGH_SPEED and FULL_SPEED clear (as ROOT_PORT_RESET_INTERRUPT * only indicates a change in the reset state). */ diff --git a/drivers/usb/musb/musb_gadget.c b/drivers/usb/musb/musb_gadget.c index b67a062f556b..95a67fea393b 100644 --- a/drivers/usb/musb/musb_gadget.c +++ b/drivers/usb/musb/musb_gadget.c @@ -704,7 +704,7 @@ static void rxstate(struct musb *musb, struct musb_request *req) * most these gadgets, end of is signified either by a short packet, * or filling the last byte of the buffer. (Sending extra data in * that last pckate should trigger an overflow fault.) But in mode 1, - * we don't get DMA completion interrrupt for short packets. + * we don't get DMA completion interrupt for short packets. * * Theoretically, we could enable DMAReq irq (MUSB_RXCSR_DMAMODE = 1), * to get endpoint interrupt on every DMA req, but that didn't seem |