diff options
Diffstat (limited to 'drivers/net/ethernet/brocade')
| -rw-r--r-- | drivers/net/ethernet/brocade/bna/bfi_ll.h | 438 | ||||
| -rw-r--r-- | drivers/net/ethernet/brocade/bna/bna.h | 1 | ||||
| -rw-r--r-- | drivers/net/ethernet/brocade/bna/bna_ctrl.c | 3078 | ||||
| -rw-r--r-- | drivers/net/ethernet/brocade/bna/bna_hw.h | 1492 | ||||
| -rw-r--r-- | drivers/net/ethernet/brocade/bna/bna_txrx.c | 4185 |
5 files changed, 0 insertions, 9194 deletions
diff --git a/drivers/net/ethernet/brocade/bna/bfi_ll.h b/drivers/net/ethernet/brocade/bna/bfi_ll.h deleted file mode 100644 index bee4d054066a..000000000000 --- a/drivers/net/ethernet/brocade/bna/bfi_ll.h +++ /dev/null @@ -1,438 +0,0 @@ -/* - * Linux network driver for Brocade Converged Network Adapter. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License (GPL) Version 2 as - * published by the Free Software Foundation - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - */ -/* - * Copyright (c) 2005-2010 Brocade Communications Systems, Inc. - * All rights reserved - * www.brocade.com - */ -#ifndef __BFI_LL_H__ -#define __BFI_LL_H__ - -#include "bfi.h" - -#pragma pack(1) - -/** - * @brief - * "enums" for all LL mailbox messages other than IOC - */ -enum { - BFI_LL_H2I_MAC_UCAST_SET_REQ = 1, - BFI_LL_H2I_MAC_UCAST_ADD_REQ = 2, - BFI_LL_H2I_MAC_UCAST_DEL_REQ = 3, - - BFI_LL_H2I_MAC_MCAST_ADD_REQ = 4, - BFI_LL_H2I_MAC_MCAST_DEL_REQ = 5, - BFI_LL_H2I_MAC_MCAST_FILTER_REQ = 6, - BFI_LL_H2I_MAC_MCAST_DEL_ALL_REQ = 7, - - BFI_LL_H2I_PORT_ADMIN_REQ = 8, - BFI_LL_H2I_STATS_GET_REQ = 9, - BFI_LL_H2I_STATS_CLEAR_REQ = 10, - - BFI_LL_H2I_RXF_PROMISCUOUS_SET_REQ = 11, - BFI_LL_H2I_RXF_DEFAULT_SET_REQ = 12, - - BFI_LL_H2I_TXQ_STOP_REQ = 13, - BFI_LL_H2I_RXQ_STOP_REQ = 14, - - BFI_LL_H2I_DIAG_LOOPBACK_REQ = 15, - - BFI_LL_H2I_SET_PAUSE_REQ = 16, - BFI_LL_H2I_MTU_INFO_REQ = 17, - - BFI_LL_H2I_RX_REQ = 18, -} ; - -enum { - BFI_LL_I2H_MAC_UCAST_SET_RSP = BFA_I2HM(1), - BFI_LL_I2H_MAC_UCAST_ADD_RSP = BFA_I2HM(2), - BFI_LL_I2H_MAC_UCAST_DEL_RSP = BFA_I2HM(3), - - BFI_LL_I2H_MAC_MCAST_ADD_RSP = BFA_I2HM(4), - BFI_LL_I2H_MAC_MCAST_DEL_RSP = BFA_I2HM(5), - BFI_LL_I2H_MAC_MCAST_FILTER_RSP = BFA_I2HM(6), - BFI_LL_I2H_MAC_MCAST_DEL_ALL_RSP = BFA_I2HM(7), - - BFI_LL_I2H_PORT_ADMIN_RSP = BFA_I2HM(8), - BFI_LL_I2H_STATS_GET_RSP = BFA_I2HM(9), - BFI_LL_I2H_STATS_CLEAR_RSP = BFA_I2HM(10), - - BFI_LL_I2H_RXF_PROMISCUOUS_SET_RSP = BFA_I2HM(11), - BFI_LL_I2H_RXF_DEFAULT_SET_RSP = BFA_I2HM(12), - - BFI_LL_I2H_TXQ_STOP_RSP = BFA_I2HM(13), - BFI_LL_I2H_RXQ_STOP_RSP = BFA_I2HM(14), - - BFI_LL_I2H_DIAG_LOOPBACK_RSP = BFA_I2HM(15), - - BFI_LL_I2H_SET_PAUSE_RSP = BFA_I2HM(16), - - BFI_LL_I2H_MTU_INFO_RSP = BFA_I2HM(17), - BFI_LL_I2H_RX_RSP = BFA_I2HM(18), - - BFI_LL_I2H_LINK_DOWN_AEN = BFA_I2HM(19), - BFI_LL_I2H_LINK_UP_AEN = BFA_I2HM(20), - - BFI_LL_I2H_PORT_ENABLE_AEN = BFA_I2HM(21), - BFI_LL_I2H_PORT_DISABLE_AEN = BFA_I2HM(22), -} ; - -/** - * @brief bfi_ll_mac_addr_req is used by: - * BFI_LL_H2I_MAC_UCAST_SET_REQ - * BFI_LL_H2I_MAC_UCAST_ADD_REQ - * BFI_LL_H2I_MAC_UCAST_DEL_REQ - * BFI_LL_H2I_MAC_MCAST_ADD_REQ - * BFI_LL_H2I_MAC_MCAST_DEL_REQ - */ -struct bfi_ll_mac_addr_req { - struct bfi_mhdr mh; /*!< common msg header */ - u8 rxf_id; - u8 rsvd1[3]; - mac_t mac_addr; - u8 rsvd2[2]; -}; - -/** - * @brief bfi_ll_mcast_filter_req is used by: - * BFI_LL_H2I_MAC_MCAST_FILTER_REQ - */ -struct bfi_ll_mcast_filter_req { - struct bfi_mhdr mh; /*!< common msg header */ - u8 rxf_id; - u8 enable; - u8 rsvd[2]; -}; - -/** - * @brief bfi_ll_mcast_del_all is used by: - * BFI_LL_H2I_MAC_MCAST_DEL_ALL_REQ - */ -struct bfi_ll_mcast_del_all_req { - struct bfi_mhdr mh; /*!< common msg header */ - u8 rxf_id; - u8 rsvd[3]; -}; - -/** - * @brief bfi_ll_q_stop_req is used by: - * BFI_LL_H2I_TXQ_STOP_REQ - * BFI_LL_H2I_RXQ_STOP_REQ - */ -struct bfi_ll_q_stop_req { - struct bfi_mhdr mh; /*!< common msg header */ - u32 q_id_mask[2]; /* !< bit-mask for queue ids */ -}; - -/** - * @brief bfi_ll_stats_req is used by: - * BFI_LL_I2H_STATS_GET_REQ - * BFI_LL_I2H_STATS_CLEAR_REQ - */ -struct bfi_ll_stats_req { - struct bfi_mhdr mh; /*!< common msg header */ - u16 stats_mask; /* !< bit-mask for non-function statistics */ - u8 rsvd[2]; - u32 rxf_id_mask[2]; /* !< bit-mask for RxF Statistics */ - u32 txf_id_mask[2]; /* !< bit-mask for TxF Statistics */ - union bfi_addr_u host_buffer; /* !< where statistics are returned */ -}; - -/** - * @brief defines for "stats_mask" above. - */ -#define BFI_LL_STATS_MAC (1 << 0) /* !< MAC Statistics */ -#define BFI_LL_STATS_BPC (1 << 1) /* !< Pause Stats from BPC */ -#define BFI_LL_STATS_RAD (1 << 2) /* !< Rx Admission Statistics */ -#define BFI_LL_STATS_RX_FC (1 << 3) /* !< Rx FC Stats from RxA */ -#define BFI_LL_STATS_TX_FC (1 << 4) /* !< Tx FC Stats from TxA */ - -#define BFI_LL_STATS_ALL 0x1f - -/** - * @brief bfi_ll_port_admin_req - */ -struct bfi_ll_port_admin_req { - struct bfi_mhdr mh; /*!< common msg header */ - u8 up; - u8 rsvd[3]; -}; - -/** - * @brief bfi_ll_rxf_req is used by: - * BFI_LL_H2I_RXF_PROMISCUOUS_SET_REQ - * BFI_LL_H2I_RXF_DEFAULT_SET_REQ - */ -struct bfi_ll_rxf_req { - struct bfi_mhdr mh; /*!< common msg header */ - u8 rxf_id; - u8 enable; - u8 rsvd[2]; -}; - -/** - * @brief bfi_ll_rxf_multi_req is used by: - * BFI_LL_H2I_RX_REQ - */ -struct bfi_ll_rxf_multi_req { - struct bfi_mhdr mh; /*!< common msg header */ - u32 rxf_id_mask[2]; - u8 enable; - u8 rsvd[3]; -}; - -/** - * @brief enum for Loopback opmodes - */ -enum { - BFI_LL_DIAG_LB_OPMODE_EXT = 0, - BFI_LL_DIAG_LB_OPMODE_CBL = 1, -}; - -/** - * @brief bfi_ll_set_pause_req is used by: - * BFI_LL_H2I_SET_PAUSE_REQ - */ -struct bfi_ll_set_pause_req { - struct bfi_mhdr mh; - u8 tx_pause; /* 1 = enable, 0 = disable */ - u8 rx_pause; /* 1 = enable, 0 = disable */ - u8 rsvd[2]; -}; - -/** - * @brief bfi_ll_mtu_info_req is used by: - * BFI_LL_H2I_MTU_INFO_REQ - */ -struct bfi_ll_mtu_info_req { - struct bfi_mhdr mh; - u16 mtu; - u8 rsvd[2]; -}; - -/** - * @brief - * Response header format used by all responses - * For both responses and asynchronous notifications - */ -struct bfi_ll_rsp { - struct bfi_mhdr mh; /*!< common msg header */ - u8 error; - u8 rsvd[3]; -}; - -/** - * @brief bfi_ll_cee_aen is used by: - * BFI_LL_I2H_LINK_DOWN_AEN - * BFI_LL_I2H_LINK_UP_AEN - */ -struct bfi_ll_aen { - struct bfi_mhdr mh; /*!< common msg header */ - u32 reason; - u8 cee_linkup; - u8 prio_map; /*!< LL priority bit-map */ - u8 rsvd[2]; -}; - -/** - * @brief - * The following error codes can be returned - * by the mbox commands - */ -enum { - BFI_LL_CMD_OK = 0, - BFI_LL_CMD_FAIL = 1, - BFI_LL_CMD_DUP_ENTRY = 2, /* !< Duplicate entry in CAM */ - BFI_LL_CMD_CAM_FULL = 3, /* !< CAM is full */ - BFI_LL_CMD_NOT_OWNER = 4, /* !< Not permitted, b'cos not owner */ - BFI_LL_CMD_NOT_EXEC = 5, /* !< Was not sent to f/w at all */ - BFI_LL_CMD_WAITING = 6, /* !< Waiting for completion (VMware) */ - BFI_LL_CMD_PORT_DISABLED = 7, /* !< port in disabled state */ -} ; - -/* Statistics */ -#define BFI_LL_TXF_ID_MAX 64 -#define BFI_LL_RXF_ID_MAX 64 - -/* TxF Frame Statistics */ -struct bfi_ll_stats_txf { - u64 ucast_octets; - u64 ucast; - u64 ucast_vlan; - - u64 mcast_octets; - u64 mcast; - u64 mcast_vlan; - - u64 bcast_octets; - u64 bcast; - u64 bcast_vlan; - - u64 errors; - u64 filter_vlan; /* frames filtered due to VLAN */ - u64 filter_mac_sa; /* frames filtered due to SA check */ -}; - -/* RxF Frame Statistics */ -struct bfi_ll_stats_rxf { - u64 ucast_octets; - u64 ucast; - u64 ucast_vlan; - - u64 mcast_octets; - u64 mcast; - u64 mcast_vlan; - - u64 bcast_octets; - u64 bcast; - u64 bcast_vlan; - u64 frame_drops; -}; - -/* FC Tx Frame Statistics */ -struct bfi_ll_stats_fc_tx { - u64 txf_ucast_octets; - u64 txf_ucast; - u64 txf_ucast_vlan; - - u64 txf_mcast_octets; - u64 txf_mcast; - u64 txf_mcast_vlan; - - u64 txf_bcast_octets; - u64 txf_bcast; - u64 txf_bcast_vlan; - - u64 txf_parity_errors; - u64 txf_timeout; - u64 txf_fid_parity_errors; -}; - -/* FC Rx Frame Statistics */ -struct bfi_ll_stats_fc_rx { - u64 rxf_ucast_octets; - u64 rxf_ucast; - u64 rxf_ucast_vlan; - - u64 rxf_mcast_octets; - u64 rxf_mcast; - u64 rxf_mcast_vlan; - - u64 rxf_bcast_octets; - u64 rxf_bcast; - u64 rxf_bcast_vlan; -}; - -/* RAD Frame Statistics */ -struct bfi_ll_stats_rad { - u64 rx_frames; - u64 rx_octets; - u64 rx_vlan_frames; - - u64 rx_ucast; - u64 rx_ucast_octets; - u64 rx_ucast_vlan; - - u64 rx_mcast; - u64 rx_mcast_octets; - u64 rx_mcast_vlan; - - u64 rx_bcast; - u64 rx_bcast_octets; - u64 rx_bcast_vlan; - - u64 rx_drops; -}; - -/* BPC Tx Registers */ -struct bfi_ll_stats_bpc { - /* transmit stats */ - u64 tx_pause[8]; - u64 tx_zero_pause[8]; /*!< Pause cancellation */ - /*!<Pause initiation rather than retention */ - u64 tx_first_pause[8]; - - /* receive stats */ - u64 rx_pause[8]; - u64 rx_zero_pause[8]; /*!< Pause cancellation */ - /*!<Pause initiation rather than retention */ - u64 rx_first_pause[8]; -}; - -/* MAC Rx Statistics */ -struct bfi_ll_stats_mac { - u64 frame_64; /* both rx and tx counter */ - u64 frame_65_127; /* both rx and tx counter */ - u64 frame_128_255; /* both rx and tx counter */ - u64 frame_256_511; /* both rx and tx counter */ - u64 frame_512_1023; /* both rx and tx counter */ - u64 frame_1024_1518; /* both rx and tx counter */ - u64 frame_1519_1522; /* both rx and tx counter */ - - /* receive stats */ - u64 rx_bytes; - u64 rx_packets; - u64 rx_fcs_error; - u64 rx_multicast; - u64 rx_broadcast; - u64 rx_control_frames; - u64 rx_pause; - u64 rx_unknown_opcode; - u64 rx_alignment_error; - u64 rx_frame_length_error; - u64 rx_code_error; - u64 rx_carrier_sense_error; - u64 rx_undersize; - u64 rx_oversize; - u64 rx_fragments; - u64 rx_jabber; - u64 rx_drop; - - /* transmit stats */ - u64 tx_bytes; - u64 tx_packets; - u64 tx_multicast; - u64 tx_broadcast; - u64 tx_pause; - u64 tx_deferral; - u64 tx_excessive_deferral; - u64 tx_single_collision; - u64 tx_muliple_collision; - u64 tx_late_collision; - u64 tx_excessive_collision; - u64 tx_total_collision; - u64 tx_pause_honored; - u64 tx_drop; - u64 tx_jabber; - u64 tx_fcs_error; - u64 tx_control_frame; - u64 tx_oversize; - u64 tx_undersize; - u64 tx_fragments; -}; - -/* Complete statistics */ -struct bfi_ll_stats { - struct bfi_ll_stats_mac mac_stats; - struct bfi_ll_stats_bpc bpc_stats; - struct bfi_ll_stats_rad rad_stats; - struct bfi_ll_stats_fc_rx fc_rx_stats; - struct bfi_ll_stats_fc_tx fc_tx_stats; - struct bfi_ll_stats_rxf rxf_stats[BFI_LL_RXF_ID_MAX]; - struct bfi_ll_stats_txf txf_stats[BFI_LL_TXF_ID_MAX]; -}; - -#pragma pack() - -#endif /* __BFI_LL_H__ */ diff --git a/drivers/net/ethernet/brocade/bna/bna.h b/drivers/net/ethernet/brocade/bna/bna.h index 1f1fa936894c..2a587c5fdc20 100644 --- a/drivers/net/ethernet/brocade/bna/bna.h +++ b/drivers/net/ethernet/brocade/bna/bna.h @@ -16,7 +16,6 @@ #include "bfa_cs.h" #include "bfa_ioc.h" #include "cna.h" -#include "bfi_ll.h" #include "bna_types.h" extern const u32 bna_napi_dim_vector[][BNA_BIAS_T_MAX]; diff --git a/drivers/net/ethernet/brocade/bna/bna_ctrl.c b/drivers/net/ethernet/brocade/bna/bna_ctrl.c deleted file mode 100644 index 7d9551778274..000000000000 --- a/drivers/net/ethernet/brocade/bna/bna_ctrl.c +++ /dev/null @@ -1,3078 +0,0 @@ -/* - * Linux network driver for Brocade Converged Network Adapter. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License (GPL) Version 2 as - * published by the Free Software Foundation - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - */ -/* - * Copyright (c) 2005-2010 Brocade Communications Systems, Inc. - * All rights reserved - * www.brocade.com - */ -#include "bna.h" -#include "bfa_cs.h" - -static void bna_device_cb_port_stopped(void *arg, enum bna_cb_status status); - -static void -bna_port_cb_link_up(struct bna_port *port, struct bfi_ll_aen *aen, - int status) -{ - int i; - u8 prio_map; - - port->llport.link_status = BNA_LINK_UP; - if (aen->cee_linkup) - port->llport.link_status = BNA_CEE_UP; - - /* Compute the priority */ - prio_map = aen->prio_map; - if (prio_map) { - for (i = 0; i < 8; i++) { - if ((prio_map >> i) & 0x1) - break; - } - port->priority = i; - } else - port->priority = 0; - - /* Dispatch events */ - bna_tx_mod_cee_link_status(&port->bna->tx_mod, aen->cee_linkup); - bna_tx_mod_prio_changed(&port->bna->tx_mod, port->priority); - port->link_cbfn(port->bna->bnad, port->llport.link_status); -} - -static void -bna_port_cb_link_down(struct bna_port *port, int status) -{ - port->llport.link_status = BNA_LINK_DOWN; - - /* Dispatch events */ - bna_tx_mod_cee_link_status(&port->bna->tx_mod, BNA_LINK_DOWN); - port->link_cbfn(port->bna->bnad, BNA_LINK_DOWN); -} - -static inline int -llport_can_be_up(struct bna_llport *llport) -{ - int ready = 0; - if (llport->type == BNA_PORT_T_REGULAR) - ready = ((llport->flags & BNA_LLPORT_F_ADMIN_UP) && - (llport->flags & BNA_LLPORT_F_RX_STARTED) && - (llport->flags & BNA_LLPORT_F_PORT_ENABLED)); - else - ready = ((llport->flags & BNA_LLPORT_F_ADMIN_UP) && - (llport->flags & BNA_LLPORT_F_RX_STARTED) && - !(llport->flags & BNA_LLPORT_F_PORT_ENABLED)); - return ready; -} - -#define llport_is_up llport_can_be_up - -enum bna_llport_event { - LLPORT_E_START = 1, - LLPORT_E_STOP = 2, - LLPORT_E_FAIL = 3, - LLPORT_E_UP = 4, - LLPORT_E_DOWN = 5, - LLPORT_E_FWRESP_UP_OK = 6, - LLPORT_E_FWRESP_UP_FAIL = 7, - LLPORT_E_FWRESP_DOWN = 8 -}; - -static void -bna_llport_cb_port_enabled(struct bna_llport *llport) -{ - llport->flags |= BNA_LLPORT_F_PORT_ENABLED; - - if (llport_can_be_up(llport)) - bfa_fsm_send_event(llport, LLPORT_E_UP); -} - -static void -bna_llport_cb_port_disabled(struct bna_llport *llport) -{ - int llport_up = llport_is_up(llport); - - llport->flags &= ~BNA_LLPORT_F_PORT_ENABLED; - - if (llport_up) - bfa_fsm_send_event(llport, LLPORT_E_DOWN); -} - -/** - * MBOX - */ -static int -bna_is_aen(u8 msg_id) -{ - switch (msg_id) { - case BFI_LL_I2H_LINK_DOWN_AEN: - case BFI_LL_I2H_LINK_UP_AEN: - case BFI_LL_I2H_PORT_ENABLE_AEN: - case BFI_LL_I2H_PORT_DISABLE_AEN: - return 1; - - default: - return 0; - } -} - -static void -bna_mbox_aen_callback(struct bna *bna, struct bfi_mbmsg *msg) -{ - struct bfi_ll_aen *aen = (struct bfi_ll_aen *)(msg); - - switch (aen->mh.msg_id) { - case BFI_LL_I2H_LINK_UP_AEN: - bna_port_cb_link_up(&bna->port, aen, aen->reason); - break; - case BFI_LL_I2H_LINK_DOWN_AEN: - bna_port_cb_link_down(&bna->port, aen->reason); - break; - case BFI_LL_I2H_PORT_ENABLE_AEN: - bna_llport_cb_port_enabled(&bna->port.llport); - break; - case BFI_LL_I2H_PORT_DISABLE_AEN: - bna_llport_cb_port_disabled(&bna->port.llport); - break; - default: - break; - } -} - -static void -bna_ll_isr(void *llarg, struct bfi_mbmsg *msg) -{ - struct bna *bna = (struct bna *)(llarg); - struct bfi_ll_rsp *mb_rsp = (struct bfi_ll_rsp *)(msg); - struct bfi_mhdr *cmd_h, *rsp_h; - struct bna_mbox_qe *mb_qe = NULL; - int to_post = 0; - u8 aen = 0; - char message[BNA_MESSAGE_SIZE]; - - aen = bna_is_aen(mb_rsp->mh.msg_id); - - if (!aen) { - mb_qe = bfa_q_first(&bna->mbox_mod.posted_q); - cmd_h = (struct bfi_mhdr *)(&mb_qe->cmd.msg[0]); - rsp_h = (struct bfi_mhdr *)(&mb_rsp->mh); - - if ((BFA_I2HM(cmd_h->msg_id) == rsp_h->msg_id) && - (cmd_h->mtag.i2htok == rsp_h->mtag.i2htok)) { - /* Remove the request from posted_q, update state */ - list_del(&mb_qe->qe); - bna->mbox_mod.msg_pending--; - if (list_empty(&bna->mbox_mod.posted_q)) - bna->mbox_mod.state = BNA_MBOX_FREE; - else - to_post = 1; - - /* Dispatch the cbfn */ - if (mb_qe->cbfn) - mb_qe->cbfn(mb_qe->cbarg, mb_rsp->error); - - /* Post the next entry, if needed */ - if (to_post) { - mb_qe = bfa_q_first(&bna->mbox_mod.posted_q); - bfa_nw_ioc_mbox_queue(&bna->device.ioc, - &mb_qe->cmd, NULL, - NULL); - } - } else { - snprintf(message, BNA_MESSAGE_SIZE, - "No matching rsp for [%d:%d:%d]\n", - mb_rsp->mh.msg_class, mb_rsp->mh.msg_id, - mb_rsp->mh.mtag.i2htok); - pr_info("%s", message); - } - - } else - bna_mbox_aen_callback(bna, msg); -} - -static void -bna_err_handler(struct bna *bna, u32 intr_status) -{ - u32 init_halt; - - if (intr_status & __HALT_STATUS_BITS) { - init_halt = readl(bna->device.ioc.ioc_regs.ll_halt); - init_halt &= ~__FW_INIT_HALT_P; - writel(init_halt, bna->device.ioc.ioc_regs.ll_halt); - } - - bfa_nw_ioc_error_isr(&bna->device.ioc); -} - -void -bna_mbox_handler(struct bna *bna, u32 intr_status) -{ - if (BNA_IS_ERR_INTR(intr_status)) { - bna_err_handler(bna, intr_status); - return; - } - if (BNA_IS_MBOX_INTR(intr_status)) - bfa_nw_ioc_mbox_isr(&bna->device.ioc); -} - -void -bna_mbox_send(struct bna *bna, struct bna_mbox_qe *mbox_qe) -{ - struct bfi_mhdr *mh; - - mh = (struct bfi_mhdr *)(&mbox_qe->cmd.msg[0]); - - mh->mtag.i2htok = htons(bna->mbox_mod.msg_ctr); - bna->mbox_mod.msg_ctr++; - bna->mbox_mod.msg_pending++; - if (bna->mbox_mod.state == BNA_MBOX_FREE) { - list_add_tail(&mbox_qe->qe, &bna->mbox_mod.posted_q); - bfa_nw_ioc_mbox_queue(&bna->device.ioc, &mbox_qe->cmd, - NULL, NULL); - bna->mbox_mod.state = BNA_MBOX_POSTED; - } else { - list_add_tail(&mbox_qe->qe, &bna->mbox_mod.posted_q); - } -} - -static void -bna_mbox_flush_q(struct bna *bna, struct list_head *q) -{ - struct bna_mbox_qe *mb_qe = NULL; - struct list_head *mb_q; - void (*cbfn)(void *arg, int status); - void *cbarg; - - mb_q = &bna->mbox_mod.posted_q; - - while (!list_empty(mb_q)) { - bfa_q_deq(mb_q, &mb_qe); - cbfn = mb_qe->cbfn; - cbarg = mb_qe->cbarg; - bfa_q_qe_init(mb_qe); - bna->mbox_mod.msg_pending--; - - if (cbfn) - cbfn(cbarg, BNA_CB_NOT_EXEC); - } - - bna->mbox_mod.state = BNA_MBOX_FREE; -} - -static void -bna_mbox_mod_start(struct bna_mbox_mod *mbox_mod) -{ -} - -static void -bna_mbox_mod_stop(struct bna_mbox_mod *mbox_mod) -{ - bna_mbox_flush_q(mbox_mod->bna, &mbox_mod->posted_q); -} - -static void -bna_mbox_mod_init(struct bna_mbox_mod *mbox_mod, struct bna *bna) -{ - bfa_nw_ioc_mbox_regisr(&bna->device.ioc, BFI_MC_LL, bna_ll_isr, bna); - mbox_mod->state = BNA_MBOX_FREE; - mbox_mod->msg_ctr = mbox_mod->msg_pending = 0; - INIT_LIST_HEAD(&mbox_mod->posted_q); - mbox_mod->bna = bna; -} - -static void -bna_mbox_mod_uninit(struct bna_mbox_mod *mbox_mod) -{ - mbox_mod->bna = NULL; -} - -/** - * LLPORT - */ -#define call_llport_stop_cbfn(llport, status)\ -do {\ - if ((llport)->stop_cbfn)\ - (llport)->stop_cbfn(&(llport)->bna->port, status);\ - (llport)->stop_cbfn = NULL;\ -} while (0) - -static void bna_fw_llport_up(struct bna_llport *llport); -static void bna_fw_cb_llport_up(void *arg, int status); -static void bna_fw_llport_down(struct bna_llport *llport); -static void bna_fw_cb_llport_down(void *arg, int status); -static void bna_llport_start(struct bna_llport *llport); -static void bna_llport_stop(struct bna_llport *llport); -static void bna_llport_fail(struct bna_llport *llport); - -enum bna_llport_state { - BNA_LLPORT_STOPPED = 1, - BNA_LLPORT_DOWN = 2, - BNA_LLPORT_UP_RESP_WAIT = 3, - BNA_LLPORT_DOWN_RESP_WAIT = 4, - BNA_LLPORT_UP = 5, - BNA_LLPORT_LAST_RESP_WAIT = 6 -}; - -bfa_fsm_state_decl(bna_llport, stopped, struct bna_llport, - enum bna_llport_event); -bfa_fsm_state_decl(bna_llport, down, struct bna_llport, - enum bna_llport_event); -bfa_fsm_state_decl(bna_llport, up_resp_wait, struct bna_llport, - enum bna_llport_event); -bfa_fsm_state_decl(bna_llport, down_resp_wait, struct bna_llport, - enum bna_llport_event); -bfa_fsm_state_decl(bna_llport, up, struct bna_llport, - enum bna_llport_event); -bfa_fsm_state_decl(bna_llport, last_resp_wait, struct bna_llport, - enum bna_llport_event); - -static struct bfa_sm_table llport_sm_table[] = { - {BFA_SM(bna_llport_sm_stopped), BNA_LLPORT_STOPPED}, - {BFA_SM(bna_llport_sm_down), BNA_LLPORT_DOWN}, - {BFA_SM(bna_llport_sm_up_resp_wait), BNA_LLPORT_UP_RESP_WAIT}, - {BFA_SM(bna_llport_sm_down_resp_wait), BNA_LLPORT_DOWN_RESP_WAIT}, - {BFA_SM(bna_llport_sm_up), BNA_LLPORT_UP}, - {BFA_SM(bna_llport_sm_last_resp_wait), BNA_LLPORT_LAST_RESP_WAIT} -}; - -static void -bna_llport_sm_stopped_entry(struct bna_llport *llport) -{ - llport->bna->port.link_cbfn((llport)->bna->bnad, BNA_LINK_DOWN); - call_llport_stop_cbfn(llport, BNA_CB_SUCCESS); -} - -static void -bna_llport_sm_stopped(struct bna_llport *llport, - enum bna_llport_event event) -{ - switch (event) { - case LLPORT_E_START: - bfa_fsm_set_state(llport, bna_llport_sm_down); - break; - - case LLPORT_E_STOP: - call_llport_stop_cbfn(llport, BNA_CB_SUCCESS); - break; - - case LLPORT_E_FAIL: - break; - - case LLPORT_E_DOWN: - /* This event is received due to Rx objects failing */ - /* No-op */ - break; - - case LLPORT_E_FWRESP_UP_OK: - case LLPORT_E_FWRESP_DOWN: - /** - * These events are received due to flushing of mbox when - * device fails - */ - /* No-op */ - break; - - default: - bfa_sm_fault(event); - } -} - -static void -bna_llport_sm_down_entry(struct bna_llport *llport) -{ - bnad_cb_port_link_status((llport)->bna->bnad, BNA_LINK_DOWN); -} - -static void -bna_llport_sm_down(struct bna_llport *llport, - enum bna_llport_event event) -{ - switch (event) { - case LLPORT_E_STOP: - bfa_fsm_set_state(llport, bna_llport_sm_stopped); - break; - - case LLPORT_E_FAIL: - bfa_fsm_set_state(llport, bna_llport_sm_stopped); - break; - - case LLPORT_E_UP: - bfa_fsm_set_state(llport, bna_llport_sm_up_resp_wait); - bna_fw_llport_up(llport); - break; - - default: - bfa_sm_fault(event); - } -} - -static void -bna_llport_sm_up_resp_wait_entry(struct bna_llport *llport) -{ - BUG_ON(!llport_can_be_up(llport)); - /** - * NOTE: Do not call bna_fw_llport_up() here. That will over step - * mbox due to down_resp_wait -> up_resp_wait transition on event - * LLPORT_E_UP - */ -} - -static void -bna_llport_sm_up_resp_wait(struct bna_llport *llport, - enum bna_llport_event event) -{ - switch (event) { - case LLPORT_E_STOP: - bfa_fsm_set_state(llport, bna_llport_sm_last_resp_wait); - break; - - case LLPORT_E_FAIL: - bfa_fsm_set_state(llport, bna_llport_sm_stopped); - break; - - case LLPORT_E_DOWN: - bfa_fsm_set_state(llport, bna_llport_sm_down_resp_wait); - break; - - case LLPORT_E_FWRESP_UP_OK: - bfa_fsm_set_state(llport, bna_llport_sm_up); - break; - - case LLPORT_E_FWRESP_UP_FAIL: - bfa_fsm_set_state(llport, bna_llport_sm_down); - break; - - case LLPORT_E_FWRESP_DOWN: - /* down_resp_wait -> up_resp_wait transition on LLPORT_E_UP */ - bna_fw_llport_up(llport); - break; - - default: - bfa_sm_fault(event); - } -} - -static void -bna_llport_sm_down_resp_wait_entry(struct bna_llport *llport) -{ - /** - * NOTE: Do not call bna_fw_llport_down() here. That will over step - * mbox due to up_resp_wait -> down_resp_wait transition on event - * LLPORT_E_DOWN - */ -} - -static void -bna_llport_sm_down_resp_wait(struct bna_llport *llport, - enum bna_llport_event event) -{ - switch (event) { - case LLPORT_E_STOP: - bfa_fsm_set_state(llport, bna_llport_sm_last_resp_wait); - break; - - case LLPORT_E_FAIL: - bfa_fsm_set_state(llport, bna_llport_sm_stopped); - break; - - case LLPORT_E_UP: - bfa_fsm_set_state(llport, bna_llport_sm_up_resp_wait); - break; - - case LLPORT_E_FWRESP_UP_OK: - /* up_resp_wait->down_resp_wait transition on LLPORT_E_DOWN */ - bna_fw_llport_down(llport); - break; - - case LLPORT_E_FWRESP_UP_FAIL: - case LLPORT_E_FWRESP_DOWN: - bfa_fsm_set_state(llport, bna_llport_sm_down); - break; - - default: - bfa_sm_fault(event); - } -} - -static void -bna_llport_sm_up_entry(struct bna_llport *llport) -{ -} - -static void -bna_llport_sm_up(struct bna_llport *llport, - enum bna_llport_event event) -{ - switch (event) { - case LLPORT_E_STOP: - bfa_fsm_set_state(llport, bna_llport_sm_last_resp_wait); - bna_fw_llport_down(llport); - break; - - case LLPORT_E_FAIL: - bfa_fsm_set_state(llport, bna_llport_sm_stopped); - break; - - case LLPORT_E_DOWN: - bfa_fsm_set_state(llport, bna_llport_sm_down_resp_wait); - bna_fw_llport_down(llport); - break; - - default: - bfa_sm_fault(event); - } -} - -static void -bna_llport_sm_last_resp_wait_entry(struct bna_llport *llport) -{ -} - -static void -bna_llport_sm_last_resp_wait(struct bna_llport *llport, - enum bna_llport_event event) -{ - switch (event) { - case LLPORT_E_FAIL: - bfa_fsm_set_state(llport, bna_llport_sm_stopped); - break; - - case LLPORT_E_DOWN: - /** - * This event is received due to Rx objects stopping in - * parallel to llport - */ - /* No-op */ - break; - - case LLPORT_E_FWRESP_UP_OK: - /* up_resp_wait->last_resp_wait transition on LLPORT_T_STOP */ - bna_fw_llport_down(llport); - break; - - case LLPORT_E_FWRESP_UP_FAIL: - case LLPORT_E_FWRESP_DOWN: - bfa_fsm_set_state(llport, bna_llport_sm_stopped); - break; - - default: - bfa_sm_fault(event); - } -} - -static void -bna_fw_llport_admin_up(struct bna_llport *llport) -{ - struct bfi_ll_port_admin_req ll_req; - - memset(&ll_req, 0, sizeof(ll_req)); - ll_req.mh.msg_class = BFI_MC_LL; - ll_req.mh.msg_id = BFI_LL_H2I_PORT_ADMIN_REQ; - ll_req.mh.mtag.h2i.lpu_id = 0; - - ll_req.up = BNA_STATUS_T_ENABLED; - - bna_mbox_qe_fill(&llport->mbox_qe, &ll_req, sizeof(ll_req), - bna_fw_cb_llport_up, llport); - - bna_mbox_send(llport->bna, &llport->mbox_qe); -} - -static void -bna_fw_llport_up(struct bna_llport *llport) -{ - if (llport->type == BNA_PORT_T_REGULAR) - bna_fw_llport_admin_up(llport); -} - -static void -bna_fw_cb_llport_up(void *arg, int status) -{ - struct bna_llport *llport = (struct bna_llport *)arg; - - bfa_q_qe_init(&llport->mbox_qe.qe); - if (status == BFI_LL_CMD_FAIL) { - if (llport->type == BNA_PORT_T_REGULAR) - llport->flags &= ~BNA_LLPORT_F_PORT_ENABLED; - else - llport->flags &= ~BNA_LLPORT_F_ADMIN_UP; - bfa_fsm_send_event(llport, LLPORT_E_FWRESP_UP_FAIL); - } else - bfa_fsm_send_event(llport, LLPORT_E_FWRESP_UP_OK); -} - -static void -bna_fw_llport_admin_down(struct bna_llport *llport) -{ - struct bfi_ll_port_admin_req ll_req; - - memset(&ll_req, 0, sizeof(ll_req)); - ll_req.mh.msg_class = BFI_MC_LL; - ll_req.mh.msg_id = BFI_LL_H2I_PORT_ADMIN_REQ; - ll_req.mh.mtag.h2i.lpu_id = 0; - - ll_req.up = BNA_STATUS_T_DISABLED; - - bna_mbox_qe_fill(&llport->mbox_qe, &ll_req, sizeof(ll_req), - bna_fw_cb_llport_down, llport); - - bna_mbox_send(llport->bna, &llport->mbox_qe); -} - -static void -bna_fw_llport_down(struct bna_llport *llport) -{ - if (llport->type == BNA_PORT_T_REGULAR) - bna_fw_llport_admin_down(llport); -} - -static void -bna_fw_cb_llport_down(void *arg, int status) -{ - struct bna_llport *llport = (struct bna_llport *)arg; - - bfa_q_qe_init(&llport->mbox_qe.qe); - bfa_fsm_send_event(llport, LLPORT_E_FWRESP_DOWN); -} - -static void -bna_port_cb_llport_stopped(struct bna_port *port, - enum bna_cb_status status) -{ - bfa_wc_down(&port->chld_stop_wc); -} - -static void -bna_llport_init(struct bna_llport *llport, struct bna *bna) -{ - llport->flags |= BNA_LLPORT_F_ADMIN_UP; - llport->flags |= BNA_LLPORT_F_PORT_ENABLED; - llport->type = BNA_PORT_T_REGULAR; - llport->bna = bna; - - llport->link_status = BNA_LINK_DOWN; - - llport->rx_started_count = 0; - - llport->stop_cbfn = NULL; - - bfa_q_qe_init(&llport->mbox_qe.qe); - - bfa_fsm_set_state(llport, bna_llport_sm_stopped); -} - -static void -bna_llport_uninit(struct bna_llport *llport) -{ - llport->flags &= ~BNA_LLPORT_F_ADMIN_UP; - llport->flags &= ~BNA_LLPORT_F_PORT_ENABLED; - - llport->bna = NULL; -} - -static void -bna_llport_start(struct bna_llport *llport) -{ - bfa_fsm_send_event(llport, LLPORT_E_START); -} - -static void -bna_llport_stop(struct bna_llport *llport) -{ - llport->stop_cbfn = bna_port_cb_llport_stopped; - - bfa_fsm_send_event(llport, LLPORT_E_STOP); -} - -static void -bna_llport_fail(struct bna_llport *llport) -{ - /* Reset the physical port status to enabled */ - llport->flags |= BNA_LLPORT_F_PORT_ENABLED; - bfa_fsm_send_event(llport, LLPORT_E_FAIL); -} - -static int -bna_llport_state_get(struct bna_llport *llport) -{ - return bfa_sm_to_state(llport_sm_table, llport->fsm); -} - -void -bna_llport_rx_started(struct bna_llport *llport) -{ - llport->rx_started_count++; - - if (llport->rx_started_count == 1) { - - llport->flags |= BNA_LLPORT_F_RX_STARTED; - - if (llport_can_be_up(llport)) - bfa_fsm_send_event(llport, LLPORT_E_UP); - } -} - -void -bna_llport_rx_stopped(struct bna_llport *llport) -{ - int llport_up = llport_is_up(llport); - - llport->rx_started_count--; - - if (llport->rx_started_count == 0) { - - llport->flags &= ~BNA_LLPORT_F_RX_STARTED; - - if (llport_up) - bfa_fsm_send_event(llport, LLPORT_E_DOWN); - } -} - -/** - * PORT - */ -#define bna_port_chld_start(port)\ -do {\ - enum bna_tx_type tx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\ - BNA_TX_T_REGULAR : BNA_TX_T_LOOPBACK;\ - enum bna_rx_type rx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\ - BNA_RX_T_REGULAR : BNA_RX_T_LOOPBACK;\ - bna_llport_start(&(port)->llport);\ - bna_tx_mod_start(&(port)->bna->tx_mod, tx_type);\ - bna_rx_mod_start(&(port)->bna->rx_mod, rx_type);\ -} while (0) - -#define bna_port_chld_stop(port)\ -do {\ - enum bna_tx_type tx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\ - BNA_TX_T_REGULAR : BNA_TX_T_LOOPBACK;\ - enum bna_rx_type rx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\ - BNA_RX_T_REGULAR : BNA_RX_T_LOOPBACK;\ - bfa_wc_up(&(port)->chld_stop_wc);\ - bfa_wc_up(&(port)->chld_stop_wc);\ - bfa_wc_up(&(port)->chld_stop_wc);\ - bna_llport_stop(&(port)->llport);\ - bna_tx_mod_stop(&(port)->bna->tx_mod, tx_type);\ - bna_rx_mod_stop(&(port)->bna->rx_mod, rx_type);\ -} while (0) - -#define bna_port_chld_fail(port)\ -do {\ - bna_llport_fail(&(port)->llport);\ - bna_tx_mod_fail(&(port)->bna->tx_mod);\ - bna_rx_mod_fail(&(port)->bna->rx_mod);\ -} while (0) - -#define bna_port_rx_start(port)\ -do {\ - enum bna_rx_type rx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\ - BNA_RX_T_REGULAR : BNA_RX_T_LOOPBACK;\ - bna_rx_mod_start(&(port)->bna->rx_mod, rx_type);\ -} while (0) - -#define bna_port_rx_stop(port)\ -do {\ - enum bna_rx_type rx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\ - BNA_RX_T_REGULAR : BNA_RX_T_LOOPBACK;\ - bfa_wc_up(&(port)->chld_stop_wc);\ - bna_rx_mod_stop(&(port)->bna->rx_mod, rx_type);\ -} while (0) - -#define call_port_stop_cbfn(port, status)\ -do {\ - if ((port)->stop_cbfn)\ - (port)->stop_cbfn((port)->stop_cbarg, status);\ - (port)->stop_cbfn = NULL;\ - (port)->stop_cbarg = NULL;\ -} while (0) - -#define call_port_pause_cbfn(port, status)\ -do {\ - if ((port)->pause_cbfn)\ - (port)->pause_cbfn((port)->bna->bnad, status);\ - (port)->pause_cbfn = NULL;\ -} while (0) - -#define call_port_mtu_cbfn(port, status)\ -do {\ - if ((port)->mtu_cbfn)\ - (port)->mtu_cbfn((port)->bna->bnad, status);\ - (port)->mtu_cbfn = NULL;\ -} while (0) - -static void bna_fw_pause_set(struct bna_port *port); -static void bna_fw_cb_pause_set(void *arg, int status); -static void bna_fw_mtu_set(struct bna_port *port); -static void bna_fw_cb_mtu_set(void *arg, int status); - -enum bna_port_event { - PORT_E_START = 1, - PORT_E_STOP = 2, - PORT_E_FAIL = 3, - PORT_E_PAUSE_CFG = 4, - PORT_E_MTU_CFG = 5, - PORT_E_CHLD_STOPPED = 6, - PORT_E_FWRESP_PAUSE = 7, - PORT_E_FWRESP_MTU = 8 -}; - -enum bna_port_state { - BNA_PORT_STOPPED = 1, - BNA_PORT_MTU_INIT_WAIT = 2, - BNA_PORT_PAUSE_INIT_WAIT = 3, - BNA_PORT_LAST_RESP_WAIT = 4, - BNA_PORT_STARTED = 5, - BNA_PORT_PAUSE_CFG_WAIT = 6, - BNA_PORT_RX_STOP_WAIT = 7, - BNA_PORT_MTU_CFG_WAIT = 8, - BNA_PORT_CHLD_STOP_WAIT = 9 -}; - -bfa_fsm_state_decl(bna_port, stopped, struct bna_port, - enum bna_port_event); -bfa_fsm_state_decl(bna_port, mtu_init_wait, struct bna_port, - enum bna_port_event); -bfa_fsm_state_decl(bna_port, pause_init_wait, struct bna_port, - enum bna_port_event); -bfa_fsm_state_decl(bna_port, last_resp_wait, struct bna_port, - enum bna_port_event); -bfa_fsm_state_decl(bna_port, started, struct bna_port, - enum bna_port_event); -bfa_fsm_state_decl(bna_port, pause_cfg_wait, struct bna_port, - enum bna_port_event); -bfa_fsm_state_decl(bna_port, rx_stop_wait, struct bna_port, - enum bna_port_event); -bfa_fsm_state_decl(bna_port, mtu_cfg_wait, struct bna_port, - enum bna_port_event); -bfa_fsm_state_decl(bna_port, chld_stop_wait, struct bna_port, - enum bna_port_event); - -static struct bfa_sm_table port_sm_table[] = { - {BFA_SM(bna_port_sm_stopped), BNA_PORT_STOPPED}, - {BFA_SM(bna_port_sm_mtu_init_wait), BNA_PORT_MTU_INIT_WAIT}, - {BFA_SM(bna_port_sm_pause_init_wait), BNA_PORT_PAUSE_INIT_WAIT}, - {BFA_SM(bna_port_sm_last_resp_wait), BNA_PORT_LAST_RESP_WAIT}, - {BFA_SM(bna_port_sm_started), BNA_PORT_STARTED}, - {BFA_SM(bna_port_sm_pause_cfg_wait), BNA_PORT_PAUSE_CFG_WAIT}, - {BFA_SM(bna_port_sm_rx_stop_wait), BNA_PORT_RX_STOP_WAIT}, - {BFA_SM(bna_port_sm_mtu_cfg_wait), BNA_PORT_MTU_CFG_WAIT}, - {BFA_SM(bna_port_sm_chld_stop_wait), BNA_PORT_CHLD_STOP_WAIT} -}; - -static void -bna_port_sm_stopped_entry(struct bna_port *port) -{ - call_port_pause_cbfn(port, BNA_CB_SUCCESS); - call_port_mtu_cbfn(port, BNA_CB_SUCCESS); - call_port_stop_cbfn(port, BNA_CB_SUCCESS); -} - -static void -bna_port_sm_stopped(struct bna_port *port, enum bna_port_event event) -{ - switch (event) { - case PORT_E_START: - bfa_fsm_set_state(port, bna_port_sm_mtu_init_wait); - break; - - case PORT_E_STOP: - call_port_stop_cbfn(port, BNA_CB_SUCCESS); - break; - - case PORT_E_FAIL: - /* No-op */ - break; - - case PORT_E_PAUSE_CFG: - call_port_pause_cbfn(port, BNA_CB_SUCCESS); - break; - - case PORT_E_MTU_CFG: - call_port_mtu_cbfn(port, BNA_CB_SUCCESS); - break; - - case PORT_E_CHLD_STOPPED: - /** - * This event is received due to LLPort, Tx and Rx objects - * failing - */ - /* No-op */ - break; - - case PORT_E_FWRESP_PAUSE: - case PORT_E_FWRESP_MTU: - /** - * These events are received due to flushing of mbox when - * device fails - */ - /* No-op */ - break; - - default: - bfa_sm_fault(event); - } -} - -static void -bna_port_sm_mtu_init_wait_entry(struct bna_port *port) -{ - bna_fw_mtu_set(port); -} - -static void -bna_port_sm_mtu_init_wait(struct bna_port *port, enum bna_port_event event) -{ - switch (event) { - case PORT_E_STOP: - bfa_fsm_set_state(port, bna_port_sm_last_resp_wait); - break; - - case PORT_E_FAIL: - bfa_fsm_set_state(port, bna_port_sm_stopped); - break; - - case PORT_E_PAUSE_CFG: - /* No-op */ - break; - - case PORT_E_MTU_CFG: - port->flags |= BNA_PORT_F_MTU_CHANGED; - break; - - case PORT_E_FWRESP_MTU: - if (port->flags & BNA_PORT_F_MTU_CHANGED) { - port->flags &= ~BNA_PORT_F_MTU_CHANGED; - bna_fw_mtu_set(port); - } else { - bfa_fsm_set_state(port, bna_port_sm_pause_init_wait); - } - break; - - default: - bfa_sm_fault(event); - } -} - -static void -bna_port_sm_pause_init_wait_entry(struct bna_port *port) -{ - bna_fw_pause_set(port); -} - -static void -bna_port_sm_pause_init_wait(struct bna_port *port, - enum bna_port_event event) -{ - switch (event) { - case PORT_E_STOP: - bfa_fsm_set_state(port, bna_port_sm_last_resp_wait); - break; - - case PORT_E_FAIL: - bfa_fsm_set_state(port, bna_port_sm_stopped); - break; - - case PORT_E_PAUSE_CFG: - port->flags |= BNA_PORT_F_PAUSE_CHANGED; - break; - - case PORT_E_MTU_CFG: - port->flags |= BNA_PORT_F_MTU_CHANGED; - break; - - case PORT_E_FWRESP_PAUSE: - if (port->flags & BNA_PORT_F_PAUSE_CHANGED) { - port->flags &= ~BNA_PORT_F_PAUSE_CHANGED; - bna_fw_pause_set(port); - } else if (port->flags & BNA_PORT_F_MTU_CHANGED) { - port->flags &= ~BNA_PORT_F_MTU_CHANGED; - bfa_fsm_set_state(port, bna_port_sm_mtu_init_wait); - } else { - bfa_fsm_set_state(port, bna_port_sm_started); - bna_port_chld_start(port); - } - break; - - default: - bfa_sm_fault(event); - } -} - -static void -bna_port_sm_last_resp_wait_entry(struct bna_port *port) -{ -} - -static void -bna_port_sm_last_resp_wait(struct bna_port *port, - enum bna_port_event event) -{ - switch (event) { - case PORT_E_FAIL: - case PORT_E_FWRESP_PAUSE: - case PORT_E_FWRESP_MTU: - bfa_fsm_set_state(port, bna_port_sm_stopped); - break; - - default: - bfa_sm_fault(event); - } -} - -static void -bna_port_sm_started_entry(struct bna_port *port) -{ - /** - * NOTE: Do not call bna_port_chld_start() here, since it will be - * inadvertently called during pause_cfg_wait->started transition - * as well - */ - call_port_pause_cbfn(port, BNA_CB_SUCCESS); - call_port_mtu_cbfn(port, BNA_CB_SUCCESS); -} - -static void -bna_port_sm_started(struct bna_port *port, - enum bna_port_event event) -{ - switch (event) { - case PORT_E_STOP: - bfa_fsm_set_state(port, bna_port_sm_chld_stop_wait); - break; - - case PORT_E_FAIL: - bfa_fsm_set_state(port, bna_port_sm_stopped); - bna_port_chld_fail(port); - break; - - case PORT_E_PAUSE_CFG: - bfa_fsm_set_state(port, bna_port_sm_pause_cfg_wait); - break; - - case PORT_E_MTU_CFG: - bfa_fsm_set_state(port, bna_port_sm_rx_stop_wait); - break; - - default: - bfa_sm_fault(event); - } -} - -static void -bna_port_sm_pause_cfg_wait_entry(struct bna_port *port) -{ - bna_fw_pause_set(port); -} - -static void -bna_port_sm_pause_cfg_wait(struct bna_port *port, - enum bna_port_event event) -{ - switch (event) { - case PORT_E_FAIL: - bfa_fsm_set_state(port, bna_port_sm_stopped); - bna_port_chld_fail(port); - break; - - case PORT_E_FWRESP_PAUSE: - bfa_fsm_set_state(port, bna_port_sm_started); - break; - - default: - bfa_sm_fault(event); - } -} - -static void -bna_port_sm_rx_stop_wait_entry(struct bna_port *port) -{ - bna_port_rx_stop(port); -} - -static void -bna_port_sm_rx_stop_wait(struct bna_port *port, - enum bna_port_event event) -{ - switch (event) { - case PORT_E_FAIL: - bfa_fsm_set_state(port, bna_port_sm_stopped); - bna_port_chld_fail(port); - break; - - case PORT_E_CHLD_STOPPED: - bfa_fsm_set_state(port, bna_port_sm_mtu_cfg_wait); - break; - - default: - bfa_sm_fault(event); - } -} - -static void -bna_port_sm_mtu_cfg_wait_entry(struct bna_port *port) -{ - bna_fw_mtu_set(port); -} - -static void -bna_port_sm_mtu_cfg_wait(struct bna_port *port, enum bna_port_event event) -{ - switch (event) { - case PORT_E_FAIL: - bfa_fsm_set_state(port, bna_port_sm_stopped); - bna_port_chld_fail(port); - break; - - case PORT_E_FWRESP_MTU: - bfa_fsm_set_state(port, bna_port_sm_started); - bna_port_rx_start(port); - break; - - default: - bfa_sm_fault(event); - } -} - -static void -bna_port_sm_chld_stop_wait_entry(struct bna_port *port) -{ - bna_port_chld_stop(port); -} - -static void -bna_port_sm_chld_stop_wait(struct bna_port *port, - enum bna_port_event event) -{ - switch (event) { - case PORT_E_FAIL: - bfa_fsm_set_state(port, bna_port_sm_stopped); - bna_port_chld_fail(port); - break; - - case PORT_E_CHLD_STOPPED: - bfa_fsm_set_state(port, bna_port_sm_stopped); - break; - - default: - bfa_sm_fault(event); - } -} - -static void -bna_fw_pause_set(struct bna_port *port) -{ - struct bfi_ll_set_pause_req ll_req; - - memset(&ll_req, 0, sizeof(ll_req)); - ll_req.mh.msg_class = BFI_MC_LL; - ll_req.mh.msg_id = BFI_LL_H2I_SET_PAUSE_REQ; - ll_req.mh.mtag.h2i.lpu_id = 0; - - ll_req.tx_pause = port->pause_config.tx_pause; - ll_req.rx_pause = port->pause_config.rx_pause; - - bna_mbox_qe_fill(&port->mbox_qe, &ll_req, sizeof(ll_req), - bna_fw_cb_pause_set, port); - - bna_mbox_send(port->bna, &port->mbox_qe); -} - -static void -bna_fw_cb_pause_set(void *arg, int status) -{ - struct bna_port *port = (struct bna_port *)arg; - - bfa_q_qe_init(&port->mbox_qe.qe); - bfa_fsm_send_event(port, PORT_E_FWRESP_PAUSE); -} - -void -bna_fw_mtu_set(struct bna_port *port) -{ - struct bfi_ll_mtu_info_req ll_req; - - bfi_h2i_set(ll_req.mh, BFI_MC_LL, BFI_LL_H2I_MTU_INFO_REQ, 0); - ll_req.mtu = htons((u16)port->mtu); - - bna_mbox_qe_fill(&port->mbox_qe, &ll_req, sizeof(ll_req), - bna_fw_cb_mtu_set, port); - bna_mbox_send(port->bna, &port->mbox_qe); -} - -void -bna_fw_cb_mtu_set(void *arg, int status) -{ - struct bna_port *port = (struct bna_port *)arg; - - bfa_q_qe_init(&port->mbox_qe.qe); - bfa_fsm_send_event(port, PORT_E_FWRESP_MTU); -} - -static void -bna_port_cb_chld_stopped(void *arg) -{ - struct bna_port *port = (struct bna_port *)arg; - - bfa_fsm_send_event(port, PORT_E_CHLD_STOPPED); -} - -static void -bna_port_init(struct bna_port *port, struct bna *bna) -{ - port->bna = bna; - port->flags = 0; - port->mtu = 0; - port->type = BNA_PORT_T_REGULAR; - - port->link_cbfn = bnad_cb_port_link_status; - - port->chld_stop_wc.wc_resume = bna_port_cb_chld_stopped; - port->chld_stop_wc.wc_cbarg = port; - port->chld_stop_wc.wc_count = 0; - - port->stop_cbfn = NULL; - port->stop_cbarg = NULL; - - port->pause_cbfn = NULL; - - port->mtu_cbfn = NULL; - - bfa_q_qe_init(&port->mbox_qe.qe); - - bfa_fsm_set_state(port, bna_port_sm_stopped); - - bna_llport_init(&port->llport, bna); -} - -static void -bna_port_uninit(struct bna_port *port) -{ - bna_llport_uninit(&port->llport); - - port->flags = 0; - - port->bna = NULL; -} - -static int -bna_port_state_get(struct bna_port *port) -{ - return bfa_sm_to_state(port_sm_table, port->fsm); -} - -static void -bna_port_start(struct bna_port *port) -{ - port->flags |= BNA_PORT_F_DEVICE_READY; - if (port->flags & BNA_PORT_F_ENABLED) - bfa_fsm_send_event(port, PORT_E_START); -} - -static void -bna_port_stop(struct bna_port *port) -{ - port->stop_cbfn = bna_device_cb_port_stopped; - port->stop_cbarg = &port->bna->device; - - port->flags &= ~BNA_PORT_F_DEVICE_READY; - bfa_fsm_send_event(port, PORT_E_STOP); -} - -static void -bna_port_fail(struct bna_port *port) -{ - port->flags &= ~BNA_PORT_F_DEVICE_READY; - bfa_fsm_send_event(port, PORT_E_FAIL); -} - -void -bna_port_cb_tx_stopped(struct bna_port *port, enum bna_cb_status status) -{ - bfa_wc_down(&port->chld_stop_wc); -} - -void -bna_port_cb_rx_stopped(struct bna_port *port, enum bna_cb_status status) -{ - bfa_wc_down(&port->chld_stop_wc); -} - -int -bna_port_mtu_get(struct bna_port *port) -{ - return port->mtu; -} - -void -bna_port_enable(struct bna_port *port) -{ - if (port->fsm != (bfa_sm_t)bna_port_sm_stopped) - return; - - port->flags |= BNA_PORT_F_ENABLED; - - if (port->flags & BNA_PORT_F_DEVICE_READY) - bfa_fsm_send_event(port, PORT_E_START); -} - -void -bna_port_disable(struct bna_port *port, enum bna_cleanup_type type, - void (*cbfn)(void *, enum bna_cb_status)) -{ - if (type == BNA_SOFT_CLEANUP) { - (*cbfn)(port->bna->bnad, BNA_CB_SUCCESS); - return; - } - - port->stop_cbfn = cbfn; - port->stop_cbarg = port->bna->bnad; - - port->flags &= ~BNA_PORT_F_ENABLED; - - bfa_fsm_send_event(port, PORT_E_STOP); -} - -void -bna_port_pause_config(struct bna_port *port, - struct bna_pause_config *pause_config, - void (*cbfn)(struct bnad *, enum bna_cb_status)) -{ - port->pause_config = *pause_config; - - port->pause_cbfn = cbfn; - - bfa_fsm_send_event(port, PORT_E_PAUSE_CFG); -} - -void -bna_port_mtu_set(struct bna_port *port, int mtu, - void (*cbfn)(struct bnad *, enum bna_cb_status)) -{ - port->mtu = mtu; - - port->mtu_cbfn = cbfn; - - bfa_fsm_send_event(port, PORT_E_MTU_CFG); -} - -void -bna_port_mac_get(struct bna_port *port, mac_t *mac) -{ - *mac = bfa_nw_ioc_get_mac(&port->bna->device.ioc); -} - -/** - * DEVICE - */ -#define enable_mbox_intr(_device)\ -do {\ - u32 intr_status;\ - bna_intr_status_get((_device)->bna, intr_status);\ - bnad_cb_device_enable_mbox_intr((_device)->bna->bnad);\ - bna_mbox_intr_enable((_device)->bna);\ -} while (0) - -#define disable_mbox_intr(_device)\ -do {\ - bna_mbox_intr_disable((_device)->bna);\ - bnad_cb_device_disable_mbox_intr((_device)->bna->bnad);\ -} while (0) - -static const struct bna_chip_regs_offset reg_offset[] = -{{HOST_PAGE_NUM_FN0, HOSTFN0_INT_STATUS, - HOSTFN0_INT_MASK, HOST_MSIX_ERR_INDEX_FN0}, -{HOST_PAGE_NUM_FN1, HOSTFN1_INT_STATUS, - HOSTFN1_INT_MASK, HOST_MSIX_ERR_INDEX_FN1}, -{HOST_PAGE_NUM_FN2, HOSTFN2_INT_STATUS, - HOSTFN2_INT_MASK, HOST_MSIX_ERR_INDEX_FN2}, -{HOST_PAGE_NUM_FN3, HOSTFN3_INT_STATUS, - HOSTFN3_INT_MASK, HOST_MSIX_ERR_INDEX_FN3}, -}; - -enum bna_device_event { - DEVICE_E_ENABLE = 1, - DEVICE_E_DISABLE = 2, - DEVICE_E_IOC_READY = 3, - DEVICE_E_IOC_FAILED = 4, - DEVICE_E_IOC_DISABLED = 5, - DEVICE_E_IOC_RESET = 6, - DEVICE_E_PORT_STOPPED = 7, -}; - -enum bna_device_state { - BNA_DEVICE_STOPPED = 1, - BNA_DEVICE_IOC_READY_WAIT = 2, - BNA_DEVICE_READY = 3, - BNA_DEVICE_PORT_STOP_WAIT = 4, - BNA_DEVICE_IOC_DISABLE_WAIT = 5, - BNA_DEVICE_FAILED = 6 -}; - -bfa_fsm_state_decl(bna_device, stopped, struct bna_device, - enum bna_device_event); -bfa_fsm_state_decl(bna_device, ioc_ready_wait, struct bna_device, - enum bna_device_event); -bfa_fsm_state_decl(bna_device, ready, struct bna_device, - enum bna_device_event); -bfa_fsm_state_decl(bna_device, port_stop_wait, struct bna_device, - enum bna_device_event); -bfa_fsm_state_decl(bna_device, ioc_disable_wait, struct bna_device, - enum bna_device_event); -bfa_fsm_state_decl(bna_device, failed, struct bna_device, - enum bna_device_event); - -static struct bfa_sm_table device_sm_table[] = { - {BFA_SM(bna_device_sm_stopped), BNA_DEVICE_STOPPED}, - {BFA_SM(bna_device_sm_ioc_ready_wait), BNA_DEVICE_IOC_READY_WAIT}, - {BFA_SM(bna_device_sm_ready), BNA_DEVICE_READY}, - {BFA_SM(bna_device_sm_port_stop_wait), BNA_DEVICE_PORT_STOP_WAIT}, - {BFA_SM(bna_device_sm_ioc_disable_wait), BNA_DEVICE_IOC_DISABLE_WAIT}, - {BFA_SM(bna_device_sm_failed), BNA_DEVICE_FAILED}, -}; - -static void -bna_device_sm_stopped_entry(struct bna_device *device) -{ - if (device->stop_cbfn) - device->stop_cbfn(device->stop_cbarg, BNA_CB_SUCCESS); - - device->stop_cbfn = NULL; - device->stop_cbarg = NULL; -} - -static void -bna_device_sm_stopped(struct bna_device *device, - enum bna_device_event event) -{ - switch (event) { - case DEVICE_E_ENABLE: - if (device->intr_type == BNA_INTR_T_MSIX) - bna_mbox_msix_idx_set(device); - bfa_nw_ioc_enable(&device->ioc); - bfa_fsm_set_state(device, bna_device_sm_ioc_ready_wait); - break; - - case DEVICE_E_DISABLE: - bfa_fsm_set_state(device, bna_device_sm_stopped); - break; - - case DEVICE_E_IOC_RESET: - enable_mbox_intr(device); - break; - - case DEVICE_E_IOC_FAILED: - bfa_fsm_set_state(device, bna_device_sm_failed); - break; - - default: - bfa_sm_fault(event); - } -} - -static void -bna_device_sm_ioc_ready_wait_entry(struct bna_device *device) -{ - /** - * Do not call bfa_ioc_enable() here. It must be called in the - * previous state due to failed -> ioc_ready_wait transition. - */ -} - -static void -bna_device_sm_ioc_ready_wait(struct bna_device *device, - enum bna_device_event event) -{ - switch (event) { - case DEVICE_E_DISABLE: - if (device->ready_cbfn) - device->ready_cbfn(device->ready_cbarg, - BNA_CB_INTERRUPT); - device->ready_cbfn = NULL; - device->ready_cbarg = NULL; - bfa_fsm_set_state(device, bna_device_sm_ioc_disable_wait); - break; - - case DEVICE_E_IOC_READY: - bfa_fsm_set_state(device, bna_device_sm_ready); - break; - - case DEVICE_E_IOC_FAILED: - bfa_fsm_set_state(device, bna_device_sm_failed); - break; - - case DEVICE_E_IOC_RESET: - enable_mbox_intr(device); - break; - - default: - bfa_sm_fault(event); - } -} - -static void -bna_device_sm_ready_entry(struct bna_device *device) -{ - bna_mbox_mod_start(&device->bna->mbox_mod); - bna_port_start(&device->bna->port); - - if (device->ready_cbfn) - device->ready_cbfn(device->ready_cbarg, - BNA_CB_SUCCESS); - device->ready_cbfn = NULL; - device->ready_cbarg = NULL; -} - -static void -bna_device_sm_ready(struct bna_device *device, enum bna_device_event event) -{ - switch (event) { - case DEVICE_E_DISABLE: - bfa_fsm_set_state(device, bna_device_sm_port_stop_wait); - break; - - case DEVICE_E_IOC_FAILED: - bfa_fsm_set_state(device, bna_device_sm_failed); - break; - - default: - bfa_sm_fault(event); - } -} - -static void -bna_device_sm_port_stop_wait_entry(struct bna_device *device) -{ - bna_port_stop(&device->bna->port); -} - -static void -bna_device_sm_port_stop_wait(struct bna_device *device, - enum bna_device_event event) -{ - switch (event) { - case DEVICE_E_PORT_STOPPED: - bna_mbox_mod_stop(&device->bna->mbox_mod); - bfa_fsm_set_state(device, bna_device_sm_ioc_disable_wait); - break; - - case DEVICE_E_IOC_FAILED: - disable_mbox_intr(device); - bna_port_fail(&device->bna->port); - break; - - default: - bfa_sm_fault(event); - } -} - -static void -bna_device_sm_ioc_disable_wait_entry(struct bna_device *device) -{ - bfa_nw_ioc_disable(&device->ioc); -} - -static void -bna_device_sm_ioc_disable_wait(struct bna_device *device, - enum bna_device_event event) -{ - switch (event) { - case DEVICE_E_IOC_DISABLED: - disable_mbox_intr(device); - bfa_fsm_set_state(device, bna_device_sm_stopped); - break; - - default: - bfa_sm_fault(event); - } -} - -static void -bna_device_sm_failed_entry(struct bna_device *device) -{ - disable_mbox_intr(device); - bna_port_fail(&device->bna->port); - bna_mbox_mod_stop(&device->bna->mbox_mod); - - if (device->ready_cbfn) - device->ready_cbfn(device->ready_cbarg, - BNA_CB_FAIL); - device->ready_cbfn = NULL; - device->ready_cbarg = NULL; -} - -static void -bna_device_sm_failed(struct bna_device *device, - enum bna_device_event event) -{ - switch (event) { - case DEVICE_E_DISABLE: - bfa_fsm_set_state(device, bna_device_sm_ioc_disable_wait); - break; - - case DEVICE_E_IOC_RESET: - enable_mbox_intr(device); - bfa_fsm_set_state(device, bna_device_sm_ioc_ready_wait); - break; - - default: - bfa_sm_fault(event); - } -} - -/* IOC callback functions */ - -static void -bna_device_cb_iocll_ready(void *dev, enum bfa_status error) -{ - struct bna_device *device = (struct bna_device *)dev; - - if (error) - bfa_fsm_send_event(device, DEVICE_E_IOC_FAILED); - else - bfa_fsm_send_event(device, DEVICE_E_IOC_READY); -} - -static void -bna_device_cb_iocll_disabled(void *dev) -{ - struct bna_device *device = (struct bna_device *)dev; - - bfa_fsm_send_event(device, DEVICE_E_IOC_DISABLED); -} - -static void -bna_device_cb_iocll_failed(void *dev) -{ - struct bna_device *device = (struct bna_device *)dev; - - bfa_fsm_send_event(device, DEVICE_E_IOC_FAILED); -} - -static void -bna_device_cb_iocll_reset(void *dev) -{ - struct bna_device *device = (struct bna_device *)dev; - - bfa_fsm_send_event(device, DEVICE_E_IOC_RESET); -} - -static struct bfa_ioc_cbfn bfa_iocll_cbfn = { - bna_device_cb_iocll_ready, - bna_device_cb_iocll_disabled, - bna_device_cb_iocll_failed, - bna_device_cb_iocll_reset -}; - -/* device */ -static void -bna_adv_device_init(struct bna_device *device, struct bna *bna, - struct bna_res_info *res_info) -{ - u8 *kva; - u64 dma; - - device->bna = bna; - - kva = res_info[BNA_RES_MEM_T_FWTRC].res_u.mem_info.mdl[0].kva; - - /** - * Attach common modules (Diag, SFP, CEE, Port) and claim respective - * DMA memory. - */ - BNA_GET_DMA_ADDR( - &res_info[BNA_RES_MEM_T_COM].res_u.mem_info.mdl[0].dma, dma); - kva = res_info[BNA_RES_MEM_T_COM].res_u.mem_info.mdl[0].kva; - - bfa_nw_cee_attach(&bna->cee, &device->ioc, bna); - bfa_nw_cee_mem_claim(&bna->cee, kva, dma); - kva += bfa_nw_cee_meminfo(); - dma += bfa_nw_cee_meminfo(); - -} - -static void -bna_device_init(struct bna_device *device, struct bna *bna, - struct bna_res_info *res_info) -{ - u64 dma; - - device->bna = bna; - - /** - * Attach IOC and claim: - * 1. DMA memory for IOC attributes - * 2. Kernel memory for FW trace - */ - bfa_nw_ioc_attach(&device->ioc, device, &bfa_iocll_cbfn); - bfa_nw_ioc_pci_init(&device->ioc, &bna->pcidev, BFI_MC_LL); - - BNA_GET_DMA_ADDR( - &res_info[BNA_RES_MEM_T_ATTR].res_u.mem_info.mdl[0].dma, dma); - bfa_nw_ioc_mem_claim(&device->ioc, - res_info[BNA_RES_MEM_T_ATTR].res_u.mem_info.mdl[0].kva, - dma); - - bna_adv_device_init(device, bna, res_info); - /* - * Initialize mbox_mod only after IOC, so that mbox handler - * registration goes through - */ - device->intr_type = - res_info[BNA_RES_INTR_T_MBOX].res_u.intr_info.intr_type; - device->vector = - res_info[BNA_RES_INTR_T_MBOX].res_u.intr_info.idl[0].vector; - bna_mbox_mod_init(&bna->mbox_mod, bna); - - device->ready_cbfn = device->stop_cbfn = NULL; - device->ready_cbarg = device->stop_cbarg = NULL; - - bfa_fsm_set_state(device, bna_device_sm_stopped); -} - -static void -bna_device_uninit(struct bna_device *device) -{ - bna_mbox_mod_uninit(&device->bna->mbox_mod); - - bfa_nw_ioc_detach(&device->ioc); - - device->bna = NULL; -} - -static void -bna_device_cb_port_stopped(void *arg, enum bna_cb_status status) -{ - struct bna_device *device = (struct bna_device *)arg; - - bfa_fsm_send_event(device, DEVICE_E_PORT_STOPPED); -} - -static int -bna_device_status_get(struct bna_device *device) -{ - return device->fsm == (bfa_fsm_t)bna_device_sm_ready; -} - -void -bna_device_enable(struct bna_device *device) -{ - if (device->fsm != (bfa_fsm_t)bna_device_sm_stopped) { - bnad_cb_device_enabled(device->bna->bnad, BNA_CB_BUSY); - return; - } - - device->ready_cbfn = bnad_cb_device_enabled; - device->ready_cbarg = device->bna->bnad; - - bfa_fsm_send_event(device, DEVICE_E_ENABLE); -} - -void -bna_device_disable(struct bna_device *device, enum bna_cleanup_type type) -{ - if (type == BNA_SOFT_CLEANUP) { - bnad_cb_device_disabled(device->bna->bnad, BNA_CB_SUCCESS); - return; - } - - device->stop_cbfn = bnad_cb_device_disabled; - device->stop_cbarg = device->bna->bnad; - - bfa_fsm_send_event(device, DEVICE_E_DISABLE); -} - -static int -bna_device_state_get(struct bna_device *device) -{ - return bfa_sm_to_state(device_sm_table, device->fsm); -} - -const u32 bna_napi_dim_vector[BNA_LOAD_T_MAX][BNA_BIAS_T_MAX] = { - {12, 12}, - {6, 10}, - {5, 10}, - {4, 8}, - {3, 6}, - {3, 6}, - {2, 4}, - {1, 2}, -}; - -/* utils */ - -static void -bna_adv_res_req(struct bna_res_info *res_info) -{ - /* DMA memory for COMMON_MODULE */ - res_info[BNA_RES_MEM_T_COM].res_type = BNA_RES_T_MEM; - res_info[BNA_RES_MEM_T_COM].res_u.mem_info.mem_type = BNA_MEM_T_DMA; - res_info[BNA_RES_MEM_T_COM].res_u.mem_info.num = 1; - res_info[BNA_RES_MEM_T_COM].res_u.mem_info.len = ALIGN( - bfa_nw_cee_meminfo(), PAGE_SIZE); - - /* Virtual memory for retreiving fw_trc */ - res_info[BNA_RES_MEM_T_FWTRC].res_type = BNA_RES_T_MEM; - res_info[BNA_RES_MEM_T_FWTRC].res_u.mem_info.mem_type = BNA_MEM_T_KVA; - res_info[BNA_RES_MEM_T_FWTRC].res_u.mem_info.num = 0; - res_info[BNA_RES_MEM_T_FWTRC].res_u.mem_info.len = 0; - - /* DMA memory for retreiving stats */ - res_info[BNA_RES_MEM_T_STATS].res_type = BNA_RES_T_MEM; - res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.mem_type = BNA_MEM_T_DMA; - res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.num = 1; - res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.len = - ALIGN(BFI_HW_STATS_SIZE, PAGE_SIZE); - - /* Virtual memory for soft stats */ - res_info[BNA_RES_MEM_T_SWSTATS].res_type = BNA_RES_T_MEM; - res_info[BNA_RES_MEM_T_SWSTATS].res_u.mem_info.mem_type = BNA_MEM_T_KVA; - res_info[BNA_RES_MEM_T_SWSTATS].res_u.mem_info.num = 1; - res_info[BNA_RES_MEM_T_SWSTATS].res_u.mem_info.len = - sizeof(struct bna_sw_stats); -} - -static void -bna_sw_stats_get(struct bna *bna, struct bna_sw_stats *sw_stats) -{ - struct bna_tx *tx; - struct bna_txq *txq; - struct bna_rx *rx; - struct bna_rxp *rxp; - struct list_head *qe; - struct list_head *txq_qe; - struct list_head *rxp_qe; - struct list_head *mac_qe; - int i; - - sw_stats->device_state = bna_device_state_get(&bna->device); - sw_stats->port_state = bna_port_state_get(&bna->port); - sw_stats->port_flags = bna->port.flags; - sw_stats->llport_state = bna_llport_state_get(&bna->port.llport); - sw_stats->priority = bna->port.priority; - - i = 0; - list_for_each(qe, &bna->tx_mod.tx_active_q) { - tx = (struct bna_tx *)qe; - sw_stats->tx_stats[i].tx_state = bna_tx_state_get(tx); - sw_stats->tx_stats[i].tx_flags = tx->flags; - - sw_stats->tx_stats[i].num_txqs = 0; - sw_stats->tx_stats[i].txq_bmap[0] = 0; - sw_stats->tx_stats[i].txq_bmap[1] = 0; - list_for_each(txq_qe, &tx->txq_q) { - txq = (struct bna_txq *)txq_qe; - if (txq->txq_id < 32) - sw_stats->tx_stats[i].txq_bmap[0] |= - ((u32)1 << txq->txq_id); - else - sw_stats->tx_stats[i].txq_bmap[1] |= - ((u32) - 1 << (txq->txq_id - 32)); - sw_stats->tx_stats[i].num_txqs++; - } - - sw_stats->tx_stats[i].txf_id = tx->txf.txf_id; - - i++; - } - sw_stats->num_active_tx = i; - - i = 0; - list_for_each(qe, &bna->rx_mod.rx_active_q) { - rx = (struct bna_rx *)qe; - sw_stats->rx_stats[i].rx_state = bna_rx_state_get(rx); - sw_stats->rx_stats[i].rx_flags = rx->rx_flags; - - sw_stats->rx_stats[i].num_rxps = 0; - sw_stats->rx_stats[i].num_rxqs = 0; - sw_stats->rx_stats[i].rxq_bmap[0] = 0; - sw_stats->rx_stats[i].rxq_bmap[1] = 0; - sw_stats->rx_stats[i].cq_bmap[0] = 0; - sw_stats->rx_stats[i].cq_bmap[1] = 0; - list_for_each(rxp_qe, &rx->rxp_q) { - rxp = (struct bna_rxp *)rxp_qe; - - sw_stats->rx_stats[i].num_rxqs += 1; - - if (rxp->type == BNA_RXP_SINGLE) { - if (rxp->rxq.single.only->rxq_id < 32) { - sw_stats->rx_stats[i].rxq_bmap[0] |= - ((u32)1 << - rxp->rxq.single.only->rxq_id); - } else { - sw_stats->rx_stats[i].rxq_bmap[1] |= - ((u32)1 << - (rxp->rxq.single.only->rxq_id - 32)); - } - } else { - if (rxp->rxq.slr.large->rxq_id < 32) { - sw_stats->rx_stats[i].rxq_bmap[0] |= - ((u32)1 << - rxp->rxq.slr.large->rxq_id); - } else { - sw_stats->rx_stats[i].rxq_bmap[1] |= - ((u32)1 << - (rxp->rxq.slr.large->rxq_id - 32)); - } - - if (rxp->rxq.slr.small->rxq_id < 32) { - sw_stats->rx_stats[i].rxq_bmap[0] |= - ((u32)1 << - rxp->rxq.slr.small->rxq_id); - } else { - sw_stats->rx_stats[i].rxq_bmap[1] |= - ((u32)1 << - (rxp->rxq.slr.small->rxq_id - 32)); - } - sw_stats->rx_stats[i].num_rxqs += 1; - } - - if (rxp->cq.cq_id < 32) - sw_stats->rx_stats[i].cq_bmap[0] |= - (1 << rxp->cq.cq_id); - else - sw_stats->rx_stats[i].cq_bmap[1] |= - (1 << (rxp->cq.cq_id - 32)); - - sw_stats->rx_stats[i].num_rxps++; - } - - sw_stats->rx_stats[i].rxf_id = rx->rxf.rxf_id; - sw_stats->rx_stats[i].rxf_state = bna_rxf_state_get(&rx->rxf); - sw_stats->rx_stats[i].rxf_oper_state = rx->rxf.rxf_oper_state; - - sw_stats->rx_stats[i].num_active_ucast = 0; - if (rx->rxf.ucast_active_mac) - sw_stats->rx_stats[i].num_active_ucast++; - list_for_each(mac_qe, &rx->rxf.ucast_active_q) - sw_stats->rx_stats[i].num_active_ucast++; - - sw_stats->rx_stats[i].num_active_mcast = 0; - list_for_each(mac_qe, &rx->rxf.mcast_active_q) - sw_stats->rx_stats[i].num_active_mcast++; - - sw_stats->rx_stats[i].rxmode_active = rx->rxf.rxmode_active; - sw_stats->rx_stats[i].vlan_filter_status = - rx->rxf.vlan_filter_status; - memcpy(sw_stats->rx_stats[i].vlan_filter_table, - rx->rxf.vlan_filter_table, - sizeof(u32) * ((BFI_MAX_VLAN + 1) / 32)); - - sw_stats->rx_stats[i].rss_status = rx->rxf.rss_status; - sw_stats->rx_stats[i].hds_status = rx->rxf.hds_status; - - i++; - } - sw_stats->num_active_rx = i; -} - -static void -bna_fw_cb_stats_get(void *arg, int status) -{ - struct bna *bna = (struct bna *)arg; - u64 *p_stats; - int i, count; - int rxf_count, txf_count; - u64 rxf_bmap, txf_bmap; - - bfa_q_qe_init(&bna->mbox_qe.qe); - - if (status == 0) { - p_stats = (u64 *)bna->stats.hw_stats; - count = sizeof(struct bfi_ll_stats) / sizeof(u64); - for (i = 0; i < count; i++) - p_stats[i] = cpu_to_be64(p_stats[i]); - - rxf_count = 0; - rxf_bmap = (u64)bna->stats.rxf_bmap[0] | - ((u64)bna->stats.rxf_bmap[1] << 32); - for (i = 0; i < BFI_LL_RXF_ID_MAX; i++) - if (rxf_bmap & ((u64)1 << i)) - rxf_count++; - - txf_count = 0; - txf_bmap = (u64)bna->stats.txf_bmap[0] | - ((u64)bna->stats.txf_bmap[1] << 32); - for (i = 0; i < BFI_LL_TXF_ID_MAX; i++) - if (txf_bmap & ((u64)1 << i)) - txf_count++; - - p_stats = (u64 *)&bna->stats.hw_stats->rxf_stats[0] + - ((rxf_count * sizeof(struct bfi_ll_stats_rxf) + - txf_count * sizeof(struct bfi_ll_stats_txf))/ - sizeof(u64)); - - /* Populate the TXF stats from the firmware DMAed copy */ - for (i = (BFI_LL_TXF_ID_MAX - 1); i >= 0; i--) - if (txf_bmap & ((u64)1 << i)) { - p_stats -= sizeof(struct bfi_ll_stats_txf)/ - sizeof(u64); - memcpy(&bna->stats.hw_stats->txf_stats[i], - p_stats, - sizeof(struct bfi_ll_stats_txf)); - } - - /* Populate the RXF stats from the firmware DMAed copy */ - for (i = (BFI_LL_RXF_ID_MAX - 1); i >= 0; i--) - if (rxf_bmap & ((u64)1 << i)) { - p_stats -= sizeof(struct bfi_ll_stats_rxf)/ - sizeof(u64); - memcpy(&bna->stats.hw_stats->rxf_stats[i], - p_stats, - sizeof(struct bfi_ll_stats_rxf)); - } - - bna_sw_stats_get(bna, bna->stats.sw_stats); - bnad_cb_stats_get(bna->bnad, BNA_CB_SUCCESS, &bna->stats); - } else - bnad_cb_stats_get(bna->bnad, BNA_CB_FAIL, &bna->stats); -} - -static void -bna_fw_stats_get(struct bna *bna) -{ - struct bfi_ll_stats_req ll_req; - - bfi_h2i_set(ll_req.mh, BFI_MC_LL, BFI_LL_H2I_STATS_GET_REQ, 0); - ll_req.stats_mask = htons(BFI_LL_STATS_ALL); - - ll_req.rxf_id_mask[0] = htonl(bna->rx_mod.rxf_bmap[0]); - ll_req.rxf_id_mask[1] = htonl(bna->rx_mod.rxf_bmap[1]); - ll_req.txf_id_mask[0] = htonl(bna->tx_mod.txf_bmap[0]); - ll_req.txf_id_mask[1] = htonl(bna->tx_mod.txf_bmap[1]); - - ll_req.host_buffer.a32.addr_hi = bna->hw_stats_dma.msb; - ll_req.host_buffer.a32.addr_lo = bna->hw_stats_dma.lsb; - - bna_mbox_qe_fill(&bna->mbox_qe, &ll_req, sizeof(ll_req), - bna_fw_cb_stats_get, bna); - bna_mbox_send(bna, &bna->mbox_qe); - - bna->stats.rxf_bmap[0] = bna->rx_mod.rxf_bmap[0]; - bna->stats.rxf_bmap[1] = bna->rx_mod.rxf_bmap[1]; - bna->stats.txf_bmap[0] = bna->tx_mod.txf_bmap[0]; - bna->stats.txf_bmap[1] = bna->tx_mod.txf_bmap[1]; -} - -void -bna_stats_get(struct bna *bna) -{ - if (bna_device_status_get(&bna->device)) - bna_fw_stats_get(bna); - else - bnad_cb_stats_get(bna->bnad, BNA_CB_FAIL, &bna->stats); -} - -/* IB */ -static void -bna_ib_coalescing_timeo_set(struct bna_ib *ib, u8 coalescing_timeo) -{ - ib->ib_config.coalescing_timeo = coalescing_timeo; - - if (ib->start_count) - ib->door_bell.doorbell_ack = BNA_DOORBELL_IB_INT_ACK( - (u32)ib->ib_config.coalescing_timeo, 0); -} - -/* RxF */ -void -bna_rxf_adv_init(struct bna_rxf *rxf, - struct bna_rx *rx, - struct bna_rx_config *q_config) -{ - switch (q_config->rxp_type) { - case BNA_RXP_SINGLE: - /* No-op */ - break; - case BNA_RXP_SLR: - rxf->ctrl_flags |= BNA_RXF_CF_SM_LG_RXQ; - break; - case BNA_RXP_HDS: - rxf->hds_cfg.hdr_type = q_config->hds_config.hdr_type; - rxf->hds_cfg.header_size = - q_config->hds_config.header_size; - rxf->forced_offset = 0; - break; - default: - break; - } - - if (q_config->rss_status == BNA_STATUS_T_ENABLED) { - rxf->ctrl_flags |= BNA_RXF_CF_RSS_ENABLE; - rxf->rss_cfg.hash_type = q_config->rss_config.hash_type; - rxf->rss_cfg.hash_mask = q_config->rss_config.hash_mask; - memcpy(&rxf->rss_cfg.toeplitz_hash_key[0], - &q_config->rss_config.toeplitz_hash_key[0], - sizeof(rxf->rss_cfg.toeplitz_hash_key)); - } -} - -static void -rxf_fltr_mbox_cmd(struct bna_rxf *rxf, u8 cmd, enum bna_status status) -{ - struct bfi_ll_rxf_req req; - - bfi_h2i_set(req.mh, BFI_MC_LL, cmd, 0); - - req.rxf_id = rxf->rxf_id; - req.enable = status; - - bna_mbox_qe_fill(&rxf->mbox_qe, &req, sizeof(req), - rxf_cb_cam_fltr_mbox_cmd, rxf); - - bna_mbox_send(rxf->rx->bna, &rxf->mbox_qe); -} - -int -rxf_process_packet_filter_ucast(struct bna_rxf *rxf) -{ - struct bna_mac *mac = NULL; - struct list_head *qe; - - /* Add additional MAC entries */ - if (!list_empty(&rxf->ucast_pending_add_q)) { - bfa_q_deq(&rxf->ucast_pending_add_q, &qe); - bfa_q_qe_init(qe); - mac = (struct bna_mac *)qe; - rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_UCAST_ADD_REQ, mac); - list_add_tail(&mac->qe, &rxf->ucast_active_q); - return 1; - } - - /* Delete MAC addresses previousely added */ - if (!list_empty(&rxf->ucast_pending_del_q)) { - bfa_q_deq(&rxf->ucast_pending_del_q, &qe); - bfa_q_qe_init(qe); - mac = (struct bna_mac *)qe; - rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_UCAST_DEL_REQ, mac); - bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod, mac); - return 1; - } - - return 0; -} - -int -rxf_process_packet_filter_promisc(struct bna_rxf *rxf) -{ - struct bna *bna = rxf->rx->bna; - - /* Enable/disable promiscuous mode */ - if (is_promisc_enable(rxf->rxmode_pending, - rxf->rxmode_pending_bitmask)) { - /* move promisc configuration from pending -> active */ - promisc_inactive(rxf->rxmode_pending, - rxf->rxmode_pending_bitmask); - rxf->rxmode_active |= BNA_RXMODE_PROMISC; - - /* Disable VLAN filter to allow all VLANs */ - __rxf_vlan_filter_set(rxf, BNA_STATUS_T_DISABLED); - rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_PROMISCUOUS_SET_REQ, - BNA_STATUS_T_ENABLED); - return 1; - } else if (is_promisc_disable(rxf->rxmode_pending, - rxf->rxmode_pending_bitmask)) { - /* move promisc configuration from pending -> active */ - promisc_inactive(rxf->rxmode_pending, - rxf->rxmode_pending_bitmask); - rxf->rxmode_active &= ~BNA_RXMODE_PROMISC; - bna->rxf_promisc_id = BFI_MAX_RXF; - - /* Revert VLAN filter */ - __rxf_vlan_filter_set(rxf, rxf->vlan_filter_status); - rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_PROMISCUOUS_SET_REQ, - BNA_STATUS_T_DISABLED); - return 1; - } - - return 0; -} - -int -rxf_process_packet_filter_allmulti(struct bna_rxf *rxf) -{ - /* Enable/disable allmulti mode */ - if (is_allmulti_enable(rxf->rxmode_pending, - rxf->rxmode_pending_bitmask)) { - /* move allmulti configuration from pending -> active */ - allmulti_inactive(rxf->rxmode_pending, - rxf->rxmode_pending_bitmask); - rxf->rxmode_active |= BNA_RXMODE_ALLMULTI; - - rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_FILTER_REQ, - BNA_STATUS_T_ENABLED); - return 1; - } else if (is_allmulti_disable(rxf->rxmode_pending, - rxf->rxmode_pending_bitmask)) { - /* move allmulti configuration from pending -> active */ - allmulti_inactive(rxf->rxmode_pending, - rxf->rxmode_pending_bitmask); - rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI; - - rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_FILTER_REQ, - BNA_STATUS_T_DISABLED); - return 1; - } - - return 0; -} - -int -rxf_clear_packet_filter_ucast(struct bna_rxf *rxf) -{ - struct bna_mac *mac = NULL; - struct list_head *qe; - - /* 1. delete pending ucast entries */ - if (!list_empty(&rxf->ucast_pending_del_q)) { - bfa_q_deq(&rxf->ucast_pending_del_q, &qe); - bfa_q_qe_init(qe); - mac = (struct bna_mac *)qe; - rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_UCAST_DEL_REQ, mac); - bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod, mac); - return 1; - } - - /* 2. clear active ucast entries; move them to pending_add_q */ - if (!list_empty(&rxf->ucast_active_q)) { - bfa_q_deq(&rxf->ucast_active_q, &qe); - bfa_q_qe_init(qe); - mac = (struct bna_mac *)qe; - rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_UCAST_DEL_REQ, mac); - list_add_tail(&mac->qe, &rxf->ucast_pending_add_q); - return 1; - } - - return 0; -} - -int -rxf_clear_packet_filter_promisc(struct bna_rxf *rxf) -{ - struct bna *bna = rxf->rx->bna; - - /* 6. Execute pending promisc mode disable command */ - if (is_promisc_disable(rxf->rxmode_pending, - rxf->rxmode_pending_bitmask)) { - /* move promisc configuration from pending -> active */ - promisc_inactive(rxf->rxmode_pending, - rxf->rxmode_pending_bitmask); - rxf->rxmode_active &= ~BNA_RXMODE_PROMISC; - bna->rxf_promisc_id = BFI_MAX_RXF; - - /* Revert VLAN filter */ - __rxf_vlan_filter_set(rxf, rxf->vlan_filter_status); - rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_PROMISCUOUS_SET_REQ, - BNA_STATUS_T_DISABLED); - return 1; - } - - /* 7. Clear active promisc mode; move it to pending enable */ - if (rxf->rxmode_active & BNA_RXMODE_PROMISC) { - /* move promisc configuration from active -> pending */ - promisc_enable(rxf->rxmode_pending, - rxf->rxmode_pending_bitmask); - rxf->rxmode_active &= ~BNA_RXMODE_PROMISC; - - /* Revert VLAN filter */ - __rxf_vlan_filter_set(rxf, rxf->vlan_filter_status); - rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_PROMISCUOUS_SET_REQ, - BNA_STATUS_T_DISABLED); - return 1; - } - - return 0; -} - -int -rxf_clear_packet_filter_allmulti(struct bna_rxf *rxf) -{ - /* 10. Execute pending allmulti mode disable command */ - if (is_allmulti_disable(rxf->rxmode_pending, - rxf->rxmode_pending_bitmask)) { - /* move allmulti configuration from pending -> active */ - allmulti_inactive(rxf->rxmode_pending, - rxf->rxmode_pending_bitmask); - rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI; - rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_FILTER_REQ, - BNA_STATUS_T_DISABLED); - return 1; - } - - /* 11. Clear active allmulti mode; move it to pending enable */ - if (rxf->rxmode_active & BNA_RXMODE_ALLMULTI) { - /* move allmulti configuration from active -> pending */ - allmulti_enable(rxf->rxmode_pending, - rxf->rxmode_pending_bitmask); - rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI; - rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_FILTER_REQ, - BNA_STATUS_T_DISABLED); - return 1; - } - - return 0; -} - -void -rxf_reset_packet_filter_ucast(struct bna_rxf *rxf) -{ - struct list_head *qe; - struct bna_mac *mac; - - /* 1. Move active ucast entries to pending_add_q */ - while (!list_empty(&rxf->ucast_active_q)) { - bfa_q_deq(&rxf->ucast_active_q, &qe); - bfa_q_qe_init(qe); - list_add_tail(qe, &rxf->ucast_pending_add_q); - } - - /* 2. Throw away delete pending ucast entries */ - while (!list_empty(&rxf->ucast_pending_del_q)) { - bfa_q_deq(&rxf->ucast_pending_del_q, &qe); - bfa_q_qe_init(qe); - mac = (struct bna_mac *)qe; - bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod, mac); - } -} - -void -rxf_reset_packet_filter_promisc(struct bna_rxf *rxf) -{ - struct bna *bna = rxf->rx->bna; - - /* 6. Clear pending promisc mode disable */ - if (is_promisc_disable(rxf->rxmode_pending, - rxf->rxmode_pending_bitmask)) { - promisc_inactive(rxf->rxmode_pending, - rxf->rxmode_pending_bitmask); - rxf->rxmode_active &= ~BNA_RXMODE_PROMISC; - bna->rxf_promisc_id = BFI_MAX_RXF; - } - - /* 7. Move promisc mode config from active -> pending */ - if (rxf->rxmode_active & BNA_RXMODE_PROMISC) { - promisc_enable(rxf->rxmode_pending, - rxf->rxmode_pending_bitmask); - rxf->rxmode_active &= ~BNA_RXMODE_PROMISC; - } - -} - -void -rxf_reset_packet_filter_allmulti(struct bna_rxf *rxf) -{ - /* 10. Clear pending allmulti mode disable */ - if (is_allmulti_disable(rxf->rxmode_pending, - rxf->rxmode_pending_bitmask)) { - allmulti_inactive(rxf->rxmode_pending, - rxf->rxmode_pending_bitmask); - rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI; - } - - /* 11. Move allmulti mode config from active -> pending */ - if (rxf->rxmode_active & BNA_RXMODE_ALLMULTI) { - allmulti_enable(rxf->rxmode_pending, - rxf->rxmode_pending_bitmask); - rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI; - } -} - -/** - * Should only be called by bna_rxf_mode_set. - * Helps deciding if h/w configuration is needed or not. - * Returns: - * 0 = no h/w change - * 1 = need h/w change - */ -static int -rxf_promisc_enable(struct bna_rxf *rxf) -{ - struct bna *bna = rxf->rx->bna; - int ret = 0; - - /* There can not be any pending disable command */ - - /* Do nothing if pending enable or already enabled */ - if (is_promisc_enable(rxf->rxmode_pending, - rxf->rxmode_pending_bitmask) || - (rxf->rxmode_active & BNA_RXMODE_PROMISC)) { - /* Schedule enable */ - } else { - /* Promisc mode should not be active in the system */ - promisc_enable(rxf->rxmode_pending, - rxf->rxmode_pending_bitmask); - bna->rxf_promisc_id = rxf->rxf_id; - ret = 1; - } - - return ret; -} - -/** - * Should only be called by bna_rxf_mode_set. - * Helps deciding if h/w configuration is needed or not. - * Returns: - * 0 = no h/w change - * 1 = need h/w change - */ -static int -rxf_promisc_disable(struct bna_rxf *rxf) -{ - struct bna *bna = rxf->rx->bna; - int ret = 0; - - /* There can not be any pending disable */ - - /* Turn off pending enable command , if any */ - if (is_promisc_enable(rxf->rxmode_pending, - rxf->rxmode_pending_bitmask)) { - /* Promisc mode should not be active */ - /* system promisc state should be pending */ - promisc_inactive(rxf->rxmode_pending, - rxf->rxmode_pending_bitmask); - /* Remove the promisc state from the system */ - bna->rxf_promisc_id = BFI_MAX_RXF; - - /* Schedule disable */ - } else if (rxf->rxmode_active & BNA_RXMODE_PROMISC) { - /* Promisc mode should be active in the system */ - promisc_disable(rxf->rxmode_pending, - rxf->rxmode_pending_bitmask); - ret = 1; - - /* Do nothing if already disabled */ - } else { - } - - return ret; -} - -/** - * Should only be called by bna_rxf_mode_set. - * Helps deciding if h/w configuration is needed or not. - * Returns: - * 0 = no h/w change - * 1 = need h/w change - */ -static int -rxf_allmulti_enable(struct bna_rxf *rxf) -{ - int ret = 0; - - /* There can not be any pending disable command */ - - /* Do nothing if pending enable or already enabled */ - if (is_allmulti_enable(rxf->rxmode_pending, - rxf->rxmode_pending_bitmask) || - (rxf->rxmode_active & BNA_RXMODE_ALLMULTI)) { - /* Schedule enable */ - } else { - allmulti_enable(rxf->rxmode_pending, - rxf->rxmode_pending_bitmask); - ret = 1; - } - - return ret; -} - -/** - * Should only be called by bna_rxf_mode_set. - * Helps deciding if h/w configuration is needed or not. - * Returns: - * 0 = no h/w change - * 1 = need h/w change - */ -static int -rxf_allmulti_disable(struct bna_rxf *rxf) -{ - int ret = 0; - - /* There can not be any pending disable */ - - /* Turn off pending enable command , if any */ - if (is_allmulti_enable(rxf->rxmode_pending, - rxf->rxmode_pending_bitmask)) { - /* Allmulti mode should not be active */ - allmulti_inactive(rxf->rxmode_pending, - rxf->rxmode_pending_bitmask); - - /* Schedule disable */ - } else if (rxf->rxmode_active & BNA_RXMODE_ALLMULTI) { - allmulti_disable(rxf->rxmode_pending, - rxf->rxmode_pending_bitmask); - ret = 1; - } - - return ret; -} - -/* RxF <- bnad */ -enum bna_cb_status -bna_rx_mode_set(struct bna_rx *rx, enum bna_rxmode new_mode, - enum bna_rxmode bitmask, - void (*cbfn)(struct bnad *, struct bna_rx *, - enum bna_cb_status)) -{ - struct bna_rxf *rxf = &rx->rxf; - int need_hw_config = 0; - - /* Process the commands */ - - if (is_promisc_enable(new_mode, bitmask)) { - /* If promisc mode is already enabled elsewhere in the system */ - if ((rx->bna->rxf_promisc_id != BFI_MAX_RXF) && - (rx->bna->rxf_promisc_id != rxf->rxf_id)) - goto err_return; - if (rxf_promisc_enable(rxf)) - need_hw_config = 1; - } else if (is_promisc_disable(new_mode, bitmask)) { - if (rxf_promisc_disable(rxf)) - need_hw_config = 1; - } - - if (is_allmulti_enable(new_mode, bitmask)) { - if (rxf_allmulti_enable(rxf)) - need_hw_config = 1; - } else if (is_allmulti_disable(new_mode, bitmask)) { - if (rxf_allmulti_disable(rxf)) - need_hw_config = 1; - } - - /* Trigger h/w if needed */ - - if (need_hw_config) { - rxf->cam_fltr_cbfn = cbfn; - rxf->cam_fltr_cbarg = rx->bna->bnad; - bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD); - } else if (cbfn) - (*cbfn)(rx->bna->bnad, rx, BNA_CB_SUCCESS); - - return BNA_CB_SUCCESS; - -err_return: - return BNA_CB_FAIL; -} - -void -/* RxF <- bnad */ -bna_rx_vlanfilter_enable(struct bna_rx *rx) -{ - struct bna_rxf *rxf = &rx->rxf; - - if (rxf->vlan_filter_status == BNA_STATUS_T_DISABLED) { - rxf->rxf_flags |= BNA_RXF_FL_VLAN_CONFIG_PENDING; - rxf->vlan_filter_status = BNA_STATUS_T_ENABLED; - bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD); - } -} - -/* Rx */ - -/* Rx <- bnad */ -void -bna_rx_coalescing_timeo_set(struct bna_rx *rx, int coalescing_timeo) -{ - struct bna_rxp *rxp; - struct list_head *qe; - - list_for_each(qe, &rx->rxp_q) { - rxp = (struct bna_rxp *)qe; - rxp->cq.ccb->rx_coalescing_timeo = coalescing_timeo; - bna_ib_coalescing_timeo_set(rxp->cq.ib, coalescing_timeo); - } -} - -/* Rx <- bnad */ -void -bna_rx_dim_reconfig(struct bna *bna, const u32 vector[][BNA_BIAS_T_MAX]) -{ - int i, j; - - for (i = 0; i < BNA_LOAD_T_MAX; i++) - for (j = 0; j < BNA_BIAS_T_MAX; j++) - bna->rx_mod.dim_vector[i][j] = vector[i][j]; -} - -/* Rx <- bnad */ -void -bna_rx_dim_update(struct bna_ccb *ccb) -{ - struct bna *bna = ccb->cq->rx->bna; - u32 load, bias; - u32 pkt_rt, small_rt, large_rt; - u8 coalescing_timeo; - - if ((ccb->pkt_rate.small_pkt_cnt == 0) && - (ccb->pkt_rate.large_pkt_cnt == 0)) - return; - - /* Arrive at preconfigured coalescing timeo value based on pkt rate */ - - small_rt = ccb->pkt_rate.small_pkt_cnt; - large_rt = ccb->pkt_rate.large_pkt_cnt; - - pkt_rt = small_rt + large_rt; - - if (pkt_rt < BNA_PKT_RATE_10K) - load = BNA_LOAD_T_LOW_4; - else if (pkt_rt < BNA_PKT_RATE_20K) - load = BNA_LOAD_T_LOW_3; - else if (pkt_rt < BNA_PKT_RATE_30K) - load = BNA_LOAD_T_LOW_2; - else if (pkt_rt < BNA_PKT_RATE_40K) - load = BNA_LOAD_T_LOW_1; - else if (pkt_rt < BNA_PKT_RATE_50K) - load = BNA_LOAD_T_HIGH_1; - else if (pkt_rt < BNA_PKT_RATE_60K) - load = BNA_LOAD_T_HIGH_2; - else if (pkt_rt < BNA_PKT_RATE_80K) - load = BNA_LOAD_T_HIGH_3; - else - load = BNA_LOAD_T_HIGH_4; - - if (small_rt > (large_rt << 1)) - bias = 0; - else - bias = 1; - - ccb->pkt_rate.small_pkt_cnt = 0; - ccb->pkt_rate.large_pkt_cnt = 0; - - coalescing_timeo = bna->rx_mod.dim_vector[load][bias]; - ccb->rx_coalescing_timeo = coalescing_timeo; - - /* Set it to IB */ - bna_ib_coalescing_timeo_set(ccb->cq->ib, coalescing_timeo); -} - -/* Tx */ -/* TX <- bnad */ -void -bna_tx_coalescing_timeo_set(struct bna_tx *tx, int coalescing_timeo) -{ - struct bna_txq *txq; - struct list_head *qe; - - list_for_each(qe, &tx->txq_q) { - txq = (struct bna_txq *)qe; - bna_ib_coalescing_timeo_set(txq->ib, coalescing_timeo); - } -} - -/* - * Private data - */ - -struct bna_ritseg_pool_cfg { - u32 pool_size; - u32 pool_entry_size; -}; -init_ritseg_pool(ritseg_pool_cfg); - -/* - * Private functions - */ -static void -bna_ucam_mod_init(struct bna_ucam_mod *ucam_mod, struct bna *bna, - struct bna_res_info *res_info) -{ - int i; - - ucam_mod->ucmac = (struct bna_mac *) - res_info[BNA_RES_MEM_T_UCMAC_ARRAY].res_u.mem_info.mdl[0].kva; - - INIT_LIST_HEAD(&ucam_mod->free_q); - for (i = 0; i < BFI_MAX_UCMAC; i++) { - bfa_q_qe_init(&ucam_mod->ucmac[i].qe); - list_add_tail(&ucam_mod->ucmac[i].qe, &ucam_mod->free_q); - } - - ucam_mod->bna = bna; -} - -static void -bna_ucam_mod_uninit(struct bna_ucam_mod *ucam_mod) -{ - struct list_head *qe; - int i = 0; - - list_for_each(qe, &ucam_mod->free_q) - i++; - - ucam_mod->bna = NULL; -} - -static void -bna_mcam_mod_init(struct bna_mcam_mod *mcam_mod, struct bna *bna, - struct bna_res_info *res_info) -{ - int i; - - mcam_mod->mcmac = (struct bna_mac *) - res_info[BNA_RES_MEM_T_MCMAC_ARRAY].res_u.mem_info.mdl[0].kva; - - INIT_LIST_HEAD(&mcam_mod->free_q); - for (i = 0; i < BFI_MAX_MCMAC; i++) { - bfa_q_qe_init(&mcam_mod->mcmac[i].qe); - list_add_tail(&mcam_mod->mcmac[i].qe, &mcam_mod->free_q); - } - - mcam_mod->bna = bna; -} - -static void -bna_mcam_mod_uninit(struct bna_mcam_mod *mcam_mod) -{ - struct list_head *qe; - int i = 0; - - list_for_each(qe, &mcam_mod->free_q) - i++; - - mcam_mod->bna = NULL; -} - -static void -bna_rit_mod_init(struct bna_rit_mod *rit_mod, - struct bna_res_info *res_info) -{ - int i; - int j; - int count; - int offset; - - rit_mod->rit = (struct bna_rit_entry *) - res_info[BNA_RES_MEM_T_RIT_ENTRY].res_u.mem_info.mdl[0].kva; - rit_mod->rit_segment = (struct bna_rit_segment *) - res_info[BNA_RES_MEM_T_RIT_SEGMENT].res_u.mem_info.mdl[0].kva; - - count = 0; - offset = 0; - for (i = 0; i < BFI_RIT_SEG_TOTAL_POOLS; i++) { - INIT_LIST_HEAD(&rit_mod->rit_seg_pool[i]); - for (j = 0; j < ritseg_pool_cfg[i].pool_size; j++) { - bfa_q_qe_init(&rit_mod->rit_segment[count].qe); - rit_mod->rit_segment[count].max_rit_size = - ritseg_pool_cfg[i].pool_entry_size; - rit_mod->rit_segment[count].rit_offset = offset; - rit_mod->rit_segment[count].rit = - &rit_mod->rit[offset]; - list_add_tail(&rit_mod->rit_segment[count].qe, - &rit_mod->rit_seg_pool[i]); - count++; - offset += ritseg_pool_cfg[i].pool_entry_size; - } - } -} - -/* - * Public functions - */ - -/* Called during probe(), before calling bna_init() */ -void -bna_res_req(struct bna_res_info *res_info) -{ - bna_adv_res_req(res_info); - - /* DMA memory for retrieving IOC attributes */ - res_info[BNA_RES_MEM_T_ATTR].res_type = BNA_RES_T_MEM; - res_info[BNA_RES_MEM_T_ATTR].res_u.mem_info.mem_type = BNA_MEM_T_DMA; - res_info[BNA_RES_MEM_T_ATTR].res_u.mem_info.num = 1; - res_info[BNA_RES_MEM_T_ATTR].res_u.mem_info.len = - ALIGN(bfa_nw_ioc_meminfo(), PAGE_SIZE); - - /* DMA memory for index segment of an IB */ - res_info[BNA_RES_MEM_T_IBIDX].res_type = BNA_RES_T_MEM; - res_info[BNA_RES_MEM_T_IBIDX].res_u.mem_info.mem_type = BNA_MEM_T_DMA; - res_info[BNA_RES_MEM_T_IBIDX].res_u.mem_info.len = - BFI_IBIDX_SIZE * BFI_IBIDX_MAX_SEGSIZE; - res_info[BNA_RES_MEM_T_IBIDX].res_u.mem_info.num = BFI_MAX_IB; - - /* Virtual memory for IB objects - stored by IB module */ - res_info[BNA_RES_MEM_T_IB_ARRAY].res_type = BNA_RES_T_MEM; - res_info[BNA_RES_MEM_T_IB_ARRAY].res_u.mem_info.mem_type = - BNA_MEM_T_KVA; - res_info[BNA_RES_MEM_T_IB_ARRAY].res_u.mem_info.num = 1; - res_info[BNA_RES_MEM_T_IB_ARRAY].res_u.mem_info.len = - BFI_MAX_IB * sizeof(struct bna_ib); - - /* Virtual memory for intr objects - stored by IB module */ - res_info[BNA_RES_MEM_T_INTR_ARRAY].res_type = BNA_RES_T_MEM; - res_info[BNA_RES_MEM_T_INTR_ARRAY].res_u.mem_info.mem_type = - BNA_MEM_T_KVA; - res_info[BNA_RES_MEM_T_INTR_ARRAY].res_u.mem_info.num = 1; - res_info[BNA_RES_MEM_T_INTR_ARRAY].res_u.mem_info.len = - BFI_MAX_IB * sizeof(struct bna_intr); - - /* Virtual memory for idx_seg objects - stored by IB module */ - res_info[BNA_RES_MEM_T_IDXSEG_ARRAY].res_type = BNA_RES_T_MEM; - res_info[BNA_RES_MEM_T_IDXSEG_ARRAY].res_u.mem_info.mem_type = - BNA_MEM_T_KVA; - res_info[BNA_RES_MEM_T_IDXSEG_ARRAY].res_u.mem_info.num = 1; - res_info[BNA_RES_MEM_T_IDXSEG_ARRAY].res_u.mem_info.len = - BFI_IBIDX_TOTAL_SEGS * sizeof(struct bna_ibidx_seg); - - /* Virtual memory for Tx objects - stored by Tx module */ - res_info[BNA_RES_MEM_T_TX_ARRAY].res_type = BNA_RES_T_MEM; - res_info[BNA_RES_MEM_T_TX_ARRAY].res_u.mem_info.mem_type = - BNA_MEM_T_KVA; - res_info[BNA_RES_MEM_T_TX_ARRAY].res_u.mem_info.num = 1; - res_info[BNA_RES_MEM_T_TX_ARRAY].res_u.mem_info.len = - BFI_MAX_TXQ * sizeof(struct bna_tx); - - /* Virtual memory for TxQ - stored by Tx module */ - res_info[BNA_RES_MEM_T_TXQ_ARRAY].res_type = BNA_RES_T_MEM; - res_info[BNA_RES_MEM_T_TXQ_ARRAY].res_u.mem_info.mem_type = - BNA_MEM_T_KVA; - res_info[BNA_RES_MEM_T_TXQ_ARRAY].res_u.mem_info.num = 1; - res_info[BNA_RES_MEM_T_TXQ_ARRAY].res_u.mem_info.len = - BFI_MAX_TXQ * sizeof(struct bna_txq); - - /* Virtual memory for Rx objects - stored by Rx module */ - res_info[BNA_RES_MEM_T_RX_ARRAY].res_type = BNA_RES_T_MEM; - res_info[BNA_RES_MEM_T_RX_ARRAY].res_u.mem_info.mem_type = - BNA_MEM_T_KVA; - res_info[BNA_RES_MEM_T_RX_ARRAY].res_u.mem_info.num = 1; - res_info[BNA_RES_MEM_T_RX_ARRAY].res_u.mem_info.len = - BFI_MAX_RXQ * sizeof(struct bna_rx); - - /* Virtual memory for RxPath - stored by Rx module */ - res_info[BNA_RES_MEM_T_RXP_ARRAY].res_type = BNA_RES_T_MEM; - res_info[BNA_RES_MEM_T_RXP_ARRAY].res_u.mem_info.mem_type = - BNA_MEM_T_KVA; - res_info[BNA_RES_MEM_T_RXP_ARRAY].res_u.mem_info.num = 1; - res_info[BNA_RES_MEM_T_RXP_ARRAY].res_u.mem_info.len = - BFI_MAX_RXQ * sizeof(struct bna_rxp); - - /* Virtual memory for RxQ - stored by Rx module */ - res_info[BNA_RES_MEM_T_RXQ_ARRAY].res_type = BNA_RES_T_MEM; - res_info[BNA_RES_MEM_T_RXQ_ARRAY].res_u.mem_info.mem_type = - BNA_MEM_T_KVA; - res_info[BNA_RES_MEM_T_RXQ_ARRAY].res_u.mem_info.num = 1; - res_info[BNA_RES_MEM_T_RXQ_ARRAY].res_u.mem_info.len = - BFI_MAX_RXQ * sizeof(struct bna_rxq); - - /* Virtual memory for Unicast MAC address - stored by ucam module */ - res_info[BNA_RES_MEM_T_UCMAC_ARRAY].res_type = BNA_RES_T_MEM; - res_info[BNA_RES_MEM_T_UCMAC_ARRAY].res_u.mem_info.mem_type = - BNA_MEM_T_KVA; - res_info[BNA_RES_MEM_T_UCMAC_ARRAY].res_u.mem_info.num = 1; - res_info[BNA_RES_MEM_T_UCMAC_ARRAY].res_u.mem_info.len = - BFI_MAX_UCMAC * sizeof(struct bna_mac); - - /* Virtual memory for Multicast MAC address - stored by mcam module */ - res_info[BNA_RES_MEM_T_MCMAC_ARRAY].res_type = BNA_RES_T_MEM; - res_info[BNA_RES_MEM_T_MCMAC_ARRAY].res_u.mem_info.mem_type = - BNA_MEM_T_KVA; - res_info[BNA_RES_MEM_T_MCMAC_ARRAY].res_u.mem_info.num = 1; - res_info[BNA_RES_MEM_T_MCMAC_ARRAY].res_u.mem_info.len = - BFI_MAX_MCMAC * sizeof(struct bna_mac); - - /* Virtual memory for RIT entries */ - res_info[BNA_RES_MEM_T_RIT_ENTRY].res_type = BNA_RES_T_MEM; - res_info[BNA_RES_MEM_T_RIT_ENTRY].res_u.mem_info.mem_type = - BNA_MEM_T_KVA; - res_info[BNA_RES_MEM_T_RIT_ENTRY].res_u.mem_info.num = 1; - res_info[BNA_RES_MEM_T_RIT_ENTRY].res_u.mem_info.len = - BFI_MAX_RIT_SIZE * sizeof(struct bna_rit_entry); - - /* Virtual memory for RIT segment table */ - res_info[BNA_RES_MEM_T_RIT_SEGMENT].res_type = BNA_RES_T_MEM; - res_info[BNA_RES_MEM_T_RIT_SEGMENT].res_u.mem_info.mem_type = - BNA_MEM_T_KVA; - res_info[BNA_RES_MEM_T_RIT_SEGMENT].res_u.mem_info.num = 1; - res_info[BNA_RES_MEM_T_RIT_SEGMENT].res_u.mem_info.len = - BFI_RIT_TOTAL_SEGS * sizeof(struct bna_rit_segment); - - /* Interrupt resource for mailbox interrupt */ - res_info[BNA_RES_INTR_T_MBOX].res_type = BNA_RES_T_INTR; - res_info[BNA_RES_INTR_T_MBOX].res_u.intr_info.intr_type = - BNA_INTR_T_MSIX; - res_info[BNA_RES_INTR_T_MBOX].res_u.intr_info.num = 1; -} - -/* Called during probe() */ -void -bna_init(struct bna *bna, struct bnad *bnad, struct bfa_pcidev *pcidev, - struct bna_res_info *res_info) -{ - bna->bnad = bnad; - bna->pcidev = *pcidev; - - bna->stats.hw_stats = (struct bfi_ll_stats *) - res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.mdl[0].kva; - bna->hw_stats_dma.msb = - res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.mdl[0].dma.msb; - bna->hw_stats_dma.lsb = - res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.mdl[0].dma.lsb; - bna->stats.sw_stats = (struct bna_sw_stats *) - res_info[BNA_RES_MEM_T_SWSTATS].res_u.mem_info.mdl[0].kva; - - bna->regs.page_addr = bna->pcidev.pci_bar_kva + - reg_offset[bna->pcidev.pci_func].page_addr; - bna->regs.fn_int_status = bna->pcidev.pci_bar_kva + - reg_offset[bna->pcidev.pci_func].fn_int_status; - bna->regs.fn_int_mask = bna->pcidev.pci_bar_kva + - reg_offset[bna->pcidev.pci_func].fn_int_mask; - - if (bna->pcidev.pci_func < 3) - bna->port_num = 0; - else - bna->port_num = 1; - - /* Also initializes diag, cee, sfp, phy_port and mbox_mod */ - bna_device_init(&bna->device, bna, res_info); - - bna_port_init(&bna->port, bna); - - bna_tx_mod_init(&bna->tx_mod, bna, res_info); - - bna_rx_mod_init(&bna->rx_mod, bna, res_info); - - bna_ib_mod_init(&bna->ib_mod, bna, res_info); - - bna_rit_mod_init(&bna->rit_mod, res_info); - - bna_ucam_mod_init(&bna->ucam_mod, bna, res_info); - - bna_mcam_mod_init(&bna->mcam_mod, bna, res_info); - - bna->rxf_promisc_id = BFI_MAX_RXF; - - /* Mbox q element for posting stat request to f/w */ - bfa_q_qe_init(&bna->mbox_qe.qe); -} - -void -bna_uninit(struct bna *bna) -{ - bna_mcam_mod_uninit(&bna->mcam_mod); - - bna_ucam_mod_uninit(&bna->ucam_mod); - - bna_ib_mod_uninit(&bna->ib_mod); - - bna_rx_mod_uninit(&bna->rx_mod); - - bna_tx_mod_uninit(&bna->tx_mod); - - bna_port_uninit(&bna->port); - - bna_device_uninit(&bna->device); - - bna->bnad = NULL; -} - -struct bna_mac * -bna_ucam_mod_mac_get(struct bna_ucam_mod *ucam_mod) -{ - struct list_head *qe; - - if (list_empty(&ucam_mod->free_q)) - return NULL; - - bfa_q_deq(&ucam_mod->free_q, &qe); - - return (struct bna_mac *)qe; -} - -void -bna_ucam_mod_mac_put(struct bna_ucam_mod *ucam_mod, struct bna_mac *mac) -{ - list_add_tail(&mac->qe, &ucam_mod->free_q); -} - -struct bna_mac * -bna_mcam_mod_mac_get(struct bna_mcam_mod *mcam_mod) -{ - struct list_head *qe; - - if (list_empty(&mcam_mod->free_q)) - return NULL; - - bfa_q_deq(&mcam_mod->free_q, &qe); - - return (struct bna_mac *)qe; -} - -void -bna_mcam_mod_mac_put(struct bna_mcam_mod *mcam_mod, struct bna_mac *mac) -{ - list_add_tail(&mac->qe, &mcam_mod->free_q); -} - -/** - * Note: This should be called in the same locking context as the call to - * bna_rit_mod_seg_get() - */ -int -bna_rit_mod_can_satisfy(struct bna_rit_mod *rit_mod, int seg_size) -{ - int i; - - /* Select the pool for seg_size */ - for (i = 0; i < BFI_RIT_SEG_TOTAL_POOLS; i++) { - if (seg_size <= ritseg_pool_cfg[i].pool_entry_size) - break; - } - - if (i == BFI_RIT_SEG_TOTAL_POOLS) - return 0; - - if (list_empty(&rit_mod->rit_seg_pool[i])) - return 0; - - return 1; -} - -struct bna_rit_segment * -bna_rit_mod_seg_get(struct bna_rit_mod *rit_mod, int seg_size) -{ - struct bna_rit_segment *seg; - struct list_head *qe; - int i; - - /* Select the pool for seg_size */ - for (i = 0; i < BFI_RIT_SEG_TOTAL_POOLS; i++) { - if (seg_size <= ritseg_pool_cfg[i].pool_entry_size) - break; - } - - if (i == BFI_RIT_SEG_TOTAL_POOLS) - return NULL; - - if (list_empty(&rit_mod->rit_seg_pool[i])) - return NULL; - - bfa_q_deq(&rit_mod->rit_seg_pool[i], &qe); - seg = (struct bna_rit_segment *)qe; - bfa_q_qe_init(&seg->qe); - seg->rit_size = seg_size; - - return seg; -} - -void -bna_rit_mod_seg_put(struct bna_rit_mod *rit_mod, - struct bna_rit_segment *seg) -{ - int i; - - /* Select the pool for seg->max_rit_size */ - for (i = 0; i < BFI_RIT_SEG_TOTAL_POOLS; i++) { - if (seg->max_rit_size == ritseg_pool_cfg[i].pool_entry_size) - break; - } - - seg->rit_size = 0; - list_add_tail(&seg->qe, &rit_mod->rit_seg_pool[i]); -} diff --git a/drivers/net/ethernet/brocade/bna/bna_hw.h b/drivers/net/ethernet/brocade/bna/bna_hw.h deleted file mode 100644 index 16a5eed4a03b..000000000000 --- a/drivers/net/ethernet/brocade/bna/bna_hw.h +++ /dev/null @@ -1,1492 +0,0 @@ -/* - * Linux network driver for Brocade Converged Network Adapter. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License (GPL) Version 2 as - * published by the Free Software Foundation - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - */ -/* - * Copyright (c) 2005-2010 Brocade Communications Systems, Inc. - * All rights reserved - * www.brocade.com - */ - -/** - * File for interrupt macros and functions - */ - -#ifndef __BNA_HW_H__ -#define __BNA_HW_H__ - -#include "bfi_reg.h" - -/** - * - * SW imposed limits - * - */ - -#ifndef BNA_BIOS_BUILD - -#define BFI_MAX_TXQ 64 -#define BFI_MAX_RXQ 64 -#define BFI_MAX_RXF 64 -#define BFI_MAX_IB 128 -#define BFI_MAX_RIT_SIZE 256 -#define BFI_RSS_RIT_SIZE 64 -#define BFI_NONRSS_RIT_SIZE 1 -#define BFI_MAX_UCMAC 256 -#define BFI_MAX_MCMAC 512 -#define BFI_IBIDX_SIZE 4 -#define BFI_MAX_VLAN 4095 - -/** - * There are 2 free IB index pools: - * pool1: 120 segments of 1 index each - * pool8: 1 segment of 8 indexes - */ -#define BFI_IBIDX_POOL1_SIZE 116 -#define BFI_IBIDX_POOL1_ENTRY_SIZE 1 -#define BFI_IBIDX_POOL2_SIZE 2 -#define BFI_IBIDX_POOL2_ENTRY_SIZE 2 -#define BFI_IBIDX_POOL8_SIZE 1 -#define BFI_IBIDX_POOL8_ENTRY_SIZE 8 -#define BFI_IBIDX_TOTAL_POOLS 3 -#define BFI_IBIDX_TOTAL_SEGS 119 /* (POOL1 + POOL2 + POOL8)_SIZE */ -#define BFI_IBIDX_MAX_SEGSIZE 8 -#define init_ibidx_pool(name) \ -static struct bna_ibidx_pool name[BFI_IBIDX_TOTAL_POOLS] = \ -{ \ - { BFI_IBIDX_POOL1_SIZE, BFI_IBIDX_POOL1_ENTRY_SIZE }, \ - { BFI_IBIDX_POOL2_SIZE, BFI_IBIDX_POOL2_ENTRY_SIZE }, \ - { BFI_IBIDX_POOL8_SIZE, BFI_IBIDX_POOL8_ENTRY_SIZE } \ -} - -/** - * There are 2 free RIT segment pools: - * Pool1: 192 segments of 1 RIT entry each - * Pool2: 1 segment of 64 RIT entry - */ -#define BFI_RIT_SEG_POOL1_SIZE 192 -#define BFI_RIT_SEG_POOL1_ENTRY_SIZE 1 -#define BFI_RIT_SEG_POOLRSS_SIZE 1 -#define BFI_RIT_SEG_POOLRSS_ENTRY_SIZE 64 -#define BFI_RIT_SEG_TOTAL_POOLS 2 -#define BFI_RIT_TOTAL_SEGS 193 /* POOL1_SIZE + POOLRSS_SIZE */ -#define init_ritseg_pool(name) \ -static struct bna_ritseg_pool_cfg name[BFI_RIT_SEG_TOTAL_POOLS] = \ -{ \ - { BFI_RIT_SEG_POOL1_SIZE, BFI_RIT_SEG_POOL1_ENTRY_SIZE }, \ - { BFI_RIT_SEG_POOLRSS_SIZE, BFI_RIT_SEG_POOLRSS_ENTRY_SIZE } \ -} - -#else /* BNA_BIOS_BUILD */ - -#define BFI_MAX_TXQ 1 -#define BFI_MAX_RXQ 1 -#define BFI_MAX_RXF 1 -#define BFI_MAX_IB 2 -#define BFI_MAX_RIT_SIZE 2 -#define BFI_RSS_RIT_SIZE 64 -#define BFI_NONRSS_RIT_SIZE 1 -#define BFI_MAX_UCMAC 1 -#define BFI_MAX_MCMAC 8 -#define BFI_IBIDX_SIZE 4 -#define BFI_MAX_VLAN 4095 -/* There is one free pool: 2 segments of 1 index each */ -#define BFI_IBIDX_POOL1_SIZE 2 -#define BFI_IBIDX_POOL1_ENTRY_SIZE 1 -#define BFI_IBIDX_TOTAL_POOLS 1 -#define BFI_IBIDX_TOTAL_SEGS 2 /* POOL1_SIZE */ -#define BFI_IBIDX_MAX_SEGSIZE 1 -#define init_ibidx_pool(name) \ -static struct bna_ibidx_pool name[BFI_IBIDX_TOTAL_POOLS] = \ -{ \ - { BFI_IBIDX_POOL1_SIZE, BFI_IBIDX_POOL1_ENTRY_SIZE } \ -} - -#define BFI_RIT_SEG_POOL1_SIZE 1 -#define BFI_RIT_SEG_POOL1_ENTRY_SIZE 1 -#define BFI_RIT_SEG_TOTAL_POOLS 1 -#define BFI_RIT_TOTAL_SEGS 1 /* POOL1_SIZE */ -#define init_ritseg_pool(name) \ -static struct bna_ritseg_pool_cfg name[BFI_RIT_SEG_TOTAL_POOLS] = \ -{ \ - { BFI_RIT_SEG_POOL1_SIZE, BFI_RIT_SEG_POOL1_ENTRY_SIZE } \ -} - -#endif /* BNA_BIOS_BUILD */ - -#define BFI_RSS_HASH_KEY_LEN 10 - -#define BFI_COALESCING_TIMER_UNIT 5 /* 5us */ -#define BFI_MAX_COALESCING_TIMEO 0xFF /* in 5us units */ -#define BFI_MAX_INTERPKT_COUNT 0xFF -#define BFI_MAX_INTERPKT_TIMEO 0xF /* in 0.5us units */ -#define BFI_TX_COALESCING_TIMEO 20 /* 20 * 5 = 100us */ -#define BFI_TX_INTERPKT_COUNT 32 -#define BFI_RX_COALESCING_TIMEO 12 /* 12 * 5 = 60us */ -#define BFI_RX_INTERPKT_COUNT 6 /* Pkt Cnt = 6 */ -#define BFI_RX_INTERPKT_TIMEO 3 /* 3 * 0.5 = 1.5us */ - -#define BFI_TXQ_WI_SIZE 64 /* bytes */ -#define BFI_RXQ_WI_SIZE 8 /* bytes */ -#define BFI_CQ_WI_SIZE 16 /* bytes */ -#define BFI_TX_MAX_WRR_QUOTA 0xFFF - -#define BFI_TX_MAX_VECTORS_PER_WI 4 -#define BFI_TX_MAX_VECTORS_PER_PKT 0xFF -#define BFI_TX_MAX_DATA_PER_VECTOR 0xFFFF -#define BFI_TX_MAX_DATA_PER_PKT 0xFFFFFF - -/* Small Q buffer size */ -#define BFI_SMALL_RXBUF_SIZE 128 - -/* Defined separately since BFA_FLASH_DMA_BUF_SZ is in bfa_flash.c */ -#define BFI_FLASH_DMA_BUF_SZ 0x010000 /* 64K DMA */ -#define BFI_HW_STATS_SIZE 0x4000 /* 16K DMA */ - -/** - * - * HW register offsets, macros - * - */ - -/* DMA Block Register Host Window Start Address */ -#define DMA_BLK_REG_ADDR 0x00013000 - -/* DMA Block Internal Registers */ -#define DMA_CTRL_REG0 (DMA_BLK_REG_ADDR + 0x000) -#define DMA_CTRL_REG1 (DMA_BLK_REG_ADDR + 0x004) -#define DMA_ERR_INT_STATUS (DMA_BLK_REG_ADDR + 0x008) -#define DMA_ERR_INT_ENABLE (DMA_BLK_REG_ADDR + 0x00c) -#define DMA_ERR_INT_STATUS_SET (DMA_BLK_REG_ADDR + 0x010) - -/* APP Block Register Address Offset from BAR0 */ -#define APP_BLK_REG_ADDR 0x00014000 - -/* Host Function Interrupt Mask Registers */ -#define HOSTFN0_INT_MASK (APP_BLK_REG_ADDR + 0x004) -#define HOSTFN1_INT_MASK (APP_BLK_REG_ADDR + 0x104) -#define HOSTFN2_INT_MASK (APP_BLK_REG_ADDR + 0x304) -#define HOSTFN3_INT_MASK (APP_BLK_REG_ADDR + 0x404) - -/** - * Host Function PCIe Error Registers - * Duplicates "Correctable" & "Uncorrectable" - * registers in PCIe Config space. - */ -#define FN0_PCIE_ERR_REG (APP_BLK_REG_ADDR + 0x014) -#define FN1_PCIE_ERR_REG (APP_BLK_REG_ADDR + 0x114) -#define FN2_PCIE_ERR_REG (APP_BLK_REG_ADDR + 0x314) -#define FN3_PCIE_ERR_REG (APP_BLK_REG_ADDR + 0x414) - -/* Host Function Error Type Status Registers */ -#define FN0_ERR_TYPE_STATUS_REG (APP_BLK_REG_ADDR + 0x018) -#define FN1_ERR_TYPE_STATUS_REG (APP_BLK_REG_ADDR + 0x118) -#define FN2_ERR_TYPE_STATUS_REG (APP_BLK_REG_ADDR + 0x318) -#define FN3_ERR_TYPE_STATUS_REG (APP_BLK_REG_ADDR + 0x418) - -/* Host Function Error Type Mask Registers */ -#define FN0_ERR_TYPE_MSK_STATUS_REG (APP_BLK_REG_ADDR + 0x01c) -#define FN1_ERR_TYPE_MSK_STATUS_REG (APP_BLK_REG_ADDR + 0x11c) -#define FN2_ERR_TYPE_MSK_STATUS_REG (APP_BLK_REG_ADDR + 0x31c) -#define FN3_ERR_TYPE_MSK_STATUS_REG (APP_BLK_REG_ADDR + 0x41c) - -/* Catapult Host Semaphore Status Registers (App block) */ -#define HOST_SEM_STS0_REG (APP_BLK_REG_ADDR + 0x630) -#define HOST_SEM_STS1_REG (APP_BLK_REG_ADDR + 0x634) -#define HOST_SEM_STS2_REG (APP_BLK_REG_ADDR + 0x638) -#define HOST_SEM_STS3_REG (APP_BLK_REG_ADDR + 0x63c) -#define HOST_SEM_STS4_REG (APP_BLK_REG_ADDR + 0x640) -#define HOST_SEM_STS5_REG (APP_BLK_REG_ADDR + 0x644) -#define HOST_SEM_STS6_REG (APP_BLK_REG_ADDR + 0x648) -#define HOST_SEM_STS7_REG (APP_BLK_REG_ADDR + 0x64c) - -/* PCIe Misc Register */ -#define PCIE_MISC_REG (APP_BLK_REG_ADDR + 0x200) - -/* Temp Sensor Control Registers */ -#define TEMPSENSE_CNTL_REG (APP_BLK_REG_ADDR + 0x250) -#define TEMPSENSE_STAT_REG (APP_BLK_REG_ADDR + 0x254) - -/* APP Block local error registers */ -#define APP_LOCAL_ERR_STAT (APP_BLK_REG_ADDR + 0x258) -#define APP_LOCAL_ERR_MSK (APP_BLK_REG_ADDR + 0x25c) - -/* PCIe Link Error registers */ -#define PCIE_LNK_ERR_STAT (APP_BLK_REG_ADDR + 0x260) -#define PCIE_LNK_ERR_MSK (APP_BLK_REG_ADDR + 0x264) - -/** - * FCoE/FIP Ethertype Register - * 31:16 -- Chip wide value for FIP type - * 15:0 -- Chip wide value for FCoE type - */ -#define FCOE_FIP_ETH_TYPE (APP_BLK_REG_ADDR + 0x280) - -/** - * Reserved Ethertype Register - * 31:16 -- Reserved - * 15:0 -- Other ethertype - */ -#define RESV_ETH_TYPE (APP_BLK_REG_ADDR + 0x284) - -/** - * Host Command Status Registers - * Each set consists of 3 registers : - * clear, set, cmd - * 16 such register sets in all - * See catapult_spec.pdf for detailed functionality - * Put each type in a single macro accessed by _num ? - */ -#define HOST_CMDSTS0_CLR_REG (APP_BLK_REG_ADDR + 0x500) -#define HOST_CMDSTS0_SET_REG (APP_BLK_REG_ADDR + 0x504) -#define HOST_CMDSTS0_REG (APP_BLK_REG_ADDR + 0x508) -#define HOST_CMDSTS1_CLR_REG (APP_BLK_REG_ADDR + 0x510) -#define HOST_CMDSTS1_SET_REG (APP_BLK_REG_ADDR + 0x514) -#define HOST_CMDSTS1_REG (APP_BLK_REG_ADDR + 0x518) -#define HOST_CMDSTS2_CLR_REG (APP_BLK_REG_ADDR + 0x520) -#define HOST_CMDSTS2_SET_REG (APP_BLK_REG_ADDR + 0x524) -#define HOST_CMDSTS2_REG (APP_BLK_REG_ADDR + 0x528) -#define HOST_CMDSTS3_CLR_REG (APP_BLK_REG_ADDR + 0x530) -#define HOST_CMDSTS3_SET_REG (APP_BLK_REG_ADDR + 0x534) -#define HOST_CMDSTS3_REG (APP_BLK_REG_ADDR + 0x538) -#define HOST_CMDSTS4_CLR_REG (APP_BLK_REG_ADDR + 0x540) -#define HOST_CMDSTS4_SET_REG (APP_BLK_REG_ADDR + 0x544) -#define HOST_CMDSTS4_REG (APP_BLK_REG_ADDR + 0x548) -#define HOST_CMDSTS5_CLR_REG (APP_BLK_REG_ADDR + 0x550) -#define HOST_CMDSTS5_SET_REG (APP_BLK_REG_ADDR + 0x554) -#define HOST_CMDSTS5_REG (APP_BLK_REG_ADDR + 0x558) -#define HOST_CMDSTS6_CLR_REG (APP_BLK_REG_ADDR + 0x560) -#define HOST_CMDSTS6_SET_REG (APP_BLK_REG_ADDR + 0x564) -#define HOST_CMDSTS6_REG (APP_BLK_REG_ADDR + 0x568) -#define HOST_CMDSTS7_CLR_REG (APP_BLK_REG_ADDR + 0x570) -#define HOST_CMDSTS7_SET_REG (APP_BLK_REG_ADDR + 0x574) -#define HOST_CMDSTS7_REG (APP_BLK_REG_ADDR + 0x578) -#define HOST_CMDSTS8_CLR_REG (APP_BLK_REG_ADDR + 0x580) -#define HOST_CMDSTS8_SET_REG (APP_BLK_REG_ADDR + 0x584) -#define HOST_CMDSTS8_REG (APP_BLK_REG_ADDR + 0x588) -#define HOST_CMDSTS9_CLR_REG (APP_BLK_REG_ADDR + 0x590) -#define HOST_CMDSTS9_SET_REG (APP_BLK_REG_ADDR + 0x594) -#define HOST_CMDSTS9_REG (APP_BLK_REG_ADDR + 0x598) -#define HOST_CMDSTS10_CLR_REG (APP_BLK_REG_ADDR + 0x5A0) -#define HOST_CMDSTS10_SET_REG (APP_BLK_REG_ADDR + 0x5A4) -#define HOST_CMDSTS10_REG (APP_BLK_REG_ADDR + 0x5A8) -#define HOST_CMDSTS11_CLR_REG (APP_BLK_REG_ADDR + 0x5B0) -#define HOST_CMDSTS11_SET_REG (APP_BLK_REG_ADDR + 0x5B4) -#define HOST_CMDSTS11_REG (APP_BLK_REG_ADDR + 0x5B8) -#define HOST_CMDSTS12_CLR_REG (APP_BLK_REG_ADDR + 0x5C0) -#define HOST_CMDSTS12_SET_REG (APP_BLK_REG_ADDR + 0x5C4) -#define HOST_CMDSTS12_REG (APP_BLK_REG_ADDR + 0x5C8) -#define HOST_CMDSTS13_CLR_REG (APP_BLK_REG_ADDR + 0x5D0) -#define HOST_CMDSTS13_SET_REG (APP_BLK_REG_ADDR + 0x5D4) -#define HOST_CMDSTS13_REG (APP_BLK_REG_ADDR + 0x5D8) -#define HOST_CMDSTS14_CLR_REG (APP_BLK_REG_ADDR + 0x5E0) -#define HOST_CMDSTS14_SET_REG (APP_BLK_REG_ADDR + 0x5E4) -#define HOST_CMDSTS14_REG (APP_BLK_REG_ADDR + 0x5E8) -#define HOST_CMDSTS15_CLR_REG (APP_BLK_REG_ADDR + 0x5F0) -#define HOST_CMDSTS15_SET_REG (APP_BLK_REG_ADDR + 0x5F4) -#define HOST_CMDSTS15_REG (APP_BLK_REG_ADDR + 0x5F8) - -/** - * LPU0 Block Register Address Offset from BAR0 - * Range 0x18000 - 0x18033 - */ -#define LPU0_BLK_REG_ADDR 0x00018000 - -/** - * LPU0 Registers - * Should they be directly used from host, - * except for diagnostics ? - * CTL_REG : Control register - * CMD_REG : Triggers exec. of cmd. in - * Mailbox memory - */ -#define LPU0_MBOX_CTL_REG (LPU0_BLK_REG_ADDR + 0x000) -#define LPU0_MBOX_CMD_REG (LPU0_BLK_REG_ADDR + 0x004) -#define LPU0_MBOX_LINK_0REG (LPU0_BLK_REG_ADDR + 0x008) -#define LPU1_MBOX_LINK_0REG (LPU0_BLK_REG_ADDR + 0x00c) -#define LPU0_MBOX_STATUS_0REG (LPU0_BLK_REG_ADDR + 0x010) -#define LPU1_MBOX_STATUS_0REG (LPU0_BLK_REG_ADDR + 0x014) -#define LPU0_ERR_STATUS_REG (LPU0_BLK_REG_ADDR + 0x018) -#define LPU0_ERR_SET_REG (LPU0_BLK_REG_ADDR + 0x020) - -/** - * LPU1 Block Register Address Offset from BAR0 - * Range 0x18400 - 0x18433 - */ -#define LPU1_BLK_REG_ADDR 0x00018400 - -/** - * LPU1 Registers - * Same as LPU0 registers above - */ -#define LPU1_MBOX_CTL_REG (LPU1_BLK_REG_ADDR + 0x000) -#define LPU1_MBOX_CMD_REG (LPU1_BLK_REG_ADDR + 0x004) -#define LPU0_MBOX_LINK_1REG (LPU1_BLK_REG_ADDR + 0x008) -#define LPU1_MBOX_LINK_1REG (LPU1_BLK_REG_ADDR + 0x00c) -#define LPU0_MBOX_STATUS_1REG (LPU1_BLK_REG_ADDR + 0x010) -#define LPU1_MBOX_STATUS_1REG (LPU1_BLK_REG_ADDR + 0x014) -#define LPU1_ERR_STATUS_REG (LPU1_BLK_REG_ADDR + 0x018) -#define LPU1_ERR_SET_REG (LPU1_BLK_REG_ADDR + 0x020) - -/** - * PSS Block Register Address Offset from BAR0 - * Range 0x18800 - 0x188DB - */ -#define PSS_BLK_REG_ADDR 0x00018800 - -/** - * PSS Registers - * For details, see catapult_spec.pdf - * ERR_STATUS_REG : Indicates error in PSS module - * RAM_ERR_STATUS_REG : Indicates RAM module that detected error - */ -#define ERR_STATUS_SET (PSS_BLK_REG_ADDR + 0x018) -#define PSS_RAM_ERR_STATUS_REG (PSS_BLK_REG_ADDR + 0x01C) - -/** - * PSS Semaphore Lock Registers, total 16 - * First read when unlocked returns 0, - * and is set to 1, atomically. - * Subsequent reads returns 1. - * To clear set the value to 0. - * Range : 0x20 to 0x5c - */ -#define PSS_SEM_LOCK_REG(_num) \ - (PSS_BLK_REG_ADDR + 0x020 + ((_num) << 2)) - -/** - * PSS Semaphore Status Registers, - * corresponding to the lock registers above - */ -#define PSS_SEM_STATUS_REG(_num) \ - (PSS_BLK_REG_ADDR + 0x060 + ((_num) << 2)) - -/** - * Catapult CPQ Registers - * Defines for Mailbox Registers - * Used to send mailbox commands to firmware from - * host. The data part is written to the MBox - * memory, registers are used to indicate that - * a commnad is resident in memory. - * - * Note : LPU0<->LPU1 mailboxes are not listed here - */ -#define CPQ_BLK_REG_ADDR 0x00019000 - -#define HOSTFN0_LPU0_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x130) -#define HOSTFN0_LPU1_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x134) -#define LPU0_HOSTFN0_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x138) -#define LPU1_HOSTFN0_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x13C) - -#define HOSTFN1_LPU0_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x140) -#define HOSTFN1_LPU1_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x144) -#define LPU0_HOSTFN1_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x148) -#define LPU1_HOSTFN1_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x14C) - -#define HOSTFN2_LPU0_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x170) -#define HOSTFN2_LPU1_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x174) -#define LPU0_HOSTFN2_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x178) -#define LPU1_HOSTFN2_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x17C) - -#define HOSTFN3_LPU0_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x180) -#define HOSTFN3_LPU1_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x184) -#define LPU0_HOSTFN3_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x188) -#define LPU1_HOSTFN3_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x18C) - -/* Host Function Force Parity Error Registers */ -#define HOSTFN0_LPU_FORCE_PERR (CPQ_BLK_REG_ADDR + 0x120) -#define HOSTFN1_LPU_FORCE_PERR (CPQ_BLK_REG_ADDR + 0x124) -#define HOSTFN2_LPU_FORCE_PERR (CPQ_BLK_REG_ADDR + 0x128) -#define HOSTFN3_LPU_FORCE_PERR (CPQ_BLK_REG_ADDR + 0x12C) - -/* LL Port[0|1] Halt Mask Registers */ -#define LL_HALT_MSK_P0 (CPQ_BLK_REG_ADDR + 0x1A0) -#define LL_HALT_MSK_P1 (CPQ_BLK_REG_ADDR + 0x1B0) - -/* LL Port[0|1] Error Mask Registers */ -#define LL_ERR_MSK_P0 (CPQ_BLK_REG_ADDR + 0x1D0) -#define LL_ERR_MSK_P1 (CPQ_BLK_REG_ADDR + 0x1D4) - -/* EMC FLI (Flash Controller) Block Register Address Offset from BAR0 */ -#define FLI_BLK_REG_ADDR 0x0001D000 - -/* EMC FLI Registers */ -#define FLI_CMD_REG (FLI_BLK_REG_ADDR + 0x000) -#define FLI_ADDR_REG (FLI_BLK_REG_ADDR + 0x004) -#define FLI_CTL_REG (FLI_BLK_REG_ADDR + 0x008) -#define FLI_WRDATA_REG (FLI_BLK_REG_ADDR + 0x00C) -#define FLI_RDDATA_REG (FLI_BLK_REG_ADDR + 0x010) -#define FLI_DEV_STATUS_REG (FLI_BLK_REG_ADDR + 0x014) -#define FLI_SIG_WD_REG (FLI_BLK_REG_ADDR + 0x018) - -/** - * RO register - * 31:16 -- Vendor Id - * 15:0 -- Device Id - */ -#define FLI_DEV_VENDOR_REG (FLI_BLK_REG_ADDR + 0x01C) -#define FLI_ERR_STATUS_REG (FLI_BLK_REG_ADDR + 0x020) - -/** - * RAD (RxAdm) Block Register Address Offset from BAR0 - * RAD0 Range : 0x20000 - 0x203FF - * RAD1 Range : 0x20400 - 0x207FF - */ -#define RAD0_BLK_REG_ADDR 0x00020000 -#define RAD1_BLK_REG_ADDR 0x00020400 - -/* RAD0 Registers */ -#define RAD0_CTL_REG (RAD0_BLK_REG_ADDR + 0x000) -#define RAD0_PE_PARM_REG (RAD0_BLK_REG_ADDR + 0x004) -#define RAD0_BCN_REG (RAD0_BLK_REG_ADDR + 0x008) - -/* Default function ID register */ -#define RAD0_DEFAULT_REG (RAD0_BLK_REG_ADDR + 0x00C) - -/* Default promiscuous ID register */ -#define RAD0_PROMISC_REG (RAD0_BLK_REG_ADDR + 0x010) - -#define RAD0_BCNQ_REG (RAD0_BLK_REG_ADDR + 0x014) - -/* - * This register selects 1 of 8 PM Q's using - * VLAN pri, for non-BCN packets without a VLAN tag - */ -#define RAD0_DEFAULTQ_REG (RAD0_BLK_REG_ADDR + 0x018) - -#define RAD0_ERR_STS (RAD0_BLK_REG_ADDR + 0x01C) -#define RAD0_SET_ERR_STS (RAD0_BLK_REG_ADDR + 0x020) -#define RAD0_ERR_INT_EN (RAD0_BLK_REG_ADDR + 0x024) -#define RAD0_FIRST_ERR (RAD0_BLK_REG_ADDR + 0x028) -#define RAD0_FORCE_ERR (RAD0_BLK_REG_ADDR + 0x02C) - -#define RAD0_IF_RCVD (RAD0_BLK_REG_ADDR + 0x030) -#define RAD0_IF_RCVD_OCTETS_HIGH (RAD0_BLK_REG_ADDR + 0x034) -#define RAD0_IF_RCVD_OCTETS_LOW (RAD0_BLK_REG_ADDR + 0x038) -#define RAD0_IF_RCVD_VLAN (RAD0_BLK_REG_ADDR + 0x03C) -#define RAD0_IF_RCVD_UCAST (RAD0_BLK_REG_ADDR + 0x040) -#define RAD0_IF_RCVD_UCAST_OCTETS_HIGH (RAD0_BLK_REG_ADDR + 0x044) -#define RAD0_IF_RCVD_UCAST_OCTETS_LOW (RAD0_BLK_REG_ADDR + 0x048) -#define RAD0_IF_RCVD_UCAST_VLAN (RAD0_BLK_REG_ADDR + 0x04C) -#define RAD0_IF_RCVD_MCAST (RAD0_BLK_REG_ADDR + 0x050) -#define RAD0_IF_RCVD_MCAST_OCTETS_HIGH (RAD0_BLK_REG_ADDR + 0x054) -#define RAD0_IF_RCVD_MCAST_OCTETS_LOW (RAD0_BLK_REG_ADDR + 0x058) -#define RAD0_IF_RCVD_MCAST_VLAN (RAD0_BLK_REG_ADDR + 0x05C) -#define RAD0_IF_RCVD_BCAST (RAD0_BLK_REG_ADDR + 0x060) -#define RAD0_IF_RCVD_BCAST_OCTETS_HIGH (RAD0_BLK_REG_ADDR + 0x064) -#define RAD0_IF_RCVD_BCAST_OCTETS_LOW (RAD0_BLK_REG_ADDR + 0x068) -#define RAD0_IF_RCVD_BCAST_VLAN (RAD0_BLK_REG_ADDR + 0x06C) -#define RAD0_DROPPED_FRAMES (RAD0_BLK_REG_ADDR + 0x070) - -#define RAD0_MAC_MAN_1H (RAD0_BLK_REG_ADDR + 0x080) -#define RAD0_MAC_MAN_1L (RAD0_BLK_REG_ADDR + 0x084) -#define RAD0_MAC_MAN_2H (RAD0_BLK_REG_ADDR + 0x088) -#define RAD0_MAC_MAN_2L (RAD0_BLK_REG_ADDR + 0x08C) -#define RAD0_MAC_MAN_3H (RAD0_BLK_REG_ADDR + 0x090) -#define RAD0_MAC_MAN_3L (RAD0_BLK_REG_ADDR + 0x094) -#define RAD0_MAC_MAN_4H (RAD0_BLK_REG_ADDR + 0x098) -#define RAD0_MAC_MAN_4L (RAD0_BLK_REG_ADDR + 0x09C) - -#define RAD0_LAST4_IP (RAD0_BLK_REG_ADDR + 0x100) - -/* RAD1 Registers */ -#define RAD1_CTL_REG (RAD1_BLK_REG_ADDR + 0x000) -#define RAD1_PE_PARM_REG (RAD1_BLK_REG_ADDR + 0x004) -#define RAD1_BCN_REG (RAD1_BLK_REG_ADDR + 0x008) - -/* Default function ID register */ -#define RAD1_DEFAULT_REG (RAD1_BLK_REG_ADDR + 0x00C) - -/* Promiscuous function ID register */ -#define RAD1_PROMISC_REG (RAD1_BLK_REG_ADDR + 0x010) - -#define RAD1_BCNQ_REG (RAD1_BLK_REG_ADDR + 0x014) - -/* - * This register selects 1 of 8 PM Q's using - * VLAN pri, for non-BCN packets without a VLAN tag - */ -#define RAD1_DEFAULTQ_REG (RAD1_BLK_REG_ADDR + 0x018) - -#define RAD1_ERR_STS (RAD1_BLK_REG_ADDR + 0x01C) -#define RAD1_SET_ERR_STS (RAD1_BLK_REG_ADDR + 0x020) -#define RAD1_ERR_INT_EN (RAD1_BLK_REG_ADDR + 0x024) - -/** - * TXA Block Register Address Offset from BAR0 - * TXA0 Range : 0x21000 - 0x213FF - * TXA1 Range : 0x21400 - 0x217FF - */ -#define TXA0_BLK_REG_ADDR 0x00021000 -#define TXA1_BLK_REG_ADDR 0x00021400 - -/* TXA Registers */ -#define TXA0_CTRL_REG (TXA0_BLK_REG_ADDR + 0x000) -#define TXA1_CTRL_REG (TXA1_BLK_REG_ADDR + 0x000) - -/** - * TSO Sequence # Registers (RO) - * Total 8 (for 8 queues) - * Holds the last seq.# for TSO frames - * See catapult_spec.pdf for more details - */ -#define TXA0_TSO_TCP_SEQ_REG(_num) \ - (TXA0_BLK_REG_ADDR + 0x020 + ((_num) << 2)) - -#define TXA1_TSO_TCP_SEQ_REG(_num) \ - (TXA1_BLK_REG_ADDR + 0x020 + ((_num) << 2)) - -/** - * TSO IP ID # Registers (RO) - * Total 8 (for 8 queues) - * Holds the last IP ID for TSO frames - * See catapult_spec.pdf for more details - */ -#define TXA0_TSO_IP_INFO_REG(_num) \ - (TXA0_BLK_REG_ADDR + 0x040 + ((_num) << 2)) - -#define TXA1_TSO_IP_INFO_REG(_num) \ - (TXA1_BLK_REG_ADDR + 0x040 + ((_num) << 2)) - -/** - * RXA Block Register Address Offset from BAR0 - * RXA0 Range : 0x21800 - 0x21BFF - * RXA1 Range : 0x21C00 - 0x21FFF - */ -#define RXA0_BLK_REG_ADDR 0x00021800 -#define RXA1_BLK_REG_ADDR 0x00021C00 - -/* RXA Registers */ -#define RXA0_CTL_REG (RXA0_BLK_REG_ADDR + 0x040) -#define RXA1_CTL_REG (RXA1_BLK_REG_ADDR + 0x040) - -/** - * PPLB Block Register Address Offset from BAR0 - * PPLB0 Range : 0x22000 - 0x223FF - * PPLB1 Range : 0x22400 - 0x227FF - */ -#define PLB0_BLK_REG_ADDR 0x00022000 -#define PLB1_BLK_REG_ADDR 0x00022400 - -/** - * PLB Registers - * Holds RL timer used time stamps in RLT tagged frames - */ -#define PLB0_ECM_TIMER_REG (PLB0_BLK_REG_ADDR + 0x05C) -#define PLB1_ECM_TIMER_REG (PLB1_BLK_REG_ADDR + 0x05C) - -/* Controls the rate-limiter on each of the priority class */ -#define PLB0_RL_CTL (PLB0_BLK_REG_ADDR + 0x060) -#define PLB1_RL_CTL (PLB1_BLK_REG_ADDR + 0x060) - -/** - * Max byte register, total 8, 0-7 - * see catapult_spec.pdf for details - */ -#define PLB0_RL_MAX_BC(_num) \ - (PLB0_BLK_REG_ADDR + 0x064 + ((_num) << 2)) -#define PLB1_RL_MAX_BC(_num) \ - (PLB1_BLK_REG_ADDR + 0x064 + ((_num) << 2)) - -/** - * RL Time Unit Register for priority 0-7 - * 4 bits per priority - * (2^rl_unit)*1us is the actual time period - */ -#define PLB0_RL_TU_PRIO (PLB0_BLK_REG_ADDR + 0x084) -#define PLB1_RL_TU_PRIO (PLB1_BLK_REG_ADDR + 0x084) - -/** - * RL byte count register, - * bytes transmitted in (rl_unit*1)us time period - * 1 per priority, 8 in all, 0-7. - */ -#define PLB0_RL_BYTE_CNT(_num) \ - (PLB0_BLK_REG_ADDR + 0x088 + ((_num) << 2)) -#define PLB1_RL_BYTE_CNT(_num) \ - (PLB1_BLK_REG_ADDR + 0x088 + ((_num) << 2)) - -/** - * RL Min factor register - * 2 bits per priority, - * 4 factors possible: 1, 0.5, 0.25, 0 - * 2'b00 - 0; 2'b01 - 0.25; 2'b10 - 0.5; 2'b11 - 1 - */ -#define PLB0_RL_MIN_REG (PLB0_BLK_REG_ADDR + 0x0A8) -#define PLB1_RL_MIN_REG (PLB1_BLK_REG_ADDR + 0x0A8) - -/** - * RL Max factor register - * 2 bits per priority, - * 4 factors possible: 1, 0.5, 0.25, 0 - * 2'b00 - 0; 2'b01 - 0.25; 2'b10 - 0.5; 2'b11 - 1 - */ -#define PLB0_RL_MAX_REG (PLB0_BLK_REG_ADDR + 0x0AC) -#define PLB1_RL_MAX_REG (PLB1_BLK_REG_ADDR + 0x0AC) - -/* MAC SERDES Address Paging register */ -#define PLB0_EMS_ADD_REG (PLB0_BLK_REG_ADDR + 0xD0) -#define PLB1_EMS_ADD_REG (PLB1_BLK_REG_ADDR + 0xD0) - -/* LL EMS Registers */ -#define LL_EMS0_BLK_REG_ADDR 0x00026800 -#define LL_EMS1_BLK_REG_ADDR 0x00026C00 - -/** - * BPC Block Register Address Offset from BAR0 - * BPC0 Range : 0x23000 - 0x233FF - * BPC1 Range : 0x23400 - 0x237FF - */ -#define BPC0_BLK_REG_ADDR 0x00023000 -#define BPC1_BLK_REG_ADDR 0x00023400 - -/** - * PMM Block Register Address Offset from BAR0 - * PMM0 Range : 0x23800 - 0x23BFF - * PMM1 Range : 0x23C00 - 0x23FFF - */ -#define PMM0_BLK_REG_ADDR 0x00023800 -#define PMM1_BLK_REG_ADDR 0x00023C00 - -/** - * HQM Block Register Address Offset from BAR0 - * HQM0 Range : 0x24000 - 0x243FF - * HQM1 Range : 0x24400 - 0x247FF - */ -#define HQM0_BLK_REG_ADDR 0x00024000 -#define HQM1_BLK_REG_ADDR 0x00024400 - -/** - * HQM Control Register - * Controls some aspects of IB - * See catapult_spec.pdf for details - */ -#define HQM0_CTL_REG (HQM0_BLK_REG_ADDR + 0x000) -#define HQM1_CTL_REG (HQM1_BLK_REG_ADDR + 0x000) - -/** - * HQM Stop Q Semaphore Registers. - * Only one Queue resource can be stopped at - * any given time. This register controls access - * to the single stop Q resource. - * See catapult_spec.pdf for details - */ -#define HQM0_RXQ_STOP_SEM (HQM0_BLK_REG_ADDR + 0x028) -#define HQM0_TXQ_STOP_SEM (HQM0_BLK_REG_ADDR + 0x02C) -#define HQM1_RXQ_STOP_SEM (HQM1_BLK_REG_ADDR + 0x028) -#define HQM1_TXQ_STOP_SEM (HQM1_BLK_REG_ADDR + 0x02C) - -/** - * LUT Block Register Address Offset from BAR0 - * LUT0 Range : 0x25800 - 0x25BFF - * LUT1 Range : 0x25C00 - 0x25FFF - */ -#define LUT0_BLK_REG_ADDR 0x00025800 -#define LUT1_BLK_REG_ADDR 0x00025C00 - -/** - * LUT Registers - * See catapult_spec.pdf for details - */ -#define LUT0_ERR_STS (LUT0_BLK_REG_ADDR + 0x000) -#define LUT1_ERR_STS (LUT1_BLK_REG_ADDR + 0x000) -#define LUT0_SET_ERR_STS (LUT0_BLK_REG_ADDR + 0x004) -#define LUT1_SET_ERR_STS (LUT1_BLK_REG_ADDR + 0x004) - -/** - * TRC (Debug/Trace) Register Offset from BAR0 - * Range : 0x26000 -- 0x263FFF - */ -#define TRC_BLK_REG_ADDR 0x00026000 - -/** - * TRC Registers - * See catapult_spec.pdf for details of each - */ -#define TRC_CTL_REG (TRC_BLK_REG_ADDR + 0x000) -#define TRC_MODS_REG (TRC_BLK_REG_ADDR + 0x004) -#define TRC_TRGC_REG (TRC_BLK_REG_ADDR + 0x008) -#define TRC_CNT1_REG (TRC_BLK_REG_ADDR + 0x010) -#define TRC_CNT2_REG (TRC_BLK_REG_ADDR + 0x014) -#define TRC_NXTS_REG (TRC_BLK_REG_ADDR + 0x018) -#define TRC_DIRR_REG (TRC_BLK_REG_ADDR + 0x01C) - -/** - * TRC Trigger match filters, total 10 - * Determines the trigger condition - */ -#define TRC_TRGM_REG(_num) \ - (TRC_BLK_REG_ADDR + 0x040 + ((_num) << 2)) - -/** - * TRC Next State filters, total 10 - * Determines the next state conditions - */ -#define TRC_NXTM_REG(_num) \ - (TRC_BLK_REG_ADDR + 0x080 + ((_num) << 2)) - -/** - * TRC Store Match filters, total 10 - * Determines the store conditions - */ -#define TRC_STRM_REG(_num) \ - (TRC_BLK_REG_ADDR + 0x0C0 + ((_num) << 2)) - -/* DOORBELLS ACCESS */ - -/** - * Catapult doorbells - * Each doorbell-queue set has - * 1 RxQ, 1 TxQ, 2 IBs in that order - * Size of each entry in 32 bytes, even though only 1 word - * is used. For Non-VM case each doorbell-q set is - * separated by 128 bytes, for VM case it is separated - * by 4K bytes - * Non VM case Range : 0x38000 - 0x39FFF - * VM case Range : 0x100000 - 0x11FFFF - * The range applies to both HQMs - */ -#define HQM_DOORBELL_BLK_BASE_ADDR 0x00038000 -#define HQM_DOORBELL_VM_BLK_BASE_ADDR 0x00100000 - -/* MEMORY ACCESS */ - -/** - * Catapult H/W Block Memory Access Address - * To the host a memory space of 32K (page) is visible - * at a time. The address range is from 0x08000 to 0x0FFFF - */ -#define HW_BLK_HOST_MEM_ADDR 0x08000 - -/** - * Catapult LUT Memory Access Page Numbers - * Range : LUT0 0xa0-0xa1 - * LUT1 0xa2-0xa3 - */ -#define LUT0_MEM_BLK_BASE_PG_NUM 0x000000A0 -#define LUT1_MEM_BLK_BASE_PG_NUM 0x000000A2 - -/** - * Catapult RxFn Database Memory Block Base Offset - * - * The Rx function database exists in LUT block. - * In PCIe space this is accessible as a 256x32 - * bit block. Each entry in this database is 4 - * (4 byte) words. Max. entries is 64. - * Address of an entry corresponding to a function - * = base_addr + (function_no. * 16) - */ -#define RX_FNDB_RAM_BASE_OFFSET 0x0000B400 - -/** - * Catapult TxFn Database Memory Block Base Offset Address - * - * The Tx function database exists in LUT block. - * In PCIe space this is accessible as a 64x32 - * bit block. Each entry in this database is 1 - * (4 byte) word. Max. entries is 64. - * Address of an entry corresponding to a function - * = base_addr + (function_no. * 4) - */ -#define TX_FNDB_RAM_BASE_OFFSET 0x0000B800 - -/** - * Catapult Unicast CAM Base Offset Address - * - * Exists in LUT memory space. - * Shared by both the LL & FCoE driver. - * Size is 256x48 bits; mapped to PCIe space - * 512x32 bit blocks. For each address, bits - * are written in the order : [47:32] and then - * [31:0]. - */ -#define UCAST_CAM_BASE_OFFSET 0x0000A800 - -/** - * Catapult Unicast RAM Base Offset Address - * - * Exists in LUT memory space. - * Shared by both the LL & FCoE driver. - * Size is 256x9 bits. - */ -#define UCAST_RAM_BASE_OFFSET 0x0000B000 - -/** - * Catapult Mulicast CAM Base Offset Address - * - * Exists in LUT memory space. - * Shared by both the LL & FCoE driver. - * Size is 256x48 bits; mapped to PCIe space - * 512x32 bit blocks. For each address, bits - * are written in the order : [47:32] and then - * [31:0]. - */ -#define MCAST_CAM_BASE_OFFSET 0x0000A000 - -/** - * Catapult VLAN RAM Base Offset Address - * - * Exists in LUT memory space. - * Size is 4096x66 bits; mapped to PCIe space as - * 8192x32 bit blocks. - * All the 4K entries are within the address range - * 0x0000 to 0x8000, so in the first LUT page. - */ -#define VLAN_RAM_BASE_OFFSET 0x00000000 - -/** - * Catapult Tx Stats RAM Base Offset Address - * - * Exists in LUT memory space. - * Size is 1024x33 bits; - * Each Tx function has 64 bytes of space - */ -#define TX_STATS_RAM_BASE_OFFSET 0x00009000 - -/** - * Catapult Rx Stats RAM Base Offset Address - * - * Exists in LUT memory space. - * Size is 1024x33 bits; - * Each Rx function has 64 bytes of space - */ -#define RX_STATS_RAM_BASE_OFFSET 0x00008000 - -/* Catapult RXA Memory Access Page Numbers */ -#define RXA0_MEM_BLK_BASE_PG_NUM 0x0000008C -#define RXA1_MEM_BLK_BASE_PG_NUM 0x0000008D - -/** - * Catapult Multicast Vector Table Base Offset Address - * - * Exists in RxA memory space. - * Organized as 512x65 bit block. - * However for each entry 16 bytes allocated (power of 2) - * Total size 512*16 bytes. - * There are two logical divisions, 256 entries each : - * a) Entries 0x00 to 0xff (256) -- Approx. MVT - * Offset 0x000 to 0xFFF - * b) Entries 0x100 to 0x1ff (256) -- Exact MVT - * Offsets 0x1000 to 0x1FFF - */ -#define MCAST_APPROX_MVT_BASE_OFFSET 0x00000000 -#define MCAST_EXACT_MVT_BASE_OFFSET 0x00001000 - -/** - * Catapult RxQ Translate Table (RIT) Base Offset Address - * - * Exists in RxA memory space - * Total no. of entries 64 - * Each entry is 1 (4 byte) word. - * 31:12 -- Reserved - * 11:0 -- Two 6 bit RxQ Ids - */ -#define FUNCTION_TO_RXQ_TRANSLATE 0x00002000 - -/* Catapult RxAdm (RAD) Memory Access Page Numbers */ -#define RAD0_MEM_BLK_BASE_PG_NUM 0x00000086 -#define RAD1_MEM_BLK_BASE_PG_NUM 0x00000087 - -/** - * Catapult RSS Table Base Offset Address - * - * Exists in RAD memory space. - * Each entry is 352 bits, but aligned on - * 64 byte (512 bit) boundary. Accessed - * 4 byte words, the whole entry can be - * broken into 11 word accesses. - */ -#define RSS_TABLE_BASE_OFFSET 0x00000800 - -/** - * Catapult CPQ Block Page Number - * This value is written to the page number registers - * to access the memory associated with the mailboxes. - */ -#define CPQ_BLK_PG_NUM 0x00000005 - -/** - * Clarification : - * LL functions are 2 & 3; can HostFn0/HostFn1 - * <-> LPU0/LPU1 memories be used ? - */ -/** - * Catapult HostFn0/HostFn1 to LPU0/LPU1 Mbox memory - * Per catapult_spec.pdf, the offset of the mbox - * memory is in the register space at an offset of 0x200 - */ -#define CPQ_BLK_REG_MBOX_ADDR (CPQ_BLK_REG_ADDR + 0x200) - -#define HOSTFN_LPU_MBOX (CPQ_BLK_REG_MBOX_ADDR + 0x000) - -/* Catapult LPU0/LPU1 to HostFn0/HostFn1 Mbox memory */ -#define LPU_HOSTFN_MBOX (CPQ_BLK_REG_MBOX_ADDR + 0x080) - -/** - * Catapult HQM Block Page Number - * This is written to the page number register for - * the appropriate function to access the memory - * associated with HQM - */ -#define HQM0_BLK_PG_NUM 0x00000096 -#define HQM1_BLK_PG_NUM 0x00000097 - -/** - * Note that TxQ and RxQ entries are interlaced - * the HQM memory, i.e RXQ0, TXQ0, RXQ1, TXQ1.. etc. - */ - -#define HQM_RXTX_Q_RAM_BASE_OFFSET 0x00004000 - -/** - * CQ Memory - * Exists in HQM Memory space - * Each entry is 16 (4 byte) words of which - * only 12 words are used for configuration - * Total 64 entries per HQM memory space - */ -#define HQM_CQ_RAM_BASE_OFFSET 0x00006000 - -/** - * Interrupt Block (IB) Memory - * Exists in HQM Memory space - * Each entry is 8 (4 byte) words of which - * only 5 words are used for configuration - * Total 128 entries per HQM memory space - */ -#define HQM_IB_RAM_BASE_OFFSET 0x00001000 - -/** - * Index Table (IT) Memory - * Exists in HQM Memory space - * Each entry is 1 (4 byte) word which - * is used for configuration - * Total 128 entries per HQM memory space - */ -#define HQM_INDX_TBL_RAM_BASE_OFFSET 0x00002000 - -/** - * PSS Block Memory Page Number - * This is written to the appropriate page number - * register to access the CPU memory. - * Also known as the PSS secondary memory (SMEM). - * Range : 0x180 to 0x1CF - * See catapult_spec.pdf for details - */ -#define PSS_BLK_PG_NUM 0x00000180 - -/** - * Offsets of different instances of PSS SMEM - * 2.5M of continuous 1T memory space : 2 blocks - * of 1M each (32 pages each, page=32KB) and 4 smaller - * blocks of 128K each (4 pages each, page=32KB) - * PSS_LMEM_INST0 is used for firmware download - */ -#define PSS_LMEM_INST0 0x00000000 -#define PSS_LMEM_INST1 0x00100000 -#define PSS_LMEM_INST2 0x00200000 -#define PSS_LMEM_INST3 0x00220000 -#define PSS_LMEM_INST4 0x00240000 -#define PSS_LMEM_INST5 0x00260000 - -#define BNA_PCI_REG_CT_ADDRSZ (0x40000) - -#define BNA_GET_PAGE_NUM(_base_page, _offset) \ - ((_base_page) + ((_offset) >> 15)) - -#define BNA_GET_PAGE_OFFSET(_offset) \ - ((_offset) & 0x7fff) - -#define BNA_GET_MEM_BASE_ADDR(_bar0, _base_offset) \ - ((_bar0) + HW_BLK_HOST_MEM_ADDR \ - + BNA_GET_PAGE_OFFSET((_base_offset))) - -#define BNA_GET_VLAN_MEM_ENTRY_ADDR(_bar0, _fn_id, _vlan_id)\ - (_bar0 + (HW_BLK_HOST_MEM_ADDR) \ - + (BNA_GET_PAGE_OFFSET(VLAN_RAM_BASE_OFFSET)) \ - + (((_fn_id) & 0x3f) << 9) \ - + (((_vlan_id) & 0xfe0) >> 3)) - -/** - * - * Interrupt related bits, flags and macros - * - */ - -#define __LPU02HOST_MBOX0_STATUS_BITS 0x00100000 -#define __LPU12HOST_MBOX0_STATUS_BITS 0x00200000 -#define __LPU02HOST_MBOX1_STATUS_BITS 0x00400000 -#define __LPU12HOST_MBOX1_STATUS_BITS 0x00800000 - -#define __LPU02HOST_MBOX0_MASK_BITS 0x00100000 -#define __LPU12HOST_MBOX0_MASK_BITS 0x00200000 -#define __LPU02HOST_MBOX1_MASK_BITS 0x00400000 -#define __LPU12HOST_MBOX1_MASK_BITS 0x00800000 - -#define __LPU2HOST_MBOX_MASK_BITS \ - (__LPU02HOST_MBOX0_MASK_BITS | __LPU02HOST_MBOX1_MASK_BITS | \ - __LPU12HOST_MBOX0_MASK_BITS | __LPU12HOST_MBOX1_MASK_BITS) - -#define __LPU2HOST_IB_STATUS_BITS 0x0000ffff - -#define BNA_IS_LPU0_MBOX_INTR(_intr_status) \ - ((_intr_status) & (__LPU02HOST_MBOX0_STATUS_BITS | \ - __LPU02HOST_MBOX1_STATUS_BITS)) - -#define BNA_IS_LPU1_MBOX_INTR(_intr_status) \ - ((_intr_status) & (__LPU12HOST_MBOX0_STATUS_BITS | \ - __LPU12HOST_MBOX1_STATUS_BITS)) - -#define BNA_IS_MBOX_INTR(_intr_status) \ - ((_intr_status) & \ - (__LPU02HOST_MBOX0_STATUS_BITS | \ - __LPU02HOST_MBOX1_STATUS_BITS | \ - __LPU12HOST_MBOX0_STATUS_BITS | \ - __LPU12HOST_MBOX1_STATUS_BITS)) - -#define __EMC_ERROR_STATUS_BITS 0x00010000 -#define __LPU0_ERROR_STATUS_BITS 0x00020000 -#define __LPU1_ERROR_STATUS_BITS 0x00040000 -#define __PSS_ERROR_STATUS_BITS 0x00080000 - -#define __HALT_STATUS_BITS 0x01000000 - -#define __EMC_ERROR_MASK_BITS 0x00010000 -#define __LPU0_ERROR_MASK_BITS 0x00020000 -#define __LPU1_ERROR_MASK_BITS 0x00040000 -#define __PSS_ERROR_MASK_BITS 0x00080000 - -#define __HALT_MASK_BITS 0x01000000 - -#define __ERROR_MASK_BITS \ - (__EMC_ERROR_MASK_BITS | __LPU0_ERROR_MASK_BITS | \ - __LPU1_ERROR_MASK_BITS | __PSS_ERROR_MASK_BITS | \ - __HALT_MASK_BITS) - -#define BNA_IS_ERR_INTR(_intr_status) \ - ((_intr_status) & \ - (__EMC_ERROR_STATUS_BITS | \ - __LPU0_ERROR_STATUS_BITS | \ - __LPU1_ERROR_STATUS_BITS | \ - __PSS_ERROR_STATUS_BITS | \ - __HALT_STATUS_BITS)) - -#define BNA_IS_MBOX_ERR_INTR(_intr_status) \ - (BNA_IS_MBOX_INTR((_intr_status)) | \ - BNA_IS_ERR_INTR((_intr_status))) - -#define BNA_IS_INTX_DATA_INTR(_intr_status) \ - ((_intr_status) & __LPU2HOST_IB_STATUS_BITS) - -#define BNA_INTR_STATUS_MBOX_CLR(_intr_status) \ -do { \ - (_intr_status) &= ~(__LPU02HOST_MBOX0_STATUS_BITS | \ - __LPU02HOST_MBOX1_STATUS_BITS | \ - __LPU12HOST_MBOX0_STATUS_BITS | \ - __LPU12HOST_MBOX1_STATUS_BITS); \ -} while (0) - -#define BNA_INTR_STATUS_ERR_CLR(_intr_status) \ -do { \ - (_intr_status) &= ~(__EMC_ERROR_STATUS_BITS | \ - __LPU0_ERROR_STATUS_BITS | \ - __LPU1_ERROR_STATUS_BITS | \ - __PSS_ERROR_STATUS_BITS | \ - __HALT_STATUS_BITS); \ -} while (0) - -#define bna_intx_disable(_bna, _cur_mask) \ -{ \ - (_cur_mask) = readl((_bna)->regs.fn_int_mask);\ - writel(0xffffffff, (_bna)->regs.fn_int_mask);\ -} - -#define bna_intx_enable(bna, new_mask) \ - writel((new_mask), (bna)->regs.fn_int_mask) - -#define bna_mbox_intr_disable(bna) \ - writel((readl((bna)->regs.fn_int_mask) | \ - (__LPU2HOST_MBOX_MASK_BITS | __ERROR_MASK_BITS)), \ - (bna)->regs.fn_int_mask) - -#define bna_mbox_intr_enable(bna) \ - writel((readl((bna)->regs.fn_int_mask) & \ - ~(__LPU2HOST_MBOX_MASK_BITS | __ERROR_MASK_BITS)), \ - (bna)->regs.fn_int_mask) - -#define bna_intr_status_get(_bna, _status) \ -{ \ - (_status) = readl((_bna)->regs.fn_int_status); \ - if ((_status)) { \ - writel((_status) & ~(__LPU02HOST_MBOX0_STATUS_BITS |\ - __LPU02HOST_MBOX1_STATUS_BITS |\ - __LPU12HOST_MBOX0_STATUS_BITS |\ - __LPU12HOST_MBOX1_STATUS_BITS), \ - (_bna)->regs.fn_int_status);\ - } \ -} - -#define bna_intr_status_get_no_clr(_bna, _status) \ - (_status) = readl((_bna)->regs.fn_int_status) - -#define bna_intr_mask_get(bna, mask) \ - (*mask) = readl((bna)->regs.fn_int_mask) - -#define bna_intr_ack(bna, intr_bmap) \ - writel((intr_bmap), (bna)->regs.fn_int_status) - -#define bna_ib_intx_disable(bna, ib_id) \ - writel(readl((bna)->regs.fn_int_mask) | \ - (1 << (ib_id)), \ - (bna)->regs.fn_int_mask) - -#define bna_ib_intx_enable(bna, ib_id) \ - writel(readl((bna)->regs.fn_int_mask) & \ - ~(1 << (ib_id)), \ - (bna)->regs.fn_int_mask) - -#define bna_mbox_msix_idx_set(_device) \ -do {\ - writel(((_device)->vector & 0x000001FF), \ - (_device)->bna->pcidev.pci_bar_kva + \ - reg_offset[(_device)->bna->pcidev.pci_func].msix_idx);\ -} while (0) - -/** - * - * TxQ, RxQ, CQ related bits, offsets, macros - * - */ - -#define BNA_Q_IDLE_STATE 0x00008001 - -#define BNA_GET_DOORBELL_BASE_ADDR(_bar0) \ - ((_bar0) + HQM_DOORBELL_BLK_BASE_ADDR) - -#define BNA_GET_DOORBELL_ENTRY_OFFSET(_entry) \ - ((HQM_DOORBELL_BLK_BASE_ADDR) \ - + (_entry << 7)) - -#define BNA_DOORBELL_IB_INT_ACK(_timeout, _events) \ - (0x80000000 | ((_timeout) << 16) | (_events)) - -#define BNA_DOORBELL_IB_INT_DISABLE (0x40000000) - -/* TxQ Entry Opcodes */ -#define BNA_TXQ_WI_SEND (0x402) /* Single Frame Transmission */ -#define BNA_TXQ_WI_SEND_LSO (0x403) /* Multi-Frame Transmission */ -#define BNA_TXQ_WI_EXTENSION (0x104) /* Extension WI */ - -/* TxQ Entry Control Flags */ -#define BNA_TXQ_WI_CF_FCOE_CRC (1 << 8) -#define BNA_TXQ_WI_CF_IPID_MODE (1 << 5) -#define BNA_TXQ_WI_CF_INS_PRIO (1 << 4) -#define BNA_TXQ_WI_CF_INS_VLAN (1 << 3) -#define BNA_TXQ_WI_CF_UDP_CKSUM (1 << 2) -#define BNA_TXQ_WI_CF_TCP_CKSUM (1 << 1) -#define BNA_TXQ_WI_CF_IP_CKSUM (1 << 0) - -#define BNA_TXQ_WI_L4_HDR_N_OFFSET(_hdr_size, _offset) \ - (((_hdr_size) << 10) | ((_offset) & 0x3FF)) - -/* - * Completion Q defines - */ -/* CQ Entry Flags */ -#define BNA_CQ_EF_MAC_ERROR (1 << 0) -#define BNA_CQ_EF_FCS_ERROR (1 << 1) -#define BNA_CQ_EF_TOO_LONG (1 << 2) -#define BNA_CQ_EF_FC_CRC_OK (1 << 3) - -#define BNA_CQ_EF_RSVD1 (1 << 4) -#define BNA_CQ_EF_L4_CKSUM_OK (1 << 5) -#define BNA_CQ_EF_L3_CKSUM_OK (1 << 6) -#define BNA_CQ_EF_HDS_HEADER (1 << 7) - -#define BNA_CQ_EF_UDP (1 << 8) -#define BNA_CQ_EF_TCP (1 << 9) -#define BNA_CQ_EF_IP_OPTIONS (1 << 10) -#define BNA_CQ_EF_IPV6 (1 << 11) - -#define BNA_CQ_EF_IPV4 (1 << 12) -#define BNA_CQ_EF_VLAN (1 << 13) -#define BNA_CQ_EF_RSS (1 << 14) -#define BNA_CQ_EF_RSVD2 (1 << 15) - -#define BNA_CQ_EF_MCAST_MATCH (1 << 16) -#define BNA_CQ_EF_MCAST (1 << 17) -#define BNA_CQ_EF_BCAST (1 << 18) -#define BNA_CQ_EF_REMOTE (1 << 19) - -#define BNA_CQ_EF_LOCAL (1 << 20) - -/** - * - * Data structures - * - */ - -enum txf_flags { - BFI_TXF_CF_ENABLE = 1 << 0, - BFI_TXF_CF_VLAN_FILTER = 1 << 8, - BFI_TXF_CF_VLAN_ADMIT = 1 << 9, - BFI_TXF_CF_VLAN_INSERT = 1 << 10, - BFI_TXF_CF_RSVD1 = 1 << 11, - BFI_TXF_CF_MAC_SA_CHECK = 1 << 12, - BFI_TXF_CF_VLAN_WI_BASED = 1 << 13, - BFI_TXF_CF_VSWITCH_MCAST = 1 << 14, - BFI_TXF_CF_VSWITCH_UCAST = 1 << 15, - BFI_TXF_CF_RSVD2 = 0x7F << 1 -}; - -enum ib_flags { - BFI_IB_CF_MASTER_ENABLE = (1 << 0), - BFI_IB_CF_MSIX_MODE = (1 << 1), - BFI_IB_CF_COALESCING_MODE = (1 << 2), - BFI_IB_CF_INTER_PKT_ENABLE = (1 << 3), - BFI_IB_CF_INT_ENABLE = (1 << 4), - BFI_IB_CF_INTER_PKT_DMA = (1 << 5), - BFI_IB_CF_ACK_PENDING = (1 << 6), - BFI_IB_CF_RESERVED1 = (1 << 7) -}; - -enum rss_hash_type { - BFI_RSS_T_V4_TCP = (1 << 11), - BFI_RSS_T_V4_IP = (1 << 10), - BFI_RSS_T_V6_TCP = (1 << 9), - BFI_RSS_T_V6_IP = (1 << 8) -}; -enum hds_header_type { - BNA_HDS_T_V4_TCP = (1 << 11), - BNA_HDS_T_V4_UDP = (1 << 10), - BNA_HDS_T_V6_TCP = (1 << 9), - BNA_HDS_T_V6_UDP = (1 << 8), - BNA_HDS_FORCED = (1 << 7), -}; -enum rxf_flags { - BNA_RXF_CF_SM_LG_RXQ = (1 << 15), - BNA_RXF_CF_DEFAULT_VLAN = (1 << 14), - BNA_RXF_CF_DEFAULT_FUNCTION_ENABLE = (1 << 13), - BNA_RXF_CF_VLAN_STRIP = (1 << 12), - BNA_RXF_CF_RSS_ENABLE = (1 << 8) -}; -struct bna_chip_regs_offset { - u32 page_addr; - u32 fn_int_status; - u32 fn_int_mask; - u32 msix_idx; -}; - -struct bna_chip_regs { - void __iomem *page_addr; - void __iomem *fn_int_status; - void __iomem *fn_int_mask; -}; - -struct bna_txq_mem { - u32 pg_tbl_addr_lo; - u32 pg_tbl_addr_hi; - u32 cur_q_entry_lo; - u32 cur_q_entry_hi; - u32 reserved1; - u32 reserved2; - u32 pg_cnt_n_prd_ptr; /* 31:16->total page count */ - /* 15:0 ->producer pointer (index?) */ - u32 entry_n_pg_size; /* 31:16->entry size */ - /* 15:0 ->page size */ - u32 int_blk_n_cns_ptr; /* 31:24->Int Blk Id; */ - /* 23:16->Int Blk Offset */ - /* 15:0 ->consumer pointer(index?) */ - u32 cns_ptr2_n_q_state; /* 31:16->cons. ptr 2; 15:0-> Q state */ - u32 nxt_qid_n_fid_n_pri; /* 17:10->next */ - /* QId;9:3->FID;2:0->Priority */ - u32 wvc_n_cquota_n_rquota; /* 31:24->WI Vector Count; */ - /* 23:12->Cfg Quota; */ - /* 11:0 ->Run Quota */ - u32 reserved3[4]; -}; - -struct bna_rxq_mem { - u32 pg_tbl_addr_lo; - u32 pg_tbl_addr_hi; - u32 cur_q_entry_lo; - u32 cur_q_entry_hi; - u32 reserved1; - u32 reserved2; - u32 pg_cnt_n_prd_ptr; /* 31:16->total page count */ - /* 15:0 ->producer pointer (index?) */ - u32 entry_n_pg_size; /* 31:16->entry size */ - /* 15:0 ->page size */ - u32 sg_n_cq_n_cns_ptr; /* 31:28->reserved; 27:24->sg count */ - /* 23:16->CQ; */ - /* 15:0->consumer pointer(index?) */ - u32 buf_sz_n_q_state; /* 31:16->buffer size; 15:0-> Q state */ - u32 next_qid; /* 17:10->next QId */ - u32 reserved3; - u32 reserved4[4]; -}; - -struct bna_rxtx_q_mem { - struct bna_rxq_mem rxq; - struct bna_txq_mem txq; -}; - -struct bna_cq_mem { - u32 pg_tbl_addr_lo; - u32 pg_tbl_addr_hi; - u32 cur_q_entry_lo; - u32 cur_q_entry_hi; - - u32 reserved1; - u32 reserved2; - u32 pg_cnt_n_prd_ptr; /* 31:16->total page count */ - /* 15:0 ->producer pointer (index?) */ - u32 entry_n_pg_size; /* 31:16->entry size */ - /* 15:0 ->page size */ - u32 int_blk_n_cns_ptr; /* 31:24->Int Blk Id; */ - /* 23:16->Int Blk Offset */ - /* 15:0 ->consumer pointer(index?) */ - u32 q_state; /* 31:16->reserved; 15:0-> Q state */ - u32 reserved3[2]; - u32 reserved4[4]; -}; - -struct bna_ib_blk_mem { - u32 host_addr_lo; - u32 host_addr_hi; - u32 clsc_n_ctrl_n_msix; /* 31:24->coalescing; */ - /* 23:16->coalescing cfg; */ - /* 15:8 ->control; */ - /* 7:0 ->msix; */ - u32 ipkt_n_ent_n_idxof; - u32 ipkt_cnt_cfg_n_unacked; - - u32 reserved[3]; -}; - -struct bna_idx_tbl_mem { - u32 idx; /* !< 31:16->res;15:0->idx; */ -}; - -struct bna_doorbell_qset { - u32 rxq[0x20 >> 2]; - u32 txq[0x20 >> 2]; - u32 ib0[0x20 >> 2]; - u32 ib1[0x20 >> 2]; -}; - -struct bna_rx_fndb_ram { - u32 rss_prop; - u32 size_routing_props; - u32 rit_hds_mcastq; - u32 control_flags; -}; - -struct bna_tx_fndb_ram { - u32 vlan_n_ctrl_flags; -}; - -/** - * @brief - * Structure which maps to RxFn Indirection Table (RIT) - * Size : 1 word - * See catapult_spec.pdf, RxA for details - */ -struct bna_rit_mem { - u32 rxq_ids; /* !< 31:12->res;11:0->two 6 bit RxQ Ids */ -}; - -/** - * @brief - * Structure which maps to RSS Table entry - * Size : 16 words - * See catapult_spec.pdf, RAD for details - */ -struct bna_rss_mem { - /* - * 31:12-> res - * 11:8 -> protocol type - * 7:0 -> hash index - */ - u32 type_n_hash; - u32 hash_key[10]; /* !< 40 byte Toeplitz hash key */ - u32 reserved[5]; -}; - -/* TxQ Vector (a.k.a. Tx-Buffer Descriptor) */ -struct bna_dma_addr { - u32 msb; - u32 lsb; -}; - -struct bna_txq_wi_vector { - u16 reserved; - u16 length; /* Only 14 LSB are valid */ - struct bna_dma_addr host_addr; /* Tx-Buf DMA addr */ -}; - -typedef u16 bna_txq_wi_opcode_t; - -typedef u16 bna_txq_wi_ctrl_flag_t; - -/** - * TxQ Entry Structure - * - * BEWARE: Load values into this structure with correct endianess. - */ -struct bna_txq_entry { - union { - struct { - u8 reserved; - u8 num_vectors; /* number of vectors present */ - bna_txq_wi_opcode_t opcode; /* Either */ - /* BNA_TXQ_WI_SEND or */ - /* BNA_TXQ_WI_SEND_LSO */ - bna_txq_wi_ctrl_flag_t flags; /* OR of all the flags */ - u16 l4_hdr_size_n_offset; - u16 vlan_tag; - u16 lso_mss; /* Only 14 LSB are valid */ - u32 frame_length; /* Only 24 LSB are valid */ - } wi; - - struct { - u16 reserved; - bna_txq_wi_opcode_t opcode; /* Must be */ - /* BNA_TXQ_WI_EXTENSION */ - u32 reserved2[3]; /* Place holder for */ - /* removed vector (12 bytes) */ - } wi_ext; - } hdr; - struct bna_txq_wi_vector vector[4]; -}; -#define wi_hdr hdr.wi -#define wi_ext_hdr hdr.wi_ext - -/* RxQ Entry Structure */ -struct bna_rxq_entry { /* Rx-Buffer */ - struct bna_dma_addr host_addr; /* Rx-Buffer DMA address */ -}; - -typedef u32 bna_cq_e_flag_t; - -/* CQ Entry Structure */ -struct bna_cq_entry { - bna_cq_e_flag_t flags; - u16 vlan_tag; - u16 length; - u32 rss_hash; - u8 valid; - u8 reserved1; - u8 reserved2; - u8 rxq_id; -}; - -#endif /* __BNA_HW_H__ */ diff --git a/drivers/net/ethernet/brocade/bna/bna_txrx.c b/drivers/net/ethernet/brocade/bna/bna_txrx.c deleted file mode 100644 index f0983c832447..000000000000 --- a/drivers/net/ethernet/brocade/bna/bna_txrx.c +++ /dev/null @@ -1,4185 +0,0 @@ -/* - * Linux network driver for Brocade Converged Network Adapter. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License (GPL) Version 2 as - * published by the Free Software Foundation - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - */ -/* - * Copyright (c) 2005-2010 Brocade Communications Systems, Inc. - * All rights reserved - * www.brocade.com - */ -#include "bna.h" -#include "bfa_cs.h" -#include "bfi.h" - -/** - * IB - */ -#define bna_ib_find_free_ibidx(_mask, _pos)\ -do {\ - (_pos) = 0;\ - while (((_pos) < (BFI_IBIDX_MAX_SEGSIZE)) &&\ - ((1 << (_pos)) & (_mask)))\ - (_pos)++;\ -} while (0) - -#define bna_ib_count_ibidx(_mask, _count)\ -do {\ - int pos = 0;\ - (_count) = 0;\ - while (pos < (BFI_IBIDX_MAX_SEGSIZE)) {\ - if ((1 << pos) & (_mask))\ - (_count) = pos + 1;\ - pos++;\ - } \ -} while (0) - -#define bna_ib_select_segpool(_count, _q_idx)\ -do {\ - int i;\ - (_q_idx) = -1;\ - for (i = 0; i < BFI_IBIDX_TOTAL_POOLS; i++) {\ - if ((_count <= ibidx_pool[i].pool_entry_size)) {\ - (_q_idx) = i;\ - break;\ - } \ - } \ -} while (0) - -struct bna_ibidx_pool { - int pool_size; - int pool_entry_size; -}; -init_ibidx_pool(ibidx_pool); - -static struct bna_intr * -bna_intr_get(struct bna_ib_mod *ib_mod, enum bna_intr_type intr_type, - int vector) -{ - struct bna_intr *intr; - struct list_head *qe; - - list_for_each(qe, &ib_mod->intr_active_q) { - intr = (struct bna_intr *)qe; - - if ((intr->intr_type == intr_type) && - (intr->vector == vector)) { - intr->ref_count++; - return intr; - } - } - - if (list_empty(&ib_mod->intr_free_q)) - return NULL; - - bfa_q_deq(&ib_mod->intr_free_q, &intr); - bfa_q_qe_init(&intr->qe); - - intr->ref_count = 1; - intr->intr_type = intr_type; - intr->vector = vector; - - list_add_tail(&intr->qe, &ib_mod->intr_active_q); - - return intr; -} - -static void -bna_intr_put(struct bna_ib_mod *ib_mod, - struct bna_intr *intr) -{ - intr->ref_count--; - - if (intr->ref_count == 0) { - intr->ib = NULL; - list_del(&intr->qe); - bfa_q_qe_init(&intr->qe); - list_add_tail(&intr->qe, &ib_mod->intr_free_q); - } -} - -void -bna_ib_mod_init(struct bna_ib_mod *ib_mod, struct bna *bna, - struct bna_res_info *res_info) -{ - int i; - int j; - int count; - u8 offset; - struct bna_doorbell_qset *qset; - unsigned long off; - - ib_mod->bna = bna; - - ib_mod->ib = (struct bna_ib *) - res_info[BNA_RES_MEM_T_IB_ARRAY].res_u.mem_info.mdl[0].kva; - ib_mod->intr = (struct bna_intr *) - res_info[BNA_RES_MEM_T_INTR_ARRAY].res_u.mem_info.mdl[0].kva; - ib_mod->idx_seg = (struct bna_ibidx_seg *) - res_info[BNA_RES_MEM_T_IDXSEG_ARRAY].res_u.mem_info.mdl[0].kva; - - INIT_LIST_HEAD(&ib_mod->ib_free_q); - INIT_LIST_HEAD(&ib_mod->intr_free_q); - INIT_LIST_HEAD(&ib_mod->intr_active_q); - - for (i = 0; i < BFI_IBIDX_TOTAL_POOLS; i++) - INIT_LIST_HEAD(&ib_mod->ibidx_seg_pool[i]); - - for (i = 0; i < BFI_MAX_IB; i++) { - ib_mod->ib[i].ib_id = i; - - ib_mod->ib[i].ib_seg_host_addr_kva = - res_info[BNA_RES_MEM_T_IBIDX].res_u.mem_info.mdl[i].kva; - ib_mod->ib[i].ib_seg_host_addr.lsb = - res_info[BNA_RES_MEM_T_IBIDX].res_u.mem_info.mdl[i].dma.lsb; - ib_mod->ib[i].ib_seg_host_addr.msb = - res_info[BNA_RES_MEM_T_IBIDX].res_u.mem_info.mdl[i].dma.msb; - - qset = (struct bna_doorbell_qset *)0; - off = (unsigned long)(&qset[i >> 1].ib0[(i & 0x1) - * (0x20 >> 2)]); - ib_mod->ib[i].door_bell.doorbell_addr = off + - BNA_GET_DOORBELL_BASE_ADDR(bna->pcidev.pci_bar_kva); - - bfa_q_qe_init(&ib_mod->ib[i].qe); - list_add_tail(&ib_mod->ib[i].qe, &ib_mod->ib_free_q); - - bfa_q_qe_init(&ib_mod->intr[i].qe); - list_add_tail(&ib_mod->intr[i].qe, &ib_mod->intr_free_q); - } - - count = 0; - offset = 0; - for (i = 0; i < BFI_IBIDX_TOTAL_POOLS; i++) { - for (j = 0; j < ibidx_pool[i].pool_size; j++) { - bfa_q_qe_init(&ib_mod->idx_seg[count]); - ib_mod->idx_seg[count].ib_seg_size = - ibidx_pool[i].pool_entry_size; - ib_mod->idx_seg[count].ib_idx_tbl_offset = offset; - list_add_tail(&ib_mod->idx_seg[count].qe, - &ib_mod->ibidx_seg_pool[i]); - count++; - offset += ibidx_pool[i].pool_entry_size; - } - } -} - -void -bna_ib_mod_uninit(struct bna_ib_mod *ib_mod) -{ - int i; - int j; - struct list_head *qe; - - i = 0; - list_for_each(qe, &ib_mod->ib_free_q) - i++; - - i = 0; - list_for_each(qe, &ib_mod->intr_free_q) - i++; - - for (i = 0; i < BFI_IBIDX_TOTAL_POOLS; i++) { - j = 0; - list_for_each(qe, &ib_mod->ibidx_seg_pool[i]) - j++; - } - - ib_mod->bna = NULL; -} - -static struct bna_ib * -bna_ib_get(struct bna_ib_mod *ib_mod, - enum bna_intr_type intr_type, - int vector) -{ - struct bna_ib *ib; - struct bna_intr *intr; - - if (intr_type == BNA_INTR_T_INTX) - vector = (1 << vector); - - intr = bna_intr_get(ib_mod, intr_type, vector); - if (intr == NULL) - return NULL; - - if (intr->ib) { - if (intr->ib->ref_count == BFI_IBIDX_MAX_SEGSIZE) { - bna_intr_put(ib_mod, intr); - return NULL; - } - intr->ib->ref_count++; - return intr->ib; - } - - if (list_empty(&ib_mod->ib_free_q)) { - bna_intr_put(ib_mod, intr); - return NULL; - } - - bfa_q_deq(&ib_mod->ib_free_q, &ib); - bfa_q_qe_init(&ib->qe); - - ib->ref_count = 1; - ib->start_count = 0; - ib->idx_mask = 0; - - ib->intr = intr; - ib->idx_seg = NULL; - intr->ib = ib; - - ib->bna = ib_mod->bna; - - return ib; -} - -static void -bna_ib_put(struct bna_ib_mod *ib_mod, struct bna_ib *ib) -{ - bna_intr_put(ib_mod, ib->intr); - - ib->ref_count--; - - if (ib->ref_count == 0) { - ib->intr = NULL; - ib->bna = NULL; - list_add_tail(&ib->qe, &ib_mod->ib_free_q); - } -} - -/* Returns index offset - starting from 0 */ -static int -bna_ib_reserve_idx(struct bna_ib *ib) -{ - struct bna_ib_mod *ib_mod = &ib->bna->ib_mod; - struct bna_ibidx_seg *idx_seg; - int idx; - int num_idx; - int q_idx; - - /* Find the first free index position */ - bna_ib_find_free_ibidx(ib->idx_mask, idx); - if (idx == BFI_IBIDX_MAX_SEGSIZE) - return -1; - - /* - * Calculate the total number of indexes held by this IB, - * including the index newly reserved above. - */ - bna_ib_count_ibidx((ib->idx_mask | (1 << idx)), num_idx); - - /* See if there is a free space in the index segment held by this IB */ - if (ib->idx_seg && (num_idx <= ib->idx_seg->ib_seg_size)) { - ib->idx_mask |= (1 << idx); - return idx; - } - - if (ib->start_count) - return -1; - - /* Allocate a new segment */ - bna_ib_select_segpool(num_idx, q_idx); - while (1) { - if (q_idx == BFI_IBIDX_TOTAL_POOLS) - return -1; - if (!list_empty(&ib_mod->ibidx_seg_pool[q_idx])) - break; - q_idx++; - } - bfa_q_deq(&ib_mod->ibidx_seg_pool[q_idx], &idx_seg); - bfa_q_qe_init(&idx_seg->qe); - - /* Free the old segment */ - if (ib->idx_seg) { - bna_ib_select_segpool(ib->idx_seg->ib_seg_size, q_idx); - list_add_tail(&ib->idx_seg->qe, &ib_mod->ibidx_seg_pool[q_idx]); - } - - ib->idx_seg = idx_seg; - - ib->idx_mask |= (1 << idx); - - return idx; -} - -static void -bna_ib_release_idx(struct bna_ib *ib, int idx) -{ - struct bna_ib_mod *ib_mod = &ib->bna->ib_mod; - struct bna_ibidx_seg *idx_seg; - int num_idx; - int cur_q_idx; - int new_q_idx; - - ib->idx_mask &= ~(1 << idx); - - if (ib->start_count) - return; - - bna_ib_count_ibidx(ib->idx_mask, num_idx); - - /* - * Free the segment, if there are no more indexes in the segment - * held by this IB - */ - if (!num_idx) { - bna_ib_select_segpool(ib->idx_seg->ib_seg_size, cur_q_idx); - list_add_tail(&ib->idx_seg->qe, - &ib_mod->ibidx_seg_pool[cur_q_idx]); - ib->idx_seg = NULL; - return; - } - - /* See if we can move to a smaller segment */ - bna_ib_select_segpool(num_idx, new_q_idx); - bna_ib_select_segpool(ib->idx_seg->ib_seg_size, cur_q_idx); - while (new_q_idx < cur_q_idx) { - if (!list_empty(&ib_mod->ibidx_seg_pool[new_q_idx])) - break; - new_q_idx++; - } - if (new_q_idx < cur_q_idx) { - /* Select the new smaller segment */ - bfa_q_deq(&ib_mod->ibidx_seg_pool[new_q_idx], &idx_seg); - bfa_q_qe_init(&idx_seg->qe); - /* Free the old segment */ - list_add_tail(&ib->idx_seg->qe, - &ib_mod->ibidx_seg_pool[cur_q_idx]); - ib->idx_seg = idx_seg; - } -} - -static int -bna_ib_config(struct bna_ib *ib, struct bna_ib_config *ib_config) -{ - if (ib->start_count) - return -1; - - ib->ib_config.coalescing_timeo = ib_config->coalescing_timeo; - ib->ib_config.interpkt_timeo = ib_config->interpkt_timeo; - ib->ib_config.interpkt_count = ib_config->interpkt_count; - ib->ib_config.ctrl_flags = ib_config->ctrl_flags; - - ib->ib_config.ctrl_flags |= BFI_IB_CF_MASTER_ENABLE; - if (ib->intr->intr_type == BNA_INTR_T_MSIX) - ib->ib_config.ctrl_flags |= BFI_IB_CF_MSIX_MODE; - - return 0; -} - -static void -bna_ib_start(struct bna_ib *ib) -{ - struct bna_ib_blk_mem ib_cfg; - struct bna_ib_blk_mem *ib_mem; - u32 pg_num; - u32 intx_mask; - int i; - void __iomem *base_addr; - unsigned long off; - - ib->start_count++; - - if (ib->start_count > 1) - return; - - ib_cfg.host_addr_lo = (u32)(ib->ib_seg_host_addr.lsb); - ib_cfg.host_addr_hi = (u32)(ib->ib_seg_host_addr.msb); - - ib_cfg.clsc_n_ctrl_n_msix = (((u32) - ib->ib_config.coalescing_timeo << 16) | - ((u32)ib->ib_config.ctrl_flags << 8) | - (ib->intr->vector)); - ib_cfg.ipkt_n_ent_n_idxof = - ((u32) - (ib->ib_config.interpkt_timeo & 0xf) << 16) | - ((u32)ib->idx_seg->ib_seg_size << 8) | - (ib->idx_seg->ib_idx_tbl_offset); - ib_cfg.ipkt_cnt_cfg_n_unacked = ((u32) - ib->ib_config.interpkt_count << 24); - - pg_num = BNA_GET_PAGE_NUM(HQM0_BLK_PG_NUM + ib->bna->port_num, - HQM_IB_RAM_BASE_OFFSET); - writel(pg_num, ib->bna->regs.page_addr); - - base_addr = BNA_GET_MEM_BASE_ADDR(ib->bna->pcidev.pci_bar_kva, - HQM_IB_RAM_BASE_OFFSET); - - ib_mem = (struct bna_ib_blk_mem *)0; - off = (unsigned long)&ib_mem[ib->ib_id].host_addr_lo; - writel(htonl(ib_cfg.host_addr_lo), base_addr + off); - - off = (unsigned long)&ib_mem[ib->ib_id].host_addr_hi; - writel(htonl(ib_cfg.host_addr_hi), base_addr + off); - - off = (unsigned long)&ib_mem[ib->ib_id].clsc_n_ctrl_n_msix; - writel(ib_cfg.clsc_n_ctrl_n_msix, base_addr + off); - - off = (unsigned long)&ib_mem[ib->ib_id].ipkt_n_ent_n_idxof; - writel(ib_cfg.ipkt_n_ent_n_idxof, base_addr + off); - - off = (unsigned long)&ib_mem[ib->ib_id].ipkt_cnt_cfg_n_unacked; - writel(ib_cfg.ipkt_cnt_cfg_n_unacked, base_addr + off); - - ib->door_bell.doorbell_ack = BNA_DOORBELL_IB_INT_ACK( - (u32)ib->ib_config.coalescing_timeo, 0); - - pg_num = BNA_GET_PAGE_NUM(HQM0_BLK_PG_NUM + ib->bna->port_num, - HQM_INDX_TBL_RAM_BASE_OFFSET); - writel(pg_num, ib->bna->regs.page_addr); - - base_addr = BNA_GET_MEM_BASE_ADDR(ib->bna->pcidev.pci_bar_kva, - HQM_INDX_TBL_RAM_BASE_OFFSET); - for (i = 0; i < ib->idx_seg->ib_seg_size; i++) { - off = (unsigned long) - ((ib->idx_seg->ib_idx_tbl_offset + i) * BFI_IBIDX_SIZE); - writel(0, base_addr + off); - } - - if (ib->intr->intr_type == BNA_INTR_T_INTX) { - bna_intx_disable(ib->bna, intx_mask); - intx_mask &= ~(ib->intr->vector); - bna_intx_enable(ib->bna, intx_mask); - } -} - -static void -bna_ib_stop(struct bna_ib *ib) -{ - u32 intx_mask; - - ib->start_count--; - - if (ib->start_count == 0) { - writel(BNA_DOORBELL_IB_INT_DISABLE, - ib->door_bell.doorbell_addr); - if (ib->intr->intr_type == BNA_INTR_T_INTX) { - bna_intx_disable(ib->bna, intx_mask); - intx_mask |= (ib->intr->vector); - bna_intx_enable(ib->bna, intx_mask); - } - } -} - -static void -bna_ib_fail(struct bna_ib *ib) -{ - ib->start_count = 0; -} - -/** - * RXF - */ -static void rxf_enable(struct bna_rxf *rxf); -static void rxf_disable(struct bna_rxf *rxf); -static void __rxf_config_set(struct bna_rxf *rxf); -static void __rxf_rit_set(struct bna_rxf *rxf); -static void __bna_rxf_stat_clr(struct bna_rxf *rxf); -static int rxf_process_packet_filter(struct bna_rxf *rxf); -static int rxf_clear_packet_filter(struct bna_rxf *rxf); -static void rxf_reset_packet_filter(struct bna_rxf *rxf); -static void rxf_cb_enabled(void *arg, int status); -static void rxf_cb_disabled(void *arg, int status); -static void bna_rxf_cb_stats_cleared(void *arg, int status); -static void __rxf_enable(struct bna_rxf *rxf); -static void __rxf_disable(struct bna_rxf *rxf); - -bfa_fsm_state_decl(bna_rxf, stopped, struct bna_rxf, - enum bna_rxf_event); -bfa_fsm_state_decl(bna_rxf, start_wait, struct bna_rxf, - enum bna_rxf_event); -bfa_fsm_state_decl(bna_rxf, cam_fltr_mod_wait, struct bna_rxf, - enum bna_rxf_event); -bfa_fsm_state_decl(bna_rxf, started, struct bna_rxf, - enum bna_rxf_event); -bfa_fsm_state_decl(bna_rxf, cam_fltr_clr_wait, struct bna_rxf, - enum bna_rxf_event); -bfa_fsm_state_decl(bna_rxf, stop_wait, struct bna_rxf, - enum bna_rxf_event); -bfa_fsm_state_decl(bna_rxf, pause_wait, struct bna_rxf, - enum bna_rxf_event); -bfa_fsm_state_decl(bna_rxf, resume_wait, struct bna_rxf, - enum bna_rxf_event); -bfa_fsm_state_decl(bna_rxf, stat_clr_wait, struct bna_rxf, - enum bna_rxf_event); - -static struct bfa_sm_table rxf_sm_table[] = { - {BFA_SM(bna_rxf_sm_stopped), BNA_RXF_STOPPED}, - {BFA_SM(bna_rxf_sm_start_wait), BNA_RXF_START_WAIT}, - {BFA_SM(bna_rxf_sm_cam_fltr_mod_wait), BNA_RXF_CAM_FLTR_MOD_WAIT}, - {BFA_SM(bna_rxf_sm_started), BNA_RXF_STARTED}, - {BFA_SM(bna_rxf_sm_cam_fltr_clr_wait), BNA_RXF_CAM_FLTR_CLR_WAIT}, - {BFA_SM(bna_rxf_sm_stop_wait), BNA_RXF_STOP_WAIT}, - {BFA_SM(bna_rxf_sm_pause_wait), BNA_RXF_PAUSE_WAIT}, - {BFA_SM(bna_rxf_sm_resume_wait), BNA_RXF_RESUME_WAIT}, - {BFA_SM(bna_rxf_sm_stat_clr_wait), BNA_RXF_STAT_CLR_WAIT} -}; - -static void -bna_rxf_sm_stopped_entry(struct bna_rxf *rxf) -{ - call_rxf_stop_cbfn(rxf, BNA_CB_SUCCESS); -} - -static void -bna_rxf_sm_stopped(struct bna_rxf *rxf, enum bna_rxf_event event) -{ - switch (event) { - case RXF_E_START: - bfa_fsm_set_state(rxf, bna_rxf_sm_start_wait); - break; - - case RXF_E_STOP: - bfa_fsm_set_state(rxf, bna_rxf_sm_stopped); - break; - - case RXF_E_FAIL: - /* No-op */ - break; - - case RXF_E_CAM_FLTR_MOD: - call_rxf_cam_fltr_cbfn(rxf, BNA_CB_SUCCESS); - break; - - case RXF_E_STARTED: - case RXF_E_STOPPED: - case RXF_E_CAM_FLTR_RESP: - /** - * These events are received due to flushing of mbox - * when device fails - */ - /* No-op */ - break; - - case RXF_E_PAUSE: - rxf->rxf_oper_state = BNA_RXF_OPER_STATE_PAUSED; - call_rxf_pause_cbfn(rxf, BNA_CB_SUCCESS); - break; - - case RXF_E_RESUME: - rxf->rxf_oper_state = BNA_RXF_OPER_STATE_RUNNING; - call_rxf_resume_cbfn(rxf, BNA_CB_SUCCESS); - break; - - default: - bfa_sm_fault(event); - } -} - -static void -bna_rxf_sm_start_wait_entry(struct bna_rxf *rxf) -{ - __rxf_config_set(rxf); - __rxf_rit_set(rxf); - rxf_enable(rxf); -} - -static void -bna_rxf_sm_start_wait(struct bna_rxf *rxf, enum bna_rxf_event event) -{ - switch (event) { - case RXF_E_STOP: - /** - * STOP is originated from bnad. When this happens, - * it can not be waiting for filter update - */ - call_rxf_start_cbfn(rxf, BNA_CB_INTERRUPT); - bfa_fsm_set_state(rxf, bna_rxf_sm_stop_wait); - break; - - case RXF_E_FAIL: - call_rxf_cam_fltr_cbfn(rxf, BNA_CB_SUCCESS); - call_rxf_start_cbfn(rxf, BNA_CB_FAIL); - bfa_fsm_set_state(rxf, bna_rxf_sm_stopped); - break; - - case RXF_E_CAM_FLTR_MOD: - /* No-op */ - break; - - case RXF_E_STARTED: - /** - * Force rxf_process_filter() to go through initial - * config - */ - if ((rxf->ucast_active_mac != NULL) && - (rxf->ucast_pending_set == 0)) - rxf->ucast_pending_set = 1; - - if (rxf->rss_status == BNA_STATUS_T_ENABLED) - rxf->rxf_flags |= BNA_RXF_FL_RSS_CONFIG_PENDING; - - rxf->rxf_flags |= BNA_RXF_FL_VLAN_CONFIG_PENDING; - - bfa_fsm_set_state(rxf, bna_rxf_sm_cam_fltr_mod_wait); - break; - - case RXF_E_PAUSE: - case RXF_E_RESUME: - rxf->rxf_flags |= BNA_RXF_FL_OPERSTATE_CHANGED; - break; - - default: - bfa_sm_fault(event); - } -} - -static void -bna_rxf_sm_cam_fltr_mod_wait_entry(struct bna_rxf *rxf) -{ - if (!rxf_process_packet_filter(rxf)) { - /* No more pending CAM entries to update */ - bfa_fsm_set_state(rxf, bna_rxf_sm_started); - } -} - -static void -bna_rxf_sm_cam_fltr_mod_wait(struct bna_rxf *rxf, enum bna_rxf_event event) -{ - switch (event) { - case RXF_E_STOP: - /** - * STOP is originated from bnad. When this happens, - * it can not be waiting for filter update - */ - call_rxf_start_cbfn(rxf, BNA_CB_INTERRUPT); - bfa_fsm_set_state(rxf, bna_rxf_sm_cam_fltr_clr_wait); - break; - - case RXF_E_FAIL: - rxf_reset_packet_filter(rxf); - call_rxf_cam_fltr_cbfn(rxf, BNA_CB_SUCCESS); - call_rxf_start_cbfn(rxf, BNA_CB_FAIL); - bfa_fsm_set_state(rxf, bna_rxf_sm_stopped); - break; - - case RXF_E_CAM_FLTR_MOD: - /* No-op */ - break; - - case RXF_E_CAM_FLTR_RESP: - if (!rxf_process_packet_filter(rxf)) { - /* No more pending CAM entries to update */ - call_rxf_cam_fltr_cbfn(rxf, BNA_CB_SUCCESS); - bfa_fsm_set_state(rxf, bna_rxf_sm_started); - } - break; - - case RXF_E_PAUSE: - case RXF_E_RESUME: - rxf->rxf_flags |= BNA_RXF_FL_OPERSTATE_CHANGED; - break; - - default: - bfa_sm_fault(event); - } -} - -static void -bna_rxf_sm_started_entry(struct bna_rxf *rxf) -{ - call_rxf_start_cbfn(rxf, BNA_CB_SUCCESS); - - if (rxf->rxf_flags & BNA_RXF_FL_OPERSTATE_CHANGED) { - if (rxf->rxf_oper_state == BNA_RXF_OPER_STATE_PAUSED) - bfa_fsm_send_event(rxf, RXF_E_PAUSE); - else - bfa_fsm_send_event(rxf, RXF_E_RESUME); - } - -} - -static void -bna_rxf_sm_started(struct bna_rxf *rxf, enum bna_rxf_event event) -{ - switch (event) { - case RXF_E_STOP: - bfa_fsm_set_state(rxf, bna_rxf_sm_cam_fltr_clr_wait); - /* Hack to get FSM start clearing CAM entries */ - bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_RESP); - break; - - case RXF_E_FAIL: - rxf_reset_packet_filter(rxf); - bfa_fsm_set_state(rxf, bna_rxf_sm_stopped); - break; - - case RXF_E_CAM_FLTR_MOD: - bfa_fsm_set_state(rxf, bna_rxf_sm_cam_fltr_mod_wait); - break; - - case RXF_E_PAUSE: - bfa_fsm_set_state(rxf, bna_rxf_sm_pause_wait); - break; - - case RXF_E_RESUME: - bfa_fsm_set_state(rxf, bna_rxf_sm_resume_wait); - break; - - default: - bfa_sm_fault(event); - } -} - -static void -bna_rxf_sm_cam_fltr_clr_wait_entry(struct bna_rxf *rxf) -{ - /** - * Note: Do not add rxf_clear_packet_filter here. - * It will overstep mbox when this transition happens: - * cam_fltr_mod_wait -> cam_fltr_clr_wait on RXF_E_STOP event - */ -} - -static void -bna_rxf_sm_cam_fltr_clr_wait(struct bna_rxf *rxf, enum bna_rxf_event event) -{ - switch (event) { - case RXF_E_FAIL: - /** - * FSM was in the process of stopping, initiated by - * bnad. When this happens, no one can be waiting for - * start or filter update - */ - rxf_reset_packet_filter(rxf); - bfa_fsm_set_state(rxf, bna_rxf_sm_stopped); - break; - - case RXF_E_CAM_FLTR_RESP: - if (!rxf_clear_packet_filter(rxf)) { - /* No more pending CAM entries to clear */ - bfa_fsm_set_state(rxf, bna_rxf_sm_stop_wait); - rxf_disable(rxf); - } - break; - - default: - bfa_sm_fault(event); - } -} - -static void -bna_rxf_sm_stop_wait_entry(struct bna_rxf *rxf) -{ - /** - * NOTE: Do not add rxf_disable here. - * It will overstep mbox when this transition happens: - * start_wait -> stop_wait on RXF_E_STOP event - */ -} - -static void -bna_rxf_sm_stop_wait(struct bna_rxf *rxf, enum bna_rxf_event event) -{ - switch (event) { - case RXF_E_FAIL: - /** - * FSM was in the process of stopping, initiated by - * bnad. When this happens, no one can be waiting for - * start or filter update - */ - bfa_fsm_set_state(rxf, bna_rxf_sm_stopped); - break; - - case RXF_E_STARTED: - /** - * This event is received due to abrupt transition from - * bna_rxf_sm_start_wait state on receiving - * RXF_E_STOP event - */ - rxf_disable(rxf); - break; - - case RXF_E_STOPPED: - /** - * FSM was in the process of stopping, initiated by - * bnad. When this happens, no one can be waiting for - * start or filter update - */ - bfa_fsm_set_state(rxf, bna_rxf_sm_stat_clr_wait); - break; - - case RXF_E_PAUSE: - rxf->rxf_oper_state = BNA_RXF_OPER_STATE_PAUSED; - break; - - case RXF_E_RESUME: - rxf->rxf_oper_state = BNA_RXF_OPER_STATE_RUNNING; - break; - - default: - bfa_sm_fault(event); - } -} - -static void -bna_rxf_sm_pause_wait_entry(struct bna_rxf *rxf) -{ - rxf->rxf_flags &= - ~(BNA_RXF_FL_OPERSTATE_CHANGED | BNA_RXF_FL_RXF_ENABLED); - __rxf_disable(rxf); -} - -static void -bna_rxf_sm_pause_wait(struct bna_rxf *rxf, enum bna_rxf_event event) -{ - switch (event) { - case RXF_E_FAIL: - /** - * FSM was in the process of disabling rxf, initiated by - * bnad. - */ - call_rxf_pause_cbfn(rxf, BNA_CB_FAIL); - bfa_fsm_set_state(rxf, bna_rxf_sm_stopped); - break; - - case RXF_E_STOPPED: - rxf->rxf_oper_state = BNA_RXF_OPER_STATE_PAUSED; - call_rxf_pause_cbfn(rxf, BNA_CB_SUCCESS); - bfa_fsm_set_state(rxf, bna_rxf_sm_started); - break; - - /* - * Since PAUSE/RESUME can only be sent by bnad, we don't expect - * any other event during these states - */ - default: - bfa_sm_fault(event); - } -} - -static void -bna_rxf_sm_resume_wait_entry(struct bna_rxf *rxf) -{ - rxf->rxf_flags &= ~(BNA_RXF_FL_OPERSTATE_CHANGED); - rxf->rxf_flags |= BNA_RXF_FL_RXF_ENABLED; - __rxf_enable(rxf); -} - -static void -bna_rxf_sm_resume_wait(struct bna_rxf *rxf, enum bna_rxf_event event) -{ - switch (event) { - case RXF_E_FAIL: - /** - * FSM was in the process of disabling rxf, initiated by - * bnad. - */ - call_rxf_resume_cbfn(rxf, BNA_CB_FAIL); - bfa_fsm_set_state(rxf, bna_rxf_sm_stopped); - break; - - case RXF_E_STARTED: - rxf->rxf_oper_state = BNA_RXF_OPER_STATE_RUNNING; - call_rxf_resume_cbfn(rxf, BNA_CB_SUCCESS); - bfa_fsm_set_state(rxf, bna_rxf_sm_started); - break; - - /* - * Since PAUSE/RESUME can only be sent by bnad, we don't expect - * any other event during these states - */ - default: - bfa_sm_fault(event); - } -} - -static void -bna_rxf_sm_stat_clr_wait_entry(struct bna_rxf *rxf) -{ - __bna_rxf_stat_clr(rxf); -} - -static void -bna_rxf_sm_stat_clr_wait(struct bna_rxf *rxf, enum bna_rxf_event event) -{ - switch (event) { - case RXF_E_FAIL: - case RXF_E_STAT_CLEARED: - bfa_fsm_set_state(rxf, bna_rxf_sm_stopped); - break; - - default: - bfa_sm_fault(event); - } -} - -static void -__rxf_enable(struct bna_rxf *rxf) -{ - struct bfi_ll_rxf_multi_req ll_req; - u32 bm[2] = {0, 0}; - - if (rxf->rxf_id < 32) - bm[0] = 1 << rxf->rxf_id; - else - bm[1] = 1 << (rxf->rxf_id - 32); - - bfi_h2i_set(ll_req.mh, BFI_MC_LL, BFI_LL_H2I_RX_REQ, 0); - ll_req.rxf_id_mask[0] = htonl(bm[0]); - ll_req.rxf_id_mask[1] = htonl(bm[1]); - ll_req.enable = 1; - - bna_mbox_qe_fill(&rxf->mbox_qe, &ll_req, sizeof(ll_req), - rxf_cb_enabled, rxf); - - bna_mbox_send(rxf->rx->bna, &rxf->mbox_qe); -} - -static void -__rxf_disable(struct bna_rxf *rxf) -{ - struct bfi_ll_rxf_multi_req ll_req; - u32 bm[2] = {0, 0}; - - if (rxf->rxf_id < 32) - bm[0] = 1 << rxf->rxf_id; - else - bm[1] = 1 << (rxf->rxf_id - 32); - - bfi_h2i_set(ll_req.mh, BFI_MC_LL, BFI_LL_H2I_RX_REQ, 0); - ll_req.rxf_id_mask[0] = htonl(bm[0]); - ll_req.rxf_id_mask[1] = htonl(bm[1]); - ll_req.enable = 0; - - bna_mbox_qe_fill(&rxf->mbox_qe, &ll_req, sizeof(ll_req), - rxf_cb_disabled, rxf); - - bna_mbox_send(rxf->rx->bna, &rxf->mbox_qe); -} - -static void -__rxf_config_set(struct bna_rxf *rxf) -{ - u32 i; - struct bna_rss_mem *rss_mem; - struct bna_rx_fndb_ram *rx_fndb_ram; - struct bna *bna = rxf->rx->bna; - void __iomem *base_addr; - unsigned long off; - - base_addr = BNA_GET_MEM_BASE_ADDR(bna->pcidev.pci_bar_kva, - RSS_TABLE_BASE_OFFSET); - - rss_mem = (struct bna_rss_mem *)0; - - /* Configure RSS if required */ - if (rxf->ctrl_flags & BNA_RXF_CF_RSS_ENABLE) { - /* configure RSS Table */ - writel(BNA_GET_PAGE_NUM(RAD0_MEM_BLK_BASE_PG_NUM + - bna->port_num, RSS_TABLE_BASE_OFFSET), - bna->regs.page_addr); - - /* temporarily disable RSS, while hash value is written */ - off = (unsigned long)&rss_mem[0].type_n_hash; - writel(0, base_addr + off); - - for (i = 0; i < BFI_RSS_HASH_KEY_LEN; i++) { - off = (unsigned long) - &rss_mem[0].hash_key[(BFI_RSS_HASH_KEY_LEN - 1) - i]; - writel(htonl(rxf->rss_cfg.toeplitz_hash_key[i]), - base_addr + off); - } - - off = (unsigned long)&rss_mem[0].type_n_hash; - writel(rxf->rss_cfg.hash_type | rxf->rss_cfg.hash_mask, - base_addr + off); - } - - /* Configure RxF */ - writel(BNA_GET_PAGE_NUM( - LUT0_MEM_BLK_BASE_PG_NUM + (bna->port_num * 2), - RX_FNDB_RAM_BASE_OFFSET), - bna->regs.page_addr); - - base_addr = BNA_GET_MEM_BASE_ADDR(bna->pcidev.pci_bar_kva, - RX_FNDB_RAM_BASE_OFFSET); - - rx_fndb_ram = (struct bna_rx_fndb_ram *)0; - - /* We always use RSS table 0 */ - off = (unsigned long)&rx_fndb_ram[rxf->rxf_id].rss_prop; - writel(rxf->ctrl_flags & BNA_RXF_CF_RSS_ENABLE, - base_addr + off); - - /* small large buffer enable/disable */ - off = (unsigned long)&rx_fndb_ram[rxf->rxf_id].size_routing_props; - writel((rxf->ctrl_flags & BNA_RXF_CF_SM_LG_RXQ) | 0x80, - base_addr + off); - - /* RIT offset, HDS forced offset, multicast RxQ Id */ - off = (unsigned long)&rx_fndb_ram[rxf->rxf_id].rit_hds_mcastq; - writel((rxf->rit_segment->rit_offset << 16) | - (rxf->forced_offset << 8) | - (rxf->hds_cfg.hdr_type & BNA_HDS_FORCED) | rxf->mcast_rxq_id, - base_addr + off); - - /* - * default vlan tag, default function enable, strip vlan bytes, - * HDS type, header size - */ - - off = (unsigned long)&rx_fndb_ram[rxf->rxf_id].control_flags; - writel(((u32)rxf->default_vlan_tag << 16) | - (rxf->ctrl_flags & - (BNA_RXF_CF_DEFAULT_VLAN | - BNA_RXF_CF_DEFAULT_FUNCTION_ENABLE | - BNA_RXF_CF_VLAN_STRIP)) | - (rxf->hds_cfg.hdr_type & ~BNA_HDS_FORCED) | - rxf->hds_cfg.header_size, - base_addr + off); -} - -void -__rxf_vlan_filter_set(struct bna_rxf *rxf, enum bna_status status) -{ - struct bna *bna = rxf->rx->bna; - int i; - - writel(BNA_GET_PAGE_NUM(LUT0_MEM_BLK_BASE_PG_NUM + - (bna->port_num * 2), VLAN_RAM_BASE_OFFSET), - bna->regs.page_addr); - - if (status == BNA_STATUS_T_ENABLED) { - /* enable VLAN filtering on this function */ - for (i = 0; i <= BFI_MAX_VLAN / 32; i++) { - writel(rxf->vlan_filter_table[i], - BNA_GET_VLAN_MEM_ENTRY_ADDR - (bna->pcidev.pci_bar_kva, rxf->rxf_id, - i * 32)); - } - } else { - /* disable VLAN filtering on this function */ - for (i = 0; i <= BFI_MAX_VLAN / 32; i++) { - writel(0xffffffff, - BNA_GET_VLAN_MEM_ENTRY_ADDR - (bna->pcidev.pci_bar_kva, rxf->rxf_id, - i * 32)); - } - } -} - -static void -__rxf_rit_set(struct bna_rxf *rxf) -{ - struct bna *bna = rxf->rx->bna; - struct bna_rit_mem *rit_mem; - int i; - void __iomem *base_addr; - unsigned long off; - - base_addr = BNA_GET_MEM_BASE_ADDR(bna->pcidev.pci_bar_kva, - FUNCTION_TO_RXQ_TRANSLATE); - - rit_mem = (struct bna_rit_mem *)0; - - writel(BNA_GET_PAGE_NUM(RXA0_MEM_BLK_BASE_PG_NUM + bna->port_num, - FUNCTION_TO_RXQ_TRANSLATE), - bna->regs.page_addr); - - for (i = 0; i < rxf->rit_segment->rit_size; i++) { - off = (unsigned long)&rit_mem[i + rxf->rit_segment->rit_offset]; - writel(rxf->rit_segment->rit[i].large_rxq_id << 6 | - rxf->rit_segment->rit[i].small_rxq_id, - base_addr + off); - } -} - -static void -__bna_rxf_stat_clr(struct bna_rxf *rxf) -{ - struct bfi_ll_stats_req ll_req; - u32 bm[2] = {0, 0}; - - if (rxf->rxf_id < 32) - bm[0] = 1 << rxf->rxf_id; - else - bm[1] = 1 << (rxf->rxf_id - 32); - - bfi_h2i_set(ll_req.mh, BFI_MC_LL, BFI_LL_H2I_STATS_CLEAR_REQ, 0); - ll_req.stats_mask = 0; - ll_req.txf_id_mask[0] = 0; - ll_req.txf_id_mask[1] = 0; - - ll_req.rxf_id_mask[0] = htonl(bm[0]); - ll_req.rxf_id_mask[1] = htonl(bm[1]); - - bna_mbox_qe_fill(&rxf->mbox_qe, &ll_req, sizeof(ll_req), - bna_rxf_cb_stats_cleared, rxf); - bna_mbox_send(rxf->rx->bna, &rxf->mbox_qe); -} - -static void -rxf_enable(struct bna_rxf *rxf) -{ - if (rxf->rxf_oper_state == BNA_RXF_OPER_STATE_PAUSED) - bfa_fsm_send_event(rxf, RXF_E_STARTED); - else { - rxf->rxf_flags |= BNA_RXF_FL_RXF_ENABLED; - __rxf_enable(rxf); - } -} - -static void -rxf_cb_enabled(void *arg, int status) -{ - struct bna_rxf *rxf = (struct bna_rxf *)arg; - - bfa_q_qe_init(&rxf->mbox_qe.qe); - bfa_fsm_send_event(rxf, RXF_E_STARTED); -} - -static void -rxf_disable(struct bna_rxf *rxf) -{ - if (rxf->rxf_oper_state == BNA_RXF_OPER_STATE_PAUSED) - bfa_fsm_send_event(rxf, RXF_E_STOPPED); - else - rxf->rxf_flags &= ~BNA_RXF_FL_RXF_ENABLED; - __rxf_disable(rxf); -} - -static void -rxf_cb_disabled(void *arg, int status) -{ - struct bna_rxf *rxf = (struct bna_rxf *)arg; - - bfa_q_qe_init(&rxf->mbox_qe.qe); - bfa_fsm_send_event(rxf, RXF_E_STOPPED); -} - -void -rxf_cb_cam_fltr_mbox_cmd(void *arg, int status) -{ - struct bna_rxf *rxf = (struct bna_rxf *)arg; - - bfa_q_qe_init(&rxf->mbox_qe.qe); - - bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_RESP); -} - -static void -bna_rxf_cb_stats_cleared(void *arg, int status) -{ - struct bna_rxf *rxf = (struct bna_rxf *)arg; - - bfa_q_qe_init(&rxf->mbox_qe.qe); - bfa_fsm_send_event(rxf, RXF_E_STAT_CLEARED); -} - -void -rxf_cam_mbox_cmd(struct bna_rxf *rxf, u8 cmd, - const struct bna_mac *mac_addr) -{ - struct bfi_ll_mac_addr_req req; - - bfi_h2i_set(req.mh, BFI_MC_LL, cmd, 0); - - req.rxf_id = rxf->rxf_id; - memcpy(&req.mac_addr, (void *)&mac_addr->addr, ETH_ALEN); - - bna_mbox_qe_fill(&rxf->mbox_qe, &req, sizeof(req), - rxf_cb_cam_fltr_mbox_cmd, rxf); - - bna_mbox_send(rxf->rx->bna, &rxf->mbox_qe); -} - -static int -rxf_process_packet_filter_mcast(struct bna_rxf *rxf) -{ - struct bna_mac *mac = NULL; - struct list_head *qe; - - /* Add multicast entries */ - if (!list_empty(&rxf->mcast_pending_add_q)) { - bfa_q_deq(&rxf->mcast_pending_add_q, &qe); - bfa_q_qe_init(qe); - mac = (struct bna_mac *)qe; - rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_ADD_REQ, mac); - list_add_tail(&mac->qe, &rxf->mcast_active_q); - return 1; - } - - /* Delete multicast entries previousely added */ - if (!list_empty(&rxf->mcast_pending_del_q)) { - bfa_q_deq(&rxf->mcast_pending_del_q, &qe); - bfa_q_qe_init(qe); - mac = (struct bna_mac *)qe; - rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_DEL_REQ, mac); - bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac); - return 1; - } - - return 0; -} - -static int -rxf_process_packet_filter_vlan(struct bna_rxf *rxf) -{ - /* Apply the VLAN filter */ - if (rxf->rxf_flags & BNA_RXF_FL_VLAN_CONFIG_PENDING) { - rxf->rxf_flags &= ~BNA_RXF_FL_VLAN_CONFIG_PENDING; - if (!(rxf->rxmode_active & BNA_RXMODE_PROMISC)) - __rxf_vlan_filter_set(rxf, rxf->vlan_filter_status); - } - - /* Apply RSS configuration */ - if (rxf->rxf_flags & BNA_RXF_FL_RSS_CONFIG_PENDING) { - rxf->rxf_flags &= ~BNA_RXF_FL_RSS_CONFIG_PENDING; - if (rxf->rss_status == BNA_STATUS_T_DISABLED) { - /* RSS is being disabled */ - rxf->ctrl_flags &= ~BNA_RXF_CF_RSS_ENABLE; - __rxf_rit_set(rxf); - __rxf_config_set(rxf); - } else { - /* RSS is being enabled or reconfigured */ - rxf->ctrl_flags |= BNA_RXF_CF_RSS_ENABLE; - __rxf_rit_set(rxf); - __rxf_config_set(rxf); - } - } - - return 0; -} - -/** - * Processes pending ucast, mcast entry addition/deletion and issues mailbox - * command. Also processes pending filter configuration - promiscuous mode, - * default mode, allmutli mode and issues mailbox command or directly applies - * to h/w - */ -static int -rxf_process_packet_filter(struct bna_rxf *rxf) -{ - /* Set the default MAC first */ - if (rxf->ucast_pending_set > 0) { - rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_UCAST_SET_REQ, - rxf->ucast_active_mac); - rxf->ucast_pending_set--; - return 1; - } - - if (rxf_process_packet_filter_ucast(rxf)) - return 1; - - if (rxf_process_packet_filter_mcast(rxf)) - return 1; - - if (rxf_process_packet_filter_promisc(rxf)) - return 1; - - if (rxf_process_packet_filter_allmulti(rxf)) - return 1; - - if (rxf_process_packet_filter_vlan(rxf)) - return 1; - - return 0; -} - -static int -rxf_clear_packet_filter_mcast(struct bna_rxf *rxf) -{ - struct bna_mac *mac = NULL; - struct list_head *qe; - - /* 3. delete pending mcast entries */ - if (!list_empty(&rxf->mcast_pending_del_q)) { - bfa_q_deq(&rxf->mcast_pending_del_q, &qe); - bfa_q_qe_init(qe); - mac = (struct bna_mac *)qe; - rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_DEL_REQ, mac); - bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac); - return 1; - } - - /* 4. clear active mcast entries; move them to pending_add_q */ - if (!list_empty(&rxf->mcast_active_q)) { - bfa_q_deq(&rxf->mcast_active_q, &qe); - bfa_q_qe_init(qe); - mac = (struct bna_mac *)qe; - rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_DEL_REQ, mac); - list_add_tail(&mac->qe, &rxf->mcast_pending_add_q); - return 1; - } - - return 0; -} - -/** - * In the rxf stop path, processes pending ucast/mcast delete queue and issues - * the mailbox command. Moves the active ucast/mcast entries to pending add q, - * so that they are added to CAM again in the rxf start path. Moves the current - * filter settings - promiscuous, default, allmutli - to pending filter - * configuration - */ -static int -rxf_clear_packet_filter(struct bna_rxf *rxf) -{ - if (rxf_clear_packet_filter_ucast(rxf)) - return 1; - - if (rxf_clear_packet_filter_mcast(rxf)) - return 1; - - /* 5. clear active default MAC in the CAM */ - if (rxf->ucast_pending_set > 0) - rxf->ucast_pending_set = 0; - - if (rxf_clear_packet_filter_promisc(rxf)) - return 1; - - if (rxf_clear_packet_filter_allmulti(rxf)) - return 1; - - return 0; -} - -static void -rxf_reset_packet_filter_mcast(struct bna_rxf *rxf) -{ - struct list_head *qe; - struct bna_mac *mac; - - /* 3. Move active mcast entries to pending_add_q */ - while (!list_empty(&rxf->mcast_active_q)) { - bfa_q_deq(&rxf->mcast_active_q, &qe); - bfa_q_qe_init(qe); - list_add_tail(qe, &rxf->mcast_pending_add_q); - } - - /* 4. Throw away delete pending mcast entries */ - while (!list_empty(&rxf->mcast_pending_del_q)) { - bfa_q_deq(&rxf->mcast_pending_del_q, &qe); - bfa_q_qe_init(qe); - mac = (struct bna_mac *)qe; - bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac); - } -} - -/** - * In the rxf fail path, throws away the ucast/mcast entries pending for - * deletion, moves all active ucast/mcast entries to pending queue so that - * they are added back to CAM in the rxf start path. Also moves the current - * filter configuration to pending filter configuration. - */ -static void -rxf_reset_packet_filter(struct bna_rxf *rxf) -{ - rxf_reset_packet_filter_ucast(rxf); - - rxf_reset_packet_filter_mcast(rxf); - - /* 5. Turn off ucast set flag */ - rxf->ucast_pending_set = 0; - - rxf_reset_packet_filter_promisc(rxf); - - rxf_reset_packet_filter_allmulti(rxf); -} - -static void -bna_rxf_init(struct bna_rxf *rxf, - struct bna_rx *rx, - struct bna_rx_config *q_config) -{ - struct list_head *qe; - struct bna_rxp *rxp; - - /* rxf_id is initialized during rx_mod init */ - rxf->rx = rx; - - INIT_LIST_HEAD(&rxf->ucast_pending_add_q); - INIT_LIST_HEAD(&rxf->ucast_pending_del_q); - rxf->ucast_pending_set = 0; - INIT_LIST_HEAD(&rxf->ucast_active_q); - rxf->ucast_active_mac = NULL; - - INIT_LIST_HEAD(&rxf->mcast_pending_add_q); - INIT_LIST_HEAD(&rxf->mcast_pending_del_q); - INIT_LIST_HEAD(&rxf->mcast_active_q); - - bfa_q_qe_init(&rxf->mbox_qe.qe); - - if (q_config->vlan_strip_status == BNA_STATUS_T_ENABLED) - rxf->ctrl_flags |= BNA_RXF_CF_VLAN_STRIP; - - rxf->rxf_oper_state = (q_config->paused) ? - BNA_RXF_OPER_STATE_PAUSED : BNA_RXF_OPER_STATE_RUNNING; - - bna_rxf_adv_init(rxf, rx, q_config); - - rxf->rit_segment = bna_rit_mod_seg_get(&rxf->rx->bna->rit_mod, - q_config->num_paths); - - list_for_each(qe, &rx->rxp_q) { - rxp = (struct bna_rxp *)qe; - if (q_config->rxp_type == BNA_RXP_SINGLE) - rxf->mcast_rxq_id = rxp->rxq.single.only->rxq_id; - else - rxf->mcast_rxq_id = rxp->rxq.slr.large->rxq_id; - break; - } - - rxf->vlan_filter_status = BNA_STATUS_T_DISABLED; - memset(rxf->vlan_filter_table, 0, - (sizeof(u32) * ((BFI_MAX_VLAN + 1) / 32))); - - /* Set up VLAN 0 for pure priority tagged packets */ - rxf->vlan_filter_table[0] |= 1; - - bfa_fsm_set_state(rxf, bna_rxf_sm_stopped); -} - -static void -bna_rxf_uninit(struct bna_rxf *rxf) -{ - struct bna *bna = rxf->rx->bna; - struct bna_mac *mac; - - bna_rit_mod_seg_put(&rxf->rx->bna->rit_mod, rxf->rit_segment); - rxf->rit_segment = NULL; - - rxf->ucast_pending_set = 0; - - while (!list_empty(&rxf->ucast_pending_add_q)) { - bfa_q_deq(&rxf->ucast_pending_add_q, &mac); - bfa_q_qe_init(&mac->qe); - bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod, mac); - } - - if (rxf->ucast_active_mac) { - bfa_q_qe_init(&rxf->ucast_active_mac->qe); - bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod, - rxf->ucast_active_mac); - rxf->ucast_active_mac = NULL; - } - - while (!list_empty(&rxf->mcast_pending_add_q)) { - bfa_q_deq(&rxf->mcast_pending_add_q, &mac); - bfa_q_qe_init(&mac->qe); - bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac); - } - - /* Turn off pending promisc mode */ - if (is_promisc_enable(rxf->rxmode_pending, - rxf->rxmode_pending_bitmask)) { - /* system promisc state should be pending */ - BUG_ON(!(bna->rxf_promisc_id == rxf->rxf_id)); - promisc_inactive(rxf->rxmode_pending, - rxf->rxmode_pending_bitmask); - bna->rxf_promisc_id = BFI_MAX_RXF; - } - /* Promisc mode should not be active */ - BUG_ON(rxf->rxmode_active & BNA_RXMODE_PROMISC); - - /* Turn off pending all-multi mode */ - if (is_allmulti_enable(rxf->rxmode_pending, - rxf->rxmode_pending_bitmask)) { - allmulti_inactive(rxf->rxmode_pending, - rxf->rxmode_pending_bitmask); - } - /* Allmulti mode should not be active */ - BUG_ON(rxf->rxmode_active & BNA_RXMODE_ALLMULTI); - - rxf->rx = NULL; -} - -static void -bna_rx_cb_rxf_started(struct bna_rx *rx, enum bna_cb_status status) -{ - bfa_fsm_send_event(rx, RX_E_RXF_STARTED); - if (rx->rxf.rxf_id < 32) - rx->bna->rx_mod.rxf_bmap[0] |= ((u32)1 << rx->rxf.rxf_id); - else - rx->bna->rx_mod.rxf_bmap[1] |= ((u32) - 1 << (rx->rxf.rxf_id - 32)); -} - -static void -bna_rxf_start(struct bna_rxf *rxf) -{ - rxf->start_cbfn = bna_rx_cb_rxf_started; - rxf->start_cbarg = rxf->rx; - rxf->rxf_flags &= ~BNA_RXF_FL_FAILED; - bfa_fsm_send_event(rxf, RXF_E_START); -} - -static void -bna_rx_cb_rxf_stopped(struct bna_rx *rx, enum bna_cb_status status) -{ - bfa_fsm_send_event(rx, RX_E_RXF_STOPPED); - if (rx->rxf.rxf_id < 32) - rx->bna->rx_mod.rxf_bmap[0] &= ~(u32)1 << rx->rxf.rxf_id; - else - rx->bna->rx_mod.rxf_bmap[1] &= ~(u32) - 1 << (rx->rxf.rxf_id - 32); -} - -static void -bna_rxf_stop(struct bna_rxf *rxf) -{ - rxf->stop_cbfn = bna_rx_cb_rxf_stopped; - rxf->stop_cbarg = rxf->rx; - bfa_fsm_send_event(rxf, RXF_E_STOP); -} - -static void -bna_rxf_fail(struct bna_rxf *rxf) -{ - rxf->rxf_flags |= BNA_RXF_FL_FAILED; - bfa_fsm_send_event(rxf, RXF_E_FAIL); -} - -int -bna_rxf_state_get(struct bna_rxf *rxf) -{ - return bfa_sm_to_state(rxf_sm_table, rxf->fsm); -} - -enum bna_cb_status -bna_rx_ucast_set(struct bna_rx *rx, u8 *ucmac, - void (*cbfn)(struct bnad *, struct bna_rx *, - enum bna_cb_status)) -{ - struct bna_rxf *rxf = &rx->rxf; - - if (rxf->ucast_active_mac == NULL) { - rxf->ucast_active_mac = - bna_ucam_mod_mac_get(&rxf->rx->bna->ucam_mod); - if (rxf->ucast_active_mac == NULL) - return BNA_CB_UCAST_CAM_FULL; - bfa_q_qe_init(&rxf->ucast_active_mac->qe); - } - - memcpy(rxf->ucast_active_mac->addr, ucmac, ETH_ALEN); - rxf->ucast_pending_set++; - rxf->cam_fltr_cbfn = cbfn; - rxf->cam_fltr_cbarg = rx->bna->bnad; - - bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD); - - return BNA_CB_SUCCESS; -} - -enum bna_cb_status -bna_rx_mcast_add(struct bna_rx *rx, u8 *addr, - void (*cbfn)(struct bnad *, struct bna_rx *, - enum bna_cb_status)) -{ - struct bna_rxf *rxf = &rx->rxf; - struct list_head *qe; - struct bna_mac *mac; - - /* Check if already added */ - list_for_each(qe, &rxf->mcast_active_q) { - mac = (struct bna_mac *)qe; - if (BNA_MAC_IS_EQUAL(mac->addr, addr)) { - if (cbfn) - (*cbfn)(rx->bna->bnad, rx, BNA_CB_SUCCESS); - return BNA_CB_SUCCESS; - } - } - - /* Check if pending addition */ - list_for_each(qe, &rxf->mcast_pending_add_q) { - mac = (struct bna_mac *)qe; - if (BNA_MAC_IS_EQUAL(mac->addr, addr)) { - if (cbfn) - (*cbfn)(rx->bna->bnad, rx, BNA_CB_SUCCESS); - return BNA_CB_SUCCESS; - } - } - - mac = bna_mcam_mod_mac_get(&rxf->rx->bna->mcam_mod); - if (mac == NULL) - return BNA_CB_MCAST_LIST_FULL; - bfa_q_qe_init(&mac->qe); - memcpy(mac->addr, addr, ETH_ALEN); - list_add_tail(&mac->qe, &rxf->mcast_pending_add_q); - - rxf->cam_fltr_cbfn = cbfn; - rxf->cam_fltr_cbarg = rx->bna->bnad; - - bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD); - - return BNA_CB_SUCCESS; -} - -enum bna_cb_status -bna_rx_mcast_listset(struct bna_rx *rx, int count, u8 *mclist, - void (*cbfn)(struct bnad *, struct bna_rx *, - enum bna_cb_status)) -{ - struct bna_rxf *rxf = &rx->rxf; - struct list_head list_head; - struct list_head *qe; - u8 *mcaddr; - struct bna_mac *mac; - struct bna_mac *mac1; - int skip; - int delete; - int need_hw_config = 0; - int i; - - /* Allocate nodes */ - INIT_LIST_HEAD(&list_head); - for (i = 0, mcaddr = mclist; i < count; i++) { - mac = bna_mcam_mod_mac_get(&rxf->rx->bna->mcam_mod); - if (mac == NULL) - goto err_return; - bfa_q_qe_init(&mac->qe); - memcpy(mac->addr, mcaddr, ETH_ALEN); - list_add_tail(&mac->qe, &list_head); - - mcaddr += ETH_ALEN; - } - - /* Schedule for addition */ - while (!list_empty(&list_head)) { - bfa_q_deq(&list_head, &qe); - mac = (struct bna_mac *)qe; - bfa_q_qe_init(&mac->qe); - - skip = 0; - - /* Skip if already added */ - list_for_each(qe, &rxf->mcast_active_q) { - mac1 = (struct bna_mac *)qe; - if (BNA_MAC_IS_EQUAL(mac1->addr, mac->addr)) { - bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, - mac); - skip = 1; - break; - } - } - - if (skip) - continue; - - /* Skip if pending addition */ - list_for_each(qe, &rxf->mcast_pending_add_q) { - mac1 = (struct bna_mac *)qe; - if (BNA_MAC_IS_EQUAL(mac1->addr, mac->addr)) { - bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, - mac); - skip = 1; - break; - } - } - - if (skip) - continue; - - need_hw_config = 1; - list_add_tail(&mac->qe, &rxf->mcast_pending_add_q); - } - - /** - * Delete the entries that are in the pending_add_q but not - * in the new list - */ - while (!list_empty(&rxf->mcast_pending_add_q)) { - bfa_q_deq(&rxf->mcast_pending_add_q, &qe); - mac = (struct bna_mac *)qe; - bfa_q_qe_init(&mac->qe); - for (i = 0, mcaddr = mclist, delete = 1; i < count; i++) { - if (BNA_MAC_IS_EQUAL(mcaddr, mac->addr)) { - delete = 0; - break; - } - mcaddr += ETH_ALEN; - } - if (delete) - bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac); - else - list_add_tail(&mac->qe, &list_head); - } - while (!list_empty(&list_head)) { - bfa_q_deq(&list_head, &qe); - mac = (struct bna_mac *)qe; - bfa_q_qe_init(&mac->qe); - list_add_tail(&mac->qe, &rxf->mcast_pending_add_q); - } - - /** - * Schedule entries for deletion that are in the active_q but not - * in the new list - */ - while (!list_empty(&rxf->mcast_active_q)) { - bfa_q_deq(&rxf->mcast_active_q, &qe); - mac = (struct bna_mac *)qe; - bfa_q_qe_init(&mac->qe); - for (i = 0, mcaddr = mclist, delete = 1; i < count; i++) { - if (BNA_MAC_IS_EQUAL(mcaddr, mac->addr)) { - delete = 0; - break; - } - mcaddr += ETH_ALEN; - } - if (delete) { - list_add_tail(&mac->qe, &rxf->mcast_pending_del_q); - need_hw_config = 1; - } else { - list_add_tail(&mac->qe, &list_head); - } - } - while (!list_empty(&list_head)) { - bfa_q_deq(&list_head, &qe); - mac = (struct bna_mac *)qe; - bfa_q_qe_init(&mac->qe); - list_add_tail(&mac->qe, &rxf->mcast_active_q); - } - - if (need_hw_config) { - rxf->cam_fltr_cbfn = cbfn; - rxf->cam_fltr_cbarg = rx->bna->bnad; - bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD); - } else if (cbfn) - (*cbfn)(rx->bna->bnad, rx, BNA_CB_SUCCESS); - - return BNA_CB_SUCCESS; - -err_return: - while (!list_empty(&list_head)) { - bfa_q_deq(&list_head, &qe); - mac = (struct bna_mac *)qe; - bfa_q_qe_init(&mac->qe); - bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac); - } - - return BNA_CB_MCAST_LIST_FULL; -} - -void -bna_rx_vlan_add(struct bna_rx *rx, int vlan_id) -{ - struct bna_rxf *rxf = &rx->rxf; - int index = (vlan_id >> 5); - int bit = (1 << (vlan_id & 0x1F)); - - rxf->vlan_filter_table[index] |= bit; - if (rxf->vlan_filter_status == BNA_STATUS_T_ENABLED) { - rxf->rxf_flags |= BNA_RXF_FL_VLAN_CONFIG_PENDING; - bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD); - } -} - -void -bna_rx_vlan_del(struct bna_rx *rx, int vlan_id) -{ - struct bna_rxf *rxf = &rx->rxf; - int index = (vlan_id >> 5); - int bit = (1 << (vlan_id & 0x1F)); - - rxf->vlan_filter_table[index] &= ~bit; - if (rxf->vlan_filter_status == BNA_STATUS_T_ENABLED) { - rxf->rxf_flags |= BNA_RXF_FL_VLAN_CONFIG_PENDING; - bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD); - } -} - -/** - * RX - */ -#define RXQ_RCB_INIT(q, rxp, qdepth, bna, _id, unmapq_mem) do { \ - struct bna_doorbell_qset *_qset; \ - unsigned long off; \ - (q)->rcb->producer_index = (q)->rcb->consumer_index = 0; \ - (q)->rcb->q_depth = (qdepth); \ - (q)->rcb->unmap_q = unmapq_mem; \ - (q)->rcb->rxq = (q); \ - (q)->rcb->cq = &(rxp)->cq; \ - (q)->rcb->bnad = (bna)->bnad; \ - _qset = (struct bna_doorbell_qset *)0; \ - off = (unsigned long)&_qset[(q)->rxq_id].rxq[0]; \ - (q)->rcb->q_dbell = off + \ - BNA_GET_DOORBELL_BASE_ADDR((bna)->pcidev.pci_bar_kva); \ - (q)->rcb->id = _id; \ -} while (0) - -#define BNA_GET_RXQS(qcfg) (((qcfg)->rxp_type == BNA_RXP_SINGLE) ? \ - (qcfg)->num_paths : ((qcfg)->num_paths * 2)) - -#define SIZE_TO_PAGES(size) (((size) >> PAGE_SHIFT) + ((((size) &\ - (PAGE_SIZE - 1)) + (PAGE_SIZE - 1)) >> PAGE_SHIFT)) - -#define call_rx_stop_callback(rx, status) \ - if ((rx)->stop_cbfn) { \ - (*(rx)->stop_cbfn)((rx)->stop_cbarg, rx, (status)); \ - (rx)->stop_cbfn = NULL; \ - (rx)->stop_cbarg = NULL; \ - } - -/* - * Since rx_enable is synchronous callback, there is no start_cbfn required. - * Instead, we'll call bnad_rx_post(rxp) so that bnad can post the buffers - * for each rxpath. - */ - -#define call_rx_disable_cbfn(rx, status) \ - if ((rx)->disable_cbfn) { \ - (*(rx)->disable_cbfn)((rx)->disable_cbarg, \ - status); \ - (rx)->disable_cbfn = NULL; \ - (rx)->disable_cbarg = NULL; \ - } \ - -#define rxqs_reqd(type, num_rxqs) \ - (((type) == BNA_RXP_SINGLE) ? (num_rxqs) : ((num_rxqs) * 2)) - -#define rx_ib_fail(rx) \ -do { \ - struct bna_rxp *rxp; \ - struct list_head *qe; \ - list_for_each(qe, &(rx)->rxp_q) { \ - rxp = (struct bna_rxp *)qe; \ - bna_ib_fail(rxp->cq.ib); \ - } \ -} while (0) - -static void __bna_multi_rxq_stop(struct bna_rxp *, u32 *); -static void __bna_rxq_start(struct bna_rxq *rxq); -static void __bna_cq_start(struct bna_cq *cq); -static void bna_rit_create(struct bna_rx *rx); -static void bna_rx_cb_multi_rxq_stopped(void *arg, int status); -static void bna_rx_cb_rxq_stopped_all(void *arg); - -bfa_fsm_state_decl(bna_rx, stopped, - struct bna_rx, enum bna_rx_event); -bfa_fsm_state_decl(bna_rx, rxf_start_wait, - struct bna_rx, enum bna_rx_event); -bfa_fsm_state_decl(bna_rx, started, - struct bna_rx, enum bna_rx_event); -bfa_fsm_state_decl(bna_rx, rxf_stop_wait, - struct bna_rx, enum bna_rx_event); -bfa_fsm_state_decl(bna_rx, rxq_stop_wait, - struct bna_rx, enum bna_rx_event); - -static const struct bfa_sm_table rx_sm_table[] = { - {BFA_SM(bna_rx_sm_stopped), BNA_RX_STOPPED}, - {BFA_SM(bna_rx_sm_rxf_start_wait), BNA_RX_RXF_START_WAIT}, - {BFA_SM(bna_rx_sm_started), BNA_RX_STARTED}, - {BFA_SM(bna_rx_sm_rxf_stop_wait), BNA_RX_RXF_STOP_WAIT}, - {BFA_SM(bna_rx_sm_rxq_stop_wait), BNA_RX_RXQ_STOP_WAIT}, -}; - -static void bna_rx_sm_stopped_entry(struct bna_rx *rx) -{ - struct bna_rxp *rxp; - struct list_head *qe_rxp; - - list_for_each(qe_rxp, &rx->rxp_q) { - rxp = (struct bna_rxp *)qe_rxp; - rx->rx_cleanup_cbfn(rx->bna->bnad, rxp->cq.ccb); - } - - call_rx_stop_callback(rx, BNA_CB_SUCCESS); -} - -static void bna_rx_sm_stopped(struct bna_rx *rx, - enum bna_rx_event event) -{ - switch (event) { - case RX_E_START: - bfa_fsm_set_state(rx, bna_rx_sm_rxf_start_wait); - break; - case RX_E_STOP: - call_rx_stop_callback(rx, BNA_CB_SUCCESS); - break; - case RX_E_FAIL: - /* no-op */ - break; - default: - bfa_sm_fault(event); - break; - } - -} - -static void bna_rx_sm_rxf_start_wait_entry(struct bna_rx *rx) -{ - struct bna_rxp *rxp; - struct list_head *qe_rxp; - struct bna_rxq *q0 = NULL, *q1 = NULL; - - /* Setup the RIT */ - bna_rit_create(rx); - - list_for_each(qe_rxp, &rx->rxp_q) { - rxp = (struct bna_rxp *)qe_rxp; - bna_ib_start(rxp->cq.ib); - GET_RXQS(rxp, q0, q1); - q0->buffer_size = bna_port_mtu_get(&rx->bna->port); - __bna_rxq_start(q0); - rx->rx_post_cbfn(rx->bna->bnad, q0->rcb); - if (q1) { - __bna_rxq_start(q1); - rx->rx_post_cbfn(rx->bna->bnad, q1->rcb); - } - __bna_cq_start(&rxp->cq); - } - - bna_rxf_start(&rx->rxf); -} - -static void bna_rx_sm_rxf_start_wait(struct bna_rx *rx, - enum bna_rx_event event) -{ - switch (event) { - case RX_E_STOP: - bfa_fsm_set_state(rx, bna_rx_sm_rxf_stop_wait); - break; - case RX_E_FAIL: - bfa_fsm_set_state(rx, bna_rx_sm_stopped); - rx_ib_fail(rx); - bna_rxf_fail(&rx->rxf); - break; - case RX_E_RXF_STARTED: - bfa_fsm_set_state(rx, bna_rx_sm_started); - break; - default: - bfa_sm_fault(event); - break; - } -} - -void -bna_rx_sm_started_entry(struct bna_rx *rx) -{ - struct bna_rxp *rxp; - struct list_head *qe_rxp; - - /* Start IB */ - list_for_each(qe_rxp, &rx->rxp_q) { - rxp = (struct bna_rxp *)qe_rxp; - bna_ib_ack(&rxp->cq.ib->door_bell, 0); - } - - bna_llport_rx_started(&rx->bna->port.llport); -} - -void -bna_rx_sm_started(struct bna_rx *rx, enum bna_rx_event event) -{ - switch (event) { - case RX_E_FAIL: - bna_llport_rx_stopped(&rx->bna->port.llport); - bfa_fsm_set_state(rx, bna_rx_sm_stopped); - rx_ib_fail(rx); - bna_rxf_fail(&rx->rxf); - break; - case RX_E_STOP: - bna_llport_rx_stopped(&rx->bna->port.llport); - bfa_fsm_set_state(rx, bna_rx_sm_rxf_stop_wait); - break; - default: - bfa_sm_fault(event); - break; - } -} - -void -bna_rx_sm_rxf_stop_wait_entry(struct bna_rx *rx) -{ - bna_rxf_stop(&rx->rxf); -} - -void -bna_rx_sm_rxf_stop_wait(struct bna_rx *rx, enum bna_rx_event event) -{ - switch (event) { - case RX_E_RXF_STOPPED: - bfa_fsm_set_state(rx, bna_rx_sm_rxq_stop_wait); - break; - case RX_E_RXF_STARTED: - /** - * RxF was in the process of starting up when - * RXF_E_STOP was issued. Ignore this event - */ - break; - case RX_E_FAIL: - bfa_fsm_set_state(rx, bna_rx_sm_stopped); - rx_ib_fail(rx); - bna_rxf_fail(&rx->rxf); - break; - default: - bfa_sm_fault(event); - break; - } - -} - -void -bna_rx_sm_rxq_stop_wait_entry(struct bna_rx *rx) -{ - struct bna_rxp *rxp = NULL; - struct bna_rxq *q0 = NULL; - struct bna_rxq *q1 = NULL; - struct list_head *qe; - u32 rxq_mask[2] = {0, 0}; - - /* Only one call to multi-rxq-stop for all RXPs in this RX */ - bfa_wc_up(&rx->rxq_stop_wc); - list_for_each(qe, &rx->rxp_q) { - rxp = (struct bna_rxp *)qe; - GET_RXQS(rxp, q0, q1); - if (q0->rxq_id < 32) - rxq_mask[0] |= ((u32)1 << q0->rxq_id); - else - rxq_mask[1] |= ((u32)1 << (q0->rxq_id - 32)); - if (q1) { - if (q1->rxq_id < 32) - rxq_mask[0] |= ((u32)1 << q1->rxq_id); - else - rxq_mask[1] |= ((u32) - 1 << (q1->rxq_id - 32)); - } - } - - __bna_multi_rxq_stop(rxp, rxq_mask); -} - -void -bna_rx_sm_rxq_stop_wait(struct bna_rx *rx, enum bna_rx_event event) -{ - struct bna_rxp *rxp = NULL; - struct list_head *qe; - - switch (event) { - case RX_E_RXQ_STOPPED: - list_for_each(qe, &rx->rxp_q) { - rxp = (struct bna_rxp *)qe; - bna_ib_stop(rxp->cq.ib); - } - /* Fall through */ - case RX_E_FAIL: - bfa_fsm_set_state(rx, bna_rx_sm_stopped); - break; - default: - bfa_sm_fault(event); - break; - } -} - -void -__bna_multi_rxq_stop(struct bna_rxp *rxp, u32 * rxq_id_mask) -{ - struct bfi_ll_q_stop_req ll_req; - - bfi_h2i_set(ll_req.mh, BFI_MC_LL, BFI_LL_H2I_RXQ_STOP_REQ, 0); - ll_req.q_id_mask[0] = htonl(rxq_id_mask[0]); - ll_req.q_id_mask[1] = htonl(rxq_id_mask[1]); - bna_mbox_qe_fill(&rxp->mbox_qe, &ll_req, sizeof(ll_req), - bna_rx_cb_multi_rxq_stopped, rxp); - bna_mbox_send(rxp->rx->bna, &rxp->mbox_qe); -} - -void -__bna_rxq_start(struct bna_rxq *rxq) -{ - struct bna_rxtx_q_mem *q_mem; - struct bna_rxq_mem rxq_cfg, *rxq_mem; - struct bna_dma_addr cur_q_addr; - /* struct bna_doorbell_qset *qset; */ - struct bna_qpt *qpt; - u32 pg_num; - struct bna *bna = rxq->rx->bna; - void __iomem *base_addr; - unsigned long off; - - qpt = &rxq->qpt; - cur_q_addr = *((struct bna_dma_addr *)(qpt->kv_qpt_ptr)); - - rxq_cfg.pg_tbl_addr_lo = qpt->hw_qpt_ptr.lsb; - rxq_cfg.pg_tbl_addr_hi = qpt->hw_qpt_ptr.msb; - rxq_cfg.cur_q_entry_lo = cur_q_addr.lsb; - rxq_cfg.cur_q_entry_hi = cur_q_addr.msb; - - rxq_cfg.pg_cnt_n_prd_ptr = ((u32)qpt->page_count << 16) | 0x0; - rxq_cfg.entry_n_pg_size = ((u32)(BFI_RXQ_WI_SIZE >> 2) << 16) | - (qpt->page_size >> 2); - rxq_cfg.sg_n_cq_n_cns_ptr = - ((u32)(rxq->rxp->cq.cq_id & 0xff) << 16) | 0x0; - rxq_cfg.buf_sz_n_q_state = ((u32)rxq->buffer_size << 16) | - BNA_Q_IDLE_STATE; - rxq_cfg.next_qid = 0x0 | (0x3 << 8); - - /* Write the page number register */ - pg_num = BNA_GET_PAGE_NUM(HQM0_BLK_PG_NUM + bna->port_num, - HQM_RXTX_Q_RAM_BASE_OFFSET); - writel(pg_num, bna->regs.page_addr); - - /* Write to h/w */ - base_addr = BNA_GET_MEM_BASE_ADDR(bna->pcidev.pci_bar_kva, - HQM_RXTX_Q_RAM_BASE_OFFSET); - - q_mem = (struct bna_rxtx_q_mem *)0; - rxq_mem = &q_mem[rxq->rxq_id].rxq; - - off = (unsigned long)&rxq_mem->pg_tbl_addr_lo; - writel(htonl(rxq_cfg.pg_tbl_addr_lo), base_addr + off); - - off = (unsigned long)&rxq_mem->pg_tbl_addr_hi; - writel(htonl(rxq_cfg.pg_tbl_addr_hi), base_addr + off); - - off = (unsigned long)&rxq_mem->cur_q_entry_lo; - writel(htonl(rxq_cfg.cur_q_entry_lo), base_addr + off); - - off = (unsigned long)&rxq_mem->cur_q_entry_hi; - writel(htonl(rxq_cfg.cur_q_entry_hi), base_addr + off); - - off = (unsigned long)&rxq_mem->pg_cnt_n_prd_ptr; - writel(rxq_cfg.pg_cnt_n_prd_ptr, base_addr + off); - - off = (unsigned long)&rxq_mem->entry_n_pg_size; - writel(rxq_cfg.entry_n_pg_size, base_addr + off); - - off = (unsigned long)&rxq_mem->sg_n_cq_n_cns_ptr; - writel(rxq_cfg.sg_n_cq_n_cns_ptr, base_addr + off); - - off = (unsigned long)&rxq_mem->buf_sz_n_q_state; - writel(rxq_cfg.buf_sz_n_q_state, base_addr + off); - - off = (unsigned long)&rxq_mem->next_qid; - writel(rxq_cfg.next_qid, base_addr + off); - - rxq->rcb->producer_index = 0; - rxq->rcb->consumer_index = 0; -} - -void -__bna_cq_start(struct bna_cq *cq) -{ - struct bna_cq_mem cq_cfg, *cq_mem; - const struct bna_qpt *qpt; - struct bna_dma_addr cur_q_addr; - u32 pg_num; - struct bna *bna = cq->rx->bna; - void __iomem *base_addr; - unsigned long off; - - qpt = &cq->qpt; - cur_q_addr = *((struct bna_dma_addr *)(qpt->kv_qpt_ptr)); - - /* - * Fill out structure, to be subsequently written - * to hardware - */ - cq_cfg.pg_tbl_addr_lo = qpt->hw_qpt_ptr.lsb; - cq_cfg.pg_tbl_addr_hi = qpt->hw_qpt_ptr.msb; - cq_cfg.cur_q_entry_lo = cur_q_addr.lsb; - cq_cfg.cur_q_entry_hi = cur_q_addr.msb; - - cq_cfg.pg_cnt_n_prd_ptr = (qpt->page_count << 16) | 0x0; - cq_cfg.entry_n_pg_size = - ((u32)(BFI_CQ_WI_SIZE >> 2) << 16) | (qpt->page_size >> 2); - cq_cfg.int_blk_n_cns_ptr = ((((u32)cq->ib_seg_offset) << 24) | - ((u32)(cq->ib->ib_id & 0xff) << 16) | 0x0); - cq_cfg.q_state = BNA_Q_IDLE_STATE; - - /* Write the page number register */ - pg_num = BNA_GET_PAGE_NUM(HQM0_BLK_PG_NUM + bna->port_num, - HQM_CQ_RAM_BASE_OFFSET); - - writel(pg_num, bna->regs.page_addr); - - /* H/W write */ - base_addr = BNA_GET_MEM_BASE_ADDR(bna->pcidev.pci_bar_kva, - HQM_CQ_RAM_BASE_OFFSET); - - cq_mem = (struct bna_cq_mem *)0; - - off = (unsigned long)&cq_mem[cq->cq_id].pg_tbl_addr_lo; - writel(htonl(cq_cfg.pg_tbl_addr_lo), base_addr + off); - - off = (unsigned long)&cq_mem[cq->cq_id].pg_tbl_addr_hi; - writel(htonl(cq_cfg.pg_tbl_addr_hi), base_addr + off); - - off = (unsigned long)&cq_mem[cq->cq_id].cur_q_entry_lo; - writel(htonl(cq_cfg.cur_q_entry_lo), base_addr + off); - - off = (unsigned long)&cq_mem[cq->cq_id].cur_q_entry_hi; - writel(htonl(cq_cfg.cur_q_entry_hi), base_addr + off); - - off = (unsigned long)&cq_mem[cq->cq_id].pg_cnt_n_prd_ptr; - writel(cq_cfg.pg_cnt_n_prd_ptr, base_addr + off); - - off = (unsigned long)&cq_mem[cq->cq_id].entry_n_pg_size; - writel(cq_cfg.entry_n_pg_size, base_addr + off); - - off = (unsigned long)&cq_mem[cq->cq_id].int_blk_n_cns_ptr; - writel(cq_cfg.int_blk_n_cns_ptr, base_addr + off); - - off = (unsigned long)&cq_mem[cq->cq_id].q_state; - writel(cq_cfg.q_state, base_addr + off); - - cq->ccb->producer_index = 0; - *(cq->ccb->hw_producer_index) = 0; -} - -void -bna_rit_create(struct bna_rx *rx) -{ - struct list_head *qe_rxp; - struct bna_rxp *rxp; - struct bna_rxq *q0 = NULL; - struct bna_rxq *q1 = NULL; - int offset; - - offset = 0; - list_for_each(qe_rxp, &rx->rxp_q) { - rxp = (struct bna_rxp *)qe_rxp; - GET_RXQS(rxp, q0, q1); - rx->rxf.rit_segment->rit[offset].large_rxq_id = q0->rxq_id; - rx->rxf.rit_segment->rit[offset].small_rxq_id = - (q1 ? q1->rxq_id : 0); - offset++; - } -} - -static int -_rx_can_satisfy(struct bna_rx_mod *rx_mod, - struct bna_rx_config *rx_cfg) -{ - if ((rx_mod->rx_free_count == 0) || - (rx_mod->rxp_free_count == 0) || - (rx_mod->rxq_free_count == 0)) - return 0; - - if (rx_cfg->rxp_type == BNA_RXP_SINGLE) { - if ((rx_mod->rxp_free_count < rx_cfg->num_paths) || - (rx_mod->rxq_free_count < rx_cfg->num_paths)) - return 0; - } else { - if ((rx_mod->rxp_free_count < rx_cfg->num_paths) || - (rx_mod->rxq_free_count < (2 * rx_cfg->num_paths))) - return 0; - } - - if (!bna_rit_mod_can_satisfy(&rx_mod->bna->rit_mod, rx_cfg->num_paths)) - return 0; - - return 1; -} - -static struct bna_rxq * -_get_free_rxq(struct bna_rx_mod *rx_mod) -{ - struct bna_rxq *rxq = NULL; - struct list_head *qe = NULL; - - bfa_q_deq(&rx_mod->rxq_free_q, &qe); - if (qe) { - rx_mod->rxq_free_count--; - rxq = (struct bna_rxq *)qe; - } - return rxq; -} - -static void -_put_free_rxq(struct bna_rx_mod *rx_mod, struct bna_rxq *rxq) -{ - bfa_q_qe_init(&rxq->qe); - list_add_tail(&rxq->qe, &rx_mod->rxq_free_q); - rx_mod->rxq_free_count++; -} - -static struct bna_rxp * -_get_free_rxp(struct bna_rx_mod *rx_mod) -{ - struct list_head *qe = NULL; - struct bna_rxp *rxp = NULL; - - bfa_q_deq(&rx_mod->rxp_free_q, &qe); - if (qe) { - rx_mod->rxp_free_count--; - - rxp = (struct bna_rxp *)qe; - } - - return rxp; -} - -static void -_put_free_rxp(struct bna_rx_mod *rx_mod, struct bna_rxp *rxp) -{ - bfa_q_qe_init(&rxp->qe); - list_add_tail(&rxp->qe, &rx_mod->rxp_free_q); - rx_mod->rxp_free_count++; -} - -static struct bna_rx * -_get_free_rx(struct bna_rx_mod *rx_mod) -{ - struct list_head *qe = NULL; - struct bna_rx *rx = NULL; - - bfa_q_deq(&rx_mod->rx_free_q, &qe); - if (qe) { - rx_mod->rx_free_count--; - - rx = (struct bna_rx *)qe; - bfa_q_qe_init(qe); - list_add_tail(&rx->qe, &rx_mod->rx_active_q); - } - - return rx; -} - -static void -_put_free_rx(struct bna_rx_mod *rx_mod, struct bna_rx *rx) -{ - bfa_q_qe_init(&rx->qe); - list_add_tail(&rx->qe, &rx_mod->rx_free_q); - rx_mod->rx_free_count++; -} - -static void -_rx_init(struct bna_rx *rx, struct bna *bna) -{ - rx->bna = bna; - rx->rx_flags = 0; - - INIT_LIST_HEAD(&rx->rxp_q); - - rx->rxq_stop_wc.wc_resume = bna_rx_cb_rxq_stopped_all; - rx->rxq_stop_wc.wc_cbarg = rx; - rx->rxq_stop_wc.wc_count = 0; - - rx->stop_cbfn = NULL; - rx->stop_cbarg = NULL; -} - -static void -_rxp_add_rxqs(struct bna_rxp *rxp, - struct bna_rxq *q0, - struct bna_rxq *q1) -{ - switch (rxp->type) { - case BNA_RXP_SINGLE: - rxp->rxq.single.only = q0; - rxp->rxq.single.reserved = NULL; - break; - case BNA_RXP_SLR: - rxp->rxq.slr.large = q0; - rxp->rxq.slr.small = q1; - break; - case BNA_RXP_HDS: - rxp->rxq.hds.data = q0; - rxp->rxq.hds.hdr = q1; - break; - default: - break; - } -} - -static void -_rxq_qpt_init(struct bna_rxq *rxq, - struct bna_rxp *rxp, - u32 page_count, - u32 page_size, - struct bna_mem_descr *qpt_mem, - struct bna_mem_descr *swqpt_mem, - struct bna_mem_descr *page_mem) -{ - int i; - - rxq->qpt.hw_qpt_ptr.lsb = qpt_mem->dma.lsb; - rxq->qpt.hw_qpt_ptr.msb = qpt_mem->dma.msb; - rxq->qpt.kv_qpt_ptr = qpt_mem->kva; - rxq->qpt.page_count = page_count; - rxq->qpt.page_size = page_size; - - rxq->rcb->sw_qpt = (void **) swqpt_mem->kva; - - for (i = 0; i < rxq->qpt.page_count; i++) { - rxq->rcb->sw_qpt[i] = page_mem[i].kva; - ((struct bna_dma_addr *)rxq->qpt.kv_qpt_ptr)[i].lsb = - page_mem[i].dma.lsb; - ((struct bna_dma_addr *)rxq->qpt.kv_qpt_ptr)[i].msb = - page_mem[i].dma.msb; - - } -} - -static void -_rxp_cqpt_setup(struct bna_rxp *rxp, - u32 page_count, - u32 page_size, - struct bna_mem_descr *qpt_mem, - struct bna_mem_descr *swqpt_mem, - struct bna_mem_descr *page_mem) -{ - int i; - - rxp->cq.qpt.hw_qpt_ptr.lsb = qpt_mem->dma.lsb; - rxp->cq.qpt.hw_qpt_ptr.msb = qpt_mem->dma.msb; - rxp->cq.qpt.kv_qpt_ptr = qpt_mem->kva; - rxp->cq.qpt.page_count = page_count; - rxp->cq.qpt.page_size = page_size; - - rxp->cq.ccb->sw_qpt = (void **) swqpt_mem->kva; - - for (i = 0; i < rxp->cq.qpt.page_count; i++) { - rxp->cq.ccb->sw_qpt[i] = page_mem[i].kva; - - ((struct bna_dma_addr *)rxp->cq.qpt.kv_qpt_ptr)[i].lsb = - page_mem[i].dma.lsb; - ((struct bna_dma_addr *)rxp->cq.qpt.kv_qpt_ptr)[i].msb = - page_mem[i].dma.msb; - - } -} - -static void -_rx_add_rxp(struct bna_rx *rx, struct bna_rxp *rxp) -{ - list_add_tail(&rxp->qe, &rx->rxp_q); -} - -static void -_init_rxmod_queues(struct bna_rx_mod *rx_mod) -{ - INIT_LIST_HEAD(&rx_mod->rx_free_q); - INIT_LIST_HEAD(&rx_mod->rxq_free_q); - INIT_LIST_HEAD(&rx_mod->rxp_free_q); - INIT_LIST_HEAD(&rx_mod->rx_active_q); - - rx_mod->rx_free_count = 0; - rx_mod->rxq_free_count = 0; - rx_mod->rxp_free_count = 0; -} - -static void -_rx_ctor(struct bna_rx *rx, int id) -{ - bfa_q_qe_init(&rx->qe); - INIT_LIST_HEAD(&rx->rxp_q); - rx->bna = NULL; - - rx->rxf.rxf_id = id; - - /* FIXME: mbox_qe ctor()?? */ - bfa_q_qe_init(&rx->mbox_qe.qe); - - rx->stop_cbfn = NULL; - rx->stop_cbarg = NULL; -} - -void -bna_rx_cb_multi_rxq_stopped(void *arg, int status) -{ - struct bna_rxp *rxp = (struct bna_rxp *)arg; - - bfa_wc_down(&rxp->rx->rxq_stop_wc); -} - -void -bna_rx_cb_rxq_stopped_all(void *arg) -{ - struct bna_rx *rx = (struct bna_rx *)arg; - - bfa_fsm_send_event(rx, RX_E_RXQ_STOPPED); -} - -static void -bna_rx_mod_cb_rx_stopped(void *arg, struct bna_rx *rx, - enum bna_cb_status status) -{ - struct bna_rx_mod *rx_mod = (struct bna_rx_mod *)arg; - - bfa_wc_down(&rx_mod->rx_stop_wc); -} - -static void -bna_rx_mod_cb_rx_stopped_all(void *arg) -{ - struct bna_rx_mod *rx_mod = (struct bna_rx_mod *)arg; - - if (rx_mod->stop_cbfn) - rx_mod->stop_cbfn(&rx_mod->bna->port, BNA_CB_SUCCESS); - rx_mod->stop_cbfn = NULL; -} - -static void -bna_rx_start(struct bna_rx *rx) -{ - rx->rx_flags |= BNA_RX_F_PORT_ENABLED; - if (rx->rx_flags & BNA_RX_F_ENABLE) - bfa_fsm_send_event(rx, RX_E_START); -} - -static void -bna_rx_stop(struct bna_rx *rx) -{ - rx->rx_flags &= ~BNA_RX_F_PORT_ENABLED; - if (rx->fsm == (bfa_fsm_t) bna_rx_sm_stopped) - bna_rx_mod_cb_rx_stopped(&rx->bna->rx_mod, rx, BNA_CB_SUCCESS); - else { - rx->stop_cbfn = bna_rx_mod_cb_rx_stopped; - rx->stop_cbarg = &rx->bna->rx_mod; - bfa_fsm_send_event(rx, RX_E_STOP); - } -} - -static void -bna_rx_fail(struct bna_rx *rx) -{ - /* Indicate port is not enabled, and failed */ - rx->rx_flags &= ~BNA_RX_F_PORT_ENABLED; - rx->rx_flags |= BNA_RX_F_PORT_FAILED; - bfa_fsm_send_event(rx, RX_E_FAIL); -} - -void -bna_rx_mod_start(struct bna_rx_mod *rx_mod, enum bna_rx_type type) -{ - struct bna_rx *rx; - struct list_head *qe; - - rx_mod->flags |= BNA_RX_MOD_F_PORT_STARTED; - if (type == BNA_RX_T_LOOPBACK) - rx_mod->flags |= BNA_RX_MOD_F_PORT_LOOPBACK; - - list_for_each(qe, &rx_mod->rx_active_q) { - rx = (struct bna_rx *)qe; - if (rx->type == type) - bna_rx_start(rx); - } -} - -void -bna_rx_mod_stop(struct bna_rx_mod *rx_mod, enum bna_rx_type type) -{ - struct bna_rx *rx; - struct list_head *qe; - - rx_mod->flags &= ~BNA_RX_MOD_F_PORT_STARTED; - rx_mod->flags &= ~BNA_RX_MOD_F_PORT_LOOPBACK; - - rx_mod->stop_cbfn = bna_port_cb_rx_stopped; - - /** - * Before calling bna_rx_stop(), increment rx_stop_wc as many times - * as we are going to call bna_rx_stop - */ - list_for_each(qe, &rx_mod->rx_active_q) { - rx = (struct bna_rx *)qe; - if (rx->type == type) - bfa_wc_up(&rx_mod->rx_stop_wc); - } - - if (rx_mod->rx_stop_wc.wc_count == 0) { - rx_mod->stop_cbfn(&rx_mod->bna->port, BNA_CB_SUCCESS); - rx_mod->stop_cbfn = NULL; - return; - } - - list_for_each(qe, &rx_mod->rx_active_q) { - rx = (struct bna_rx *)qe; - if (rx->type == type) - bna_rx_stop(rx); - } -} - -void -bna_rx_mod_fail(struct bna_rx_mod *rx_mod) -{ - struct bna_rx *rx; - struct list_head *qe; - - rx_mod->flags &= ~BNA_RX_MOD_F_PORT_STARTED; - rx_mod->flags &= ~BNA_RX_MOD_F_PORT_LOOPBACK; - - list_for_each(qe, &rx_mod->rx_active_q) { - rx = (struct bna_rx *)qe; - bna_rx_fail(rx); - } -} - -void bna_rx_mod_init(struct bna_rx_mod *rx_mod, struct bna *bna, - struct bna_res_info *res_info) -{ - int index; - struct bna_rx *rx_ptr; - struct bna_rxp *rxp_ptr; - struct bna_rxq *rxq_ptr; - - rx_mod->bna = bna; - rx_mod->flags = 0; - - rx_mod->rx = (struct bna_rx *) - res_info[BNA_RES_MEM_T_RX_ARRAY].res_u.mem_info.mdl[0].kva; - rx_mod->rxp = (struct bna_rxp *) - res_info[BNA_RES_MEM_T_RXP_ARRAY].res_u.mem_info.mdl[0].kva; - rx_mod->rxq = (struct bna_rxq *) - res_info[BNA_RES_MEM_T_RXQ_ARRAY].res_u.mem_info.mdl[0].kva; - - /* Initialize the queues */ - _init_rxmod_queues(rx_mod); - - /* Build RX queues */ - for (index = 0; index < BFI_MAX_RXQ; index++) { - rx_ptr = &rx_mod->rx[index]; - _rx_ctor(rx_ptr, index); - list_add_tail(&rx_ptr->qe, &rx_mod->rx_free_q); - rx_mod->rx_free_count++; - } - - /* build RX-path queue */ - for (index = 0; index < BFI_MAX_RXQ; index++) { - rxp_ptr = &rx_mod->rxp[index]; - rxp_ptr->cq.cq_id = index; - bfa_q_qe_init(&rxp_ptr->qe); - list_add_tail(&rxp_ptr->qe, &rx_mod->rxp_free_q); - rx_mod->rxp_free_count++; - } - - /* build RXQ queue */ - for (index = 0; index < BFI_MAX_RXQ; index++) { - rxq_ptr = &rx_mod->rxq[index]; - rxq_ptr->rxq_id = index; - - bfa_q_qe_init(&rxq_ptr->qe); - list_add_tail(&rxq_ptr->qe, &rx_mod->rxq_free_q); - rx_mod->rxq_free_count++; - } - - rx_mod->rx_stop_wc.wc_resume = bna_rx_mod_cb_rx_stopped_all; - rx_mod->rx_stop_wc.wc_cbarg = rx_mod; - rx_mod->rx_stop_wc.wc_count = 0; -} - -void -bna_rx_mod_uninit(struct bna_rx_mod *rx_mod) -{ - struct list_head *qe; - int i; - - i = 0; - list_for_each(qe, &rx_mod->rx_free_q) - i++; - - i = 0; - list_for_each(qe, &rx_mod->rxp_free_q) - i++; - - i = 0; - list_for_each(qe, &rx_mod->rxq_free_q) - i++; - - rx_mod->bna = NULL; -} - -int -bna_rx_state_get(struct bna_rx *rx) -{ - return bfa_sm_to_state(rx_sm_table, rx->fsm); -} - -void -bna_rx_res_req(struct bna_rx_config *q_cfg, struct bna_res_info *res_info) -{ - u32 cq_size, hq_size, dq_size; - u32 cpage_count, hpage_count, dpage_count; - struct bna_mem_info *mem_info; - u32 cq_depth; - u32 hq_depth; - u32 dq_depth; - - dq_depth = q_cfg->q_depth; - hq_depth = ((q_cfg->rxp_type == BNA_RXP_SINGLE) ? 0 : q_cfg->q_depth); - cq_depth = dq_depth + hq_depth; - - BNA_TO_POWER_OF_2_HIGH(cq_depth); - cq_size = cq_depth * BFI_CQ_WI_SIZE; - cq_size = ALIGN(cq_size, PAGE_SIZE); - cpage_count = SIZE_TO_PAGES(cq_size); - - BNA_TO_POWER_OF_2_HIGH(dq_depth); - dq_size = dq_depth * BFI_RXQ_WI_SIZE; - dq_size = ALIGN(dq_size, PAGE_SIZE); - dpage_count = SIZE_TO_PAGES(dq_size); - - if (BNA_RXP_SINGLE != q_cfg->rxp_type) { - BNA_TO_POWER_OF_2_HIGH(hq_depth); - hq_size = hq_depth * BFI_RXQ_WI_SIZE; - hq_size = ALIGN(hq_size, PAGE_SIZE); - hpage_count = SIZE_TO_PAGES(hq_size); - } else { - hpage_count = 0; - } - - /* CCB structures */ - res_info[BNA_RX_RES_MEM_T_CCB].res_type = BNA_RES_T_MEM; - mem_info = &res_info[BNA_RX_RES_MEM_T_CCB].res_u.mem_info; - mem_info->mem_type = BNA_MEM_T_KVA; - mem_info->len = sizeof(struct bna_ccb); - mem_info->num = q_cfg->num_paths; - - /* RCB structures */ - res_info[BNA_RX_RES_MEM_T_RCB].res_type = BNA_RES_T_MEM; - mem_info = &res_info[BNA_RX_RES_MEM_T_RCB].res_u.mem_info; - mem_info->mem_type = BNA_MEM_T_KVA; - mem_info->len = sizeof(struct bna_rcb); - mem_info->num = BNA_GET_RXQS(q_cfg); - - /* Completion QPT */ - res_info[BNA_RX_RES_MEM_T_CQPT].res_type = BNA_RES_T_MEM; - mem_info = &res_info[BNA_RX_RES_MEM_T_CQPT].res_u.mem_info; - mem_info->mem_type = BNA_MEM_T_DMA; - mem_info->len = cpage_count * sizeof(struct bna_dma_addr); - mem_info->num = q_cfg->num_paths; - - /* Completion s/w QPT */ - res_info[BNA_RX_RES_MEM_T_CSWQPT].res_type = BNA_RES_T_MEM; - mem_info = &res_info[BNA_RX_RES_MEM_T_CSWQPT].res_u.mem_info; - mem_info->mem_type = BNA_MEM_T_KVA; - mem_info->len = cpage_count * sizeof(void *); - mem_info->num = q_cfg->num_paths; - - /* Completion QPT pages */ - res_info[BNA_RX_RES_MEM_T_CQPT_PAGE].res_type = BNA_RES_T_MEM; - mem_info = &res_info[BNA_RX_RES_MEM_T_CQPT_PAGE].res_u.mem_info; - mem_info->mem_type = BNA_MEM_T_DMA; - mem_info->len = PAGE_SIZE; - mem_info->num = cpage_count * q_cfg->num_paths; - - /* Data QPTs */ - res_info[BNA_RX_RES_MEM_T_DQPT].res_type = BNA_RES_T_MEM; - mem_info = &res_info[BNA_RX_RES_MEM_T_DQPT].res_u.mem_info; - mem_info->mem_type = BNA_MEM_T_DMA; - mem_info->len = dpage_count * sizeof(struct bna_dma_addr); - mem_info->num = q_cfg->num_paths; - - /* Data s/w QPTs */ - res_info[BNA_RX_RES_MEM_T_DSWQPT].res_type = BNA_RES_T_MEM; - mem_info = &res_info[BNA_RX_RES_MEM_T_DSWQPT].res_u.mem_info; - mem_info->mem_type = BNA_MEM_T_KVA; - mem_info->len = dpage_count * sizeof(void *); - mem_info->num = q_cfg->num_paths; - - /* Data QPT pages */ - res_info[BNA_RX_RES_MEM_T_DPAGE].res_type = BNA_RES_T_MEM; - mem_info = &res_info[BNA_RX_RES_MEM_T_DPAGE].res_u.mem_info; - mem_info->mem_type = BNA_MEM_T_DMA; - mem_info->len = PAGE_SIZE; - mem_info->num = dpage_count * q_cfg->num_paths; - - /* Hdr QPTs */ - res_info[BNA_RX_RES_MEM_T_HQPT].res_type = BNA_RES_T_MEM; - mem_info = &res_info[BNA_RX_RES_MEM_T_HQPT].res_u.mem_info; - mem_info->mem_type = BNA_MEM_T_DMA; - mem_info->len = hpage_count * sizeof(struct bna_dma_addr); - mem_info->num = (hpage_count ? q_cfg->num_paths : 0); - - /* Hdr s/w QPTs */ - res_info[BNA_RX_RES_MEM_T_HSWQPT].res_type = BNA_RES_T_MEM; - mem_info = &res_info[BNA_RX_RES_MEM_T_HSWQPT].res_u.mem_info; - mem_info->mem_type = BNA_MEM_T_KVA; - mem_info->len = hpage_count * sizeof(void *); - mem_info->num = (hpage_count ? q_cfg->num_paths : 0); - - /* Hdr QPT pages */ - res_info[BNA_RX_RES_MEM_T_HPAGE].res_type = BNA_RES_T_MEM; - mem_info = &res_info[BNA_RX_RES_MEM_T_HPAGE].res_u.mem_info; - mem_info->mem_type = BNA_MEM_T_DMA; - mem_info->len = (hpage_count ? PAGE_SIZE : 0); - mem_info->num = (hpage_count ? (hpage_count * q_cfg->num_paths) : 0); - - /* RX Interrupts */ - res_info[BNA_RX_RES_T_INTR].res_type = BNA_RES_T_INTR; - res_info[BNA_RX_RES_T_INTR].res_u.intr_info.intr_type = BNA_INTR_T_MSIX; - res_info[BNA_RX_RES_T_INTR].res_u.intr_info.num = q_cfg->num_paths; -} - -struct bna_rx * -bna_rx_create(struct bna *bna, struct bnad *bnad, - struct bna_rx_config *rx_cfg, - struct bna_rx_event_cbfn *rx_cbfn, - struct bna_res_info *res_info, - void *priv) -{ - struct bna_rx_mod *rx_mod = &bna->rx_mod; - struct bna_rx *rx; - struct bna_rxp *rxp; - struct bna_rxq *q0; - struct bna_rxq *q1; - struct bna_intr_info *intr_info; - u32 page_count; - struct bna_mem_descr *ccb_mem; - struct bna_mem_descr *rcb_mem; - struct bna_mem_descr *unmapq_mem; - struct bna_mem_descr *cqpt_mem; - struct bna_mem_descr *cswqpt_mem; - struct bna_mem_descr *cpage_mem; - struct bna_mem_descr *hqpt_mem; /* Header/Small Q qpt */ - struct bna_mem_descr *dqpt_mem; /* Data/Large Q qpt */ - struct bna_mem_descr *hsqpt_mem; /* s/w qpt for hdr */ - struct bna_mem_descr *dsqpt_mem; /* s/w qpt for data */ - struct bna_mem_descr *hpage_mem; /* hdr page mem */ - struct bna_mem_descr *dpage_mem; /* data page mem */ - int i, cpage_idx = 0, dpage_idx = 0, hpage_idx = 0; - int dpage_count, hpage_count, rcb_idx; - struct bna_ib_config ibcfg; - /* Fail if we don't have enough RXPs, RXQs */ - if (!_rx_can_satisfy(rx_mod, rx_cfg)) - return NULL; - - /* Initialize resource pointers */ - intr_info = &res_info[BNA_RX_RES_T_INTR].res_u.intr_info; - ccb_mem = &res_info[BNA_RX_RES_MEM_T_CCB].res_u.mem_info.mdl[0]; - rcb_mem = &res_info[BNA_RX_RES_MEM_T_RCB].res_u.mem_info.mdl[0]; - unmapq_mem = &res_info[BNA_RX_RES_MEM_T_UNMAPQ].res_u.mem_info.mdl[0]; - cqpt_mem = &res_info[BNA_RX_RES_MEM_T_CQPT].res_u.mem_info.mdl[0]; - cswqpt_mem = &res_info[BNA_RX_RES_MEM_T_CSWQPT].res_u.mem_info.mdl[0]; - cpage_mem = &res_info[BNA_RX_RES_MEM_T_CQPT_PAGE].res_u.mem_info.mdl[0]; - hqpt_mem = &res_info[BNA_RX_RES_MEM_T_HQPT].res_u.mem_info.mdl[0]; - dqpt_mem = &res_info[BNA_RX_RES_MEM_T_DQPT].res_u.mem_info.mdl[0]; - hsqpt_mem = &res_info[BNA_RX_RES_MEM_T_HSWQPT].res_u.mem_info.mdl[0]; - dsqpt_mem = &res_info[BNA_RX_RES_MEM_T_DSWQPT].res_u.mem_info.mdl[0]; - hpage_mem = &res_info[BNA_RX_RES_MEM_T_HPAGE].res_u.mem_info.mdl[0]; - dpage_mem = &res_info[BNA_RX_RES_MEM_T_DPAGE].res_u.mem_info.mdl[0]; - - /* Compute q depth & page count */ - page_count = res_info[BNA_RX_RES_MEM_T_CQPT_PAGE].res_u.mem_info.num / - rx_cfg->num_paths; - - dpage_count = res_info[BNA_RX_RES_MEM_T_DPAGE].res_u.mem_info.num / - rx_cfg->num_paths; - - hpage_count = res_info[BNA_RX_RES_MEM_T_HPAGE].res_u.mem_info.num / - rx_cfg->num_paths; - /* Get RX pointer */ - rx = _get_free_rx(rx_mod); - _rx_init(rx, bna); - rx->priv = priv; - rx->type = rx_cfg->rx_type; - - rx->rcb_setup_cbfn = rx_cbfn->rcb_setup_cbfn; - rx->rcb_destroy_cbfn = rx_cbfn->rcb_destroy_cbfn; - rx->ccb_setup_cbfn = rx_cbfn->ccb_setup_cbfn; - rx->ccb_destroy_cbfn = rx_cbfn->ccb_destroy_cbfn; - /* Following callbacks are mandatory */ - rx->rx_cleanup_cbfn = rx_cbfn->rx_cleanup_cbfn; - rx->rx_post_cbfn = rx_cbfn->rx_post_cbfn; - - if (rx->bna->rx_mod.flags & BNA_RX_MOD_F_PORT_STARTED) { - switch (rx->type) { - case BNA_RX_T_REGULAR: - if (!(rx->bna->rx_mod.flags & - BNA_RX_MOD_F_PORT_LOOPBACK)) - rx->rx_flags |= BNA_RX_F_PORT_ENABLED; - break; - case BNA_RX_T_LOOPBACK: - if (rx->bna->rx_mod.flags & BNA_RX_MOD_F_PORT_LOOPBACK) - rx->rx_flags |= BNA_RX_F_PORT_ENABLED; - break; - } - } - - for (i = 0, rcb_idx = 0; i < rx_cfg->num_paths; i++) { - rxp = _get_free_rxp(rx_mod); - rxp->type = rx_cfg->rxp_type; - rxp->rx = rx; - rxp->cq.rx = rx; - - /* Get required RXQs, and queue them to rx-path */ - q0 = _get_free_rxq(rx_mod); - if (BNA_RXP_SINGLE == rx_cfg->rxp_type) - q1 = NULL; - else - q1 = _get_free_rxq(rx_mod); - - /* Initialize IB */ - if (1 == intr_info->num) { - rxp->cq.ib = bna_ib_get(&bna->ib_mod, - intr_info->intr_type, - intr_info->idl[0].vector); - rxp->vector = intr_info->idl[0].vector; - } else { - rxp->cq.ib = bna_ib_get(&bna->ib_mod, - intr_info->intr_type, - intr_info->idl[i].vector); - - /* Map the MSI-x vector used for this RXP */ - rxp->vector = intr_info->idl[i].vector; - } - - rxp->cq.ib_seg_offset = bna_ib_reserve_idx(rxp->cq.ib); - - ibcfg.coalescing_timeo = BFI_RX_COALESCING_TIMEO; - ibcfg.interpkt_count = BFI_RX_INTERPKT_COUNT; - ibcfg.interpkt_timeo = BFI_RX_INTERPKT_TIMEO; - ibcfg.ctrl_flags = BFI_IB_CF_INT_ENABLE; - - bna_ib_config(rxp->cq.ib, &ibcfg); - - /* Link rxqs to rxp */ - _rxp_add_rxqs(rxp, q0, q1); - - /* Link rxp to rx */ - _rx_add_rxp(rx, rxp); - - q0->rx = rx; - q0->rxp = rxp; - - /* Initialize RCB for the large / data q */ - q0->rcb = (struct bna_rcb *) rcb_mem[rcb_idx].kva; - RXQ_RCB_INIT(q0, rxp, rx_cfg->q_depth, bna, 0, - (void *)unmapq_mem[rcb_idx].kva); - rcb_idx++; - (q0)->rx_packets = (q0)->rx_bytes = 0; - (q0)->rx_packets_with_error = (q0)->rxbuf_alloc_failed = 0; - - /* Initialize RXQs */ - _rxq_qpt_init(q0, rxp, dpage_count, PAGE_SIZE, - &dqpt_mem[i], &dsqpt_mem[i], &dpage_mem[dpage_idx]); - q0->rcb->page_idx = dpage_idx; - q0->rcb->page_count = dpage_count; - dpage_idx += dpage_count; - - /* Call bnad to complete rcb setup */ - if (rx->rcb_setup_cbfn) - rx->rcb_setup_cbfn(bnad, q0->rcb); - - if (q1) { - q1->rx = rx; - q1->rxp = rxp; - - q1->rcb = (struct bna_rcb *) rcb_mem[rcb_idx].kva; - RXQ_RCB_INIT(q1, rxp, rx_cfg->q_depth, bna, 1, - (void *)unmapq_mem[rcb_idx].kva); - rcb_idx++; - (q1)->buffer_size = (rx_cfg)->small_buff_size; - (q1)->rx_packets = (q1)->rx_bytes = 0; - (q1)->rx_packets_with_error = - (q1)->rxbuf_alloc_failed = 0; - - _rxq_qpt_init(q1, rxp, hpage_count, PAGE_SIZE, - &hqpt_mem[i], &hsqpt_mem[i], - &hpage_mem[hpage_idx]); - q1->rcb->page_idx = hpage_idx; - q1->rcb->page_count = hpage_count; - hpage_idx += hpage_count; - - /* Call bnad to complete rcb setup */ - if (rx->rcb_setup_cbfn) - rx->rcb_setup_cbfn(bnad, q1->rcb); - } - /* Setup RXP::CQ */ - rxp->cq.ccb = (struct bna_ccb *) ccb_mem[i].kva; - _rxp_cqpt_setup(rxp, page_count, PAGE_SIZE, - &cqpt_mem[i], &cswqpt_mem[i], &cpage_mem[cpage_idx]); - rxp->cq.ccb->page_idx = cpage_idx; - rxp->cq.ccb->page_count = page_count; - cpage_idx += page_count; - - rxp->cq.ccb->pkt_rate.small_pkt_cnt = 0; - rxp->cq.ccb->pkt_rate.large_pkt_cnt = 0; - - rxp->cq.ccb->producer_index = 0; - rxp->cq.ccb->q_depth = rx_cfg->q_depth + - ((rx_cfg->rxp_type == BNA_RXP_SINGLE) ? - 0 : rx_cfg->q_depth); - rxp->cq.ccb->i_dbell = &rxp->cq.ib->door_bell; - rxp->cq.ccb->rcb[0] = q0->rcb; - if (q1) - rxp->cq.ccb->rcb[1] = q1->rcb; - rxp->cq.ccb->cq = &rxp->cq; - rxp->cq.ccb->bnad = bna->bnad; - rxp->cq.ccb->hw_producer_index = - ((volatile u32 *)rxp->cq.ib->ib_seg_host_addr_kva + - (rxp->cq.ib_seg_offset * BFI_IBIDX_SIZE)); - *(rxp->cq.ccb->hw_producer_index) = 0; - rxp->cq.ccb->intr_type = intr_info->intr_type; - rxp->cq.ccb->intr_vector = (intr_info->num == 1) ? - intr_info->idl[0].vector : - intr_info->idl[i].vector; - rxp->cq.ccb->rx_coalescing_timeo = - rxp->cq.ib->ib_config.coalescing_timeo; - rxp->cq.ccb->id = i; - - /* Call bnad to complete CCB setup */ - if (rx->ccb_setup_cbfn) - rx->ccb_setup_cbfn(bnad, rxp->cq.ccb); - - } /* for each rx-path */ - - bna_rxf_init(&rx->rxf, rx, rx_cfg); - - bfa_fsm_set_state(rx, bna_rx_sm_stopped); - - return rx; -} - -void -bna_rx_destroy(struct bna_rx *rx) -{ - struct bna_rx_mod *rx_mod = &rx->bna->rx_mod; - struct bna_ib_mod *ib_mod = &rx->bna->ib_mod; - struct bna_rxq *q0 = NULL; - struct bna_rxq *q1 = NULL; - struct bna_rxp *rxp; - struct list_head *qe; - - bna_rxf_uninit(&rx->rxf); - - while (!list_empty(&rx->rxp_q)) { - bfa_q_deq(&rx->rxp_q, &rxp); - GET_RXQS(rxp, q0, q1); - /* Callback to bnad for destroying RCB */ - if (rx->rcb_destroy_cbfn) - rx->rcb_destroy_cbfn(rx->bna->bnad, q0->rcb); - q0->rcb = NULL; - q0->rxp = NULL; - q0->rx = NULL; - _put_free_rxq(rx_mod, q0); - if (q1) { - /* Callback to bnad for destroying RCB */ - if (rx->rcb_destroy_cbfn) - rx->rcb_destroy_cbfn(rx->bna->bnad, q1->rcb); - q1->rcb = NULL; - q1->rxp = NULL; - q1->rx = NULL; - _put_free_rxq(rx_mod, q1); - } - rxp->rxq.slr.large = NULL; - rxp->rxq.slr.small = NULL; - if (rxp->cq.ib) { - if (rxp->cq.ib_seg_offset != 0xff) - bna_ib_release_idx(rxp->cq.ib, - rxp->cq.ib_seg_offset); - bna_ib_put(ib_mod, rxp->cq.ib); - rxp->cq.ib = NULL; - } - /* Callback to bnad for destroying CCB */ - if (rx->ccb_destroy_cbfn) - rx->ccb_destroy_cbfn(rx->bna->bnad, rxp->cq.ccb); - rxp->cq.ccb = NULL; - rxp->rx = NULL; - _put_free_rxp(rx_mod, rxp); - } - - list_for_each(qe, &rx_mod->rx_active_q) { - if (qe == &rx->qe) { - list_del(&rx->qe); - bfa_q_qe_init(&rx->qe); - break; - } - } - - rx->bna = NULL; - rx->priv = NULL; - _put_free_rx(rx_mod, rx); -} - -void -bna_rx_enable(struct bna_rx *rx) -{ - if (rx->fsm != (bfa_sm_t)bna_rx_sm_stopped) - return; - - rx->rx_flags |= BNA_RX_F_ENABLE; - if (rx->rx_flags & BNA_RX_F_PORT_ENABLED) - bfa_fsm_send_event(rx, RX_E_START); -} - -void -bna_rx_disable(struct bna_rx *rx, enum bna_cleanup_type type, - void (*cbfn)(void *, struct bna_rx *, - enum bna_cb_status)) -{ - if (type == BNA_SOFT_CLEANUP) { - /* h/w should not be accessed. Treat we're stopped */ - (*cbfn)(rx->bna->bnad, rx, BNA_CB_SUCCESS); - } else { - rx->stop_cbfn = cbfn; - rx->stop_cbarg = rx->bna->bnad; - - rx->rx_flags &= ~BNA_RX_F_ENABLE; - - bfa_fsm_send_event(rx, RX_E_STOP); - } -} - -/** - * TX - */ -#define call_tx_stop_cbfn(tx, status)\ -do {\ - if ((tx)->stop_cbfn)\ - (tx)->stop_cbfn((tx)->stop_cbarg, (tx), status);\ - (tx)->stop_cbfn = NULL;\ - (tx)->stop_cbarg = NULL;\ -} while (0) - -#define call_tx_prio_change_cbfn(tx, status)\ -do {\ - if ((tx)->prio_change_cbfn)\ - (tx)->prio_change_cbfn((tx)->bna->bnad, (tx), status);\ - (tx)->prio_change_cbfn = NULL;\ -} while (0) - -static void bna_tx_mod_cb_tx_stopped(void *tx_mod, struct bna_tx *tx, - enum bna_cb_status status); -static void bna_tx_cb_txq_stopped(void *arg, int status); -static void bna_tx_cb_stats_cleared(void *arg, int status); -static void __bna_tx_stop(struct bna_tx *tx); -static void __bna_tx_start(struct bna_tx *tx); -static void __bna_txf_stat_clr(struct bna_tx *tx); - -enum bna_tx_event { - TX_E_START = 1, - TX_E_STOP = 2, - TX_E_FAIL = 3, - TX_E_TXQ_STOPPED = 4, - TX_E_PRIO_CHANGE = 5, - TX_E_STAT_CLEARED = 6, -}; - -enum bna_tx_state { - BNA_TX_STOPPED = 1, - BNA_TX_STARTED = 2, - BNA_TX_TXQ_STOP_WAIT = 3, - BNA_TX_PRIO_STOP_WAIT = 4, - BNA_TX_STAT_CLR_WAIT = 5, -}; - -bfa_fsm_state_decl(bna_tx, stopped, struct bna_tx, - enum bna_tx_event); -bfa_fsm_state_decl(bna_tx, started, struct bna_tx, - enum bna_tx_event); -bfa_fsm_state_decl(bna_tx, txq_stop_wait, struct bna_tx, - enum bna_tx_event); -bfa_fsm_state_decl(bna_tx, prio_stop_wait, struct bna_tx, - enum bna_tx_event); -bfa_fsm_state_decl(bna_tx, stat_clr_wait, struct bna_tx, - enum bna_tx_event); - -static struct bfa_sm_table tx_sm_table[] = { - {BFA_SM(bna_tx_sm_stopped), BNA_TX_STOPPED}, - {BFA_SM(bna_tx_sm_started), BNA_TX_STARTED}, - {BFA_SM(bna_tx_sm_txq_stop_wait), BNA_TX_TXQ_STOP_WAIT}, - {BFA_SM(bna_tx_sm_prio_stop_wait), BNA_TX_PRIO_STOP_WAIT}, - {BFA_SM(bna_tx_sm_stat_clr_wait), BNA_TX_STAT_CLR_WAIT}, -}; - -static void -bna_tx_sm_stopped_entry(struct bna_tx *tx) -{ - struct bna_txq *txq; - struct list_head *qe; - - list_for_each(qe, &tx->txq_q) { - txq = (struct bna_txq *)qe; - (tx->tx_cleanup_cbfn)(tx->bna->bnad, txq->tcb); - } - - call_tx_stop_cbfn(tx, BNA_CB_SUCCESS); -} - -static void -bna_tx_sm_stopped(struct bna_tx *tx, enum bna_tx_event event) -{ - switch (event) { - case TX_E_START: - bfa_fsm_set_state(tx, bna_tx_sm_started); - break; - - case TX_E_STOP: - bfa_fsm_set_state(tx, bna_tx_sm_stopped); - break; - - case TX_E_FAIL: - /* No-op */ - break; - - case TX_E_PRIO_CHANGE: - call_tx_prio_change_cbfn(tx, BNA_CB_SUCCESS); - break; - - case TX_E_TXQ_STOPPED: - /** - * This event is received due to flushing of mbox when - * device fails - */ - /* No-op */ - break; - - default: - bfa_sm_fault(event); - } -} - -static void -bna_tx_sm_started_entry(struct bna_tx *tx) -{ - struct bna_txq *txq; - struct list_head *qe; - - __bna_tx_start(tx); - - /* Start IB */ - list_for_each(qe, &tx->txq_q) { - txq = (struct bna_txq *)qe; - bna_ib_ack(&txq->ib->door_bell, 0); - } -} - -static void -bna_tx_sm_started(struct bna_tx *tx, enum bna_tx_event event) -{ - struct bna_txq *txq; - struct list_head *qe; - - switch (event) { - case TX_E_STOP: - bfa_fsm_set_state(tx, bna_tx_sm_txq_stop_wait); - __bna_tx_stop(tx); - break; - - case TX_E_FAIL: - list_for_each(qe, &tx->txq_q) { - txq = (struct bna_txq *)qe; - bna_ib_fail(txq->ib); - (tx->tx_stall_cbfn)(tx->bna->bnad, txq->tcb); - } - bfa_fsm_set_state(tx, bna_tx_sm_stopped); - break; - - case TX_E_PRIO_CHANGE: - bfa_fsm_set_state(tx, bna_tx_sm_prio_stop_wait); - break; - - default: - bfa_sm_fault(event); - } -} - -static void -bna_tx_sm_txq_stop_wait_entry(struct bna_tx *tx) -{ -} - -static void -bna_tx_sm_txq_stop_wait(struct bna_tx *tx, enum bna_tx_event event) -{ - struct bna_txq *txq; - struct list_head *qe; - - switch (event) { - case TX_E_FAIL: - bfa_fsm_set_state(tx, bna_tx_sm_stopped); - break; - - case TX_E_TXQ_STOPPED: - list_for_each(qe, &tx->txq_q) { - txq = (struct bna_txq *)qe; - bna_ib_stop(txq->ib); - } - bfa_fsm_set_state(tx, bna_tx_sm_stat_clr_wait); - break; - - case TX_E_PRIO_CHANGE: - /* No-op */ - break; - - default: - bfa_sm_fault(event); - } -} - -static void -bna_tx_sm_prio_stop_wait_entry(struct bna_tx *tx) -{ - __bna_tx_stop(tx); -} - -static void -bna_tx_sm_prio_stop_wait(struct bna_tx *tx, enum bna_tx_event event) -{ - struct bna_txq *txq; - struct list_head *qe; - - switch (event) { - case TX_E_STOP: - bfa_fsm_set_state(tx, bna_tx_sm_txq_stop_wait); - break; - - case TX_E_FAIL: - call_tx_prio_change_cbfn(tx, BNA_CB_FAIL); - bfa_fsm_set_state(tx, bna_tx_sm_stopped); - break; - - case TX_E_TXQ_STOPPED: - list_for_each(qe, &tx->txq_q) { - txq = (struct bna_txq *)qe; - bna_ib_stop(txq->ib); - (tx->tx_cleanup_cbfn)(tx->bna->bnad, txq->tcb); - } - call_tx_prio_change_cbfn(tx, BNA_CB_SUCCESS); - bfa_fsm_set_state(tx, bna_tx_sm_started); - break; - - case TX_E_PRIO_CHANGE: - /* No-op */ - break; - - default: - bfa_sm_fault(event); - } -} - -static void -bna_tx_sm_stat_clr_wait_entry(struct bna_tx *tx) -{ - __bna_txf_stat_clr(tx); -} - -static void -bna_tx_sm_stat_clr_wait(struct bna_tx *tx, enum bna_tx_event event) -{ - switch (event) { - case TX_E_FAIL: - case TX_E_STAT_CLEARED: - bfa_fsm_set_state(tx, bna_tx_sm_stopped); - break; - - default: - bfa_sm_fault(event); - } -} - -static void -__bna_txq_start(struct bna_tx *tx, struct bna_txq *txq) -{ - struct bna_rxtx_q_mem *q_mem; - struct bna_txq_mem txq_cfg; - struct bna_txq_mem *txq_mem; - struct bna_dma_addr cur_q_addr; - u32 pg_num; - void __iomem *base_addr; - unsigned long off; - - /* Fill out structure, to be subsequently written to hardware */ - txq_cfg.pg_tbl_addr_lo = txq->qpt.hw_qpt_ptr.lsb; - txq_cfg.pg_tbl_addr_hi = txq->qpt.hw_qpt_ptr.msb; - cur_q_addr = *((struct bna_dma_addr *)(txq->qpt.kv_qpt_ptr)); - txq_cfg.cur_q_entry_lo = cur_q_addr.lsb; - txq_cfg.cur_q_entry_hi = cur_q_addr.msb; - - txq_cfg.pg_cnt_n_prd_ptr = (txq->qpt.page_count << 16) | 0x0; - - txq_cfg.entry_n_pg_size = ((u32)(BFI_TXQ_WI_SIZE >> 2) << 16) | - (txq->qpt.page_size >> 2); - txq_cfg.int_blk_n_cns_ptr = ((((u32)txq->ib_seg_offset) << 24) | - ((u32)(txq->ib->ib_id & 0xff) << 16) | 0x0); - - txq_cfg.cns_ptr2_n_q_state = BNA_Q_IDLE_STATE; - txq_cfg.nxt_qid_n_fid_n_pri = (((tx->txf.txf_id & 0x3f) << 3) | - (txq->priority & 0x7)); - txq_cfg.wvc_n_cquota_n_rquota = - ((((u32)BFI_TX_MAX_WRR_QUOTA & 0xfff) << 12) | - (BFI_TX_MAX_WRR_QUOTA & 0xfff)); - - /* Setup the page and write to H/W */ - - pg_num = BNA_GET_PAGE_NUM(HQM0_BLK_PG_NUM + tx->bna->port_num, - HQM_RXTX_Q_RAM_BASE_OFFSET); - writel(pg_num, tx->bna->regs.page_addr); - - base_addr = BNA_GET_MEM_BASE_ADDR(tx->bna->pcidev.pci_bar_kva, - HQM_RXTX_Q_RAM_BASE_OFFSET); - q_mem = (struct bna_rxtx_q_mem *)0; - txq_mem = &q_mem[txq->txq_id].txq; - - /* - * The following 4 lines, is a hack b'cos the H/W needs to read - * these DMA addresses as little endian - */ - - off = (unsigned long)&txq_mem->pg_tbl_addr_lo; - writel(htonl(txq_cfg.pg_tbl_addr_lo), base_addr + off); - - off = (unsigned long)&txq_mem->pg_tbl_addr_hi; - writel(htonl(txq_cfg.pg_tbl_addr_hi), base_addr + off); - - off = (unsigned long)&txq_mem->cur_q_entry_lo; - writel(htonl(txq_cfg.cur_q_entry_lo), base_addr + off); - - off = (unsigned long)&txq_mem->cur_q_entry_hi; - writel(htonl(txq_cfg.cur_q_entry_hi), base_addr + off); - - off = (unsigned long)&txq_mem->pg_cnt_n_prd_ptr; - writel(txq_cfg.pg_cnt_n_prd_ptr, base_addr + off); - - off = (unsigned long)&txq_mem->entry_n_pg_size; - writel(txq_cfg.entry_n_pg_size, base_addr + off); - - off = (unsigned long)&txq_mem->int_blk_n_cns_ptr; - writel(txq_cfg.int_blk_n_cns_ptr, base_addr + off); - - off = (unsigned long)&txq_mem->cns_ptr2_n_q_state; - writel(txq_cfg.cns_ptr2_n_q_state, base_addr + off); - - off = (unsigned long)&txq_mem->nxt_qid_n_fid_n_pri; - writel(txq_cfg.nxt_qid_n_fid_n_pri, base_addr + off); - - off = (unsigned long)&txq_mem->wvc_n_cquota_n_rquota; - writel(txq_cfg.wvc_n_cquota_n_rquota, base_addr + off); - - txq->tcb->producer_index = 0; - txq->tcb->consumer_index = 0; - *(txq->tcb->hw_consumer_index) = 0; - -} - -static void -__bna_txq_stop(struct bna_tx *tx, struct bna_txq *txq) -{ - struct bfi_ll_q_stop_req ll_req; - u32 bit_mask[2] = {0, 0}; - if (txq->txq_id < 32) - bit_mask[0] = (u32)1 << txq->txq_id; - else - bit_mask[1] = (u32)1 << (txq->txq_id - 32); - - memset(&ll_req, 0, sizeof(ll_req)); - ll_req.mh.msg_class = BFI_MC_LL; - ll_req.mh.msg_id = BFI_LL_H2I_TXQ_STOP_REQ; - ll_req.mh.mtag.h2i.lpu_id = 0; - ll_req.q_id_mask[0] = htonl(bit_mask[0]); - ll_req.q_id_mask[1] = htonl(bit_mask[1]); - - bna_mbox_qe_fill(&tx->mbox_qe, &ll_req, sizeof(ll_req), - bna_tx_cb_txq_stopped, tx); - - bna_mbox_send(tx->bna, &tx->mbox_qe); -} - -static void -__bna_txf_start(struct bna_tx *tx) -{ - struct bna_tx_fndb_ram *tx_fndb; - struct bna_txf *txf = &tx->txf; - void __iomem *base_addr; - unsigned long off; - - writel(BNA_GET_PAGE_NUM(LUT0_MEM_BLK_BASE_PG_NUM + - (tx->bna->port_num * 2), TX_FNDB_RAM_BASE_OFFSET), - tx->bna->regs.page_addr); - - base_addr = BNA_GET_MEM_BASE_ADDR(tx->bna->pcidev.pci_bar_kva, - TX_FNDB_RAM_BASE_OFFSET); - - tx_fndb = (struct bna_tx_fndb_ram *)0; - off = (unsigned long)&tx_fndb[txf->txf_id].vlan_n_ctrl_flags; - - writel(((u32)txf->vlan << 16) | txf->ctrl_flags, - base_addr + off); - - if (tx->txf.txf_id < 32) - tx->bna->tx_mod.txf_bmap[0] |= ((u32)1 << tx->txf.txf_id); - else - tx->bna->tx_mod.txf_bmap[1] |= ((u32) - 1 << (tx->txf.txf_id - 32)); -} - -static void -__bna_txf_stop(struct bna_tx *tx) -{ - struct bna_tx_fndb_ram *tx_fndb; - u32 page_num; - u32 ctl_flags; - struct bna_txf *txf = &tx->txf; - void __iomem *base_addr; - unsigned long off; - - /* retrieve the running txf_flags & turn off enable bit */ - page_num = BNA_GET_PAGE_NUM(LUT0_MEM_BLK_BASE_PG_NUM + - (tx->bna->port_num * 2), TX_FNDB_RAM_BASE_OFFSET); - writel(page_num, tx->bna->regs.page_addr); - - base_addr = BNA_GET_MEM_BASE_ADDR(tx->bna->pcidev.pci_bar_kva, - TX_FNDB_RAM_BASE_OFFSET); - tx_fndb = (struct bna_tx_fndb_ram *)0; - off = (unsigned long)&tx_fndb[txf->txf_id].vlan_n_ctrl_flags; - - ctl_flags = readl(base_addr + off); - ctl_flags &= ~BFI_TXF_CF_ENABLE; - - writel(ctl_flags, base_addr + off); - - if (tx->txf.txf_id < 32) - tx->bna->tx_mod.txf_bmap[0] &= ~((u32)1 << tx->txf.txf_id); - else - tx->bna->tx_mod.txf_bmap[0] &= ~((u32) - 1 << (tx->txf.txf_id - 32)); -} - -static void -__bna_txf_stat_clr(struct bna_tx *tx) -{ - struct bfi_ll_stats_req ll_req; - u32 txf_bmap[2] = {0, 0}; - if (tx->txf.txf_id < 32) - txf_bmap[0] = ((u32)1 << tx->txf.txf_id); - else - txf_bmap[1] = ((u32)1 << (tx->txf.txf_id - 32)); - bfi_h2i_set(ll_req.mh, BFI_MC_LL, BFI_LL_H2I_STATS_CLEAR_REQ, 0); - ll_req.stats_mask = 0; - ll_req.rxf_id_mask[0] = 0; - ll_req.rxf_id_mask[1] = 0; - ll_req.txf_id_mask[0] = htonl(txf_bmap[0]); - ll_req.txf_id_mask[1] = htonl(txf_bmap[1]); - - bna_mbox_qe_fill(&tx->mbox_qe, &ll_req, sizeof(ll_req), - bna_tx_cb_stats_cleared, tx); - bna_mbox_send(tx->bna, &tx->mbox_qe); -} - -static void -__bna_tx_start(struct bna_tx *tx) -{ - struct bna_txq *txq; - struct list_head *qe; - - list_for_each(qe, &tx->txq_q) { - txq = (struct bna_txq *)qe; - bna_ib_start(txq->ib); - __bna_txq_start(tx, txq); - } - - __bna_txf_start(tx); - - list_for_each(qe, &tx->txq_q) { - txq = (struct bna_txq *)qe; - txq->tcb->priority = txq->priority; - (tx->tx_resume_cbfn)(tx->bna->bnad, txq->tcb); - } -} - -static void -__bna_tx_stop(struct bna_tx *tx) -{ - struct bna_txq *txq; - struct list_head *qe; - - list_for_each(qe, &tx->txq_q) { - txq = (struct bna_txq *)qe; - (tx->tx_stall_cbfn)(tx->bna->bnad, txq->tcb); - } - - __bna_txf_stop(tx); - - list_for_each(qe, &tx->txq_q) { - txq = (struct bna_txq *)qe; - bfa_wc_up(&tx->txq_stop_wc); - } - - list_for_each(qe, &tx->txq_q) { - txq = (struct bna_txq *)qe; - __bna_txq_stop(tx, txq); - } -} - -static void -bna_txq_qpt_setup(struct bna_txq *txq, int page_count, int page_size, - struct bna_mem_descr *qpt_mem, - struct bna_mem_descr *swqpt_mem, - struct bna_mem_descr *page_mem) -{ - int i; - - txq->qpt.hw_qpt_ptr.lsb = qpt_mem->dma.lsb; - txq->qpt.hw_qpt_ptr.msb = qpt_mem->dma.msb; - txq->qpt.kv_qpt_ptr = qpt_mem->kva; - txq->qpt.page_count = page_count; - txq->qpt.page_size = page_size; - - txq->tcb->sw_qpt = (void **) swqpt_mem->kva; - - for (i = 0; i < page_count; i++) { - txq->tcb->sw_qpt[i] = page_mem[i].kva; - - ((struct bna_dma_addr *)txq->qpt.kv_qpt_ptr)[i].lsb = - page_mem[i].dma.lsb; - ((struct bna_dma_addr *)txq->qpt.kv_qpt_ptr)[i].msb = - page_mem[i].dma.msb; - - } -} - -static void -bna_tx_free(struct bna_tx *tx) -{ - struct bna_tx_mod *tx_mod = &tx->bna->tx_mod; - struct bna_txq *txq; - struct bna_ib_mod *ib_mod = &tx->bna->ib_mod; - struct list_head *qe; - - while (!list_empty(&tx->txq_q)) { - bfa_q_deq(&tx->txq_q, &txq); - bfa_q_qe_init(&txq->qe); - if (txq->ib) { - if (txq->ib_seg_offset != -1) - bna_ib_release_idx(txq->ib, - txq->ib_seg_offset); - bna_ib_put(ib_mod, txq->ib); - txq->ib = NULL; - } - txq->tcb = NULL; - txq->tx = NULL; - list_add_tail(&txq->qe, &tx_mod->txq_free_q); - } - - list_for_each(qe, &tx_mod->tx_active_q) { - if (qe == &tx->qe) { - list_del(&tx->qe); - bfa_q_qe_init(&tx->qe); - break; - } - } - - tx->bna = NULL; - tx->priv = NULL; - list_add_tail(&tx->qe, &tx_mod->tx_free_q); -} - -static void -bna_tx_cb_txq_stopped(void *arg, int status) -{ - struct bna_tx *tx = (struct bna_tx *)arg; - - bfa_q_qe_init(&tx->mbox_qe.qe); - bfa_wc_down(&tx->txq_stop_wc); -} - -static void -bna_tx_cb_txq_stopped_all(void *arg) -{ - struct bna_tx *tx = (struct bna_tx *)arg; - - bfa_fsm_send_event(tx, TX_E_TXQ_STOPPED); -} - -static void -bna_tx_cb_stats_cleared(void *arg, int status) -{ - struct bna_tx *tx = (struct bna_tx *)arg; - - bfa_q_qe_init(&tx->mbox_qe.qe); - - bfa_fsm_send_event(tx, TX_E_STAT_CLEARED); -} - -static void -bna_tx_start(struct bna_tx *tx) -{ - tx->flags |= BNA_TX_F_PORT_STARTED; - if (tx->flags & BNA_TX_F_ENABLED) - bfa_fsm_send_event(tx, TX_E_START); -} - -static void -bna_tx_stop(struct bna_tx *tx) -{ - tx->stop_cbfn = bna_tx_mod_cb_tx_stopped; - tx->stop_cbarg = &tx->bna->tx_mod; - - tx->flags &= ~BNA_TX_F_PORT_STARTED; - bfa_fsm_send_event(tx, TX_E_STOP); -} - -static void -bna_tx_fail(struct bna_tx *tx) -{ - tx->flags &= ~BNA_TX_F_PORT_STARTED; - bfa_fsm_send_event(tx, TX_E_FAIL); -} - -static void -bna_tx_prio_changed(struct bna_tx *tx, int prio) -{ - struct bna_txq *txq; - struct list_head *qe; - - list_for_each(qe, &tx->txq_q) { - txq = (struct bna_txq *)qe; - txq->priority = prio; - } - - bfa_fsm_send_event(tx, TX_E_PRIO_CHANGE); -} - -static void -bna_tx_cee_link_status(struct bna_tx *tx, int cee_link) -{ - if (cee_link) - tx->flags |= BNA_TX_F_PRIO_LOCK; - else - tx->flags &= ~BNA_TX_F_PRIO_LOCK; -} - -static void -bna_tx_mod_cb_tx_stopped(void *arg, struct bna_tx *tx, - enum bna_cb_status status) -{ - struct bna_tx_mod *tx_mod = (struct bna_tx_mod *)arg; - - bfa_wc_down(&tx_mod->tx_stop_wc); -} - -static void -bna_tx_mod_cb_tx_stopped_all(void *arg) -{ - struct bna_tx_mod *tx_mod = (struct bna_tx_mod *)arg; - - if (tx_mod->stop_cbfn) - tx_mod->stop_cbfn(&tx_mod->bna->port, BNA_CB_SUCCESS); - tx_mod->stop_cbfn = NULL; -} - -void -bna_tx_res_req(int num_txq, int txq_depth, struct bna_res_info *res_info) -{ - u32 q_size; - u32 page_count; - struct bna_mem_info *mem_info; - - res_info[BNA_TX_RES_MEM_T_TCB].res_type = BNA_RES_T_MEM; - mem_info = &res_info[BNA_TX_RES_MEM_T_TCB].res_u.mem_info; - mem_info->mem_type = BNA_MEM_T_KVA; - mem_info->len = sizeof(struct bna_tcb); - mem_info->num = num_txq; - - q_size = txq_depth * BFI_TXQ_WI_SIZE; - q_size = ALIGN(q_size, PAGE_SIZE); - page_count = q_size >> PAGE_SHIFT; - - res_info[BNA_TX_RES_MEM_T_QPT].res_type = BNA_RES_T_MEM; - mem_info = &res_info[BNA_TX_RES_MEM_T_QPT].res_u.mem_info; - mem_info->mem_type = BNA_MEM_T_DMA; - mem_info->len = page_count * sizeof(struct bna_dma_addr); - mem_info->num = num_txq; - - res_info[BNA_TX_RES_MEM_T_SWQPT].res_type = BNA_RES_T_MEM; - mem_info = &res_info[BNA_TX_RES_MEM_T_SWQPT].res_u.mem_info; - mem_info->mem_type = BNA_MEM_T_KVA; - mem_info->len = page_count * sizeof(void *); - mem_info->num = num_txq; - - res_info[BNA_TX_RES_MEM_T_PAGE].res_type = BNA_RES_T_MEM; - mem_info = &res_info[BNA_TX_RES_MEM_T_PAGE].res_u.mem_info; - mem_info->mem_type = BNA_MEM_T_DMA; - mem_info->len = PAGE_SIZE; - mem_info->num = num_txq * page_count; - - res_info[BNA_TX_RES_INTR_T_TXCMPL].res_type = BNA_RES_T_INTR; - res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info.intr_type = - BNA_INTR_T_MSIX; - res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info.num = num_txq; -} - -struct bna_tx * -bna_tx_create(struct bna *bna, struct bnad *bnad, - struct bna_tx_config *tx_cfg, - struct bna_tx_event_cbfn *tx_cbfn, - struct bna_res_info *res_info, void *priv) -{ - struct bna_intr_info *intr_info; - struct bna_tx_mod *tx_mod = &bna->tx_mod; - struct bna_tx *tx; - struct bna_txq *txq; - struct list_head *qe; - struct bna_ib_mod *ib_mod = &bna->ib_mod; - struct bna_doorbell_qset *qset; - struct bna_ib_config ib_config; - int page_count; - int page_size; - int page_idx; - int i; - unsigned long off; - - intr_info = &res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info; - page_count = (res_info[BNA_TX_RES_MEM_T_PAGE].res_u.mem_info.num) / - tx_cfg->num_txq; - page_size = res_info[BNA_TX_RES_MEM_T_PAGE].res_u.mem_info.len; - - /** - * Get resources - */ - - if ((intr_info->num != 1) && (intr_info->num != tx_cfg->num_txq)) - return NULL; - - /* Tx */ - - if (list_empty(&tx_mod->tx_free_q)) - return NULL; - bfa_q_deq(&tx_mod->tx_free_q, &tx); - bfa_q_qe_init(&tx->qe); - - /* TxQs */ - - INIT_LIST_HEAD(&tx->txq_q); - for (i = 0; i < tx_cfg->num_txq; i++) { - if (list_empty(&tx_mod->txq_free_q)) - goto err_return; - - bfa_q_deq(&tx_mod->txq_free_q, &txq); - bfa_q_qe_init(&txq->qe); - list_add_tail(&txq->qe, &tx->txq_q); - txq->ib = NULL; - txq->ib_seg_offset = -1; - txq->tx = tx; - } - - /* IBs */ - i = 0; - list_for_each(qe, &tx->txq_q) { - txq = (struct bna_txq *)qe; - - if (intr_info->num == 1) - txq->ib = bna_ib_get(ib_mod, intr_info->intr_type, - intr_info->idl[0].vector); - else - txq->ib = bna_ib_get(ib_mod, intr_info->intr_type, - intr_info->idl[i].vector); - - if (txq->ib == NULL) - goto err_return; - - txq->ib_seg_offset = bna_ib_reserve_idx(txq->ib); - if (txq->ib_seg_offset == -1) - goto err_return; - - i++; - } - - /* - * Initialize - */ - - /* Tx */ - - tx->tcb_setup_cbfn = tx_cbfn->tcb_setup_cbfn; - tx->tcb_destroy_cbfn = tx_cbfn->tcb_destroy_cbfn; - /* Following callbacks are mandatory */ - tx->tx_stall_cbfn = tx_cbfn->tx_stall_cbfn; - tx->tx_resume_cbfn = tx_cbfn->tx_resume_cbfn; - tx->tx_cleanup_cbfn = tx_cbfn->tx_cleanup_cbfn; - - list_add_tail(&tx->qe, &tx_mod->tx_active_q); - tx->bna = bna; - tx->priv = priv; - tx->txq_stop_wc.wc_resume = bna_tx_cb_txq_stopped_all; - tx->txq_stop_wc.wc_cbarg = tx; - tx->txq_stop_wc.wc_count = 0; - - tx->type = tx_cfg->tx_type; - - tx->flags = 0; - if (tx->bna->tx_mod.flags & BNA_TX_MOD_F_PORT_STARTED) { - switch (tx->type) { - case BNA_TX_T_REGULAR: - if (!(tx->bna->tx_mod.flags & - BNA_TX_MOD_F_PORT_LOOPBACK)) - tx->flags |= BNA_TX_F_PORT_STARTED; - break; - case BNA_TX_T_LOOPBACK: - if (tx->bna->tx_mod.flags & BNA_TX_MOD_F_PORT_LOOPBACK) - tx->flags |= BNA_TX_F_PORT_STARTED; - break; - } - } - if (tx->bna->tx_mod.cee_link) - tx->flags |= BNA_TX_F_PRIO_LOCK; - - /* TxQ */ - - i = 0; - page_idx = 0; - list_for_each(qe, &tx->txq_q) { - txq = (struct bna_txq *)qe; - txq->priority = tx_mod->priority; - txq->tcb = (struct bna_tcb *) - res_info[BNA_TX_RES_MEM_T_TCB].res_u.mem_info.mdl[i].kva; - txq->tx_packets = 0; - txq->tx_bytes = 0; - - /* IB */ - - ib_config.coalescing_timeo = BFI_TX_COALESCING_TIMEO; - ib_config.interpkt_timeo = 0; /* Not used */ - ib_config.interpkt_count = BFI_TX_INTERPKT_COUNT; - ib_config.ctrl_flags = (BFI_IB_CF_INTER_PKT_DMA | - BFI_IB_CF_INT_ENABLE | - BFI_IB_CF_COALESCING_MODE); - bna_ib_config(txq->ib, &ib_config); - - /* TCB */ - - txq->tcb->producer_index = 0; - txq->tcb->consumer_index = 0; - txq->tcb->hw_consumer_index = (volatile u32 *) - ((volatile u8 *)txq->ib->ib_seg_host_addr_kva + - (txq->ib_seg_offset * BFI_IBIDX_SIZE)); - *(txq->tcb->hw_consumer_index) = 0; - txq->tcb->q_depth = tx_cfg->txq_depth; - txq->tcb->unmap_q = (void *) - res_info[BNA_TX_RES_MEM_T_UNMAPQ].res_u.mem_info.mdl[i].kva; - qset = (struct bna_doorbell_qset *)0; - off = (unsigned long)&qset[txq->txq_id].txq[0]; - txq->tcb->q_dbell = off + - BNA_GET_DOORBELL_BASE_ADDR(bna->pcidev.pci_bar_kva); - txq->tcb->i_dbell = &txq->ib->door_bell; - txq->tcb->intr_type = intr_info->intr_type; - txq->tcb->intr_vector = (intr_info->num == 1) ? - intr_info->idl[0].vector : - intr_info->idl[i].vector; - txq->tcb->txq = txq; - txq->tcb->bnad = bnad; - txq->tcb->id = i; - - /* QPT, SWQPT, Pages */ - bna_txq_qpt_setup(txq, page_count, page_size, - &res_info[BNA_TX_RES_MEM_T_QPT].res_u.mem_info.mdl[i], - &res_info[BNA_TX_RES_MEM_T_SWQPT].res_u.mem_info.mdl[i], - &res_info[BNA_TX_RES_MEM_T_PAGE]. - res_u.mem_info.mdl[page_idx]); - txq->tcb->page_idx = page_idx; - txq->tcb->page_count = page_count; - page_idx += page_count; - - /* Callback to bnad for setting up TCB */ - if (tx->tcb_setup_cbfn) - (tx->tcb_setup_cbfn)(bna->bnad, txq->tcb); - - i++; - } - - /* TxF */ - - tx->txf.ctrl_flags = BFI_TXF_CF_ENABLE | BFI_TXF_CF_VLAN_WI_BASED; - tx->txf.vlan = 0; - - /* Mbox element */ - bfa_q_qe_init(&tx->mbox_qe.qe); - - bfa_fsm_set_state(tx, bna_tx_sm_stopped); - - return tx; - -err_return: - bna_tx_free(tx); - return NULL; -} - -void -bna_tx_destroy(struct bna_tx *tx) -{ - /* Callback to bnad for destroying TCB */ - if (tx->tcb_destroy_cbfn) { - struct bna_txq *txq; - struct list_head *qe; - - list_for_each(qe, &tx->txq_q) { - txq = (struct bna_txq *)qe; - (tx->tcb_destroy_cbfn)(tx->bna->bnad, txq->tcb); - } - } - - bna_tx_free(tx); -} - -void -bna_tx_enable(struct bna_tx *tx) -{ - if (tx->fsm != (bfa_sm_t)bna_tx_sm_stopped) - return; - - tx->flags |= BNA_TX_F_ENABLED; - - if (tx->flags & BNA_TX_F_PORT_STARTED) - bfa_fsm_send_event(tx, TX_E_START); -} - -void -bna_tx_disable(struct bna_tx *tx, enum bna_cleanup_type type, - void (*cbfn)(void *, struct bna_tx *, enum bna_cb_status)) -{ - if (type == BNA_SOFT_CLEANUP) { - (*cbfn)(tx->bna->bnad, tx, BNA_CB_SUCCESS); - return; - } - - tx->stop_cbfn = cbfn; - tx->stop_cbarg = tx->bna->bnad; - - tx->flags &= ~BNA_TX_F_ENABLED; - - bfa_fsm_send_event(tx, TX_E_STOP); -} - -int -bna_tx_state_get(struct bna_tx *tx) -{ - return bfa_sm_to_state(tx_sm_table, tx->fsm); -} - -void -bna_tx_mod_init(struct bna_tx_mod *tx_mod, struct bna *bna, - struct bna_res_info *res_info) -{ - int i; - - tx_mod->bna = bna; - tx_mod->flags = 0; - - tx_mod->tx = (struct bna_tx *) - res_info[BNA_RES_MEM_T_TX_ARRAY].res_u.mem_info.mdl[0].kva; - tx_mod->txq = (struct bna_txq *) - res_info[BNA_RES_MEM_T_TXQ_ARRAY].res_u.mem_info.mdl[0].kva; - - INIT_LIST_HEAD(&tx_mod->tx_free_q); - INIT_LIST_HEAD(&tx_mod->tx_active_q); - - INIT_LIST_HEAD(&tx_mod->txq_free_q); - - for (i = 0; i < BFI_MAX_TXQ; i++) { - tx_mod->tx[i].txf.txf_id = i; - bfa_q_qe_init(&tx_mod->tx[i].qe); - list_add_tail(&tx_mod->tx[i].qe, &tx_mod->tx_free_q); - - tx_mod->txq[i].txq_id = i; - bfa_q_qe_init(&tx_mod->txq[i].qe); - list_add_tail(&tx_mod->txq[i].qe, &tx_mod->txq_free_q); - } - - tx_mod->tx_stop_wc.wc_resume = bna_tx_mod_cb_tx_stopped_all; - tx_mod->tx_stop_wc.wc_cbarg = tx_mod; - tx_mod->tx_stop_wc.wc_count = 0; -} - -void -bna_tx_mod_uninit(struct bna_tx_mod *tx_mod) -{ - struct list_head *qe; - int i; - - i = 0; - list_for_each(qe, &tx_mod->tx_free_q) - i++; - - i = 0; - list_for_each(qe, &tx_mod->txq_free_q) - i++; - - tx_mod->bna = NULL; -} - -void -bna_tx_mod_start(struct bna_tx_mod *tx_mod, enum bna_tx_type type) -{ - struct bna_tx *tx; - struct list_head *qe; - - tx_mod->flags |= BNA_TX_MOD_F_PORT_STARTED; - if (type == BNA_TX_T_LOOPBACK) - tx_mod->flags |= BNA_TX_MOD_F_PORT_LOOPBACK; - - list_for_each(qe, &tx_mod->tx_active_q) { - tx = (struct bna_tx *)qe; - if (tx->type == type) - bna_tx_start(tx); - } -} - -void -bna_tx_mod_stop(struct bna_tx_mod *tx_mod, enum bna_tx_type type) -{ - struct bna_tx *tx; - struct list_head *qe; - - tx_mod->flags &= ~BNA_TX_MOD_F_PORT_STARTED; - tx_mod->flags &= ~BNA_TX_MOD_F_PORT_LOOPBACK; - - tx_mod->stop_cbfn = bna_port_cb_tx_stopped; - - /** - * Before calling bna_tx_stop(), increment tx_stop_wc as many times - * as we are going to call bna_tx_stop - */ - list_for_each(qe, &tx_mod->tx_active_q) { - tx = (struct bna_tx *)qe; - if (tx->type == type) - bfa_wc_up(&tx_mod->tx_stop_wc); - } - - if (tx_mod->tx_stop_wc.wc_count == 0) { - tx_mod->stop_cbfn(&tx_mod->bna->port, BNA_CB_SUCCESS); - tx_mod->stop_cbfn = NULL; - return; - } - - list_for_each(qe, &tx_mod->tx_active_q) { - tx = (struct bna_tx *)qe; - if (tx->type == type) - bna_tx_stop(tx); - } -} - -void -bna_tx_mod_fail(struct bna_tx_mod *tx_mod) -{ - struct bna_tx *tx; - struct list_head *qe; - - tx_mod->flags &= ~BNA_TX_MOD_F_PORT_STARTED; - tx_mod->flags &= ~BNA_TX_MOD_F_PORT_LOOPBACK; - - list_for_each(qe, &tx_mod->tx_active_q) { - tx = (struct bna_tx *)qe; - bna_tx_fail(tx); - } -} - -void -bna_tx_mod_prio_changed(struct bna_tx_mod *tx_mod, int prio) -{ - struct bna_tx *tx; - struct list_head *qe; - - if (prio != tx_mod->priority) { - tx_mod->priority = prio; - - list_for_each(qe, &tx_mod->tx_active_q) { - tx = (struct bna_tx *)qe; - bna_tx_prio_changed(tx, prio); - } - } -} - -void -bna_tx_mod_cee_link_status(struct bna_tx_mod *tx_mod, int cee_link) -{ - struct bna_tx *tx; - struct list_head *qe; - - tx_mod->cee_link = cee_link; - - list_for_each(qe, &tx_mod->tx_active_q) { - tx = (struct bna_tx *)qe; - bna_tx_cee_link_status(tx, cee_link); - } -} |
