diff options
Diffstat (limited to 'drivers/media')
| -rw-r--r-- | drivers/media/dvb/frontends/s5h1432.c | 45 | ||||
| -rw-r--r-- | drivers/media/dvb/frontends/s5h1432.h | 43 | ||||
| -rw-r--r-- | drivers/media/video/cx231xx/cx231xx-417.c | 675 | ||||
| -rw-r--r-- | drivers/media/video/cx231xx/cx231xx-avcore.c | 135 | ||||
| -rw-r--r-- | drivers/media/video/cx231xx/cx231xx-dif.h | 34 | ||||
| -rw-r--r-- | drivers/media/video/cx231xx/cx231xx.h | 12 |
6 files changed, 461 insertions, 483 deletions
diff --git a/drivers/media/dvb/frontends/s5h1432.c b/drivers/media/dvb/frontends/s5h1432.c index 5fc3bf5f1c0b..0c6dcb90d168 100644 --- a/drivers/media/dvb/frontends/s5h1432.c +++ b/drivers/media/dvb/frontends/s5h1432.c @@ -1,23 +1,22 @@ /* - Samsung s5h1432 DVB-T demodulator driver - - Copyright (C) 2009 Bill Liu <Bill.Liu@Conexant.com> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - -*/ + * Samsung s5h1432 DVB-T demodulator driver + * + * Copyright (C) 2009 Bill Liu <Bill.Liu@Conexant.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ #include <linux/kernel.h> #include <linux/init.h> @@ -162,7 +161,7 @@ static int s5h1432_set_IF(struct dvb_frontend *fe, u32 ifFreqHz) value = (u32) (((48000 - (ifFreqHz / 1000)) * 512 * (u32) 32768) / (48 * 1000)); printk(KERN_INFO - "Default IFFreq %d :reg value = 0x%x \n", + "Default IFFreq %d :reg value = 0x%x\n", ifFreqHz, value); s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, (u8) value & 0xFF); @@ -379,7 +378,6 @@ error: kfree(state); return NULL; } - EXPORT_SYMBOL(s5h1432_attach); static struct dvb_frontend_ops s5h1432_ops = { @@ -415,8 +413,3 @@ MODULE_PARM_DESC(debug, "Enable verbose debug messages"); MODULE_DESCRIPTION("Samsung s5h1432 DVB-T Demodulator driver"); MODULE_AUTHOR("Bill Liu"); MODULE_LICENSE("GPL"); - -/* - * Local variables: - * c-basic-offset: 8 - */ diff --git a/drivers/media/dvb/frontends/s5h1432.h b/drivers/media/dvb/frontends/s5h1432.h index 6ed654fb9b16..b57438c32546 100644 --- a/drivers/media/dvb/frontends/s5h1432.h +++ b/drivers/media/dvb/frontends/s5h1432.h @@ -1,23 +1,23 @@ /* - Samsung s5h1432 VSB/QAM demodulator driver - - Copyright (C) 2009 Bill Liu <Bill.Liu@Conexant.com> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - -*/ + * Samsung s5h1432 VSB/QAM demodulator driver + * + * Copyright (C) 2009 Bill Liu <Bill.Liu@Conexant.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ #ifndef __S5H1432_H__ #define __S5H1432_H__ @@ -89,8 +89,3 @@ static inline struct dvb_frontend *s5h1432_attach(const struct s5h1432_config #endif /* CONFIG_DVB_s5h1432 */ #endif /* __s5h1432_H__ */ - -/* - * Local variables: - * c-basic-offset: 8 - */ diff --git a/drivers/media/video/cx231xx/cx231xx-417.c b/drivers/media/video/cx231xx/cx231xx-417.c index 6fb2d1743569..a5b1b13d1fd6 100644 --- a/drivers/media/video/cx231xx/cx231xx-417.c +++ b/drivers/media/video/cx231xx/cx231xx-417.c @@ -43,7 +43,7 @@ #define CX231xx_FIRM_IMAGE_SIZE 376836 #define CX231xx_FIRM_IMAGE_NAME "v4l-cx23885-enc.fw" -/* for polaris ITVC*/ +/* for polaris ITVC */ #define ITVC_WRITE_DIR 0x03FDFC00 #define ITVC_READ_DIR 0x0001FC00 @@ -66,8 +66,7 @@ #define MCI_REGISTER_MODE 0x70 -/*Read and write modes - for polaris ITVC*/ +/* Read and write modes for polaris ITVC */ #define MCI_MODE_REGISTER_READ 0x000 #define MCI_MODE_REGISTER_WRITE 0x100 #define MCI_MODE_MEMORY_READ 0x000 @@ -250,20 +249,22 @@ enum cx231xx_mute_video_shift { #define IVTV_REG_VPU (0x9058) #define IVTV_REG_APU (0xA064) -/**** Bit definitions for MC417_RWD and MC417_OEN registers *** - bits 31-16 -+-----------+ -| Reserved | -+-----------+ - bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 -+-------+-------+-------+-------+-------+-------+-------+-------+ -| MIWR# | MIRD# | MICS# |MIRDY# |MIADDR3|MIADDR2|MIADDR1|MIADDR0| -+-------+-------+-------+-------+-------+-------+-------+-------+ - bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 -+-------+-------+-------+-------+-------+-------+-------+-------+ -|MIDATA7|MIDATA6|MIDATA5|MIDATA4|MIDATA3|MIDATA2|MIDATA1|MIDATA0| -+-------+-------+-------+-------+-------+-------+-------+-------+ -***/ +/* + * Bit definitions for MC417_RWD and MC417_OEN registers + * + * bits 31-16 + *+-----------+ + *| Reserved | + *|+-----------+ + *| bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 + *|+-------+-------+-------+-------+-------+-------+-------+-------+ + *|| MIWR# | MIRD# | MICS# |MIRDY# |MIADDR3|MIADDR2|MIADDR1|MIADDR0| + *|+-------+-------+-------+-------+-------+-------+-------+-------+ + *| bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 + *|+-------+-------+-------+-------+-------+-------+-------+-------+ + *||MIDATA7|MIDATA6|MIDATA5|MIDATA4|MIDATA3|MIDATA2|MIDATA1|MIDATA0| + *|+-------+-------+-------+-------+-------+-------+-------+-------+ + */ #define MC417_MIWR 0x8000 #define MC417_MIRD 0x4000 #define MC417_MICS 0x2000 @@ -272,12 +273,12 @@ enum cx231xx_mute_video_shift { #define MC417_MIDATA 0x00FF -/*** Bit definitions for MC417_CTL register **** - bits 31-6 bits 5-4 bit 3 bits 2-1 Bit 0 -+--------+-------------+--------+--------------+------------+ -|Reserved|MC417_SPD_CTL|Reserved|MC417_GPIO_SEL|UART_GPIO_EN| -+--------+-------------+--------+--------------+------------+ -***/ +/* Bit definitions for MC417_CTL register **** + *bits 31-6 bits 5-4 bit 3 bits 2-1 Bit 0 + *+--------+-------------+--------+--------------+------------+ + *|Reserved|MC417_SPD_CTL|Reserved|MC417_GPIO_SEL|UART_GPIO_EN| + *+--------+-------------+--------+--------------+------------+ + */ #define MC417_SPD_CTL(x) (((x) << 4) & 0x00000030) #define MC417_GPIO_SEL(x) (((x) << 1) & 0x00000006) #define MC417_UART_GPIO_EN 0x00000001 @@ -320,299 +321,294 @@ int getITVCReg(struct cx231xx *dev, u32 gpio_direction, u32 *pValue) } int waitForMciComplete(struct cx231xx *dev) { - u32 gpio; - u32 gpio_driection = 0; - u8 count = 0; - getITVCReg(dev, gpio_driection, &gpio); + u32 gpio; + u32 gpio_driection = 0; + u8 count = 0; + getITVCReg(dev, gpio_driection, &gpio); - while (!(gpio&0x020000)) { - msleep(10); + while (!(gpio&0x020000)) { + msleep(10); - getITVCReg(dev, gpio_driection, &gpio); + getITVCReg(dev, gpio_driection, &gpio); - if (count++ > 100) { - dprintk(3, "ERROR: Timeout - gpio=%x\n", gpio); - return -1; + if (count++ > 100) { + dprintk(3, "ERROR: Timeout - gpio=%x\n", gpio); + return -1; + } } - } return 0; } + int mc417_register_write(struct cx231xx *dev, u16 address, u32 value) { - u32 temp; + u32 temp; int status = 0; - temp = 0x82|MCI_REGISTER_DATA_BYTE0|((value&0x000000FF)<<8); - temp = temp<<10; - status = setITVCReg(dev, ITVC_WRITE_DIR, temp); + temp = 0x82|MCI_REGISTER_DATA_BYTE0|((value&0x000000FF)<<8); + temp = temp<<10; + status = setITVCReg(dev, ITVC_WRITE_DIR, temp); if (status < 0) return status; - temp = temp|((0x05)<<10); - setITVCReg(dev, ITVC_WRITE_DIR, temp); - - /*write data byte 1;*/ - temp = 0x82|MCI_REGISTER_DATA_BYTE1|(value&0x0000FF00); - temp = temp<<10; - setITVCReg(dev, ITVC_WRITE_DIR, temp); - temp = temp|((0x05)<<10); - setITVCReg(dev, ITVC_WRITE_DIR, temp); - - /*write data byte 2;*/ - temp = 0x82|MCI_REGISTER_DATA_BYTE2|((value&0x00FF0000)>>8); - temp = temp<<10; - setITVCReg(dev, ITVC_WRITE_DIR, temp); - temp = temp|((0x05)<<10); - setITVCReg(dev, ITVC_WRITE_DIR, temp); - - /*write data byte 3;*/ - temp = 0x82|MCI_REGISTER_DATA_BYTE3|((value&0xFF000000)>>16); - temp = temp<<10; - setITVCReg(dev, ITVC_WRITE_DIR, temp); - temp = temp|((0x05)<<10); - setITVCReg(dev, ITVC_WRITE_DIR, temp); - - /*write address byte 0;*/ - temp = 0x82|MCI_REGISTER_ADDRESS_BYTE0|((address&0x000000FF)<<8); - temp = temp<<10; - setITVCReg(dev, ITVC_WRITE_DIR, temp); - temp = temp|((0x05)<<10); - setITVCReg(dev, ITVC_WRITE_DIR, temp); - - /*write address byte 1;*/ - temp = 0x82|MCI_REGISTER_ADDRESS_BYTE1|(address&0x0000FF00); - temp = temp<<10; - setITVCReg(dev, ITVC_WRITE_DIR, temp); - temp = temp|((0x05)<<10); - setITVCReg(dev, ITVC_WRITE_DIR, temp); - - /*Write that the mode is write.*/ - temp = 0x82 | MCI_REGISTER_MODE | MCI_MODE_REGISTER_WRITE; - temp = temp<<10; - setITVCReg(dev, ITVC_WRITE_DIR, temp); - temp = temp|((0x05)<<10); - setITVCReg(dev, ITVC_WRITE_DIR, temp); - - return waitForMciComplete(dev); - + temp = temp|((0x05)<<10); + setITVCReg(dev, ITVC_WRITE_DIR, temp); + + /*write data byte 1;*/ + temp = 0x82|MCI_REGISTER_DATA_BYTE1|(value&0x0000FF00); + temp = temp<<10; + setITVCReg(dev, ITVC_WRITE_DIR, temp); + temp = temp|((0x05)<<10); + setITVCReg(dev, ITVC_WRITE_DIR, temp); + + /*write data byte 2;*/ + temp = 0x82|MCI_REGISTER_DATA_BYTE2|((value&0x00FF0000)>>8); + temp = temp<<10; + setITVCReg(dev, ITVC_WRITE_DIR, temp); + temp = temp|((0x05)<<10); + setITVCReg(dev, ITVC_WRITE_DIR, temp); + + /*write data byte 3;*/ + temp = 0x82|MCI_REGISTER_DATA_BYTE3|((value&0xFF000000)>>16); + temp = temp<<10; + setITVCReg(dev, ITVC_WRITE_DIR, temp); + temp = temp|((0x05)<<10); + setITVCReg(dev, ITVC_WRITE_DIR, temp); + + /*write address byte 0;*/ + temp = 0x82|MCI_REGISTER_ADDRESS_BYTE0|((address&0x000000FF)<<8); + temp = temp<<10; + setITVCReg(dev, ITVC_WRITE_DIR, temp); + temp = temp|((0x05)<<10); + setITVCReg(dev, ITVC_WRITE_DIR, temp); + + /*write address byte 1;*/ + temp = 0x82|MCI_REGISTER_ADDRESS_BYTE1|(address&0x0000FF00); + temp = temp<<10; + setITVCReg(dev, ITVC_WRITE_DIR, temp); + temp = temp|((0x05)<<10); + setITVCReg(dev, ITVC_WRITE_DIR, temp); + + /*Write that the mode is write.*/ + temp = 0x82 | MCI_REGISTER_MODE | MCI_MODE_REGISTER_WRITE; + temp = temp<<10; + setITVCReg(dev, ITVC_WRITE_DIR, temp); + temp = temp|((0x05)<<10); + setITVCReg(dev, ITVC_WRITE_DIR, temp); + + return waitForMciComplete(dev); } - int mc417_register_read(struct cx231xx *dev, u16 address, u32 *value) { - /*write address byte 0;*/ - u32 temp; - u32 return_value = 0; + /*write address byte 0;*/ + u32 temp; + u32 return_value = 0; int ret = 0; - temp = 0x82|MCI_REGISTER_ADDRESS_BYTE0|((address&0x00FF)<<8); - temp = temp<<10; - setITVCReg(dev, ITVC_WRITE_DIR, temp); - temp = temp|((0x05)<<10); - setITVCReg(dev, ITVC_WRITE_DIR, temp); - - /*write address byte 1;*/ - temp = 0x82|MCI_REGISTER_ADDRESS_BYTE1|(address&0xFF00); - temp = temp<<10; - setITVCReg(dev, ITVC_WRITE_DIR, temp); - temp = temp|((0x05)<<10); - setITVCReg(dev, ITVC_WRITE_DIR, temp); - - /*write that the mode is read;*/ - temp = 0x82 | MCI_REGISTER_MODE | MCI_MODE_REGISTER_READ; - temp = temp<<10; - setITVCReg(dev, ITVC_WRITE_DIR, temp); - temp = temp|((0x05)<<10); - setITVCReg(dev, ITVC_WRITE_DIR, temp); - - /*wait for the MIRDY line to be asserted , - signalling that the read is done;*/ - ret = waitForMciComplete(dev); - - - /*switch the DATA- GPIO to input mode;*/ - - /*Read data byte 0;*/ - temp = (0x82|MCI_REGISTER_DATA_BYTE0)<<10; - setITVCReg(dev, ITVC_READ_DIR, temp); - temp = ((0x81|MCI_REGISTER_DATA_BYTE0)<<10); - setITVCReg(dev, ITVC_READ_DIR, temp); - getITVCReg(dev, ITVC_READ_DIR, &temp); - return_value |= ((temp&0x03FC0000)>>18); - setITVCReg(dev, ITVC_READ_DIR, (0x87<<10)); - - /* Read data byte 1;*/ - temp = (0x82|MCI_REGISTER_DATA_BYTE1)<<10; - setITVCReg(dev, ITVC_READ_DIR, temp); - temp = ((0x81|MCI_REGISTER_DATA_BYTE1)<<10); - setITVCReg(dev, ITVC_READ_DIR, temp); - getITVCReg(dev, ITVC_READ_DIR, &temp); - - return_value |= ((temp&0x03FC0000)>>10); - setITVCReg(dev, ITVC_READ_DIR, (0x87<<10)); - - /*Read data byte 2;*/ - temp = (0x82|MCI_REGISTER_DATA_BYTE2)<<10; - setITVCReg(dev, ITVC_READ_DIR, temp); - temp = ((0x81|MCI_REGISTER_DATA_BYTE2)<<10); - setITVCReg(dev, ITVC_READ_DIR, temp); - getITVCReg(dev, ITVC_READ_DIR, &temp); - return_value |= ((temp&0x03FC0000)>>2); - setITVCReg(dev, ITVC_READ_DIR, (0x87<<10)); - - /*Read data byte 3;*/ - temp = (0x82|MCI_REGISTER_DATA_BYTE3)<<10; - setITVCReg(dev, ITVC_READ_DIR, temp); - temp = ((0x81|MCI_REGISTER_DATA_BYTE3)<<10); - setITVCReg(dev, ITVC_READ_DIR, temp); - getITVCReg(dev, ITVC_READ_DIR, &temp); - return_value |= ((temp&0x03FC0000)<<6); - setITVCReg(dev, ITVC_READ_DIR, (0x87<<10)); + temp = 0x82 | MCI_REGISTER_ADDRESS_BYTE0 | ((address & 0x00FF) << 8); + temp = temp << 10; + setITVCReg(dev, ITVC_WRITE_DIR, temp); + temp = temp | ((0x05) << 10); + setITVCReg(dev, ITVC_WRITE_DIR, temp); + + /*write address byte 1;*/ + temp = 0x82 | MCI_REGISTER_ADDRESS_BYTE1 | (address & 0xFF00); + temp = temp << 10; + setITVCReg(dev, ITVC_WRITE_DIR, temp); + temp = temp | ((0x05) << 10); + setITVCReg(dev, ITVC_WRITE_DIR, temp); + + /*write that the mode is read;*/ + temp = 0x82 | MCI_REGISTER_MODE | MCI_MODE_REGISTER_READ; + temp = temp << 10; + setITVCReg(dev, ITVC_WRITE_DIR, temp); + temp = temp | ((0x05) << 10); + setITVCReg(dev, ITVC_WRITE_DIR, temp); + + /*wait for the MIRDY line to be asserted , + signalling that the read is done;*/ + ret = waitForMciComplete(dev); + + /*switch the DATA- GPIO to input mode;*/ + + /*Read data byte 0;*/ + temp = (0x82 | MCI_REGISTER_DATA_BYTE0) << 10; + setITVCReg(dev, ITVC_READ_DIR, temp); + temp = ((0x81 | MCI_REGISTER_DATA_BYTE0) << 10); + setITVCReg(dev, ITVC_READ_DIR, temp); + getITVCReg(dev, ITVC_READ_DIR, &temp); + return_value |= ((temp & 0x03FC0000) >> 18); + setITVCReg(dev, ITVC_READ_DIR, (0x87 << 10)); + + /* Read data byte 1;*/ + temp = (0x82 | MCI_REGISTER_DATA_BYTE1) << 10; + setITVCReg(dev, ITVC_READ_DIR, temp); + temp = ((0x81 | MCI_REGISTER_DATA_BYTE1) << 10); + setITVCReg(dev, ITVC_READ_DIR, temp); + getITVCReg(dev, ITVC_READ_DIR, &temp); + + return_value |= ((temp & 0x03FC0000) >> 10); + setITVCReg(dev, ITVC_READ_DIR, (0x87 << 10)); + + /*Read data byte 2;*/ + temp = (0x82 | MCI_REGISTER_DATA_BYTE2) << 10; + setITVCReg(dev, ITVC_READ_DIR, temp); + temp = ((0x81 | MCI_REGISTER_DATA_BYTE2) << 10); + setITVCReg(dev, ITVC_READ_DIR, temp); + getITVCReg(dev, ITVC_READ_DIR, &temp); + return_value |= ((temp & 0x03FC0000) >> 2); + setITVCReg(dev, ITVC_READ_DIR, (0x87 << 10)); + + /*Read data byte 3;*/ + temp = (0x82 | MCI_REGISTER_DATA_BYTE3) << 10; + setITVCReg(dev, ITVC_READ_DIR, temp); + temp = ((0x81 | MCI_REGISTER_DATA_BYTE3) << 10); + setITVCReg(dev, ITVC_READ_DIR, temp); + getITVCReg(dev, ITVC_READ_DIR, &temp); + return_value |= ((temp & 0x03FC0000) << 6); + setITVCReg(dev, ITVC_READ_DIR, (0x87 << 10)); *value = return_value; - return ret; + return ret; } int mc417_memory_write(struct cx231xx *dev, u32 address, u32 value) { + /*write data byte 0;*/ - /*write data byte 0;*/ - - u32 temp; + u32 temp; int ret = 0; - temp = 0x82|MCI_MEMORY_DATA_BYTE0|((value&0x000000FF)<<8); - temp = temp<<10; - ret = setITVCReg(dev, ITVC_WRITE_DIR, temp); + temp = 0x82 | MCI_MEMORY_DATA_BYTE0|((value & 0x000000FF) << 8); + temp = temp << 10; + ret = setITVCReg(dev, ITVC_WRITE_DIR, temp); if (ret < 0) return ret; - temp = temp|((0x05)<<10); - setITVCReg(dev, ITVC_WRITE_DIR, temp); - - /*write data byte 1;*/ - temp = 0x82|MCI_MEMORY_DATA_BYTE1|(value&0x0000FF00); - temp = temp<<10; - setITVCReg(dev, ITVC_WRITE_DIR, temp); - temp = temp|((0x05)<<10); - setITVCReg(dev, ITVC_WRITE_DIR, temp); - - /*write data byte 2;*/ - temp = 0x82|MCI_MEMORY_DATA_BYTE2|((value&0x00FF0000)>>8); - temp = temp<<10; - setITVCReg(dev, ITVC_WRITE_DIR, temp); - temp = temp|((0x05)<<10); - setITVCReg(dev, ITVC_WRITE_DIR, temp); - - /*write data byte 3;*/ - temp = 0x82|MCI_MEMORY_DATA_BYTE3|((value&0xFF000000)>>16); - temp = temp<<10; - setITVCReg(dev, ITVC_WRITE_DIR, temp); - temp = temp|((0x05)<<10); - setITVCReg(dev, ITVC_WRITE_DIR, temp); - - /* write address byte 2;*/ - temp = 0x82|MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_WRITE | + temp = temp | ((0x05) << 10); + setITVCReg(dev, ITVC_WRITE_DIR, temp); + + /*write data byte 1;*/ + temp = 0x82 | MCI_MEMORY_DATA_BYTE1 | (value & 0x0000FF00); + temp = temp << 10; + setITVCReg(dev, ITVC_WRITE_DIR, temp); + temp = temp | ((0x05) << 10); + setITVCReg(dev, ITVC_WRITE_DIR, temp); + + /*write data byte 2;*/ + temp = 0x82|MCI_MEMORY_DATA_BYTE2|((value&0x00FF0000)>>8); + temp = temp<<10; + setITVCReg(dev, ITVC_WRITE_DIR, temp); + temp = temp|((0x05)<<10); + setITVCReg(dev, ITVC_WRITE_DIR, temp); + + /*write data byte 3;*/ + temp = 0x82|MCI_MEMORY_DATA_BYTE3|((value&0xFF000000)>>16); + temp = temp<<10; + setITVCReg(dev, ITVC_WRITE_DIR, temp); + temp = temp|((0x05)<<10); + setITVCReg(dev, ITVC_WRITE_DIR, temp); + + /* write address byte 2;*/ + temp = 0x82|MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_WRITE | ((address & 0x003F0000)>>8); - temp = temp<<10; - setITVCReg(dev, ITVC_WRITE_DIR, temp); - temp = temp|((0x05)<<10); - setITVCReg(dev, ITVC_WRITE_DIR, temp); - - /* write address byte 1;*/ - temp = 0x82|MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00); - temp = temp<<10; - setITVCReg(dev, ITVC_WRITE_DIR, temp); - temp = temp|((0x05)<<10); - setITVCReg(dev, ITVC_WRITE_DIR, temp); - - /* write address byte 0;*/ - temp = 0x82|MCI_MEMORY_ADDRESS_BYTE0|((address & 0x00FF)<<8); - temp = temp<<10; - setITVCReg(dev, ITVC_WRITE_DIR, temp); - temp = temp|((0x05)<<10); - setITVCReg(dev, ITVC_WRITE_DIR, temp); - - /*wait for MIRDY line;*/ - waitForMciComplete(dev); - -return 0; + temp = temp<<10; + setITVCReg(dev, ITVC_WRITE_DIR, temp); + temp = temp|((0x05)<<10); + setITVCReg(dev, ITVC_WRITE_DIR, temp); + + /* write address byte 1;*/ + temp = 0x82|MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00); + temp = temp<<10; + setITVCReg(dev, ITVC_WRITE_DIR, temp); + temp = temp|((0x05)<<10); + setITVCReg(dev, ITVC_WRITE_DIR, temp); + + /* write address byte 0;*/ + temp = 0x82|MCI_MEMORY_ADDRESS_BYTE0|((address & 0x00FF)<<8); + temp = temp<<10; + setITVCReg(dev, ITVC_WRITE_DIR, temp); + temp = temp|((0x05)<<10); + setITVCReg(dev, ITVC_WRITE_DIR, temp); + + /*wait for MIRDY line;*/ + waitForMciComplete(dev); + return 0; } int mc417_memory_read(struct cx231xx *dev, u32 address, u32 *value) { - - u32 temp = 0; - u32 return_value = 0; + u32 temp = 0; + u32 return_value = 0; int ret = 0; - /*write address byte 2;*/ - temp = 0x82|MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_READ | + /*write address byte 2;*/ + temp = 0x82|MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_READ | ((address & 0x003F0000)>>8); - temp = temp<<10; - ret = setITVCReg(dev, ITVC_WRITE_DIR, temp); + temp = temp<<10; + ret = setITVCReg(dev, ITVC_WRITE_DIR, temp); if (ret < 0) return ret; - temp = temp|((0x05)<<10); - setITVCReg(dev, ITVC_WRITE_DIR, temp); - - /*write address byte 1*/ - temp = 0x82|MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00); - temp = temp<<10; - setITVCReg(dev, ITVC_WRITE_DIR, temp); - temp = temp|((0x05)<<10); - setITVCReg(dev, ITVC_WRITE_DIR, temp); - - /*write address byte 0*/ - temp = 0x82|MCI_MEMORY_ADDRESS_BYTE0 | ((address & 0x00FF)<<8); - temp = temp<<10; - setITVCReg(dev, ITVC_WRITE_DIR, temp); - temp = temp|((0x05)<<10); - setITVCReg(dev, ITVC_WRITE_DIR, temp); - - /*Wait for MIRDY line*/ - ret = waitForMciComplete(dev); - - - /*Read data byte 3;*/ - temp = (0x82|MCI_MEMORY_DATA_BYTE3)<<10; - setITVCReg(dev, ITVC_READ_DIR, temp); - temp = ((0x81|MCI_MEMORY_DATA_BYTE3)<<10); - setITVCReg(dev, ITVC_READ_DIR, temp); - getITVCReg(dev, ITVC_READ_DIR, &temp); - return_value |= ((temp&0x03FC0000)<<6); - setITVCReg(dev, ITVC_READ_DIR, (0x87<<10)); - - /*Read data byte 2;*/ - temp = (0x82|MCI_MEMORY_DATA_BYTE2)<<10; - setITVCReg(dev, ITVC_READ_DIR, temp); - temp = ((0x81|MCI_MEMORY_DATA_BYTE2)<<10); - setITVCReg(dev, ITVC_READ_DIR, temp); - getITVCReg(dev, ITVC_READ_DIR, &temp); - return_value |= ((temp&0x03FC0000)>>2); - setITVCReg(dev, ITVC_READ_DIR, (0x87<<10)); - - /* Read data byte 1;*/ - temp = (0x82|MCI_MEMORY_DATA_BYTE1)<<10; - setITVCReg(dev, ITVC_READ_DIR, temp); - temp = ((0x81|MCI_MEMORY_DATA_BYTE1)<<10); - setITVCReg(dev, ITVC_READ_DIR, temp); - getITVCReg(dev, ITVC_READ_DIR, &temp); - return_value |= ((temp&0x03FC0000)>>10); - setITVCReg(dev, ITVC_READ_DIR, (0x87<<10)); - - /*Read data byte 0;*/ - temp = (0x82|MCI_MEMORY_DATA_BYTE0)<<10; - setITVCReg(dev, ITVC_READ_DIR, temp); - temp = ((0x81|MCI_MEMORY_DATA_BYTE0)<<10); - setITVCReg(dev, ITVC_READ_DIR, temp); - getITVCReg(dev, ITVC_READ_DIR, &temp); - return_value |= ((temp&0x03FC0000)>>18); - setITVCReg(dev, ITVC_READ_DIR, (0x87<<10)); + temp = temp|((0x05)<<10); + setITVCReg(dev, ITVC_WRITE_DIR, temp); + + /*write address byte 1*/ + temp = 0x82|MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00); + temp = temp<<10; + setITVCReg(dev, ITVC_WRITE_DIR, temp); + temp = temp|((0x05)<<10); + setITVCReg(dev, ITVC_WRITE_DIR, temp); + + /*write address byte 0*/ + temp = 0x82|MCI_MEMORY_ADDRESS_BYTE0 | ((address & 0x00FF)<<8); + temp = temp<<10; + setITVCReg(dev, ITVC_WRITE_DIR, temp); + temp = temp|((0x05)<<10); + setITVCReg(dev, ITVC_WRITE_DIR, temp); + + /*Wait for MIRDY line*/ + ret = waitForMciComplete(dev); + + + /*Read data byte 3;*/ + temp = (0x82|MCI_MEMORY_DATA_BYTE3)<<10; + setITVCReg(dev, ITVC_READ_DIR, temp); + temp = ((0x81|MCI_MEMORY_DATA_BYTE3)<<10); + setITVCReg(dev, ITVC_READ_DIR, temp); + getITVCReg(dev, ITVC_READ_DIR, &temp); + return_value |= ((temp&0x03FC0000)<<6); + setITVCReg(dev, ITVC_READ_DIR, (0x87<<10)); + + /*Read data byte 2;*/ + temp = (0x82|MCI_MEMORY_DATA_BYTE2)<<10; + setITVCReg(dev, ITVC_READ_DIR, temp); + temp = ((0x81|MCI_MEMORY_DATA_BYTE2)<<10); + setITVCReg(dev, ITVC_READ_DIR, temp); + getITVCReg(dev, ITVC_READ_DIR, &temp); + return_value |= ((temp&0x03FC0000)>>2); + setITVCReg(dev, ITVC_READ_DIR, (0x87<<10)); + + /* Read data byte 1;*/ + temp = (0x82|MCI_MEMORY_DATA_BYTE1)<<10; + setITVCReg(dev, ITVC_READ_DIR, temp); + temp = ((0x81|MCI_MEMORY_DATA_BYTE1)<<10); + setITVCReg(dev, ITVC_READ_DIR, temp); + getITVCReg(dev, ITVC_READ_DIR, &temp); + return_value |= ((temp&0x03FC0000)>>10); + setITVCReg(dev, ITVC_READ_DIR, (0x87<<10)); + + /*Read data byte 0;*/ + temp = (0x82|MCI_MEMORY_DATA_BYTE0)<<10; + setITVCReg(dev, ITVC_READ_DIR, temp); + temp = ((0x81|MCI_MEMORY_DATA_BYTE0)<<10); + setITVCReg(dev, ITVC_READ_DIR, temp); + getITVCReg(dev, ITVC_READ_DIR, &temp); + return_value |= ((temp&0x03FC0000)>>18); + setITVCReg(dev, ITVC_READ_DIR, (0x87<<10)); *value = return_value; - return ret; + return ret; } void mc417_gpio_set(struct cx231xx *dev, u32 mask) @@ -884,74 +880,73 @@ void mciWriteMemoryToGPIO(struct cx231xx *dev, u32 address, u32 value, u32 temp = 0; int i = 0; - temp = 0x82|MCI_MEMORY_DATA_BYTE0|((value&0x000000FF)<<8); - temp = temp<<10; - *p_fw_image = temp; - p_fw_image++; - temp = temp|((0x05)<<10); - *p_fw_image = temp; - p_fw_image++; - - /*write data byte 1;*/ - temp = 0x82|MCI_MEMORY_DATA_BYTE1|(value&0x0000FF00); - temp = temp<<10; - *p_fw_image = temp; - p_fw_image++; - temp = temp|((0x05)<<10); - *p_fw_image = temp; - p_fw_image++; - - /*write data byte 2;*/ - temp = 0x82|MCI_MEMORY_DATA_BYTE2|((value&0x00FF0000)>>8); - temp = temp<<10; - *p_fw_image = temp; - p_fw_image++; - temp = temp|((0x05)<<10); - *p_fw_image = temp; - p_fw_image++; - - /*write data byte 3;*/ - temp = 0x82|MCI_MEMORY_DATA_BYTE3|((value&0xFF000000)>>16); - temp = temp<<10; - *p_fw_image = temp; - p_fw_image++; - temp = temp|((0x05)<<10); - *p_fw_image = temp; - p_fw_image++; - - /* write address byte 2;*/ - temp = 0x82|MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_WRITE | - ((address & 0x003F0000)>>8); - temp = temp<<10; - *p_fw_image = temp; - p_fw_image++; - temp = temp|((0x05)<<10); - *p_fw_image = temp; - p_fw_image++; - - /* write address byte 1;*/ - temp = 0x82|MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00); - temp = temp<<10; - *p_fw_image = temp; - p_fw_image++; - temp = temp|((0x05)<<10); - *p_fw_image = temp; - p_fw_image++; - - /* write address byte 0;*/ - temp = 0x82|MCI_MEMORY_ADDRESS_BYTE0|((address & 0x00FF)<<8); - temp = temp<<10; - *p_fw_image = temp; - p_fw_image++; - temp = temp|((0x05)<<10); - *p_fw_image = temp; - p_fw_image++; - - for (i = 0; i < 6; i++) { - *p_fw_image = 0xFFFFFFFF; + temp = 0x82|MCI_MEMORY_DATA_BYTE0|((value&0x000000FF)<<8); + temp = temp<<10; + *p_fw_image = temp; + p_fw_image++; + temp = temp|((0x05)<<10); + *p_fw_image = temp; p_fw_image++; - } + /*write data byte 1;*/ + temp = 0x82|MCI_MEMORY_DATA_BYTE1|(value&0x0000FF00); + temp = temp<<10; + *p_fw_image = temp; + p_fw_image++; + temp = temp|((0x05)<<10); + *p_fw_image = temp; + p_fw_image++; + + /*write data byte 2;*/ + temp = 0x82|MCI_MEMORY_DATA_BYTE2|((value&0x00FF0000)>>8); + temp = temp<<10; + *p_fw_image = temp; + p_fw_image++; + temp = temp|((0x05)<<10); + *p_fw_image = temp; + p_fw_image++; + + /*write data byte 3;*/ + temp = 0x82|MCI_MEMORY_DATA_BYTE3|((value&0xFF000000)>>16); + temp = temp<<10; + *p_fw_image = temp; + p_fw_image++; + temp = temp|((0x05)<<10); + *p_fw_image = temp; + p_fw_image++; + + /* write address byte 2;*/ + temp = 0x82|MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_WRITE | + ((address & 0x003F0000)>>8); + temp = temp<<10; + *p_fw_image = temp; + p_fw_image++; + temp = temp|((0x05)<<10); + *p_fw_image = temp; + p_fw_image++; + + /* write address byte 1;*/ + temp = 0x82|MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00); + temp = temp<<10; + *p_fw_image = temp; + p_fw_image++; + temp = temp|((0x05)<<10); + *p_fw_image = temp; + p_fw_image++; + + /* write address byte 0;*/ + temp = 0x82|MCI_MEMORY_ADDRESS_BYTE0|((address & 0x00FF)<<8); + temp = temp<<10; + *p_fw_image = temp; + p_fw_image++; + temp = temp|((0x05)<<10); + *p_fw_image = temp; + p_fw_image++; + + for (i = 0; i < 6; i++) { + *p_fw_image = 0xFFFFFFFF; + p_fw_image++; + } } @@ -1055,7 +1050,7 @@ static int cx231xx_load_firmware(struct cx231xx *dev) p_fw_data += 1; } -/*download the firmware by ep5-out*/ + /*download the firmware by ep5-out*/ for (frame = 0; frame < (int)(CX231xx_FIRM_IMAGE_SIZE*20/_buffer_size); frame++) { @@ -2112,7 +2107,7 @@ static const struct v4l2_ioctl_ops mpeg_ioctl_ops = { .vidioc_g_std = vidioc_g_std, .vidioc_enum_input = vidioc_enum_input, .vidioc_enumaudio = vidioc_enumaudio, - .vidioc_g_audio = vidioc_g_audio, + .vidioc_g_audio = vidioc_g_audio, .vidioc_g_input = vidioc_g_input, .vidioc_s_input = vidioc_s_input, .vidioc_g_tuner = vidioc_g_tuner, diff --git a/drivers/media/video/cx231xx/cx231xx-avcore.c b/drivers/media/video/cx231xx/cx231xx-avcore.c index 2d773b31da1e..4e082435a1b1 100644 --- a/drivers/media/video/cx231xx/cx231xx-avcore.c +++ b/drivers/media/video/cx231xx/cx231xx-avcore.c @@ -55,7 +55,7 @@ *******************************************************************************/ /****************************************************************************** * VERVE REGISTER * - * * + * * ******************************************************************************/ static int verve_write_byte(struct cx231xx *dev, u8 saddr, u8 data) { @@ -936,11 +936,11 @@ void cx231xx_enable656(struct cx231xx *dev) { u8 temp = 0; int status; - /*enable TS1 data[0:7] as output to export 656*/ + /*enable TS1 data[0:7] as output to export 656*/ status = vid_blk_write_byte(dev, TS1_PIN_CTL0, 0xFF); - /*enable TS1 clock as output to export 656*/ + /*enable TS1 clock as output to export 656*/ status = vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp); temp = temp|0x04; @@ -1344,13 +1344,13 @@ void cx231xx_dump_HH_reg(struct cx231xx *dev) i = i+3; } - status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value); - cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value); - vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390); - status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value); - cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value); - + status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value); + cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value); + vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390); + status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value); + cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value); } + void cx231xx_dump_SC_reg(struct cx231xx *dev) { u8 value[4] = { 0, 0, 0, 0 }; @@ -1455,12 +1455,12 @@ void cx231xx_Setup_AFE_for_LowIF(struct cx231xx *dev) /* - config colibri to lo-if mode + config colibri to lo-if mode - FIXME: ntf_mode = 2'b00 by default. But set 0x1 would reduce - the diff IF input by half, + FIXME: ntf_mode = 2'b00 by default. But set 0x1 would reduce + the diff IF input by half, - for low-if agc defect + for low-if agc defect */ status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3, &value); @@ -1535,10 +1535,9 @@ void cx231xx_set_Colibri_For_LowIF(struct cx231xx *dev, u32 if_freq, u32 cx231xx_Get_Colibri_CarrierOffset(u32 mode, u32 standerd) { - u32 colibri_carrier_offset = 0; - + u32 colibri_carrier_offset = 0; - if (mode == TUNER_MODE_FM_RADIO) { + if (mode == TUNER_MODE_FM_RADIO) { colibri_carrier_offset = 1100000; } else if (standerd & (V4L2_STD_NTSC | V4L2_STD_NTSC_M_JP)) { colibri_carrier_offset = 4832000; /*4.83MHz */ @@ -1549,74 +1548,70 @@ u32 cx231xx_Get_Colibri_CarrierOffset(u32 mode, u32 standerd) colibri_carrier_offset = 2100000; /*2.10MHz */ } - - return colibri_carrier_offset; + return colibri_carrier_offset; } void cx231xx_set_DIF_bandpass(struct cx231xx *dev, u32 if_freq, u8 spectral_invert, u32 mode) { - - unsigned long pll_freq_word; - int status = 0; - u32 dif_misc_ctrl_value = 0; - u64 pll_freq_u64 = 0; - u32 i = 0; - + unsigned long pll_freq_word; + int status = 0; + u32 dif_misc_ctrl_value = 0; + u64 pll_freq_u64 = 0; + u32 i = 0; cx231xx_info("if_freq=%d;spectral_invert=0x%x;mode=0x%x\n", if_freq, spectral_invert, mode); - if (mode == TUNER_MODE_FM_RADIO) { - pll_freq_word = 0x905A1CAC; - status = vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word); - - } else /*KSPROPERTY_TUNER_MODE_TV*/{ - /* Calculate the PLL frequency word based on the adjusted if_freq*/ - pll_freq_word = if_freq; - pll_freq_u64 = (u64)pll_freq_word << 28L; - do_div(pll_freq_u64, 50000000); - pll_freq_word = (u32)pll_freq_u64; - /*pll_freq_word = 0x3463497;*/ - status = vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word); - - if (spectral_invert) { - if_freq -= 400000; - /* Enable Spectral Invert*/ - status = vid_blk_read_word(dev, DIF_MISC_CTRL, - &dif_misc_ctrl_value); - dif_misc_ctrl_value = dif_misc_ctrl_value | 0x00200000; - status = vid_blk_write_word(dev, DIF_MISC_CTRL, - dif_misc_ctrl_value); - } else { - if_freq += 400000; - /* Disable Spectral Invert*/ - status = vid_blk_read_word(dev, DIF_MISC_CTRL, - &dif_misc_ctrl_value); - dif_misc_ctrl_value = dif_misc_ctrl_value & 0xFFDFFFFF; - status = vid_blk_write_word(dev, DIF_MISC_CTRL, - dif_misc_ctrl_value); - } + if (mode == TUNER_MODE_FM_RADIO) { + pll_freq_word = 0x905A1CAC; + status = vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word); - if_freq = (if_freq/100000)*100000; + } else /*KSPROPERTY_TUNER_MODE_TV*/{ + /* Calculate the PLL frequency word based on the adjusted if_freq*/ + pll_freq_word = if_freq; + pll_freq_u64 = (u64)pll_freq_word << 28L; + do_div(pll_freq_u64, 50000000); + pll_freq_word = (u32)pll_freq_u64; + /*pll_freq_word = 0x3463497;*/ + status = vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word); - if (if_freq < 3000000) - if_freq = 3000000; + if (spectral_invert) { + if_freq -= 400000; + /* Enable Spectral Invert*/ + status = vid_blk_read_word(dev, DIF_MISC_CTRL, + &dif_misc_ctrl_value); + dif_misc_ctrl_value = dif_misc_ctrl_value | 0x00200000; + status = vid_blk_write_word(dev, DIF_MISC_CTRL, + dif_misc_ctrl_value); + } else { + if_freq += 400000; + /* Disable Spectral Invert*/ + status = vid_blk_read_word(dev, DIF_MISC_CTRL, + &dif_misc_ctrl_value); + dif_misc_ctrl_value = dif_misc_ctrl_value & 0xFFDFFFFF; + status = vid_blk_write_word(dev, DIF_MISC_CTRL, + dif_misc_ctrl_value); + } + + if_freq = (if_freq/100000)*100000; - if (if_freq > 16000000) - if_freq = 16000000; - } + if (if_freq < 3000000) + if_freq = 3000000; - cx231xx_info("Enter IF=%zd\n", - sizeof(Dif_set_array)/sizeof(struct dif_settings)); - for (i = 0; i < sizeof(Dif_set_array)/sizeof(struct dif_settings); i++) { - if (Dif_set_array[i].if_freq == if_freq) { - status = vid_blk_write_word(dev, - Dif_set_array[i].register_address, Dif_set_array[i].value); + if (if_freq > 16000000) + if_freq = 16000000; } - } + cx231xx_info("Enter IF=%zd\n", + sizeof(Dif_set_array)/sizeof(struct dif_settings)); + for (i = 0; i < sizeof(Dif_set_array)/sizeof(struct dif_settings); i++) { + if (Dif_set_array[i].if_freq == if_freq) { + status = vid_blk_write_word(dev, + Dif_set_array[i].register_address, Dif_set_array[i].value); + } + } } /****************************************************************************** @@ -2122,8 +2117,8 @@ int cx231xx_tuner_post_channel_change(struct cx231xx *dev) { int status = 0; u32 dwval; - cx231xx_info("cx231xx_tuner_post_channel_change dev->tuner_type =0%d\n", - dev->tuner_type); + cx231xx_info("cx231xx_tuner_post_channel_change dev->tuner_type =0%d\n", + dev->tuner_type); /* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for * SECAM L/B/D standards */ status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval); diff --git a/drivers/media/video/cx231xx/cx231xx-dif.h b/drivers/media/video/cx231xx/cx231xx-dif.h index 8187afcb0145..2b63c2f6d3b0 100644 --- a/drivers/media/video/cx231xx/cx231xx-dif.h +++ b/drivers/media/video/cx231xx/cx231xx-dif.h @@ -1,21 +1,21 @@ /* - cx231xx-dif.h - driver for Conexant Cx23100/101/102 USB video capture devices - - Copyright {C} 2009 <Bill.Liu@conexant.com> - - This program is free software, you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation, either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY, without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program, if not, write to the Free Software - Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * cx231xx-dif.h - driver for Conexant Cx23100/101/102 USB video capture devices + * + * Copyright {C} 2009 <Bill.Liu@conexant.com> + * + * This program is free software, you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY, without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program, if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #ifndef _CX231XX_DIF_H diff --git a/drivers/media/video/cx231xx/cx231xx.h b/drivers/media/video/cx231xx/cx231xx.h index f9cdc01a7faa..7631135b6420 100644 --- a/drivers/media/video/cx231xx/cx231xx.h +++ b/drivers/media/video/cx231xx/cx231xx.h @@ -56,13 +56,13 @@ /* Boards supported by driver */ #define CX231XX_BOARD_UNKNOWN 0 -#define CX231XX_BOARD_CNXT_CARRAERA 1 -#define CX231XX_BOARD_CNXT_SHELBY 2 -#define CX231XX_BOARD_CNXT_RDE_253S 3 -#define CX231XX_BOARD_CNXT_RDU_253S 4 +#define CX231XX_BOARD_CNXT_CARRAERA 1 +#define CX231XX_BOARD_CNXT_SHELBY 2 +#define CX231XX_BOARD_CNXT_RDE_253S 3 +#define CX231XX_BOARD_CNXT_RDU_253S 4 #define CX231XX_BOARD_CNXT_VIDEO_GRABBER 5 -#define CX231XX_BOARD_CNXT_RDE_250 6 -#define CX231XX_BOARD_CNXT_RDU_250 7 +#define CX231XX_BOARD_CNXT_RDE_250 6 +#define CX231XX_BOARD_CNXT_RDU_250 7 #define CX231XX_BOARD_HAUPPAUGE_EXETER 8 #define CX231XX_BOARD_HAUPPAUGE_USBLIVE2 9 |
